Semiconductor structure and forming method thereof
By forming a shallow trench isolation structure in the semiconductor structure, making the top surface of the storage region lower than the top surface of the floating gate layer, and forming a dielectric material layer and a control gate material layer on the floating gate layer, the problem of insufficient structural performance of memory devices is solved, the overall performance is improved and the fabrication process is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2026-03-10
AI Technical Summary
In existing semiconductor structures, the performance of memory devices needs improvement, which affects the overall performance of semiconductor devices.
By forming a shallow trench isolation structure on the substrate, such that the top surface of the storage area is lower than the top surface of the floating gate layer, and forming a conformal dielectric material layer covering the shallow trench isolation structure on the floating gate layer, and forming a control gate material layer on the dielectric material layer, the thickness of the storage area and the logic area is consistent, thereby maintaining uniformity when removing part of the material layer.
This improves the performance of memory device structures, enhances the overall performance of semiconductor devices, and reduces the fabrication difficulty of gate stack structures.
Smart Images
Figure CN121645867A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] With the development of semiconductor technology, more and more electronic products require greater intelligence, which places higher demands on their storage devices. Flash memory (Flash Memory) is a low-cost, highly integrated semiconductor storage device widely used in the electronics industry. Based on different structures, flash memory can be divided into two types: NOR Flash and NAND Flash. Among them, NOR Flash is widely used in electronic products because it can execute on-chip and has faster data read speeds and stronger reliability.
[0003] Furthermore, to reduce chip size, NOR Flash and other logic devices can be simultaneously integrated onto a single chip, resulting in an embedded NOR Flash device. Therefore, the semiconductor structure of an embedded NOR Flash device can be divided into a memory region with a memory device structure and a logic region with a logic device structure.
[0004] However, in the semiconductor structures formed by existing technologies, the performance of memory devices located in the memory region needs to be improved, which affects the overall performance of semiconductor devices. Summary of the Invention
[0005] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, so as to improve the performance of the memory device structure in the semiconductor structure, thereby improving the overall performance of the semiconductor device.
[0006] This disclosure provides a method for forming a semiconductor structure, including:
[0007] A substrate is provided, the substrate comprising a substrate, a plurality of gate insulating layers located on the substrate, and a floating gate layer located on the gate insulating layers, the plurality of gate insulating layers being discretely disposed on the substrate based on isolation trenches; wherein, the substrate includes a logic region and a memory region;
[0008] A shallow trench isolation structure is formed within the isolation trench, wherein at least the top surface of the shallow trench isolation structure located in the storage area is lower than the top surface of the floating grid stack structure;
[0009] A conformal dielectric material layer covering the shallow trench isolation structure is formed on the floating gate layer;
[0010] A control gate material layer is formed on the dielectric material layer;
[0011] Remove a portion of the control gate material layer, the dielectric material layer, and a portion of the thickness of the floating gate layer, leaving the dielectric material layer remaining in the storage area as the dielectric layer and the control gate material layer remaining in the storage area as the control gate layer;
[0012] Using the gate insulating layer as the stop layer, the floating gate layer of the logic region and part of the floating gate layer of the memory region are removed, and the remaining floating gate layer, dielectric layer and control gate layer in the memory region form the gate stack structure.
[0013] Optionally, the substrate further includes a gate sacrificial layer located on the floating gate layer;
[0014] The substrate provided includes:
[0015] A substrate is provided, a gate insulating material layer on the substrate, a floating gate material layer on the gate insulating material layer, and a gate sacrificial material layer on the floating gate material layer;
[0016] The gate sacrificial material layer is graphically represented to form an isolation trench pattern that exposes a portion of the floating gate material layer.
[0017] Remove the floating gate material layer, gate insulating material layer and part of the substrate exposed by the isolation trench pattern, and form a plurality of isolation trenches on the substrate that penetrate the gate sacrificial material layer, the floating gate material layer and the gate insulating layer;
[0018] The remaining gate sacrificial material layer is used as the gate sacrificial layer, the remaining floating gate material layer is used as the floating gate layer, and the remaining gate insulating material layer is used as the gate insulating layer.
[0019] Optionally, the substrate further includes: a gate sacrificial layer located on the floating gate layer, and a first mask layer located on the gate sacrificial layer;
[0020] The substrate provided includes:
[0021] A substrate is provided, and a gate insulating material layer on the substrate, a floating gate material layer on the gate insulating material layer, a gate sacrificial material layer on the floating gate material layer, and a first mask material layer on the gate sacrificial material layer are provided.
[0022] The first mask material layer is patterned to form a second isolation trench pattern that exposes a portion of the gate sacrificial material layer;
[0023] Remove the gate sacrificial material layer, floating gate material layer, gate insulating material layer and part of the substrate exposed by the second isolation trench pattern, and form a plurality of isolation trenches on the substrate that penetrate the first mask material layer, the gate sacrificial material layer, the floating gate material layer and the gate insulating layer;
[0024] The remaining first mask material layer is used as the first mask layer, the remaining gate sacrificial material layer is used as the gate sacrificial layer, the remaining floating gate material layer is used as the floating gate layer, and the remaining gate insulating material layer is used as the gate insulating layer.
[0025] Optionally, before forming the shallow trench isolation structure within the isolation trench, the method further includes:
[0026] A protective layer is formed within the isolation trench, covering the bottom and sidewalls of the isolation trench.
[0027] Optionally, forming a shallow trench isolation structure within the isolation trench includes:
[0028] A shallow trench isolation material layer is formed to completely fill the isolation trench;
[0029] Using the floating grid layer as a stop layer, the shallow trench isolation material layer is planarized, and the remaining shallow trench isolation material layer forms the shallow trench isolation structure.
[0030] The shallow trench isolation structure is etched away to remove a portion of its thickness, so that the top surface of the shallow trench isolation structure is lower than the top surface of the floating gate stack structure.
[0031] Optionally, forming a shallow trench isolation structure within the isolation trench includes:
[0032] A shallow trench isolation material layer is formed to completely fill the isolation trench;
[0033] The shallow trench isolation material layer is flattened, and the remaining shallow trench isolation material layer is used as a shallow trench isolation structure, wherein the top surface of the shallow trench isolation structure is higher than the top surface of the floating grid layer;
[0034] The first mask layer and the gate sacrificial layer are removed by etching.
[0035] Optionally, after etching away the first mask layer and the gate sacrificial layer, the process further includes:
[0036] A second mask material layer is formed to conformally cover the shallow trench isolation structure;
[0037] The second mask material layer is patterned to form a mask pattern that exposes the storage area;
[0038] Remove the exposed portion of the thickness of the shallow trench isolation structure in the storage area so that the top surface of the shallow trench isolation structure located in the storage area is lower than the top surface of the floating gate stack structure;
[0039] Remove the remaining second mask material layer.
[0040] Optionally, the dielectric material layer is formed using a furnace tube deposition process, and the dielectric material layer has a stacked structure, including an oxide layer, a nitride layer, and an oxide layer stacked sequentially.
[0041] Optionally, removing a portion of the control gate material layer, the dielectric material layer, and a portion of the thickness of the floating gate layer includes:
[0042] A third mask layer is formed on the control gate material layer, wherein the first mask pattern in the third mask layer exposes a portion of the control gate material layer in the memory region and the control gate material layer in the logic region, and the masked area of the first mask pattern is located in the floating gate layer of the memory region.
[0043] Remove the control gate material layer, the dielectric material layer, and a portion of the thickness of the floating gate layer exposed by the first mask pattern.
[0044] Optionally, removing the floating gate layer of the logic area and part of the floating gate layer of the memory area includes:
[0045] A fourth mask layer is formed on the floating gate layer, wherein the second mask pattern in the fourth mask layer exposes a portion of the floating gate layer in the memory area and the floating gate layer in the logic area, and the masked area of the second mask pattern includes the control gate layer and both sides of the control gate layer;
[0046] Using the gate insulating layer as a stop layer, the floating gate layer exposed by the second mask pattern is removed.
[0047] This disclosure also provides a semiconductor structure, including:
[0048] The substrate includes a substrate, a plurality of gate insulating layers located on the substrate, and a gate stack structure located on the gate insulating layers, wherein the plurality of gate insulating layers are discretely disposed on the substrate based on a shallow trench isolation structure;
[0049] The substrate includes a logic region and a memory region. The gate stack structure is located in the memory region and includes a floating gate layer, a dielectric layer, and a control gate layer. The top surface of the shallow trench isolation structure located in the memory region is lower than the top surface of the floating gate layer.
[0050] Compared with the prior art, the technical solution of the present disclosure has the following advantages:
[0051] This disclosure provides a semiconductor structure and a method for forming the same. The method uses a substrate including a base, a plurality of gate insulating layers discretely disposed on the substrate based on isolation trenches, and a floating gate layer on the gate insulating layers. The substrate includes a logic region and a memory region. A shallow trench isolation structure is formed within the isolation trenches, wherein at least the top surface of the shallow trench isolation structure located in the memory region is lower than the top surface of the floating gate layer. A conformal dielectric material layer covering the shallow trench isolation structure is formed on the floating gate layer. Furthermore, when a control gate material layer is formed on the dielectric material layer, memory isolation is ensured. The control gate material layer, dielectric material layer, and floating gate layer of the memory region and logic region have the same thickness, so that when a portion of the control gate material layer, the dielectric material layer, and a portion of the floating gate layer are removed, the uniformity of the control gate material layer, dielectric material layer, and floating gate layer of the memory region and logic region can be maintained. Therefore, when the floating gate layer of the logic region and a portion of the floating gate layer of the memory region are removed with the gate insulating layer as the stop layer, and the remaining floating gate layer, dielectric material layer, and control gate layer of the memory region form a gate stack structure, the performance of the memory device structure in the formed semiconductor structure can be improved, and the overall performance of the semiconductor device can be enhanced.
[0052] Furthermore, the consistent thickness of the floating gate layers in the memory and logic regions provides a suitable process window for the subsequent removal of the floating gate layers in the logic and memory regions, thereby reducing the fabrication difficulty of the gate stack structure. Attached Figure Description
[0053] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0054] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0055] Figures 7 to 31 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure provided in this disclosure. Detailed Implementation
[0056] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0057] As the background technology shows, the performance of memory device structures in existing semiconductor devices needs improvement, which affects the overall performance of the semiconductor devices. This paper analyzes the reasons for this problem based on existing technology.
[0058] refer to Figures 1 to 6 A schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure is shown.
[0059] like Figure 1 As shown, a substrate is provided, the substrate including a substrate 1 and shallow trench isolation structures 2 disposed on the substrate 1.
[0060] The shallow trench isolation structure 2 can be formed using deposition, photolithography, and etching processes. The etching process can be wet etching, dry etching, or a combination of both. In a specific example, a protective material layer and a mask material layer can be sequentially deposited on a substrate, using the mask material layer as a mask. Then, a photolithography process is used to form an isolation trench pattern on the substrate, exposing a portion of the protective material layer. An etching process is then used to remove the exposed protective material layer and part of the substrate, forming an isolation trench on the substrate. A deposition process is then used to form a shallow trench isolation structure that completely fills the isolation trench. Finally, the remaining mask material layer and protective material layer are removed to form... Figure 1 The structure shown.
[0061] like Figure 2 As shown, a gate insulating layer 31 is formed on the substrate, and a floating gate layer 32 is formed on the gate insulating layer 31.
[0062] Specifically, the gate insulating layer 31 can be discretely disposed on the substrate based on the shallow trench isolation structure. Since the gate insulating layer 31 is discretely disposed on the substrate based on the shallow trench isolation structure, the floating gate layer 32 formed on the gate insulating layer 31 can also be discretely disposed based on the shallow trench isolation structure. In a specific example, the gate insulating layer and the floating gate layer can be formed using a deposition process.
[0063] like Figure 3 As shown, the substrate is divided into a storage area 4 and a logic area 5, wherein the top surface of the shallow trench isolation structure and the floating gate layer located in the storage area is lower than the top surface of the shallow trench isolation structure and the floating gate layer located in the logic area.
[0064] In a specific example, photolithography and planarization processes can be used to divide the substrate into memory and logic regions. By coating the substrate with photoresist and using the photoresist as a mask for illumination, a mask pattern is formed that exposes a portion of the shallow trench isolation structure and floating gate layer. The exposed area of the mask pattern is designated as the memory region, and the concealed area as the logic region (as shown by the black area in the figure). Then, a planarization process is used to remove a portion of the thickness of the shallow trench isolation structure and floating gate layer located in the memory region, so that the top surface of the shallow trench isolation structure and floating gate layer in the memory region is lower than the top surface of the shallow trench isolation structure and floating gate layer in the logic region. In an optional example, after removing a portion of the thickness of the shallow trench isolation structure and floating gate layer in the memory region to divide the substrate into memory and logic regions, the photoresist covering the logic region can be removed.
[0065] like Figure 4 As shown, a shallow trench isolation structure with a portion of its thickness removed forms corresponding grooves 6 and 7 in the storage area and logic area.
[0066] like Figure 5 As shown, a gate stack structure 9 is formed in the storage region, the gate stack structure including a floating gate layer 32, a dielectric layer 81 and a control gate layer 82.
[0067] In a specific example, when forming a gate stack structure in the memory region, a dielectric material layer and a control gate material layer can be sequentially formed on the floating gate layer of the memory region first. The dielectric material layer can specifically be a stack structure, such as a silicon oxide layer-silicon nitride layer-silicon oxide layer (ONO). Then, using photolithography, a mask pattern exposing a portion of the control gate material layer is formed on the control gate material layer. Using the floating gate layer 32 of the memory region as a stop layer, the exposed control gate material layer and dielectric material layer of the mask pattern are removed, leaving the remaining dielectric material layer as the dielectric layer and the remaining control gate material layer as the control gate layer. Then, using the gate insulating layer 31 of the memory region as a stop layer, the exposed floating gate layer of the memory region is removed, leaving the remaining floating gate layer, dielectric layer, and control gate layer as the gate stack structure. Here, the gate stack structure can be understood as a structure used to form a memory device in the memory region.
[0068] like Figure 6 As shown, the floating gate layer with a portion of the logic area thickness is removed.
[0069] In a specific example, an etching process can be used to remove a portion of the floating gate layer in the logic region. The etching process can be wet etching, dry etching, or a combination of wet etching and dry etching.
[0070] Based on the aforementioned semiconductor structure formation process, the inventors discovered that when shallow trench isolation structures are first formed using deposition, photolithography, and etching processes, the isolation trench pattern formed by photolithography may deform, leading to dimensional shrinkage. This makes it prone to defects, such as voids, in the subsequent deposition of the floating gate layer on the substrate, ultimately affecting the signal storage capability of the memory device in the formed semiconductor structure. Furthermore, the thickness of the floating gate layer is determined by the planarization process; however, due to technical fluctuations in the planarization process and limitations in precise thickness control, the thickness of the floating gate layer is prone to variation. Consequently, when the gate stack structure is subsequently formed in the memory region, the performance uniformity of the gate stack structure is poor, reducing the overall performance of the formed semiconductor device.
[0071] Furthermore, when removing the floating gate layer with a certain thickness in the logic region, the difference in the thickness of the floating gate layer between the logic region and the memory region narrows the process window for removing the floating gate layer in the logic region, increasing the technical difficulty of removing the floating gate layer with a certain thickness in the logic region.
[0072] Therefore, to solve the above-mentioned technical problems, this disclosure provides a semiconductor structure and a method for forming the same. The method involves a substrate including a base, a plurality of gate insulating layers discretely disposed on the substrate based on isolation trenches, and a floating gate layer on the gate insulating layers. The substrate includes a logic region and a storage region. A shallow trench isolation structure is formed within the isolation trenches, wherein at least the top surface of the shallow trench isolation structure located in the storage region is lower than the top surface of the floating gate layer. A conformally conformal dielectric material layer covering the shallow trench isolation structure is then formed on the floating gate layer, and a control gate material layer is formed on the dielectric material layer. This ensures that the thickness of the control gate material layer, dielectric material layer, and floating gate layer in the memory region and the logic region is consistent. This allows the uniformity of the control gate material layer, dielectric material layer, and floating gate layer in the memory region and the logic region to be maintained when a portion of the control gate material layer, dielectric material layer, and floating gate layer of a certain thickness are removed. As a result, when the floating gate layer in the logic region and a portion of the floating gate layer in the memory region are removed using the gate insulating layer as a stop layer, and the remaining floating gate layer, dielectric material layer, and control gate layer in the memory region form a gate stack structure, the performance of the memory device structure in the formed semiconductor structure can be improved, thereby enhancing the overall performance of the semiconductor device.
[0073] Furthermore, the fact that the control gate material layer and the floating gate layer of the memory region and the logic region have the same thickness provides a suitable process window for the subsequent removal of the floating gate layer of the logic region and part of the floating gate layer of the memory region, thereby reducing the difficulty of fabricating the gate stack structure.
[0074] To make the above-mentioned objects, features and advantages of the embodiments of this disclosure more apparent and understandable, specific embodiments of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.
[0075] Figures 7 to 31 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to the present disclosure.
[0076] refer to Figures 7 to 9 Or refer to Figures 14 to 16 A substrate is provided, the substrate including a substrate 100, a plurality of gate insulating layers 111 located on the substrate and a floating gate layer 112 located on the gate insulating layers, the plurality of gate insulating layers 111 being discretely disposed on the substrate 100 based on isolation trenches 120; wherein, the substrate includes a logic region I and a memory region II.
[0077] The logic region I is the region in the semiconductor structure used to form logic devices; the memory region II is the region in the semiconductor structure used to form memory devices. The logic region and memory region may have significant differences in thickness, for example, the thickness of the floating gate layer or other layer structures.
[0078] The substrate 100 provides a process platform for subsequent process fabrication; specifically, the substrate 100 is used to form a NOR Flash device. The substrate 100 can be a silicon substrate epitaxially grown with a P-type source / drain structure. In other embodiments, the substrate material can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. Those skilled in the art can select the appropriate material based on actual needs. The substrate material can be suitable for process requirements or easily integrated.
[0079] The gate insulating layer 111 is formed on the substrate 100 to isolate the substrate and prevent the charge stored in the subsequently formed floating gate layer 112 from entering the substrate 100, thereby reducing charge loss and achieving the "floating gate" effect of the flash memory. The material of the gate insulating layer can be, for example, silicon oxide. The floating gate layer 112 is used to contain and control the charge, and its material can be polysilicon. In an optional example, the thickness of the gate insulating layer can be [missing information]. (angstroms), the thickness of the floating gate layer can be... In one specific example, the gate insulating layer and the floating gate layer located on the gate insulating layer may be formed using a deposition and photolithography process.
[0080] To improve device reliability, reduce leakage current, and enhance circuit isolation performance, multiple gate insulating layers can be discretely disposed on the substrate 100 based on isolation trenches 120. Where the gate insulating layers are discretely disposed on the substrate based on isolation trenches, the floating gate layers formed on the gate insulating layers can also be discretely disposed based on isolation trenches. The isolation trenches 120 can be created using STI technology by excavating a series of shallow and wide trenches on the substrate to separate the floating gate stack structures, facilitating the subsequent formation of corresponding devices in corresponding areas.
[0081] In an optional example, to form isolation trenches on the substrate, the substrate further includes a gate sacrificial layer 113 located on the floating gate layer. Specifically, the step of providing the substrate may include:
[0082] Reference Figure 7 A substrate 100 is provided, and a gate insulating material layer 101, a floating gate material layer 102, and a gate sacrificial material layer 103 are provided on the substrate.
[0083] The substrate 100 may be a semiconductor substrate, such as silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. Alternatively, the substrate may be other types of substrates, such as silicon-on-insulator substrates or germanium-on-insulator substrates, which may be selected by those skilled in the art according to actual needs.
[0084] In this embodiment, the gate insulating material layer 101 and the floating gate material layer 102 can be formed using a furnace tube deposition process. Furnace tube deposition is a technique such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) where a gaseous or solid source material is directly converted into a solid form and adhered to the substrate under vacuum or low pressure through a high-temperature or low-temperature reaction. The material of the gate insulating material layer 101 can be, for example, silicon oxide. The material of the floating gate material layer 102 can be, for example, polycrystalline silicon.
[0085] The gate sacrificial material layer 103 can be formed by a deposition process, and the material of the gate sacrificial material layer 103 can be silicon oxide, silicon nitride, etc.
[0086] Reference Figure 8 The gate sacrificial material layer 103 is graphically represented to form an isolation trench pattern 1031 that exposes a portion of the floating gate material layer;
[0087] The gate sacrificial material layer 103 is patterned by photolithography to form an isolation trench pattern 1031 that exposes part of the floating gate material layer. Then, the exposed floating gate material layer, gate insulating material layer and part of the substrate can be etched and removed using the gate sacrificial material layer as a mask to form an isolation trench.
[0088] Reference Figure 9 Remove the exposed floating gate material layer, gate insulating material layer, and part of the substrate from the isolation trench pattern, and form a plurality of isolation trenches 120 on the substrate that penetrate the gate sacrificial material layer, the floating gate material layer, and the gate insulating material layer, with the remaining gate sacrificial material layer as the gate sacrificial layer 113, the remaining floating gate material layer as the floating gate layer 112, and the remaining gate insulating material layer as the gate insulating layer 111;
[0089] In a specific example, the isolation trench can be formed by using STI (Shallow Trench Isolation) technology to remove the floating gate material layer, gate insulating material layer and part of the substrate exposed by the isolation trench pattern.
[0090] Next, refer to Figure 10 A protective layer 121 is formed in the isolation trench, and the protective layer 121 covers the bottom and sidewalls of the isolation trench 120;
[0091] It is understandable that during the process of removing the exposed floating gate material layer, gate insulating material layer, and part of the substrate from the isolation trench pattern to form the isolation trench, there is a possibility that the sidewalls of the formed isolation trench may be uneven. Therefore, to repair the sidewall damage of the isolation trench, a protective layer 121 can be formed within the isolation trench. For example, the protective layer can be formed using a deposition process, wherein the thickness of the protective layer is very small to avoid affecting the formed semiconductor structure. Furthermore, based on the formed protective layer, which covers the bottom and sidewalls of the isolation trench, the included angle between the bottom and sidewalls of the isolation trench is also rounded, reducing the intensity of the local electric field and preventing electric field breakdown.
[0092] refer to Figures 11 to 13 Or refer to Figures 18 to 20 A shallow trench isolation structure 130 is formed in the isolation trench, wherein the top surface of the shallow trench isolation structure 130 located at least in storage area II is lower than the top surface of the floating grid layer 112.
[0093] It should be noted that the storage regions of the semiconductor structure used in flash memory typically require deep-trench-oxide (DTI) structures to achieve high-density and durable charge storage. Therefore, after forming isolation trenches on the substrate, these trenches need to be filled to form shallow trench isolation structures to isolate different memory cells.
[0094] In one example, the shallow trench isolation structure can be formed using deposition, planarization, and etching processes. Specifically, the step of forming the shallow trench isolation structure within the isolation trench may include:
[0095] Reference Figure 11 This forms a shallow trench isolation material 131 that completely fills the isolation trench;
[0096] The shallow trench isolation material 131 may be formed by a deposition process, and the material of the shallow trench isolation material 131 may be, for example, silicon oxide.
[0097] Reference Figure 12 Using the floating grid layer 112 as a stop layer, the shallow trench isolation material layer is planarized, and the remaining shallow trench isolation material layer is used as the shallow trench isolation structure 130.
[0098] During the planarization of the shallow trench isolation material layer using the floating gate layer as a stop layer, the gate sacrificial layer can be removed. Furthermore, based on the design requirements of flash memory, a portion of the floating gate layer's thickness can be removed during the planarization process using the floating gate layer as a stop layer, ensuring the remaining floating gate layer meets the thickness requirements.
[0099] Reference Figure 13 The shallow trench isolation structure 130 is etched away to remove part of its thickness, so that the top surface of the shallow trench isolation structure 130 is lower than the top surface of the floating gate layer 112.
[0100] It should be noted that the logic region is used to form logic elements, such as transistors and circuit components. Its height requirements for the shallow trench isolation structure are not high, and the need for height adjustment of the shallow trench isolation structure is relatively small compared to the memory region. Therefore, to meet the height difference between the shallow trench isolation structures of the logic region and the memory region, additional processing, such as multiple photolithography steps, may be required for the memory region to ensure the height requirements of the shallow trench isolation structure. Simultaneously, maintaining a sufficient height difference between the shallow trench isolation structures of the logic region and the memory is crucial to ensuring the reliability of data storage and the normal operation of the logic functions in the formed semiconductor structure.
[0101] In another alternative example, to form a shallow trench isolation structure that meets the requirements on the substrate, the substrate further includes a gate sacrificial layer 113 located on the floating gate layer, and a first mask layer 114 located on the gate sacrificial layer. Specifically, the step of providing the substrate may include:
[0102] Reference Figure 14The system provides a substrate 100 and a gate insulating material layer 101, a floating gate material layer 102, a gate sacrificial material layer 103, and a first mask layer 104 on the gate sacrificial layer.
[0103] The first mask layer 104 may be formed by a deposition process, and the material of the first mask layer 104 may be, for example, silicon nitride.
[0104] Reference Figure 15 The first mask material layer 104 is patterned to form a second isolation trench pattern 1041 that exposes a portion of the gate sacrificial material layer 103;
[0105] The first mask material layer 104 is patterned by photolithography to form an isolation trench pattern 1041 that exposes part of the gate sacrificial material layer 103. Then, the exposed gate sacrificial material layer, floating gate material layer, gate insulating material layer and part of the substrate can be etched and removed using the first mask material layer as a mask to form an isolation trench.
[0106] Reference Figure 16 Remove the gate sacrificial material layer exposed by the second isolation trench pattern, as well as the floating gate material layer, the gate insulating material layer, and part of the substrate, and form a plurality of isolation trenches 120 on the substrate that penetrate the first mask material layer, the gate sacrificial material layer, the floating gate material layer, and the gate insulating material layer. Use the remaining first mask material layer as the first mask layer 114, the remaining gate sacrificial material layer as the gate sacrificial layer 113, the remaining floating gate material layer as the floating gate layer 112, and the remaining gate insulating material layer as the gate insulating layer 111.
[0107] In a specific example, the isolation trench can be formed by using STI (Shallow Trench Isolation) technology to remove the gate sacrificial material layer, floating gate material layer, gate insulating material layer and part of the substrate exposed by the isolation trench pattern.
[0108] Next, refer to Figure 17 A protective layer 121' is formed in the isolation trench, and the protective layer 121' covers the bottom and sidewalls of the isolation trench 120;
[0109] refer to Figure 18 This forms a shallow trench isolation material layer 131 that completely fills the isolation trench;
[0110] refer to Figure 19 The shallow trench isolation material layer is flattened, and the remaining shallow trench isolation material layer is used as the shallow trench isolation structure 130. The top surface of the shallow trench isolation structure 130 is higher than the top surface of the floating grid layer 112.
[0111] refer to Figure 20 The first mask layer and the gate sacrificial layer are removed by etching.
[0112] In an alternative example, the first mask layer and the gate sacrificial layer can be removed using a wet etching process. Specifically, the first mask layer and the gate sacrificial layer can be removed using HPO (hypophosphoric acid) and HF (hydrofluoric acid).
[0113] It is understandable that after removing the first mask layer and the gate sacrificial layer, the shallow trench isolation structures located in the memory area and the logic area have the same height. Therefore, to achieve a height difference in the shallow trench isolation structures between the memory area and the logic area, further reference can be made. Figures 21 to 24 .
[0114] Reference Figure 21 A second mask material layer 105 is formed to cover the shallow trench isolation structure;
[0115] The second mask material layer can be a photoresist layer, and the structure of the memory region can be exposed by photolithography and development.
[0116] Reference Figure 22 The second mask material layer is patterned to form a mask pattern 1051 that exposes the storage area;
[0117] Reference Figure 23 The shallow trench isolation structure 130 with a portion of its thickness exposed in the storage area is removed so that the top surface of the shallow trench isolation structure 130 located in the storage area is lower than the top surface of the floating gate layer 112.
[0118] As an alternative implementation, an etching process can be used to remove the exposed portion of the shallow trench isolation structure in the storage area. The etching process can be wet etching, dry etching, or a combination of wet and dry etching.
[0119] Reference Figure 24 Remove the remaining second mask material layer.
[0120] Next, refer to Figure 25 A conformal dielectric material layer 141 covering the shallow trench isolation structure is formed on the floating gate layer.
[0121] The dielectric material layer 141 can be formed using a deposition process, specifically a furnace tube deposition process, to isolate the subsequently formed control gate material layer from the floating gate layer. The dielectric material layer 141 can be a stacked structure, such as an ONO layer, comprising sequentially stacked oxide layers, nitride layers, and oxide layers, wherein the oxide is, for example, silicon oxide, and the nitride is, for example, silicon nitride.
[0122] refer to Figure 26 or Figure 27 A control gate material layer is formed on the dielectric material layer 141. Figure 26 The winning number is 142. Figure 27 The Chinese citation number is 142'.
[0123] The control gate material layer prepares for the subsequent formation of the control gate (CG). The control gate material layer can be formed using a deposition process, and the material of the control gate material layer can be the same as that of the floating gate layer, such as polysilicon.
[0124] In a specific example where the shallow trench isolation structure between the storage area and the logic area has a height difference, the control gate material layer formed on the dielectric material layer 141 can be specifically referred to... Figure 26 As shown.
[0125] In a specific example where the shallow trench isolation structure height is the same for the storage area and the logic area, the control gate material layer formed on the dielectric material layer 141 can be specifically referred to... Figure 27 As shown.
[0126] It is understandable that although the shallow trench isolation structure between the memory region and the logic region has a height difference, the floating gate layer thickness of the memory region and the logic region is the same. Compared with the method of removing a portion of the floating gate layer when the thickness of the floating gate layer of the memory region and the logic region is inconsistent, this embodiment can effectively increase the process window for removal, thereby providing a suitable process window for removing a portion of the floating gate layer thickness of the logic region and the memory region, and reducing the fabrication process difficulty of the gate stack structure.
[0127] refer to Figure 28 or Figure 29 Part of the control gate material layer, the dielectric material layer, and a portion of the floating gate layer are removed, leaving the remaining dielectric material layer in the memory region as the dielectric layer, and the remaining control gate material layer in the memory region as the control gate layer. Figure 28 A schematic diagram of a structure forming dielectric layer 150 and control gate layer 160 in an example where there is a height difference in the shallow trench isolation structure between the storage area and the logic area; Figure 29 This is a schematic diagram of a structure in which a dielectric layer 150 and a control gate layer 160' are formed in an example where the shallow trench isolation structure of the storage area and the logic area has the same height.
[0128] In an optional example, a photolithography and etching process can be used to remove a portion of the control gate material layer, the dielectric material layer, and a portion of the floating gate layer, leaving the remaining dielectric material layer in the memory region as the dielectric layer and the remaining control gate material layer in the memory region as the control gate layer. The etching process can be wet etching, dry etching, or a combination of wet and dry etching. By removing a portion of the control gate material layer, the dielectric material layer, and a portion of the floating gate layer, the subsequently formed gate stack structure can meet the design requirements of the semiconductor structure. Even after removing a portion of the floating gate layer, the top surface of the remaining floating gate layer in the memory region is still higher than the top surface of the shallow trench isolation structure.
[0129] In a specific example, the process of removing a portion of the control gate material layer, the dielectric material layer, and a portion of the floating gate layer may include: First, forming a patterned third mask layer on the control gate material layer, wherein a first mask pattern in the third mask layer exposes a portion of the control gate material layer located in the memory region and a portion of the control gate material layer located in the logic region, and the masked area of the first mask pattern is located in the floating gate layer of the memory region; wherein, the third mask layer may be a photoresist layer, and the portion of the control gate material layer located in the memory region and the control gate material layer located in the logic region may be exposed by photolithography and development. Second, removing the control gate material layer, the dielectric material layer, and a portion of the floating gate layer exposed by the first mask pattern. The removal of the control gate material layer, the dielectric layer, and a portion of the floating gate layer exposed by the first mask pattern may be performed using an etching process, which may be wet etching, dry etching, or a combination of wet and dry etching.
[0130] It should be noted that, in this embodiment, when removing part of the control gate material layer, dielectric material layer, and a portion of the floating gate layer, the positions of the control gate material layers exposed in the memory area and the control gate material layers exposed in the logic area by the mask pattern, as well as the positions of the floating gate layers in the memory area covered by the mask pattern, can be set according to the design requirements of the flash memory structure. This embodiment does not impose any limitations on this. For example... Figure 28 As shown, the masking area of the mask pattern is located in the storage area of the floating gate layer, which consists of two floating gate layers near the shallow trench isolation structure and a portion of the shallow trench isolation structure; or, the area where the floating gate layers are discretely set based on the shallow trench isolation structure.
[0131] refer to Figure 30 or Figure 31 Using the gate insulating layer as a stop layer, the floating gate layer in the logic region and part of the floating gate layer in the memory region are removed, leaving the remaining floating gate layer, dielectric layer, and control gate layer in the memory region as the gate stack structure. Figure 30In an example where there is a height difference in the shallow trench isolation structure between the storage area and the logic area, the gate insulating layer is used as the stop layer, the floating gate layer of the logic area and part of the floating gate layer of the storage area are removed, and the remaining floating gate layer, dielectric layer and control gate layer in the storage area are used as the gate stack structure 170. Figure 31 In an example where the shallow trench isolation structure of the memory region and the logic region has the same height, a schematic diagram of the gate stack structure 170' is shown, with the gate insulating layer as the stop layer, the floating gate layer of the logic region and part of the floating gate layer of the memory region are removed, and the remaining floating gate layer, dielectric layer and control gate layer in the memory region are used as the gate stack structure.
[0132] In an optional example, a photolithography and etching process can be used to remove the floating gate layer of the logic region and part of the floating gate layer of the memory region. The etching process can be wet etching, dry etching, or a combination of wet and dry etching. By removing the floating gate layer of the logic region and part of the floating gate layer of the memory region, the basic functional structure of flash memory, namely the gate stack structure, can be formed in the memory region.
[0133] In a specific example, the process of removing the floating gate layer in the logic region and a portion of the floating gate layer in the memory region, using the gate insulating layer as a stop layer, may include: First, forming a patterned fourth mask layer on the floating gate layer. A second mask pattern in the fourth mask layer exposes a portion of the floating gate layer in the memory region and a portion of the floating gate layer in the logic region. The masked area of the second mask pattern includes the control gate layer and both sides of the control gate layer. The fourth mask layer may be a photoresist layer, allowing the exposure of the portion of the floating gate layer in the memory region and the floating gate layer in the logic region through photolithography and development. Second, using the gate insulating layer as a stop layer, removing the floating gate layer exposed by the second mask pattern. When removing the floating gate layer exposed by the second mask pattern using the gate insulating layer as a stop layer, an etching process may be used. This etching process may be wet etching, dry etching, or a combination of wet and dry etching.
[0134] As can be seen, the embodiments of this disclosure include a substrate, a plurality of gate insulating layers discretely disposed on the substrate based on isolation trenches, and a floating gate layer on the gate insulating layers. The substrate includes a logic region and a storage region. A shallow trench isolation structure is formed within the isolation trenches, wherein at least the top surface of the shallow trench isolation structure located in the storage region is lower than the top surface of the floating gate layer. A conformally conformal dielectric material layer covering the shallow trench isolation structure is formed on the floating gate layer, and a control gate material layer is formed on the dielectric material layer, thus ensuring control of the storage region and the logic region. The gate material layer, dielectric material layer, and floating gate layer have the same thickness, which ensures that when a portion of the control gate material layer, dielectric material layer, and floating gate layer of a certain thickness are removed, the uniformity of the control gate material layer, dielectric material layer, and floating gate layer in the memory region and logic region can be maintained. Therefore, when the floating gate layer in the logic region and a portion of the floating gate layer in the memory region are removed with the gate insulating layer as the stop layer, and the remaining floating gate layer, dielectric layer, and control gate layer in the memory region form a gate stack structure, the performance of the memory device structure in the formed semiconductor structure can be improved, thereby enhancing the overall performance of the semiconductor device.
[0135] Furthermore, the consistent thickness of the floating gate layers in the memory and logic regions provides a suitable process window for the subsequent removal of the floating gate layers in the logic and memory regions, thereby reducing the fabrication difficulty of the gate stack structure.
[0136] In another embodiment of this disclosure, a semiconductor structure is also provided, with reference to... Figure 30 or Figure 31 The diagram illustrates a semiconductor structure. The semiconductor structure includes: a substrate, the substrate comprising a substrate 100, a plurality of gate insulating layers 111 located on the substrate, and a gate stack structure located on the gate insulating layers. Figure 30 The winning number is 170. Figure 31 (Ref. 170'), the plurality of gate insulating layers are discretely disposed on the substrate 100 based on a shallow trench isolation structure 130.
[0137] The substrate includes a logic region I and a memory region II. The gate stack structure is located in memory region II and includes a floating gate layer 112, a dielectric layer 150, and a control gate layer. Figure 30 The winning number is 160. Figure 31 (The reference numeral is 160'); the top surface of the shallow trench isolation structure 130 located at least in storage area II is lower than the top surface of the floating gate layer 112.
[0138] It should be noted that the semiconductor structure described in this embodiment can be formed using the formation method described in this embodiment, or it can be formed using other formation methods. Specific descriptions of the semiconductor structure and its formation method described in this embodiment can be referenced interchangeably, and will not be repeated here.
[0139] The foregoing describes multiple embodiment schemes provided by the present disclosure. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and made public by the present disclosure.
[0140] While the embodiments disclosed herein are as described above, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.
Claims
1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate, the substrate comprising a substrate, a plurality of gate insulating layers located on the substrate and a floating gate layer located on the gate insulating layers, the plurality of gate insulating layers being separately arranged on the substrate based on isolation trenches; wherein the substrate comprises a logic region and a storage region; forming a shallow trench isolation structure in the isolation trench, wherein the top surface of the shallow trench isolation structure located at least in the storage region is lower than the top surface of the floating gate layer; forming a dielectric material layer conformally covering the shallow trench isolation structure on the floating gate layer; forming a control gate material layer on the dielectric material layer; removing part of the control gate material layer, the dielectric material layer and part of the thickness of the floating gate layer, so that the dielectric material layer remaining in the storage region is a dielectric layer, and the control gate material layer remaining in the storage region is a control gate layer; removing the floating gate layer of the logic region and part of the floating gate layer of the storage region with the gate insulating layer as a stop layer, so that the floating gate layer, the dielectric layer and the control gate layer remaining in the storage region form a gate stack structure.
2. The method of claim 1, wherein The substrate further comprises a gate sacrificial layer located on the floating gate layer; The method of providing a substrate comprises: providing a substrate and a gate insulating material layer located on the substrate, a floating gate material layer located on the gate insulating material layer, and a gate sacrificial material layer located on the floating gate material layer; patterning the gate sacrificial material layer to form an isolation trench pattern exposing part of the floating gate material layer; removing the floating gate material layer exposed by the isolation trench pattern, and the gate insulating material layer and part of the substrate, forming a plurality of isolation trenches penetrating through the gate sacrificial material layer, the floating gate material layer and the gate insulating material layer on the substrate, so that the remaining gate sacrificial material layer is a gate sacrificial layer, the remaining floating gate material layer is a floating gate layer, and the remaining gate insulating material layer is a gate insulating layer.
3. The method of claim 1, wherein The substrate further comprises a gate sacrificial layer located on the floating gate layer, and a first mask layer located on the gate sacrificial layer; The method of providing a substrate comprises: providing a substrate and a gate insulating material layer located on the substrate, a floating gate material layer located on the gate insulating material layer, a gate sacrificial material layer located on the floating gate material layer, and a first mask material layer located on the gate sacrificial material layer; patterning the first mask material layer to form a second isolation trench pattern exposing part of the gate sacrificial material layer; removing the gate sacrificial material layer exposed by the second isolation trench pattern, and the floating gate material layer, the gate insulating material layer and part of the substrate, forming a plurality of isolation trenches penetrating through the first mask material layer, the gate sacrificial material layer, the floating gate material layer and the gate insulating material layer on the substrate, so that the remaining first mask material layer is a first mask layer, the remaining gate sacrificial material layer is a gate sacrificial layer, the remaining floating gate material layer is a floating gate layer, and the remaining gate insulating material layer is a gate insulating layer.
4. The method of forming a semiconductor structure according to any one of claims 2 or 3, wherein, Before forming a shallow trench isolation structure in the isolation trench, the method further comprises: forming a protective layer in the isolation trench, the protective layer covering the bottom and sidewall of the isolation trench.
5. The method of claim 2, wherein the step of forming the semiconductor structure is performed by a method selected from the group consisting of: epitaxial growth, chemical vapor deposition, physical vapor deposition, and combinations thereof. The method of forming a shallow trench isolation structure in the isolation trench comprises: forming a shallow trench isolation material layer completely filling the isolation trench; The shallow trench isolation material layer is planarized by taking the floating gate layer as a stop layer, so as to form a shallow trench isolation structure with a top surface higher than that of the floating gate layer. The shallow trench isolation structure is etched to have a top surface lower than that of the floating gate layer.
6. The method of claim 3, wherein the step of forming the semiconductor structure is performed by a method comprising: The shallow trench isolation structure formed in the isolation trench comprises: forming a shallow trench isolation material layer completely filling the isolation trench; planarizing the shallow trench isolation material layer to form a shallow trench isolation structure with a top surface higher than that of the floating gate layer; the first mask layer and the gate sacrificial layer are etched.
7. The method of claim 6, wherein the step of forming the semiconductor structure is performed by a method comprising: After the first mask layer and the gate sacrificial layer are etched, the method further comprises: forming a second mask material layer covering the shallow trench isolation structure; forming a mask pattern exposing the storage area by patterning the second mask material layer; the shallow trench isolation structure exposed in the storage area is etched to have a top surface lower than that of the floating gate layer in the storage area; the remaining second mask material layer is removed.
8. The method of claim 1, wherein The dielectric material layer is formed by a furnace tube deposition process, and the dielectric material layer is a stacked structure comprising oxide layers, nitride layers and oxide layers stacked in sequence.
9. The method of claim 1, wherein The control gate material layer, the dielectric material layer and part of the floating gate layer are removed by: forming a third mask layer patterned on the control gate material layer, wherein a first mask pattern in the third mask layer exposes part of the control gate material layer in the storage area and the control gate material layer in the logic area, and a mask area of the first mask pattern is located in the floating gate layer in the storage area; the control gate material layer, the dielectric material layer and part of the floating gate layer exposed by the first mask pattern are removed.
10. The method of claim 9, wherein the step of forming the semiconductor structure is performed by a method comprising: The floating gate layer in the logic area and part of the floating gate layer in the storage area are removed by taking the gate insulating layer as a stop layer, which comprises: forming a fourth mask layer patterned on the floating gate layer, wherein a second mask pattern in the fourth mask layer exposes part of the floating gate layer in the storage area and the floating gate layer in the logic area, and a mask area of the second mask pattern comprises the control gate layer and both sides of the control gate layer; the floating gate layer exposed by the second mask pattern is removed by taking the gate insulating layer as a stop layer.
11. A semiconductor structure, characterized by The method comprises: a substrate comprising a substrate, a plurality of gate insulating layers arranged on the substrate based on shallow trench isolation structures, and a gate stack structure on the gate insulating layers; wherein the substrate comprises a logic area and a storage area, the gate stack structure is located in the storage area, and the gate stack structure comprises a floating gate layer, a dielectric layer and a control gate layer; at least the top surface of the shallow trench isolation structure in the storage area is lower than that of the floating gate layer.