Semiconductor structure and forming method

Abstract

The invention provides a semiconductor structure and a forming method, and the semiconductor structure comprises a substrate which comprises a first region; the plurality of word line structures are arranged on the first region in a discrete manner; the selection tube gate is positioned on one side of the word line structure; the first dielectric layer is located on the substrate and covers the word line structures and the selection tube grid, air columns are arranged in the first dielectric layer, the air columns are located between the adjacent word line structures, and the height of the air columns is larger than that of the word line structures; a barrier layer located on the surface of the first dielectric layer; the second dielectric layer is located on the surface of the barrier layer, and the hardness of the barrier layer is larger than that of the second dielectric layer; the barrier layer can play a role in pressure dispersion, so that the pressure of the second dielectric layer on the air column is reduced in the process of forming the second dielectric layer, the problem that the height of the air column is compressed is avoided or reduced, and the breakdown voltage between the word line structures can be improved; and meanwhile, the barrier layer has a barrier effect and can prevent hydrogen ions in the second dielectric layer from diffusing into the first dielectric layer, so that the performance of the finally formed semiconductor structure is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method. BACKGROUND

[0002] NAND flash (NAND device) as an important flash device, because the structure has very high cell density, can achieve high storage density, and its write and erase speed is very fast, so it is widely used in various types of memory cards, and is gradually replacing the mechanical hard disk solid state disk.

[0003] With the shrinking of the device size, the word line spacing size of the NAND device block area is also decreasing, which will cause serious inter-cell coupling interference problem of the floating gate type memory, thereby affecting the size of the cell threshold voltage, the programming and reading speed of the memory array. In order to solve this problem, the air gap isolation technology process is introduced into the production of NAND flash, by introducing the material with the lowest dielectric constant-air between the floating gate and the floating gate, to improve the capacitive coupling effect between the word line floating gate of the device.

[0004] However, the quality of the NAND flash still needs to be improved. SUMMARY

[0005] The technical problem solved by the present application is to provide a semiconductor structure and a forming method to improve the quality of the semiconductor structure.

[0006] The technical scheme of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a first area; a plurality of discrete arranged word line structures on the first area; a selection gate on one side of the word line structure; a first dielectric layer on the substrate and covering the word line structure and the selection gate, the first dielectric layer having an air column therein, the air column being located between adjacent word line structures, the height of the air column being higher than the height of the word line structure; a barrier layer on the surface of the first dielectric layer; a second dielectric layer on the surface of the barrier layer, the hardness of the barrier layer being greater than the hardness of the second dielectric layer.

[0007] Optionally, the thickness of the second dielectric layer ranges from 2000 angstroms to 3000 angstroms, and the material of the second dielectric layer comprises silicon dioxide.

[0008] Optionally, the material of the first dielectric layer is silane.

[0009] Optionally, further comprising: a repair layer between the first dielectric layer and the barrier layer.

[0010] Optionally, the material of the barrier layer comprises silicon oxynitride.

[0011] Optionally, the side wall is further included.

[0012] Optionally, the second region is further included, which is adjacent to the first region, and the second region is located at one side of the select gate, and the third dielectric layer is formed on the second region, and the first dielectric layer further extends to the surface of the third dielectric layer.

[0013] Correspondingly, the application further provides a forming method of a semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first region; forming a plurality of discrete arranged word line structures and a select gate located at one side of the word line structures on the first region; forming a first dielectric layer covering the word line structures and the select gate on the substrate, wherein the first dielectric layer has an air column, the air column is formed between the adjacent word line structures, and the height of the air column is higher than the height of the word line structures; forming a barrier layer on the surface of the first dielectric layer; and forming a second dielectric layer on the surface of the barrier layer, wherein the hardness of the barrier layer is greater than the hardness of the second dielectric layer.

[0014] Optionally, the forming method of the second dielectric layer comprises the following steps: using a plasma enhanced process, and taking tetraethoxysilane as a precursor to form an initial second dielectric layer on the surface of the barrier layer; and performing a planarization treatment on the initial second dielectric layer to form the second dielectric layer.

[0015] Optionally, the thickness of the initial second dielectric layer ranges from 5100 angstroms to 5500 angstroms.

[0016] Optionally, the forming process of the first dielectric layer comprises a plasma enhanced process, and silane is used as a raw material.

[0017] Optionally, the substrate further comprises a second region adjacent to the first region, and before the first dielectric layer is formed, the following steps are further included: a third dielectric layer is formed on the substrate surface of the second region, and the first dielectric layer further extends to the surface of the third dielectric layer.

[0018] Optionally, before the third dielectric layer is formed, the following steps are further included: a sacrificial layer is formed on the substrate surface between the adjacent word line structures, the substrate surface between the word line structures and the select gate, and the sacrificial layer is also located on the sidewall of the select gate; a fourth dielectric layer is formed on the surface of the sacrificial layer and the substrate surface of the second region; and the third dielectric layer is formed on the surface of the fourth dielectric layer.

[0019] Optionally, before forming the first dielectric layer, further comprising: removing the third dielectric layer, the fourth dielectric layer and the sacrificial layer between the adjacent word line structures and between the word line structure and the select gate of the first region to expose the surface of the substrate between the adjacent word line structures and between the word line structure and the select gate.

[0020] Optionally, the thickness of the third dielectric layer of the second region, the thickness of the first dielectric layer, the thickness of the barrier layer and the thickness of the second dielectric layer are in the range of 4900 angstroms to 5200 angstroms.

[0021] Optionally, the time of the planarization process is in the range of 33s to 39s.

[0022] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0023] In the forming method of the technical scheme, after forming the first dielectric layer on the substrate, the first dielectric layer has an air column formed between the adjacent word line structures, wherein the height of the air column is higher than the height of the word line structure, a barrier layer is formed on the surface of the first dielectric layer, a second dielectric layer is formed on the surface of the barrier layer, and the hardness of the barrier layer is greater than the hardness of the second dielectric layer; after forming the barrier layer on the surface of the first dielectric layer, the second dielectric layer is formed, and the barrier layer can play a role of pressure dispersion, so that the pressure of the second dielectric layer on the air column is reduced in the process of forming the second dielectric layer, thereby avoiding or reducing the problem that the height of the air column is compressed, which helps to improve the breakdown voltage between the word line structures; at the same time, the barrier layer has a blocking effect to prevent hydrogen ions in the second dielectric layer from diffusing into the first dielectric layer, thereby ensuring the performance of the finally formed semiconductor structure.

[0024] Further, the forming method of the second dielectric layer comprises using a plasma enhanced process to form an initial second dielectric layer on the surface of the barrier layer by taking tetraethoxysilane as a precursor, performing planarization treatment on the initial second dielectric layer to form the second dielectric layer, wherein the thickness of the initial second dielectric layer is in the range of 5100 angstroms to 5500 angstroms, and here the thicker initial second dielectric layer increases the distance between the grinding point and the air column in the process of forming the second dielectric layer by planarization, and in combination with the role of pressure dispersion of the barrier layer, the compression of the height of the air column in the planarization process is greatly reduced, which has a wider range of use. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figures 1 to 6 is a structure diagram corresponding to the semiconductor structure forming process in an embodiment;

[0026] Figures 7 to 10This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0027] As described in the background section, the quality of NAND flash memory in the prior art still needs improvement. This will be explained in detail below with reference to the accompanying drawings.

[0028] Please refer to Figure 1 The substrate 100 includes a first region I and a second region II adjacent to the first region I; a plurality of discretely arranged word line structures 101 and a select gate 102 located on one side of the word line structure 101 are formed on the surface of the substrate 100 in the first region I, and the sidewall of the select gate 102 has a sidewall 103; an oxide layer 104 is formed on the surface of the substrate 100 in the second region II; a first dielectric layer 105 is formed on the surface of the substrate 100 covering the word line structure 101, the select gate 102 and the oxide layer 104, and the first dielectric layer 105 forms air columns 106 between adjacent word line structures 101, the height of the air columns 106 being higher than the height of the word line structure 101.

[0029] Please refer to Figure 2 An initial second dielectric layer 107 is formed on the surface of the first dielectric layer 105.

[0030] Please refer to Figure 3 The initial second dielectric layer 107 is planarized to form a second dielectric layer 108.

[0031] Please refer to Figure 4 A barrier layer 109 is formed on the surface of the second dielectric layer 108.

[0032] Please refer to Figure 5 An initial third dielectric layer 110 is formed on the surface of the barrier layer 109.

[0033] Please refer to Figure 6 The initial third dielectric layer 110 is planarized to form the third dielectric layer 111.

[0034] The inventors discovered that after the initial second dielectric layer 107 is formed, the initial second dielectric layer 107 is planarized. During the planarization process, the initial second dielectric layer 107 is subjected to mechanical pressure, which compresses the height of the air column 106 (dashed box in the figure), thereby reducing the overall height of the air column, affecting the breakdown voltage between word line structures, and limiting the use of semiconductor structures to a certain extent.

[0035] The inventors have found that, after forming a first dielectric layer on a substrate, an air column is formed in the first dielectric layer between adjacent word line structures, wherein the height of the air column is higher than the height of the word line structures, a barrier layer is formed on the surface of the first dielectric layer, a second dielectric layer is formed on the surface of the barrier layer, and the hardness of the barrier layer is greater than the hardness of the second dielectric layer; after forming the barrier layer on the surface of the first dielectric layer, the second dielectric layer is formed again, the barrier layer can play a role of pressure dispersion, thereby reducing the pressure of the second dielectric layer on the air column during the formation of the second dielectric layer, so as to avoid or reduce the problem that the height of the air column is compressed, which helps to improve the breakdown voltage between the word line structures; at the same time, the barrier layer has a blocking effect to prevent hydrogen ions in the second dielectric layer from diffusing into the first dielectric layer, thereby ensuring the performance of the finally formed semiconductor structure.

[0036] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0037] First, refer to Figure 7 , a substrate 200 is provided, which includes a first region I.

[0038] In this embodiment, the material of the substrate 200 is silicon.

[0039] In other embodiments, the material of the substrate 200 can also be silicon germanium and other semiconductor materials.

[0040] In this embodiment, the substrate 200 also includes a second region II adjacent to the first region I.

[0041] In this embodiment, the second region II serves as an active area (AA).

[0042] In this embodiment, a plurality of discrete word line structures 201 and a select gate 202 located on one side of the word line structures 201 are formed on the first region I.

[0043] In this embodiment, the word line structures 201 (WL) and the select gate 202 are formed by a self-aligned double patterning process.

[0044] In this embodiment, four word line structures 201 are shown in the figure.

[0045] In the embodiment, a third dielectric layer 203 is formed in the second region II. Before forming the third dielectric layer 203, a sacrificial layer is formed on the surface of the substrate 200 between the adjacent word line structures 201 and between the word line structure 201 and the select gate 202, and the sacrificial layer is also formed on the sidewall of the select gate 202. A fourth dielectric layer 211 is formed on the surface of the sacrificial layer and the surface of the substrate 200 in the second region II. The surface of the fourth dielectric layer 211 forms the third dielectric layer 203.

[0046] In the embodiment, the third dielectric layer 203, the fourth dielectric layer 211 and the sacrificial layer between the adjacent word line structures 201 and between the word line structure 201 and the select gate 202 in the first region I are removed to expose the surface of the substrate 200 between the adjacent word line structures 201 and between the word line structure 201 and the select gate 202. The sacrificial layer on the sidewall of the select gate 202 serves as a sidewall 204.

[0047] In the embodiment, the material of the fourth dielectric layer 211 can be silicon nitride.

[0048] In the embodiment, please continue to refer to Figure 7 A first dielectric layer 205 is formed on the substrate 200 to cover the word line structure 201 and the select gate 202. The first dielectric layer 205 has an air column 206 formed between the adjacent word line structures 201. The height (H) of the air column 206 is higher than the height (h) of the word line structure 201.

[0049] In the embodiment, the first dielectric layer 205 also extends to the surface of the third dielectric layer 203 in the second region II.

[0050] In the embodiment, the forming process of the first dielectric layer 205 includes a plasma enhanced (PE) process, and silane (SiH4) is used as the raw material.

[0051] In the embodiment, after the PE-SiH4 deposition, the air column 206 can be formed between the word line structures 201 due to the low surface mobility and poor step coverage of PE-SiH4.

[0052] In the embodiment, the top surface of the air column 206 is about 110 angstroms higher than the top surface of the word line structure 201.

[0053] In the embodiment, after the first dielectric layer 205 is formed, a repair layer 207 is formed on the surface of the first dielectric layer 205 before the barrier layer is formed.

[0054] In this embodiment, the material of the repair layer 207 is silicon oxide.

[0055] In this embodiment, in order to prevent some small gaps from existing on the surface of the first dielectric layer 205 after the formation of the first dielectric layer 205, the repair layer 207 can be used to repair these gaps.

[0056] In this embodiment, the thickness of the repair layer 207 is 350 angstroms to 390 angstroms.

[0057] In this embodiment, the process of forming the repair layer 207 is an atomic layer deposition process.

[0058] In this embodiment, the reason for using the atomic layer deposition process to form the repair layer 207 is that the repair layer 207 formed by the atomic layer deposition process has good step coverage, so as to be perfectly matched with the first dielectric layer 205, thereby ensuring the quality of the surface after the formation of the repair layer 207, and preparing for the formation of a high-quality semiconductor structure.

[0059] Please refer to Figure 8 A barrier layer 208 is formed on the surface of the first dielectric layer 205.

[0060] In this embodiment, the material of the barrier layer 208 is silicon oxynitride.

[0061] In other embodiments, the material of the barrier layer 208 can also be silicon nitride, silicon carbide, etc.

[0062] In this embodiment, the process of forming the barrier layer 208 is a chemical vapor deposition process.

[0063] In other embodiments, the process of forming the barrier layer 208 can also be a physical vapor deposition process, etc.

[0064] In this embodiment, the barrier layer 208 is formed after the formation of the first dielectric layer 205, and has a large hardness, which can play a certain supporting and protecting role. In the subsequent process of forming the second dielectric layer, it can block the mechanical pressure of the second dielectric layer from being transmitted downward, thereby reducing the height compression of the air column 206 and avoiding affecting the breakdown voltage between the word line structure 201 and the word line structure 201.

[0065] In this embodiment, the barrier layer 208 also has a blocking effect, which can block the diffusion of hydrogen ions in the second dielectric layer into the first dielectric layer 205, thereby avoiding affecting the performance of the formed semiconductor structure.

[0066] A second dielectric layer is formed on the surface of the barrier layer 208, the hardness of the barrier layer 208 is greater than the hardness of the second dielectric layer, for details, please refer to Figures 9 to 10 .

[0067] Please refer to Figure 9 , a plasma enhanced process is adopted to form an initial second dielectric layer 209 on the surface of the barrier layer 208 by taking tetraethoxysilane as a precursor.

[0068] Please refer to Figure 10 The initial second dielectric layer 209 is subjected to a planarization process to form the second dielectric layer 210.

[0069] In this embodiment, the thickness of the initial second dielectric layer 209 ranges from 5100 angstroms to 5500 angstroms. Here, the thicker initial second dielectric layer 209 is utilized to increase the distance between the polishing point and the air column 206 during the planarization process to form the second dielectric layer 210, and the barrier layer 208 can play a role in pressure dispersion, greatly reducing the compression of the height of the air column 206 during the planarization process, and having a wider range of use.

[0070] In this embodiment, the thickness of the second dielectric layer 210 ranges from 2000 angstroms to 3000 angstroms, and the material of the second dielectric layer 210 includes silicon dioxide.

[0071] In this embodiment, the time range of the planarization process is 33s to 39s.

[0072] In this embodiment, the rough polishing and fine polishing time is increased to 33s to 39s, which can greatly improve the quality of the second dielectric layer 210 after planarization, and the total thickness of the oxide layer on the second region II is between 4900 angstroms and 5200 angstroms, specifically the sum of the thickness of the third dielectric layer 203, the thickness of the first dielectric layer 205, the thickness of the barrier layer 208 and the thickness of the second dielectric layer 210 in the second region II. In this way, the total thickness of the oxide layer on the second region II also matches the planarization process scheme, and subsequent tests show that the breakdown voltage between the word line structure 201 and the word line structure 201 increases by about 4V after planarization, which has a wider range of application.

[0073] In this embodiment, after forming a barrier layer 208 on the surface of the first dielectric layer 205, a second dielectric layer 210 is formed. The barrier layer 208 can disperse pressure, thereby reducing the pressure of the second dielectric layer 210 on the air column 206 during the formation of the second dielectric layer 210. This avoids or reduces the problem of the height of the air column 206 being compressed, which helps to improve the breakdown voltage between word line structures 201. At the same time, the barrier layer 208 can prevent hydrogen ions in the second dielectric layer 210 from diffusing into the first dielectric layer 205, thereby ensuring the performance of the final semiconductor structure. Combined with the relatively thick initial second dielectric layer 209, the distance between the grinding points and the air column 206 is increased during the planarization process of forming the second dielectric layer 210. Combined with the pressure dispersion effect of the barrier layer 208, the compression of the height of the air column 206 during the planarization process is greatly reduced, which has a wide range of applications.

[0074] Accordingly, the present invention also provides a semiconductor structure, please refer to... Figure 10 The system includes a substrate 200, which includes a first region I; a plurality of discretely arranged word line structures 201 located on the first region I; a select gate 202 located on one side of the word line structures 201; a first dielectric layer 205 located on the substrate 200 and covering the word line structures 201 and the select gate 202, the first dielectric layer 205 having air columns 206 located between adjacent word line structures 201, the height of the air columns 206 being higher than the height of the word line structures 201; a barrier layer 208 located on the surface of the first dielectric layer 205; and a second dielectric layer 210 located on the surface of the barrier layer 208, the hardness of the barrier layer 208 being greater than the hardness of the second dielectric layer 210.

[0075] In this embodiment, a barrier layer 208 is formed on the surface of the first dielectric layer 205, and a second dielectric layer 210 is formed on the surface of the barrier layer 208. The hardness of the barrier layer 208 is greater than that of the second dielectric layer 210. After the barrier layer 208 is formed on the surface of the first dielectric layer 205, the second dielectric layer 210 is formed. The barrier layer 208 can play a role in pressure dispersion, thereby reducing the pressure of the second dielectric layer 210 on the air column 206 during the formation of the second dielectric layer 210. This avoids or reduces the problem of the height of the air column 206 being compressed, which helps to improve the breakdown voltage between word line structures 201. At the same time, the barrier layer 208 has a blocking effect, which can prevent hydrogen ions in the second dielectric layer 210 from diffusing into the first dielectric layer 205, thereby ensuring the performance of the finally formed semiconductor structure.

[0076] In this embodiment, the thickness of the second dielectric layer 210 ranges from 2000 angstroms to 3000 angstroms, and the material of the second dielectric layer 210 includes silicon dioxide.

[0077] In this embodiment, before forming the second dielectric layer 210, an initial second dielectric layer 209 with a thickness ranging from 5100 angstroms to 5500 angstroms is first formed, and then planarization is performed to form the second dielectric layer 210. Since the initial second dielectric layer 209 has a relatively thick thickness, the distance between the grinding point and the air column 206 is increased. Combined with the barrier layer 208, it can play a role in pressure dispersion, which greatly reduces the compression of the height of the air column 206 during the planarization process, and has a wide range of applications.

[0078] In this embodiment, the material of the first dielectric layer 205 is silane.

[0079] In this embodiment, a repair layer 207 is also included, located between the first dielectric layer 205 and the barrier layer 208.

[0080] In this embodiment, the material of the barrier layer 208 includes silicon oxynitride.

[0081] In this embodiment, it also includes a sidewall 204 located on one side of the selection grid 202.

[0082] In this embodiment, it further includes: a second region II adjacent to the first region I, the second region II being located on one side of the selection gate 202, the second region II having a third dielectric layer 203, and the first dielectric layer 205 extending to the surface of the third dielectric layer 203.

[0083] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The method comprises: providing a substrate, the substrate comprising a first region; forming a plurality of discrete word line structures on the first region and a select gate on a side of the word line structures; forming a first dielectric layer on the substrate and covering the word line structures and the select gate, the first dielectric layer having air columns formed therein between adjacent word line structures, the air columns having a height higher than a height of the word line structures; forming a barrier layer on a surface of the first dielectric layer; forming a second dielectric layer on a surface of the barrier layer, the barrier layer having a hardness greater than a hardness of the second dielectric layer. The second dielectric layer has a thickness ranging from 2000 angstroms to 3000 angstroms, and the second dielectric layer comprises silicon dioxide.

2. The semiconductor structure of claim 1, wherein, The first dielectric layer comprises silane.

3. The semiconductor structure of claim 1, wherein, The method further comprises:

4. The semiconductor structure of claim 1, wherein, forming a repair layer between the first dielectric layer and the barrier layer. The barrier layer comprises silicon oxynitride.

5. The semiconductor structure of claim 1, wherein, The method further comprises:

6. The semiconductor structure of claim 1, wherein, forming a sidewall on a side of the select gate. The method further comprises:

7. The semiconductor structure of claim 1, wherein, forming a second region adjacent to the first region, the second region being on a side of the select gate, and the second region having a third dielectric layer formed thereon, and the first dielectric layer extending to a surface of the third dielectric layer. The method comprises:

8. A method of forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region; forming a plurality of discrete word line structures on the first region and a select gate on a side of the word line structures; forming a first dielectric layer on the substrate and covering the word line structures and the select gate, the first dielectric layer having air columns formed therein between adjacent word line structures, the air columns having a height higher than a height of the word line structures; forming a barrier layer on a surface of the first dielectric layer; forming a second dielectric layer on a surface of the barrier layer, the barrier layer having a hardness greater than a hardness of the second dielectric layer. The method of forming the second dielectric layer comprises:

9. The method of forming a semiconductor structure of claim 8, wherein, forming an initial second dielectric layer on the surface of the barrier layer using a plasma enhanced process with tetraethoxysilane as a precursor; planarizing the initial second dielectric layer to form the second dielectric layer. The initial second dielectric layer has a thickness ranging from 5100 angstroms to 5500 angstroms.

10. The method of forming a semiconductor structure of claim 9, wherein, The first dielectric layer is formed using a plasma enhanced process with silane as a raw material.

11. The method of forming a semiconductor structure of claim 8, wherein, The substrate further comprises a second region adjacent to the first region, and before forming the first dielectric layer, the method further comprises: forming a third dielectric layer on a surface of the substrate of the second region, and the first dielectric layer extending to a surface of the third dielectric layer.

12. The method of forming a semiconductor structure of claim 8, wherein, Before forming the third dielectric layer, the method further comprises: forming a sacrificial layer on a surface of the substrate between the adjacent word line structures, on a surface of the substrate between the word line structures and the select gate, and on a sidewall of the select gate; forming a fourth dielectric layer on a surface of the sacrificial layer and on the surface of the substrate of the second region; and forming the third dielectric layer on a surface of the fourth dielectric layer.

13. The method of forming a semiconductor structure of claim 12, wherein, ​ 14. The method of forming a semiconductor structure of claim 13, wherein, Before forming the first dielectric layer, further comprising: removing the third dielectric layer, the fourth dielectric layer and the sacrificial layer between the word line structures adjacent to the first region and between the word line structures and the select gate, to expose the surface of the substrate between the word line structures adjacent to the first region and between the word line structures and the select gate.

15. The method of forming a semiconductor structure of claim 12, wherein, The sum of the thickness of the third dielectric layer of the second region, the thickness of the first dielectric layer, the thickness of the blocking layer and the thickness of the second dielectric layer ranges from 4900 angstroms to 5200 angstroms.

16. The method of forming a semiconductor structure of claim 9, wherein, The time range of the planarization process ranges from 33s to 39s.

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