Chip, memory and electronic equipment

Abstract

The invention provides a chip, a memory and electronic equipment, and belongs to the field of storage. The chip comprises a substrate; the memory cells are formed on the substrate, each memory cell comprises a ferroelectric capacitor, and each ferroelectric capacitor comprises a first electrode, a second electrode and a ferroelectric layer; the material of the filling structure has a negative thermal expansion coefficient; the filling structure is arranged on one side of the ferroelectric capacitor. According to the structure, the stress perpendicular to the ferroelectric layer is greatly reduced, formation of a ferroelectric O phase and orientation of a polarization axis in the electric field direction are facilitated, thermal budget can be reduced, damage of high temperature to the ferroelectric layer and an interface is reduced, and ferroelectric performance and thermal stability are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage, in particular to a chip, a memory and an electronic device. BACKGROUND

[0002] The development of the Internet of Things, artificial intelligence and wearable electronic devices has strong demand for low-cost and low-power embedded memories. Ferroelectric random access memory (FeRAM) is a new type of memory that uses the two spontaneous polarization states of ferroelectricity to write and read "0" and "1", and can maintain data even after power failure. Hafnium oxide-based ferroelectric memory is a type of memory made by applying hafnium dioxide-based ferroelectric materials, which has the advantages of low power consumption, high speed, high reliability, etc., and is considered a potential solution for the next generation of non-volatile memory technology.

[0003] The improvement of the ferroelectric performance of hafnium oxide-based materials is mainly achieved by increasing the proportion of ferroelectric phase and optimizing the orientation of the ferroelectric domain axis. In the existing three-dimensional ferroelectric capacitor structure, the stress perpendicular to the ferroelectric layer is large, which is not conducive to the formation of the ferroelectric orthorhombic phase (O phase) and the orientation of the polarization axis, thereby not conducive to the improvement of the ferroelectric performance. SUMMARY

[0004] The present application provides a chip, a memory and an electronic device. By using a specific filling structure to fill in the groove of the ferroelectric capacitor, the stress perpendicular to the ferroelectric layer is greatly reduced, which is conducive to the formation of the ferroelectric O phase and the orientation of the polarization axis along the direction of the electric field.

[0005] In a first aspect, the present application provides a chip, comprising a substrate, and a plurality of memory cells formed on the substrate, the plurality of memory cells comprising a ferroelectric capacitor and a transistor, the ferroelectric capacitor comprising: a first electrode, a second electrode, a ferroelectric layer; a filling structure, the material of the filling structure having a negative thermal expansion coefficient, the filling structure being disposed in the ferroelectric capacitor. It should be noted that the filling structure disposed in the ferroelectric capacitor includes being disposed between the first electrode and the ferroelectric layer, and being disposed between the ferroelectric layer and the second electrode.

[0006] By using a filling structure with a negative thermal expansion coefficient to be disposed in the ferroelectric capacitor, the negative thermal expansion coefficient material can reduce the stress perpendicular to the direction of the ferroelectric layer generated in the process of manufacturing the ferroelectric capacitor, such as the stress perpendicular to the direction of the ferroelectric layer generated in the rapid thermal annealing process or the UV curing process, thereby facilitating the orientation of the polarization axis and better promoting the formation of the ferroelectric O phase, and improving the ferroelectric performance. At the same time, by introducing a filling structure with a negative thermal expansion coefficient into the ferroelectric capacitor, the thermal budget can also be reduced, and the damage of high temperature to the ferroelectric layer can be reduced.

[0007] In a possible implementation of the first aspect of the application, the first electrode, the ferroelectric layer, the second electrode and the filling structure are stacked along a thickness direction of the memory cell to form the ferroelectric capacitor.

[0008] In a possible implementation of the first aspect of the application, one side of the substrate has a recess, the first electrode is arranged to contact an inner surface of the recess, the ferroelectric layer is arranged to contact an inner surface of the first electrode, the second electrode is arranged to contact an inner surface of the ferroelectric layer, and the filling structure is arranged in the ferroelectric capacitor. That is, it can be understood that the first electrode, the ferroelectric layer and the second electrode are arranged in a “recessed” manner in the recess of the substrate.

[0009] In a possible implementation of the first aspect of the application, the filling structure is arranged between the first electrode and the ferroelectric layer.

[0010] In a possible implementation of the first aspect of the application, the filling structure is arranged between the ferroelectric layer and the second electrode.

[0011] It can be understood that when the first electrode, the ferroelectric layer and the second electrode are arranged in a “recessed” manner in the recess of the substrate, the filling structure is also arranged in a “recessed” manner between the first electrode and the ferroelectric layer, or between the ferroelectric layer and the second electrode.

[0012] In a possible implementation of the first aspect of the application, the first electrode and the insulating layer are sequentially stacked to form a stack structure, the stack structure has a recess, the ferroelectric layer is arranged to contact an inner surface of the recess, the second electrode is arranged to contact an inner surface of the ferroelectric layer, and the filling structure is arranged in the ferroelectric capacitor.

[0013] In a possible implementation of the first aspect of the application, the filling structure is arranged between the stack structure and the ferroelectric layer.

[0014] By arranging the filling structure between the stack structure and the ferroelectric layer, the expansion of the filling structure during rapid annealing cooling is conducive to repairing the rough interface formed by etching, improving the electrical contact between the ferroelectric layer and the metal electrode, and further improving the ferroelectric performance.

[0015] In a possible implementation of the first aspect of the application, the filling structure is arranged between the ferroelectric layer and the second electrode.

[0016] In a possible implementation of the first aspect of the application, the filling material has a negative thermal expansion coefficient in the range of -273℃ to 777℃.

[0017] Therefore, the material of the filling structure has a negative thermal expansion coefficient in a very wide temperature range, so that the filling structure can reduce the stress perpendicular to the ferroelectric layer direction generated in the rapid thermal annealing process or the UV curing process in a wide temperature range, and is more conducive to the orientation of the polarization axis and better promotes the formation of the ferroelectric O phase.

[0018] In a possible implementation of the first aspect of the application, the material of the filling structure includes ZrMo2O8, ZrW2O8, HfMo2O8, HfW2O8.

[0019] In a second aspect, the application provides a chip, including a substrate, and a plurality of memory cells formed on the substrate, the plurality of memory cells including a ferroelectric capacitor and a transistor, the ferroelectric capacitor including: a first electrode, a second electrode, a ferroelectric layer; a filling structure, the material of the filling structure having a negative thermal expansion coefficient, the filling structure being arranged on a side of the first electrode away from the ferroelectric layer, and / or a side of the second electrode away from the ferroelectric layer.

[0020] It should be noted that the filling structure can be arranged on a side of the first electrode away from the ferroelectric layer, or a side of the second electrode away from the ferroelectric layer, or both sides of the first electrode and the second electrode away from the ferroelectric layer. By using the filling structure with a negative thermal expansion coefficient, the negative thermal expansion coefficient material can reduce the stress perpendicular to the ferroelectric layer direction generated in the process of manufacturing the ferroelectric capacitor, such as the stress perpendicular to the ferroelectric layer direction generated in the rapid thermal annealing process or the UV curing process, thereby facilitating the orientation of the polarization axis and better promoting the formation of the ferroelectric O phase, and improving the ferroelectric performance. At the same time, by introducing the filling structure with a negative thermal expansion coefficient into the ferroelectric capacitor, the thermal budget can also be reduced, and the damage of the ferroelectric layer caused by high temperature can be reduced. In addition, the filling structure with a negative thermal expansion coefficient partially replaces the traditional metal electrode material to form on the ferroelectric capacitor structure, and there is no impurity ion diffusion to the ferroelectric layer, further improving the ferroelectric performance and thermal stability.

[0021] In a possible implementation of the second aspect of the application, the first electrode, the ferroelectric layer, the second electrode and the filling structure are stacked along the thickness direction of the memory cell to form the ferroelectric capacitor.

[0022] In a possible implementation of the second aspect of the application, one side of the substrate has a groove, the first electrode is arranged to contact the inner surface of the groove, the ferroelectric layer is arranged to contact the inner surface of the first electrode, the second electrode is arranged to contact the inner surface of the ferroelectric layer, and the filling structure is arranged on a side of the first electrode away from the ferroelectric layer, and / or a side of the second electrode away from the ferroelectric layer.

[0023] In one possible embodiment of the second aspect of this application, the filling structure is disposed in contact with the inner surface of the second electrode.

[0024] By stacking the various components of the capacitor in this way, and setting the filling structure in contact with the inner surface of the second electrode, that is, forming a groove structure on the second electrode of the capacitor, the filling structure with a negative thermal expansion coefficient formed in the groove structure can have a larger contact area with the capacitor, thereby better reducing the stress in the direction perpendicular to the ferroelectric layer, which is more conducive to the formation of the ferroelectric O phase and the orientation of the polarization axis.

[0025] In one possible embodiment of the second aspect of this application, the filling structure is disposed between the substrate and the first electrode.

[0026] By placing the filling structure between the substrate and the first electrode, the expansion of the filling structure during rapid annealing and cooling helps to fill and repair the rough interface formed by etching, improve the electrical contact of the etched interface, and thus further enhance the ferroelectric performance.

[0027] In one possible embodiment of the second aspect of this application, a first electrode and an insulating layer are stacked sequentially to form a stacked structure. The stacked structure has a groove, a ferroelectric layer is disposed in contact with the inner surface of the groove, a second electrode is disposed in contact with the inner surface of the ferroelectric layer, and a filling structure is disposed on the side of the second electrode away from the ferroelectric layer.

[0028] In one possible embodiment of the second aspect of this application, the filling structure is disposed in contact with the inner surface of the second electrode.

[0029] In one possible embodiment of the second aspect of this application, the filler material has a negative coefficient of thermal expansion in the range of -273°C to 777°C.

[0030] In one possible embodiment of the second aspect of this application, the material of the filling structure includes ZrMo2O8, ZrW2O8, HfMo2O8, and HfW2O.

[0031] Thirdly, this application provides a method for fabricating a chip, which includes providing a substrate; forming a first electrode, a ferroelectric layer, a second electrode, and a filling structure on one side of the substrate, wherein the ferroelectric layer is at least partially formed between the first electrode and the second electrode, and the filling structure is formed in the ferroelectric capacitor.

[0032] In one possible implementation of the third aspect, a groove is formed on one side of the substrate; a first electrode is formed on the inner surface of the groove;

[0033] A ferroelectric layer is formed on the inner surface of the first electrode; a second electrode is formed on the inner surface of the ferroelectric layer; and a filling structure is formed between the first electrode and the ferroelectric layer, and / or between the ferroelectric layer and the second electrode.

[0034] In one possible implementation of the third aspect, a first electrode and an insulating layer are stacked sequentially to form a stacked structure; a groove is formed in the stacked structure; a ferroelectric layer is formed on the inner surface of the groove; a second electrode is formed on the inner surface of the ferroelectric layer; and a filling structure is formed between the stacked structure and the ferroelectric layer, and / or between the ferroelectric layer and the second electrode.

[0035] Fourthly, this application provides a method for fabricating a chip, comprising providing a substrate; forming a first electrode, a ferroelectric layer, a second electrode, and a filling structure on one side of the substrate, wherein the ferroelectric layer is at least partially formed between the first electrode and the second electrode, and the filling structure is formed on the side of the first electrode away from the ferroelectric layer, and / or, on the side of the second electrode away from the ferroelectric layer.

[0036] In one possible implementation of the fourth aspect, a groove is formed on one side of the substrate; a first electrode is formed on the inner surface of the groove;

[0037] A ferroelectric layer is formed on the inner surface of the first electrode; a second electrode is formed on the inner surface of the ferroelectric layer; a filling structure is formed on the inner surface of the second electrode and / or between the substrate and the first electrode.

[0038] In one possible implementation of the fourth aspect, a first electrode and an insulating layer are stacked sequentially to form a stacked structure; a groove is formed in the stacked structure; a ferroelectric layer is formed on the inner surface of the groove; a second electrode is formed on the inner surface of the ferroelectric layer; and a filling structure is disposed in contact with the inner surface of the second electrode.

[0039] Fifthly, this application provides a memory, including a controller, and a chip as provided in the first or second aspect of this application, or a chip manufactured according to the chip fabrication method in accordance with the third or fourth aspect of this application.

[0040] In a sixth aspect, this application provides an electronic device, including a circuit board and a memory as provided in aspect five of this application. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of an electronic device provided in an embodiment of this application;

[0042] Figure 2a This is a schematic diagram of the structure of a ferroelectric memory provided in an embodiment of this application;

[0043] Figure 2b This is a circuit structure diagram of a memory cell provided in this application;

[0044] Figure 2c This is a circuit diagram of a memory array provided in this application;

[0045] Figure 3aThis is a schematic diagram of the structure of a ferroelectric capacitor provided in this application;

[0046] Figure 3b This is a schematic diagram of another ferroelectric capacitor provided in this application;

[0047] Figure 3c This is a top view of another ferroelectric capacitor structure provided in this application;

[0048] Figure 3d This is a schematic diagram of another ferroelectric capacitor provided in this application;

[0049] Figure 3e This is a top view of another ferroelectric capacitor structure provided in this application;

[0050] Figure 3f This is a schematic diagram of another ferroelectric capacitor provided in this application;

[0051] Figure 3g This is a top view of another ferroelectric capacitor structure provided in this application;

[0052] Figure 3h This is a schematic diagram of another ferroelectric capacitor provided in this application;

[0053] Figure 3i This is a top view of another ferroelectric capacitor structure provided in this application;

[0054] Figure 4a This is a flowchart of a method for preparing a ferroelectric capacitor provided in this application;

[0055] Figures 4b-4e This is a process diagram of the fabrication of a ferroelectric capacitor provided in this application;

[0056] Figure 5a This is a schematic diagram of another ferroelectric capacitor provided in this application;

[0057] Figure 5b This is a top view of another ferroelectric capacitor structure provided in this application;

[0058] Figure 5c This is a schematic diagram of another ferroelectric capacitor provided in this application;

[0059] Figure 5d This is a top view of another ferroelectric capacitor structure provided in this application;

[0060] Figure 5e This is a schematic diagram of another ferroelectric capacitor provided in this application;

[0061] Figure 5f This is a top view of another ferroelectric capacitor structure provided in this application;

[0062] Figure 6a This is a flowchart of another method for preparing a ferroelectric capacitor provided in this application;

[0063] Figures 6b-6f This is a diagram illustrating the fabrication process of another ferroelectric capacitor provided in this application. Detailed Implementation

[0064] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0065] In the following description, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0066] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0067] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0068] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0069] Exemplary embodiments are described in this application with reference to cross-sectional views and / or plan views and / or equivalent circuit diagrams, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0070] The following is an explanation of the technical terms used in this application.

[0071] Ferroelectric materials are materials that can maintain spontaneous polarization by applying an electric field to align their internal electric dipole moments, even when the externally applied electric field is removed. In other words, ferroelectrics are materials in which the polarization intensity (polarization) value (or electric field) is semi-permanently retained, even after a constant voltage is applied and the voltage is restored to zero volts.

[0072] Ferroelectric layers are thin-film materials exhibiting ferroelectric properties, representing an important class of functional thin-film materials. Like bulk materials, they possess a range of characteristics including dielectric properties, ferroelectric switching effects, piezoelectric effects, pyroelectric effects, electro-optic effects, acousto-optic effects, light refraction effects, and nonlinear optical effects. These effects can be used individually to fabricate different functional devices, or two or more effects can be combined to create multifunctional devices, integrated devices, or sensitive devices.

[0073] The transistors involved in the embodiments of this application can be metal-oxide-semiconductor (MOS) field-effect transistors (hereinafter referred to as MOS transistors). In the embodiments of this application, the control terminal of the transistor can refer to the gate of the transistor. In one possible embodiment, the first terminal of the transistor can refer to the source, and the second terminal can refer to the drain. In another possible embodiment, the first terminal of the transistor can refer to the drain, and the second terminal can refer to the source.

[0074] Figure 1An electronic device 200 is provided for embodiments of this application. This electronic device 200 can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, a financial terminal product, or a communication electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products include in-vehicle navigation systems, in-vehicle high-density digital video discs (DVDs), etc. Financial terminal products include automated teller machines (ATMs), self-service terminals, etc. Communication electronics products include servers, storage devices, radar, base stations, and other communication equipment. The embodiments of this application do not impose any special restrictions on the specific form of the above-mentioned electronic devices.

[0075] Electronic device 200 includes a bus 205, and a system-on-chip (SOC) 210 and a read-only memory (ROM) 220 connected to the bus 205. The SOC 210 can be used to process data, such as processing application data, processing image data, and caching temporary data. The ROM 220 can be used to store non-volatile data, such as audio files and video files. The ROM 220 can be a PROM (programmable read-only memory), an EPROM (erasable programmable read-only memory), flash memory, etc. In addition, electronic device 200 may also include a communication chip 230 and a power management chip 240. The communication chip 230 can be used for protocol stack processing, or for amplifying and filtering analog radio frequency signals, or simultaneously performing the above functions. The power management chip 240 can be used to supply power to other chips.

[0076] In one embodiment, the SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and random access memory (RAM) 213 for caching data. The AP 211, GPU 212, and RAM 213 may be integrated into a single die, or integrated into multiple dies and packaged in a single package structure, such as using 2.5D, 3D packaging, or other advanced packaging technologies. In one embodiment, the AP 211 and GPU 212 are integrated into one die, and the RAM 213 is integrated into another die; these two dies are packaged in a single package structure to achieve faster inter-die data transfer rates and higher data transfer bandwidth.

[0077] Figure 2a This is a schematic diagram of a ferroelectric memory provided in an embodiment of this application. The ferroelectric memory 1 can be as follows: Figure 1 The RAM213 shown is referenced. Figure 2aAs shown, the ferroelectric memory 1 includes a storage array 11 and peripheral circuitry 12. The peripheral circuitry 12 includes one or more of the following circuit structures: a decoder 121, a driver 122, a timing controller 123, a buffer 124, or an input / output driver 125. In one embodiment, the storage array 11 includes multiple storage cells 10 arranged in an array. Each storage cell 10 may include a selection transistor and at least one ferroelectric capacitor. Each storage cell 10 can be used to store one bit or more bits of data. Storage cells 10 may also include signal lines such as word lines (WL) and bit lines (BL). Each storage cell 10 is electrically connected to a corresponding signal line (WL, BL, etc.). By receiving the control level output from one or more of the signal lines such as word lines (WL, BL), bit lines, etc., the storage cell 10 to be read or written in the storage array 11 is selected, thereby changing the polarization direction of the ferroelectric capacitor in the storage cell 10, thus realizing data read / write operations. The decoder 121 is used to decode the address of the storage cell 10. Decoder 121 decodes the received address to determine the memory cell 10 to be accessed. Driver 122 controls the signal line level based on the decoding result generated by decoder 121, thereby enabling access to the specified memory cell 10. Buffer 124 buffers the read data, for example, using FIFO (first-in first-out). Timing controller 123 controls the timing of buffer 124 and controls driver 122 to drive the signal lines in memory array 11. Input / output driver 125 drives transmission signals, such as the received data signal and the data signal to be sent, enabling long-distance transmission of data signals. The storage principle of ferroelectric memory is to change the polarization direction of ferroelectric capacitors through an electric field, thereby storing different amounts of charge to represent different data storage states. Since the polarization direction of ferroelectric capacitors can be maintained after the electric field is removed, ferroelectric memory is a non-volatile memory. The stored data can be retained for a long time without periodic refresh, thus significantly reducing power consumption. The aforementioned memory array 11 can be integrated with one or more circuit structures in the peripheral circuit 12 (i.e., one or more of 121, 122, 123, 124, 125) into a single memory chip.

[0078] Figure 2b The circuit structure diagram of one of the storage cells 10 of FeRAM is given, as follows: Figure 2b The memory cell 10 includes at least two ferroelectric capacitors C and one transistor Tr, for example, Figure 2b Three ferroelectric capacitors are given as an example (e.g.) Figure 2bA memory cell containing ferroelectric capacitors C1, C2, and C3 can be called a 1TnC memory cell. Here, the transistor Tr can be a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0079] In addition, the memory cell 10 also includes word line (WL), bit line (BL), and plate line (PL) signal lines. In this memory cell 10, the first terminal of transistor Tr is electrically connected to the bit line BL, the control terminal of transistor Tr is electrically connected to the word line WL, the second terminal of transistor Tr is electrically connected to the first electrode of ferroelectric capacitor C, and the second electrode of ferroelectric capacitor C is electrically connected to the plate line PL. One of the drain or source terminals of transistor Tr is called the first terminal, and the corresponding other terminal is called the second terminal. The control terminal of transistor Tr is the gate.

[0080] Figure 2b The illustrated memory cell 10 can be used to store multiple bits of data, thereby increasing the storage capacity of each memory cell. In particular, these ferroelectric capacitors C share a single transistor Tr, which further reduces the number of transistors in each memory cell 10, thus increasing storage density.

[0081] The above Figure 2b The storage cells 10 shown can be arranged in an array to form a storage array, wherein each storage cell 10 has the same circuit structure, for example, Figure 2c The illustrated storage array exemplarily includes four storage cells: storage cell 101, storage cell 102, storage cell 103, and storage cell 104. Those skilled in the art can design the arrangement and number of storage cells 10 in the storage array according to the storage capacity requirements of the ferroelectric memory. In one embodiment, the storage array may further include more storage cells 10, and these storage cells 10 may be arranged in mutually perpendicular X, Y, and Z directions to form a three-dimensional storage array.

[0082] This application primarily addresses stress modulation in three-dimensional hafnium oxide-based ferroelectric memory devices. It employs a filling structure with a negative thermal expansion coefficient to replace the metal electrode in filling the grooves of the three-dimensional ferroelectric capacitor, reducing stress perpendicular to the ferroelectric layer. This stress modulation effectively reduces stress perpendicular to the ferroelectric layer, making the stress distribution of the three-dimensional ferroelectric capacitor closer to that in a two-dimensional metal-ferroelectric-metal (MFM) structure, which is beneficial for the polarization axis alignment along the electric field direction. Furthermore, when a material with a negative thermal expansion coefficient is placed at the substrate etching interface, the expansion during rapid annealing and cooling helps fill and repair the rough interface formed by etching, improving the electrical contact of the interface and further enhancing ferroelectric performance.

[0083] Figures 3a-3i This is a schematic diagram of the ferroelectric capacitor provided in this application. The ferroelectric capacitor provided in the embodiments of this application can be applied to... Figure 2a , Figure 2b In the storage cell 10 of the ferroelectric memory, and Figure 2c In the storage array of four storage units: storage unit 101, storage unit 102, storage unit 103, and storage unit 104.

[0084] like Figure 3a The diagram shows a structural schematic of a ferroelectric capacitor 300 provided in this application. Multiple ferroelectric capacitors 300 are formed on one side of a substrate 301. Each ferroelectric capacitor 300 includes a first electrode 302, a ferroelectric layer 303, and a second electrode 304, which are sequentially stacked along the thickness direction of the ferroelectric capacitor to form the ferroelectric capacitor 300. Furthermore, a filling structure 305 is provided on one side of the ferroelectric capacitor. The filling structure 305 can be disposed between the first electrode 302 and the ferroelectric layer 303. Optionally, the filling structure 305 can also be disposed between the substrate 301 and the first electrode 302, or between the ferroelectric layer 303 and the second electrode 304, or on the surface of the second electrode 304 away from the substrate 301. It should be noted that the filling structure 305 can be disposed individually in one of the aforementioned four locations, or in two or three of the aforementioned four locations, or simultaneously in all four locations.

[0085] like Figure 3b The diagram shown is a structural schematic of another possible configuration of the ferroelectric capacitor 300 provided in this application. Figure 3c This is a top view of the ferroelectric capacitor. Figure 3bIt is known that a groove is formed on one side of the substrate 301. The first electrode 302, the ferroelectric layer 303, and the second electrode 304 are stacked in a concave shape in the groove to form a ferroelectric capacitor 300. A filling structure 305 is formed in the groove surrounded by the second electrode 304. Specifically, the first electrode 302 is disposed in contact with the inner surface of the groove, the ferroelectric layer 303 is disposed in contact with the inner surface of the first electrode 302, the second electrode 304 is disposed in contact with the inner surface of the ferroelectric layer 303, and the filling structure 305 is disposed on the side of the first electrode away from the ferroelectric layer and / or the side of the second electrode away from the ferroelectric layer, for example, as shown in the figure. Figure 3b As shown, the filling structure 305 is disposed in contact with the inner surface of the second electrode, that is, disposed in the groove formed by the second electrode. Or as... Figure 3d As shown, the filling structure 305 can also be disposed between the substrate 301 and the first electrode 302, that is, disposed in contact with the outer surface of the first electrode 302. Figure 3e This is the corresponding top view.

[0086] In one possible implementation, the filling structure 305 can also be disposed in the ferroelectric capacitor, for example, as shown in the figure. Figure 3f As shown, it is disposed between the first electrode 302 and the ferroelectric layer 303, that is, in contact with the inner surface of the first electrode 302. Figure 3g This is the corresponding top view. Or, as shown below... Figure 3h As shown, it is disposed between the ferroelectric layer 303 and the second electrode 304, that is, in contact with the inner surface of the second electrode 304. Figure 3i This is the corresponding top view.

[0087] It should be noted that the filling structure 305 can be set in one of the aforementioned four positions, or it can be set in two or three of the aforementioned four positions, or the filling structure 305 can be set in all four positions.

[0088] In one possible implementation, the first electrode 302, the ferroelectric layer 303, and the second electrode 304 have the same geometry, for example, the thickness of the inner surface and the thickness of the bottom are the same.

[0089] In one possible implementation, the first electrode 302 can be titanium nitride (TiN) or other conductive materials. This embodiment does not limit the material of the first electrode 302.

[0090] In one possible implementation, the ferroelectric layer 303 can be hafnium zirconium oxide (HZO), and the ratio of hafnium Hf to zirconium Zr can be any ratio, for example, 1:1. This embodiment does not limit the material of the ferroelectric layer 303.

[0091] In one possible implementation, the second electrode 304 can be TiN or other conductive materials. This application does not limit the material of the second electrode 304.

[0092] In one possible implementation, the filling structure 305 can be ZrMo2O8. This application does not limit the material of the filling structure 305, and it can also be ZrW2O8, HfMo2O8, HfW2O, SiO2, Si, SiGe, SiC, h-BN and Graphite.

[0093] Figure 4a This is a flowchart of a method for preparing a ferroelectric capacitor provided in this application. Figures 4b-4e This is a cross-sectional view illustrating the fabrication process of a ferroelectric capacitor provided in this application. The following is in conjunction with... Figures 4a-4e The preparation method and process of a ferroelectric capacitor provided in the embodiments of this application will be explained.

[0094] S401: As Figure 4b As shown, a stacked structure of substrate 301, photoresist (PR), and hard mask (HM) is provided. Specifically, substrate 301, PR, and HM can be stacked sequentially from bottom to top, and substrate 301 can be a Si substrate.

[0095] S402: As Figure 4c As shown, selective etching is performed on the stacked structure. Specifically, the substrate 301 can be etched into an island shape.

[0096] S403: As Figure 4d As shown, a first electrode 302, a ferroelectric layer 303, and a second electrode 304 are formed.

[0097] In one possible implementation, the first electrode 302, the ferroelectric layer 303, and the second electrode 304 are stacked in a concave shape in the groove. Specifically, the first electrode 302 is stacked in contact with the inner surface of the groove, the ferroelectric layer 303 is stacked in contact with the inner surface of the first electrode 302, and the second electrode 304 is stacked in contact with the inner surface of the ferroelectric layer 303.

[0098] In one possible implementation, the first electrode 302, the ferroelectric layer 303, and the second electrode 304 are deposited using the ALD method. Alternatively, deposition processes such as plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and plasma-enhanced atomic layer deposition (PEALD) can be employed. This application does not limit the deposition process.

[0099] In one possible implementation, the first electrode 302 can be titanium nitride (TiN) or other conductive materials. This embodiment does not limit the material of the first electrode 302.

[0100] In one possible implementation, the ferroelectric layer 303 can be hafnium zirconium oxide (HZO), and the ratio of hafnium Hf to zirconium Zr can be any ratio, for example, 1:1. This embodiment does not limit the material of the ferroelectric layer 303.

[0101] In one possible implementation, the second electrode 304 can be TiN or other conductive materials. This application does not limit the material of the second electrode 304.

[0102] S404: As Figure 4d As shown, a filling structure 305 is formed. That is, the filling structure 305 is disposed on the side of the second electrode 304 away from the ferroelectric layer 303. In one possible implementation, the filling structure 305 can be formed by deposition. The deposition method for the filling structure 305 can be CVD, or PECVD, PVD, ALD, PEALD, etc. This application does not limit the deposition process. In one possible implementation, the material of the filling structure 305 is a material with a negative coefficient of thermal expansion, such as ZrMo2O8. This application does not limit the material of the filling structure 305; it can also be ZrW2O8, HfMo2O8, HfW2O, SiO2, Si, SiGe, SiC, h-BN, or Graphite.

[0103] S405: Crystallize the ferroelectric layer 303. In one possible implementation, the method for crystallizing the ferroelectric layer 303 can be rapid thermal annealing, ultraviolet curing (UV curing), or other methods.

[0104] S406: As Figure 4eAs shown, the top film layer is removed to isolate the device. In one possible implementation, the top film layer is removed by chemical mechanical polishing (CMP), ultimately forming a ferroelectric capacitor and filling structure 305 in the groove of substrate 301.

[0105] It should be noted that, in implementing step S403, in one possible implementation, such as Figure 3d As shown, after etching the substrate 301 and before forming the first electrode 302, a filling structure 305 is formed on the substrate 301, that is, the filling structure 305 is disposed on the side of the first electrode away from the ferroelectric layer 303. Subsequent steps are the same as S403-S406. Optionally, after performing step S403, step S404 can be skipped, and steps S405-S406 can be performed directly, that is, the filling structure 305 is not formed on the second electrode 304. This embodiment will not be described in detail.

[0106] In one possible implementation, such as Figure 3f As shown, after forming the first electrode 302, a filling structure 305 is formed on the first electrode 302, that is, the filling structure 305 is formed between the first electrode 302 and the ferroelectric layer 303, that is, the filling structure 305 is disposed in the ferroelectric capacitor 300. The subsequent steps are the same as S404-S406, that is, the filling structure 305 is also formed on the second electrode. Optionally, the subsequent steps can skip step S404 and directly implement steps S405-S406, that is, the filling structure 305 is not formed on the second electrode 304. This embodiment will not be described in detail.

[0107] In one possible implementation, such as Figure 3h As shown, after forming the ferroelectric layer 303, a filling structure 305 is formed on the ferroelectric layer 303, that is, the filling structure 305 is formed between the ferroelectric layer 303 and the second electrode 304, that is, the filling structure 305 is disposed in the ferroelectric capacitor 300. Subsequent steps can be the same as S404-S406, that is, the filling structure 305 is also formed on the second electrode. Optionally, subsequent steps can also skip step S404 and directly implement steps S405-S406, which will not be described in detail in this embodiment.

[0108] The material of the filling structure 305 is a material with a negative thermal expansion coefficient, such as ZrMo2O8. This application does not limit the material of the filling structure 305, and it can also be ZrW2O8, HfMo2O8, HfW2O, SiO2, Si, SiGe, SiC, h-BN and Graphite.

[0109] It should be noted that the material of the filling structure 305 provided in this application embodiment is a material with a negative thermal expansion coefficient, such as ZrMo2O8. This application does not limit the material of the filling structure 305, and it can also be ZrW2O8, HfMo2O8, or HfW2O.

[0110] It should be further noted that the embodiments of this application do not limit the process steps for setting the location and setting method of forming the filling structure 305.

[0111] As shown in Table 1, this application compares the effects of replacing the metal electrode with a filling structure having a negative thermal expansion coefficient and not using a filling structure having a negative thermal expansion coefficient. Specifically, device 1 is a ferroelectric capacitor without introducing a material with a negative thermal expansion coefficient, and device 2 is a ferroelectric capacitor with a material with a negative thermal expansion coefficient placed between the electrode and the ferroelectric layer. The introduction of the material with a negative thermal expansion coefficient can significantly increase the material's remanent polarization intensity by 2 times, 2Pr.

[0112] Device 2 Pr (pC / cm2) Device 1 (without negative thermal expansion material) 30 Device 2 (with negative thermal expansion material) 40

[0113] Table 1 Performance Comparison of Devices with and without Negative Thermal Expansion Coefficients Table 1 Performance Comparison of Devices with and without Negative Thermal Expansion Coefficients

[0114] In this embodiment, a filling structure with a negative thermal expansion coefficient, such as ZrMo2O8, is used to fill the grooves in the ferroelectric device. This significantly reduces the stress perpendicular to the ferroelectric layer during rapid thermal annealing or UV curing, which is beneficial for the polarization axis distribution along the applied electric field direction and thus more conducive to the formation of the ferroelectric O phase. Introducing a filling structure with a negative thermal expansion coefficient for stress regulation can reduce the thermal budget and minimize damage to the ferroelectric layer and interface during high-temperature annealing. Simultaneously, the grooves are not filled with traditional metal electrode materials, preventing impurity ions from diffusing into the ferroelectric layer, thus improving ferroelectric performance and thermal stability. This provides a new and reliable approach for fabricating high-performance, high-durability ferroelectric memories. Furthermore, when a material with a negative thermal expansion coefficient is placed between the metal electrode and the substrate, the expansion during rapid annealing and cooling helps fill and repair the rough interface formed by etching, improving the electrical contact between the ferroelectric layer and the metal electrode interface, thereby further enhancing ferroelectric performance.

[0115] Figures 5a-5f This application provides a schematic diagram of another ferroelectric capacitor. The ferroelectric capacitor provided in this embodiment can be applied to... Figure 2a , Figure 2b In the storage cell 10 of the ferroelectric memory, and Figure 2c In the storage array of four storage units: storage unit 101, storage unit 102, storage unit 103, and storage unit 104.

[0116] This application provides a three-dimensional columnar ferroelectric memory with stacked stress regulation. A substrate 501, an insulating layer 502, and a first electrode 503 are alternately stacked to form a stacked structure 500. The stacked structure 500 has a groove. A ferroelectric layer 504 is disposed in contact with the inner surface of the groove, and a second electrode 505 is disposed in contact with the inner surface of the ferroelectric layer 504. A filling structure is located on the side of the second electrode 505 away from the ferroelectric layer 504, for example... Figure 5a As shown, the filling structure 506 is disposed in contact with the inner surface of the second electrode, that is, formed in the groove surrounded by the second electrode. Figure 5b This is the corresponding top view.

[0117] In one possible implementation, such as Figure 5c As shown, the filling structure 506 can also be disposed in the ferroelectric capacitor, for example, between the stacked structure 500 and the ferroelectric layer 504, i.e., in contact with at least part of the first electrode. Figure 5d This is the corresponding top view. Or, as shown below... Figure 5e As shown, the filling structure 506 is disposed between the ferroelectric layer 504 and the second electrode 505, that is, in contact with the second electrode 505. Figure 5f This is the corresponding top view.

[0118] In one possible implementation, the filling structure 506 can be set in one of the three positions mentioned above, or in any two of the three positions, or the filling structure 506 can be set in all three positions.

[0119] In one possible implementation, the method for depositing the insulating layer 502 and the first electrode 503 stack can be PVD, or it can be PECVD, PVD, ALD, PEALD and other deposition processes. This application does not limit the deposition process; the stack is etched with high aspect ratio to create openings to obtain grooves, such as columnar grooves.

[0120] In one possible implementation, the first electrode 503 can be tungsten W, or it can be other conductive materials. This embodiment does not limit the material of the first electrode 503.

[0121] In one possible implementation, the ferroelectric layer 504 can be hafnium-zirconium oxide (HZO), with any ratio of Hf to Zr, such as 1:1. The ferroelectric layer 504 can also be other materials. This embodiment does not limit the material of the ferroelectric layer 504.

[0122] In one possible implementation, the second electrode 505 can be a combination of two electrodes, such as... Figure 5aAs shown, the electrode may include a first portion 5051 and a second portion 5052. The first portion 5051 may be TiN or other materials, and the second portion 5052 may be W or other conductive materials. This application does not limit the materials of the first portion 5051 and the second portion 5052. In this embodiment, compared to the case where the second electrode is only W, it is more conducive to the crystallization of the ferroelectric layer.

[0123] In one possible implementation, the filling structure can be ZrMo2O8. It should be noted that this application does not limit the material of the filling structure, and it can also be ZrW2O8, HfMo2O8, or HfW2O.

[0124] Figure 6a This is a flowchart of another method for preparing a ferroelectric capacitor provided in this application. Figures 6b-6f This is a cross-sectional view showing the fabrication process of a ferroelectric capacitor provided in this application. The following is in conjunction with... Figures 6a-6f The preparation method and process of a ferroelectric capacitor provided in the embodiments of this application will be explained.

[0125] S601: As Figure 6b As shown, a substrate 501 is provided, and a stacked structure of an insulating layer 502 and a first electrode 503 is formed on the substrate. In one possible implementation, the stacked structure of the insulating layer 502 and the first electrode 503 can be deposited by PVD, or by deposition processes such as PECVD, PVD, ALD, and PEALD. This application does not limit the deposition process.

[0126] In one possible approach, the insulating layer 502 may be silicon nitride, silicon dioxide, or silicon carbide, or other insulating materials. This application does not limit the material of the insulating layer.

[0127] In one possible approach, the first electrode 503 can be a W electrode or other conductive material. This application does not limit the material of the first electrode 503.

[0128] In one possible approach, the substrate 501 can be a SiO2 substrate, or it can be another material.

[0129] S602: As Figure 6c As shown, grooves are formed in the stacked structure. In one possible implementation, the grooves are obtained by etching to create openings in the stack, such as columnar grooves. Furthermore, a high aspect ratio etching can be selected to create openings in the stack.

[0130] S603: As Figure 6dAs shown, a ferroelectric layer 504 is formed on the inner surface of the groove. In one possible implementation, HZO can be deposited using the ALD method to form the ferroelectric layer 504. Other deposition processes include PECVD, PVD, ALD, and PEALD. This application does not limit the deposition process. Specifically, the Hf:Zr ratio used in the HZO can be 1:1.

[0131] S604: As Figure 6e As shown, the second electrode 505 is disposed in contact with the inner surface of the ferroelectric layer 504. In one possible implementation, the second electrode 505 is deposited using the ALD method. Other deposition processes include PECVD, PVD, ALD, and PEALD; this application does not limit the deposition process. In one possible implementation, the second electrode 505 may include a first portion 5051 and a second portion 5052. The first portion may be a 3nm TiN electrode, and the second portion may be a 3nm W electrode.

[0132] S605: As Figure 6f As shown, a filling structure 506 is formed on the inner surface of the second electrode 505. That is, the filling structure 506 is formed in the groove surrounded by the second electrode 505, which means that the filling structure 506 is disposed on the side of the second electrode 505 away from the ferroelectric layer 504.

[0133] In one possible implementation, the material filling structure 506 can be ZrMo2O8. This application does not limit the material of filling structure 506, and it can also be ZrW2O8, HfMo2O8, or HfW2O.

[0134] In one possible implementation, the method for depositing the filling structure can be CVD, or it can be PECVD, PVD, ALD, PEALD and other deposition processes. This application does not limit the deposition process.

[0135] S606: To crystallize the ferroelectric layer 504. In one possible implementation, the method for crystallizing the ferroelectric layer 504 can be rapid thermal annealing, ultraviolet curing (UV curing), or other methods.

[0136] It should be noted that, in implementing step S603, in one possible implementation, such as Figure 5cAs shown, before forming the ferroelectric layer 504, a filling structure 506 is disposed on the inner surface of the stacked structure, that is, the filling structure 506 is disposed between the inner surface of the stacked structure and the ferroelectric layer 504, that is, the filling structure 506 is disposed in the ferroelectric capacitor. Subsequent steps are the same as S604-S606. Optionally, step S605 can be omitted, and steps S604 and S606 can be performed directly. This embodiment will not be described in detail. The material of the filling structure 506 can be ZrMo2O8. This application does not limit the material of the filling structure 506, and it can also be ZrW2O8, HfMo2O8, or HfW2O.

[0137] In another possible implementation, such as Figure 5e As shown, after forming the ferroelectric layer 504, a filling structure 506 is disposed on the inner surface of the ferroelectric layer 504, that is, the filling structure 506 is disposed between the ferroelectric layer 504 and the second electrode 505, that is, the filling structure 506 is disposed in the ferroelectric capacitor. Subsequent steps are the same as S604-S606. Optionally, subsequent steps may omit step S605 and directly perform steps S604 and S606, which will not be described in detail in this embodiment. The material of the filling structure 506 can be ZrMo2O8. This application does not limit the material of the filling structure 506, and it can also be ZrW2O8, HfMo2O8, or HfW2O.

[0138] This application's implementation example, in a three-dimensional ferroelectric capacitor structure, significantly reduces stress perpendicular to the ferroelectric layer during rapid thermal annealing or UV curing by partially replacing the metal electrodes in the deep trenches with a material having a negative coefficient of thermal expansion. This is beneficial for the polarization axis distribution along the applied electric field direction, and therefore more conducive to the formation of the ferroelectric O phase. Stress regulation through the introduction of a filling structure with a negative coefficient of thermal expansion reduces the thermal budget and minimizes damage to the ferroelectric layer and interface during high-temperature annealing. Simultaneously, the absence of traditional metal electrode material filling the trenches prevents impurity ions from diffusing into the ferroelectric layer, improving ferroelectric performance and thermal stability, and providing a new and reliable approach for fabricating high-performance, high-durability ferroelectric memories. Furthermore, when the material with a negative coefficient of thermal expansion is placed between the ferroelectric layer and the stacked structure, its expansion during rapid annealing helps fill and repair the rough interface formed by etching, improving the electrical contact between the ferroelectric layer and the metal electrode interface, thereby further enhancing ferroelectric performance.

[0139] It is worth mentioning that, due to limitations in process conditions or other factors, there may be some deviations or errors in the actual process, which may cause the "sameness" described above to be not entirely accurate. For example, the "sameness" described above may refer to the sameness that is allowed within the allowable range of error. Of course, "sameness" can also be understood as "substantially the same" or "completely the same". Therefore, as long as the "sameness" relationship described above roughly meets the above conditions, it falls within the protection scope of this application.

[0140] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0141] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized by Comprising: a substrate; a plurality of memory cells formed on one side of the substrate, each of the memory cells comprising a ferroelectric capacitor and a transistor, the ferroelectric capacitor comprising: a first electrode, a second electrode, a ferroelectric layer; a filling structure, a material of the filling structure having a negative thermal expansion coefficient, the filling structure being disposed in the ferroelectric capacitor.

2. The chip according to claim 1, characterized in that, The first electrode, the ferroelectric layer, the second electrode and the filling structure are stacked to form the ferroelectric capacitor.

3. The chip according to claim 1 or 2, characterized in that, One side of the substrate has a recess, the first electrode is disposed in contact with an inner surface of the recess, the ferroelectric layer is disposed in contact with an inner surface of the first electrode, the second electrode is disposed in contact with an inner surface of the ferroelectric layer, and the filling structure is disposed in the ferroelectric capacitor.

4. The chip of claim 3, wherein The filling structure is disposed between the first electrode and the ferroelectric layer.

5. The chip of claim 3, wherein, The filling structure is disposed between the ferroelectric layer and the second electrode.

6. The chip of claim 1, wherein, The first electrode and an insulating layer are sequentially stacked to form a stacked structure, the stacked structure has a recess, the ferroelectric layer is disposed in contact with an inner surface of the recess, the second electrode is disposed in contact with an inner surface of the ferroelectric layer, and the filling structure is disposed in the ferroelectric capacitor.

7. The chip of claim 6, wherein The filling structure is disposed between the stacked structure and the ferroelectric layer.

8. The chip of claim 6, wherein, The filling structure is disposed between the ferroelectric layer and the second electrode.

9. The chip according to any one of claims 1 to 8, characterized in that The material of the filling structure has a negative thermal expansion coefficient in the range of -273℃ to 777℃.

10. The chip according to any one of claims 1 to 9, characterized in that The material of the filling structure comprises at least one of ZrMo2O8, ZrW2O8, HfMo2O8, HfW2O8.

11. A chip, characterized by Comprising: a substrate; a plurality of memory cells formed on one side of the substrate, each of the memory cells comprising a ferroelectric capacitor and a transistor, the ferroelectric capacitor comprising: a first electrode, a second electrode, a ferroelectric layer; a filling structure, a material of the filling structure having a negative thermal expansion coefficient, the filling structure being disposed on a side of the first electrode away from the ferroelectric layer, and / or on a side of the second electrode away from the ferroelectric layer.

12. The chip of claim 11, wherein, The first electrode, the ferroelectric layer, the second electrode and the filling structure are stacked to form the ferroelectric capacitor.

13. The chip according to claim 11 or 12, characterized in that One side of the substrate has a recess, the first electrode is disposed in contact with an inner surface of the recess, the ferroelectric layer is disposed in contact with an inner surface of the first electrode, the second electrode is disposed in contact with an inner surface of the ferroelectric layer, and the filling structure is disposed on a side of the first electrode away from the ferroelectric layer, and / or on a side of the second electrode away from the ferroelectric layer.

14. The chip of claim 13, wherein, The filling structure is disposed in contact with an inner surface of the second electrode.

15. The chip of claim 13, wherein, The filling structure is disposed between the substrate and the first electrode.

16. The chip of claim 11, wherein, The first electrode and an insulating layer are sequentially stacked to form a stacked structure, the stacked structure has a recess, the ferroelectric layer is disposed in contact with an inner surface of the recess, the second electrode is disposed in contact with an inner surface of the ferroelectric layer, and the filling structure is disposed on a side of the second electrode away from the ferroelectric layer.

17. The chip of claim 16, wherein, The filling structure is disposed in contact with an inner surface of the second electrode.

18. The chip according to any of claims 11-17, characterized by The material of the filling structure has a negative thermal expansion coefficient in the range of -273℃ to 777℃.

19. The chip according to any of claims 11-18, characterized by The material of the filling structure comprises at least one of ZrMo2O8, ZrW2O8, HfMo2O8, HfW2O8.

20. A method of fabricating a chip, characterized by, Comprising: providing a substrate; forming a first electrode, a ferroelectric layer, a second electrode, a filling structure on one side of the substrate; the ferroelectric layer is formed at least partially between the first electrode and the second electrode; the filling structure is formed on the side of the first electrode away from the ferroelectric layer, and / or on the side of the second electrode away from the ferroelectric layer.

21. The manufacturing method of claim 20, wherein, forming a recess on one side of the substrate; the first electrode is formed on the inner surface of the recess; the ferroelectric layer is formed on the inner surface of the first electrode; the second electrode is formed on the inner surface of the ferroelectric layer; the filling structure is formed between the first electrode and the ferroelectric layer, and / or between the ferroelectric layer and the second electrode.

22. The manufacturing method of claim 20, wherein, the first electrode and an insulating layer are stacked in sequence to form a stacked structure; forming a recess in the stacked structure; the ferroelectric layer is formed on the inner surface of the recess; the second electrode is formed on the inner surface of the ferroelectric layer; the filling structure is formed between the stacked structure and the ferroelectric layer, and / or between the ferroelectric layer and the second electrode.

23. A method of fabricating a chip, characterized by, Comprising: providing a substrate; forming a first electrode, a ferroelectric layer, a second electrode, a filling structure on one side of the substrate; the ferroelectric layer is formed at least partially between the first electrode and the second electrode; the filling structure is formed on the side of the first electrode away from the ferroelectric layer, and / or on the side of the second electrode away from the ferroelectric layer.

24. The manufacturing method of claim 23, wherein, forming a recess on one side of the substrate; the first electrode is formed on the inner surface of the recess; the ferroelectric layer is formed on the inner surface of the first electrode; the second electrode is formed on the inner surface of the ferroelectric layer; the filling structure is formed on the inner surface of the second electrode, and / or between the substrate and the first electrode.

25. The manufacturing method of claim 23, wherein, the first electrode and an insulating layer are stacked in sequence to form a stacked structure; forming a recess in the stacked structure; the ferroelectric layer is formed on the inner surface of the recess; the second electrode is formed on the inner surface of the ferroelectric layer; the filling structure is formed on the inner surface of the second electrode.

26. A memory, comprising: A chip as claimed in any one of claims 1-19 or obtained by the manufacturing method of any one of claims 20-25, and a controller.

27. An electronic device, comprising: A memory as claimed in claim 26, and a circuit board, wherein the circuit board and the memory are electrically connected.

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