Memory device and manufacturing method thereof
By designing the projection relationship of the memory chips and the connection of conductive sheets on the substrate, the cracking problem caused by the suspension of 3D NAND chips was solved, which improved the yield and storage capacity of storage devices and reduced costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2026-03-10
AI Technical Summary
In existing technologies, the Micro Secure Digital Memory Card uses a ladder-stacking method to stack three-dimensional NAND flash memory, resulting in some chips being suspended and unable to withstand stress, thus cracking and affecting yield.
By stacking memory chips on a substrate, the projection relationship between adjacent chips is designed to avoid the problem of suspended chips, and the contact area is increased and stress concentration is reduced by connecting them with conductive sheets and solder.
This improved the yield rate and storage capacity of storage devices, reduced manufacturing costs, and increased production efficiency and product reliability.
Smart Images
Figure CN121645902A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of storage, in particular to a storage device and a manufacturing method thereof. BACKGROUND
[0002] In the related art, a micro secure digital memory card (MICRO SD) realizes large-capacity storage by a three-dimensional NAND flash memory (3D NAND) in a stepped stacking manner. However, because the circuit layer thickness of the 3D NAND is large, and the stacking manner is stepped, part of the 3D NAND is suspended in the air. When the 3D NAND is ground to below 35 um, the suspended 3D NAND cannot withstand stress and causes a large number of chips to crack, which reduces the yield of the product and makes it impossible to realize mass production. SUMMARY
[0003] In view of this, the present application provides a manufacturing method of a storage device, which is beneficial to reduce the problem of cracking of storage chips caused by excessive stress and improve the yield of the storage device.
[0004] In addition, the present application also provides a storage device.
[0005] The present application provides a manufacturing method of a storage device, comprising the steps of: providing a substrate, the substrate having a thickness direction; stacking a plurality of storage chips on the substrate, defining each adjacent two storage chips as including a proximal storage chip and a distal storage chip, the distance between the proximal storage chip and the substrate being less than the distance between the distal storage chip and the substrate, wherein, along the thickness direction, the projection of the distal storage chip is located within the proximal storage chip, and the projection of the proximal storage chip closest to the substrate is located within the substrate; the distal storage chip is electrically connected to the adjacent proximal storage chip, and the proximal storage chip closest to the substrate is electrically connected to the substrate.
[0006] In some possible implementation manners, the surface of the substrate is provided with a plurality of connection pads, and the manufacturing method further comprises the steps of: providing a copper-nickel alloy layer on the connection pads; providing solder or a copper pillar on the copper-nickel alloy layer; and connecting the proximal storage chip closest to the substrate to the substrate through the solder or the copper pillar.
[0007] In some possible implementation manners, the step of sequentially stacking a plurality of storage chips on the substrate comprises: providing a conductive sheet between each adjacent proximal storage chip and distal storage chip, the conductive sheet electrically connecting the proximal storage chip and the distal storage chip.
[0008] In some possible implementation, the number of the memory chips is 16.
[0009] In some possible implementation, the method further comprises the step of: disposing a package on the substrate, the package covering the plurality of memory chips.
[0010] A memory device comprises a substrate and a plurality of memory chips. The substrate has a thickness direction, and the plurality of memory chips are stacked on the substrate. Each two adjacent memory chips comprise a proximal memory chip and a distal memory chip. The distance between the proximal memory chip and the substrate is less than the distance between the distal memory chip and the substrate. In the thickness direction, the projection of the distal memory chip is located within the proximal memory chip. The projection of the proximal memory chip closest to the substrate is located within the substrate. The distal memory chip is electrically connected to the adjacent proximal memory chip. The proximal memory chip closest to the substrate is electrically connected to the substrate.
[0011] In some possible implementation, the memory device further comprises a plurality of conductive sheets. Each two adjacent proximal memory chip and distal memory chip is disposed with a conductive sheet. The thickness of the conductive sheet is 0.5-2 μm. The conductive sheet is electrically connected to the proximal memory chip and the distal memory chip.
[0012] In some possible implementation, the plurality of memory chips have the same shape. The peripheries of the plurality of memory chips are flush.
[0013] In some possible implementation, the plurality of memory chips are divided into two groups of memory chips, and the two groups of memory chips are spaced apart on the substrate.
[0014] In some possible implementation, the memory device further comprises a chip mounting film disposed between the proximal memory chip closest to the substrate and the substrate.
[0015] The memory device provided in the application comprises a substrate and a plurality of memory chips stacked on the substrate. The plurality of memory chips are arranged in a stacking manner, so that the projection of the distal memory chip in each two adjacent memory chips is located within the proximal memory chip. In this way, the problem of suspension between the two adjacent memory chips is avoided, and the contact area between the two adjacent memory chips is increased. The problem of cracking of the memory chip caused by excessive stress is reduced, and the yield of the memory device is improved. In addition, the plurality of memory chips are arranged in a stacking manner, so that the space in the thickness direction of the substrate is effectively utilized, and the storage capacity of the memory device is maximized. BRIEF DESCRIPTION OF DRAWINGS
[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application.
[0018] Figure 2 for Figure 1 The storage device shown is a cross-sectional view along line II-II.
[0019] Figure 3 for Figure 1 The storage device shown is a cross-sectional view along line III-III.
[0020] Figure 4 for Figure 1 A schematic diagram of the conductive sheet of the storage device.
[0021] Figure 5 A cross-sectional view of a storage device provided in another embodiment of this application.
[0022] Figure 6 A cross-sectional view of a storage device provided in yet another embodiment of this application.
[0023] Figure 7 This is a schematic diagram of the structure of a storage device provided in another embodiment of this application.
[0024] Figure 8 A flowchart illustrating the manufacturing method of the storage device provided in this application.
[0025] Explanation of main component symbols
[0026] Storage device 100
[0027] Substrate 10
[0028] Second connecting pad 101
[0029] Memory chip 11
[0030] Near-end memory chip 11a
[0031] Remote storage chip 11b
[0032] 11c memory chipset
[0033] First connecting pad 111
[0034] Controller 12
[0035] Passive Component 13
[0036] Conductive sheet 20
[0037] Main Road 21
[0038] First Bypass 22
[0039] Second bypass 23
[0040] Thickness direction A
[0041] Length direction B Detailed Implementation
[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0043] Please see Figure 1 This application provides a storage device 100 for efficiently and reliably storing and managing data. Specifically, the storage device 100 can be a MICRO SD memory card (Micro Secure Digital Memory Card), a solid-state drive (SSD), a USB flash drive, or a CFexpress card (CompactFlash Express). This embodiment uses a MICRO SD memory card as an example for illustration.
[0044] The storage device 100 comprises a substrate 10, a plurality of storage chips 11, a controller 12 and a passive element 13 disposed on the substrate 10. The plurality of storage chips 11 are electrically connected to the controller 12. The controller 12 and the passive element 13 are electrically connected to the substrate 10 respectively. The substrate 10 is used to provide a basis for physical support and electrical connection, and specifically comprises one of a printed circuit board (PCB), a ceramic substrate and a flexible substrate. The plurality of storage chips 11 are used to store data, and specifically comprise one of a three-dimensional NAND flash memory, a Nor flash memory die and a dynamic random access memory chip. The controller 12 is used to manage and control the read and write operations of data, and specifically comprises one of a SATA controller 12 (Serial Advanced Technology Attachment controller), a PCIe controller 12 (Peripheral Component Interconnect Express controller) and an NVMe controller 12 (Non-Volatile Memory Express controller). The passive element 13 is used to stabilize the performance of the circuit and filter, and specifically comprises at least one of a capacitor, a resistor and an inductor.
[0045] Referring to Figure 2 and Figure 3 , the substrate 10 has a thickness direction A, and the plurality of storage chips 11 are stacked on the substrate 10. Each storage chip 11 is substantially in the shape of a sheet, and each adjacent two storage chips 11 are defined as a proximal storage chip 11a and a distal storage chip 11b. The proximal storage chip 11a is the one of each adjacent two storage chips 11 that is closer to the substrate 10, and the distal storage chip 11b is the one of each adjacent two storage chips 11 that is farther from the substrate 10. The thickness of each storage chip 11 is not more than 35 μm.
[0046] As viewed along the thickness direction A, the projection of the distal storage chip 11b is located within the proximal storage chip 11a, and the projection of the storage chip 11a closest to the substrate 10 is located within the substrate 10. The distal storage chip 11b is electrically connected to the adjacent proximal storage chip 11a, and the proximal storage chip 11a closest to the substrate 10 is electrically connected to the substrate 10. That is, there is no overhanging situation between the two adjacent storage chips 11, and the proximal storage chip 11a and the distal storage chip 11b have the largest contact area, so that there is no overhanging situation between any two adjacent storage chips 11.
[0047] The storage device 100 provided in the present application avoids the problem of suspension between two adjacent storage chips 11 by stacking multiple storage chips 11 on the substrate 10 and arranging the stacking mode of the multiple storage chips 11 such that the projection of the storage chip 11 farther from the substrate 10 is located in the storage chip 11 closer to the substrate 10, thereby increasing the contact area between two adjacent storage chips 11 and reducing the problem of cracking of the storage chip 11 caused by excessive stress, and improving the yield of the storage device 100. In addition, the multiple storage chips 11 are arranged in a stacked mode, thereby effectively utilizing the space in the thickness direction A of the substrate 10 and maximizing the improvement of the storage capacity of the storage device 100.
[0048] Referring to Figure 3 and Figure 4 In the present embodiment, the distal storage chip 11b is also electrically connected to the proximal storage chip 11a that is not adjacent or another distal storage chip 11b that is not adjacent. The storage device 100 further comprises multiple conductive sheets 20, each of which is used to connect the multiple storage chips 11. The conductive sheet 20 comprises a main path 21, a first bypass 22, and multiple second bypasses 23. The first bypass 22 is connected to one end of the main path 21 substantially perpendicularly, and the first bypass 22 is towards one side of the main path 21. The multiple second bypasses 23 are connected to the main path 21 substantially perpendicularly, and the multiple second bypasses 23 are arranged at intervals, and the distance between each adjacent two second bypasses 23 is substantially the same as the thickness of one storage chip 11, so that each second bypass 23 can be connected to one side of the storage chip 11. The first bypass 22 is connected to the substrate 10. In this way, the electrical connection between any two storage chips and the electrical connection between any one storage chip 11 and the substrate 10 are achieved. The distance between each adjacent two second bypasses 23 is less than 35 μm, and the thickness of the first bypass 22 and the second bypass 23 is 0.5 μm-2 μm. The electrical connection between the multiple storage chips 11 and between the multiple storage chips 11 and the substrate 10 is achieved by using the conductive sheet 20, which is conducive to reducing the flying wire welding, thereby reducing the manufacturing cost of the storage device 100 and improving the production efficiency.
[0049] Referring to Figure 2 and Figure 3In the embodiment, the shapes of the plurality of memory chips 11 are substantially the same, and the peripheries of the plurality of memory chips 11 are substantially flush. That is, the plurality of memory chips 11 are stacked to form a cuboid shape, and the memory chips 11 have a length direction B. When viewed along the length direction B, a plurality of first connection pads 111 are arranged at one side of each memory chip 11 with a spacing. When viewed along the thickness direction A, the plurality of first connection pads 111 of two adjacent memory chips 11 are arranged one by one in correspondence, and the side of each memory chip 11 on which the plurality of first connection pads 111 are arranged faces the substrate 10, and the plurality of second bypasses 23 of one conductive sheet 20 are connected to the corresponding plurality of first connection pads 111. The plurality of conductive sheets 20 are arranged with a spacing along the length direction B, so as to realize the connection of each first connection pad 111 of the plurality of stacked memory chips to the substrate 10.
[0050] Referring to Figure 5 In another embodiment, the shapes of the memory chips 11 are different, and the peripheries of the plurality of stacked memory chips 11 are in a stepped shape. Specifically, taking five memory chips as an example, in each of two adjacent memory chips 11, the cross-sectional width of the proximal memory chip 11a is greater than that of the distal memory chip 11b. When viewed along the thickness direction A, the five memory chips 11 are stacked in the middle, so that the five stacked memory chips 11 are substantially in a pagoda shape. Referring to Figure 6 In yet another embodiment, the five memory chips 11 are arranged in alignment at one end, so that the five stacked memory chips 11 are substantially in a flag shape.
[0051] Referring to Figure 7 In another embodiment, the plurality of memory chips 11 are divided into two memory chip groups 11c, and the two memory chip groups 11c are arranged with a spacing on the substrate 10. It can be understood that in other embodiments, the plurality of memory chips 11 can be divided into three or more memory chip groups 11c, and the three or more memory chip groups 11c are arranged with a spacing on the substrate 10 and are electrically connected to the substrate 10 by the conductive sheet 20. Among them, the number of memory chips is 16.
[0052] In the embodiment, a chip mounting film is arranged between each adjacent proximal memory chip 11a and distal memory chip 11b, which is used to reduce stress concentration, increase the mechanical connection strength between the memory chips 11, and provide electrical insulation protection.
[0053] Referring to Figure 1 and Figure 8 An embodiment of the present application further provides a manufacturing method of the storage device 100, comprising the steps of:
[0054] S1, providing a substrate 10, the substrate 10 has a thickness direction A.
[0055] S2, stacking a plurality of memory chips 11 on the substrate 10, defining each adjacent two memory chips 11 including a near-end memory chip 11a and a far-end memory chip 11b, the distance between the near-end memory chip 11a and the substrate 10 is less than the distance between the far-end memory chip 11b and the substrate 10, wherein, along the thickness direction A, the projection of the far-end memory chip 11b is located within the near-end memory chip 11a, and the projection of the near-end memory chip 11a closest to the substrate 10 is located within the substrate 10. The far-end memory chip 11b is electrically connected to the adjacent near-end memory chip 11a, and the near-end memory chip 11a closest to the substrate 10 is electrically connected to the substrate 10.
[0056] In the embodiment, the step S2 specifically includes:
[0057] S21, disposing a conductive sheet 20 between each adjacent near-end memory chip 11a and far-end memory chip 11b, the conductive sheet 20 electrically connecting the near-end memory chip 11a and the far-end memory chip 11b. Wherein, each conductive sheet 20 is used to connect a plurality of memory chips 11. The conductive sheet 20 includes a main path 21, a first bypass 22, and a plurality of second bypasses 23. The first bypass 22 is connected to one end of the main path 21 substantially perpendicularly, and the first bypass 22 is towards one side of the main path 21. The plurality of second bypasses 23 are connected to the main path 21 substantially perpendicularly, and the plurality of second bypasses 23 are arranged at intervals, and the distance between each adjacent two second bypasses 23 is substantially the same as the thickness of one memory chip 11, so that each second bypass 23 can be connected to one side of the memory chip 11. The first bypass 22 is connected to the substrate 10.
[0058] In the embodiment, the surface of the substrate 10 is provided with a plurality of second connection pads 101 (see Figure 3 ), and the manufacturing method further includes the steps of:
[0059] S3, disposing a copper-nickel alloy layer 111a on the second connection pad 101, wherein the copper-nickel alloy layer 101a is used to enhance the corrosion resistance and wear resistance of the second connection pad 101.
[0060] S4, disposing a solder 101b on the copper-nickel alloy layer 101a. Wherein, the solder 101b includes one of Tin-Lead Solder, Lead-Free Solder, and Silver Solder. In other embodiments of the present application, the solder 101b can be replaced by a copper pillar.
[0061] S5, connecting the near-end memory chip 11a closest to the substrate 10 and the solder 101b. Specifically, the first bypass 22 and the second connection pad 101 are connected by reflow soldering. In other embodiments of the present application, the copper pillar and the second connection pad 101 are connected by thermal compression soldering.
[0062] In the present embodiment, the manufacturing method further comprises the steps of:
[0063] S6, disposing a package on the substrate 10, the package covering the plurality of memory chips 11. The package can be a polymer material to provide physical protection and environmental isolation.
[0064] S7, performing functional testing and reliability verification on the storage device 100, specifically including read-write performance testing, electrical characteristic testing, and durability testing, to ensure that each storage device 100 meets design specifications and quality requirements.
[0065] Through the above embodiments, the present application provides a manufacturing method of a storage device 100, effectively improving the structural strength and reliability of the storage device 100, significantly reducing the cracking problem of the memory chip 11 caused by stress concentration, and improving the yield and service life of the product. By reasonably designing the stacking structure of the memory chip 11 and the layout of the conductive sheet 20, the effective connection and electrical performance between each memory chip 11 are ensured, which is suitable for various high-density storage application scenarios, such as high-speed photographic equipment, data center storage devices 100, and mobile device storage expansion.
[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not limiting. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present application.
Claims
1. A manufacturing method of a storage device, characterized by, The method comprises the steps of: providing a substrate, the substrate having a thickness direction; stacking a plurality of memory chips on the substrate, defining each adjacent two memory chips including a near-end memory chip and a far-end memory chip, the distance between the near-end memory chip and the substrate being smaller than the distance between the far-end memory chip and the substrate, wherein, along the thickness direction, the projection of the far-end memory chip is located within the near-end memory chip, and the projection of the near-end memory chip closest to the substrate is located within the substrate; the far-end memory chip is electrically connected to the adjacent near-end memory chip, and the near-end memory chip closest to the substrate is electrically connected to the substrate.
2. The production method according to claim 1, wherein The surface of the substrate is provided with a plurality of connection pads, and the manufacturing method further comprises the steps of: providing a copper-nickel alloy layer on the connection pads; providing solder or a copper pillar on the copper-nickel alloy layer; connecting the near-end memory chip closest to the substrate to the substrate through the solder or the copper pillar.
3. The production method according to claim 1, wherein The step of "stacking a plurality of memory chips on the substrate in sequence" comprises: providing a conductive sheet between each adjacent near-end memory chip and far-end memory chip, the conductive sheet electrically connecting the near-end memory chip and the far-end memory chip.
4. The production method according to claim 3, wherein The number of memory chips is 16.
5. The production method according to claim 1, wherein The method further comprises the step of: providing a package on the substrate, the package covering a plurality of memory chips.
6. A storage device, characterized by The method comprises: a substrate, the substrate having a thickness direction, a plurality of memory chips, the plurality of memory chips being stacked on the substrate, defining each adjacent two memory chips including a near-end memory chip and a far-end memory chip, the distance between the near-end memory chip and the substrate being smaller than the distance between the far-end memory chip and the substrate, along the thickness direction, the projection of the far-end memory chip is located within the near-end memory chip, and the projection of the near-end memory chip closest to the substrate is located within the substrate, the far-end memory chip is electrically connected to the adjacent near-end memory chip, and the near-end memory chip closest to the substrate is electrically connected to the substrate.
7. The storage device of claim 6, wherein, The method further comprises a plurality of conductive sheets, one conductive sheet being provided between each adjacent near-end memory chip and far-end memory chip, the thickness of the conductive sheet being 0.5 μm to 2 μm, and the conductive sheet electrically connecting the near-end memory chip and the far-end memory chip.
8. The storage device of claim 6, wherein, The plurality of memory chips are identical in shape, and the peripheries of the plurality of memory chips are flush.
9. The storage device of claim 6, wherein, The plurality of memory chips are divided into two memory chip groups, and the two memory chip groups are spaced apart on the substrate.
10. The storage device of claim 6, wherein, The memory device further comprises a chip mounting film, the chip mounting film being provided between the near-end memory chip closest to the substrate and the substrate.