Package structure

Abstract

The invention provides a packaging structure. The packaging structure comprises a processing module, a storage module and a power regulation module. The processing module includes a processing element having a first side configured to receive power. The power conditioning module is disposed adjacent to the processing module. The power conditioning module includes a first portion and a second portion. The first portion is configured to decouple a first noise from a first power signal and to transmit the first power signal to the first side of the processing element. The second portion is configured to transmit a second power signal to the storage module.

Description

Technical Field

[0001] This disclosure generally relates to a packaging structure. Background Technology

[0002] Currently, electronic components within a package designed to receive power and transmit signals via opposite sides may include decoupling capacitors. The package may further include a fan-out redistribution layer (RDL) connecting the electronic components to solder balls. However, depending on the arrangement of the decoupling capacitors, the power path can be relatively long, undesirably reducing power efficiency and power supply stability. For example, the decoupling capacitors may be mounted outside the fan-out RDL of the package, the electronic components may have active surfaces facing the decoupling capacitors and configured to receive electrical signals, and the power signals may be received by the solder balls and transmitted through the fan-out RDL, bypassing the decoupling capacitors, and then transmitted again through the fan-out RDL, and then through conductive posts to the back side of the electronic components. Summary of the Invention

[0003] In one or more arrangements, a package structure includes a processing module, a storage module, and a power conditioning module. The processing module includes a processing element having a first side configured to receive power. The power conditioning module is disposed adjacent to the processing module. The power conditioning module includes a first portion and a second portion. The first portion is configured to decouple a first power signal from first noise and transmit the first power signal to the first side of the processing element. The second portion is configured to transmit a second power signal to the storage module.

[0004] In one or more arrangements, a package structure includes a processing module, a storage module, and a power regulation module. The processing module includes a processing element and a decoupling element. The processing element has a first side. The decoupling element is configured to decouple a first noise from a first power signal and transmit the first power signal to the first side of the processing element. The storage module is located above the processing module. The power regulation module is disposed adjacent to the processing module and configured to transmit the first signal to the storage module.

[0005] In one or more arrangements, an encapsulation structure includes a processing module and a power conditioning module. The processing module includes a processing element having a first side configured to receive power. The power conditioning module is disposed adjacent to the processing module. The power conditioning module is configured to transmit power signals. The power path is configured to transmit power signals by extending horizontally through the power conditioning module toward the first side of the processing element. Attached Figure Description

[0006] The aspects of this disclosure are better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale, and the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 It is a cross-section of an encapsulation structure arranged according to some of the present disclosure.

[0008] Figure 2 It is a cross-section of an encapsulation structure arranged according to some of the present disclosure.

[0009] Figure 3 It is a cross-section of an encapsulation structure arranged according to some of the present disclosure.

[0010] Figure 4 It is a cross-section of an encapsulation structure arranged according to some of the present disclosure.

[0011] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. This disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0012] Figure 1 This is a cross-section of a package structure 1 arranged according to some of the present disclosure. The package structure 1 may include substrates 110, 130 and 150, encapsulants 120 and 160, a processing module 20, a power conditioning module 30, a storage module 50, connecting elements 71, 72, 73, 75 and 76, and electrical contacts 81 and 83.

[0013] Substrate 110 can support and electrically connect to processing module 20 and power conditioning module 30. Substrate 110 may comprise, for example, a printed circuit board, such as a paper copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber copper foil laminate. Substrate 110 may include interconnect structures, such as multiple conductive traces and / or multiple conductive vias. In some arrangements, substrate 110 comprises a ceramic material, a metal plate, an organic substrate, or a lead frame. In some arrangements, substrate 110 may comprise a coreless substrate. In some arrangements, substrate 110 may comprise two substrates, including a core layer and conductive material and / or structures disposed on the upper and bottom surfaces of substrate 110. The conductive material and / or structures may comprise multiple conductive traces. In some arrangements, substrate 110 includes a dielectric layer 110d, a conductive layer 110r (also referred to as a "circuit layer" or "fan-out redistribution layer (RDL)"), and conductive pads 110c1 and 110c2, as well as a conductive via 110v electrically connecting the conductive pads 110c1 and 110c2 to the conductive layer 110r. The conductive pads 110c1 and 110c2, the conductive layer 110r, and the conductive via 110v may contain conductive materials such as metals or metal alloys. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof. Substrate 110 may be referred to as a redistribution layer (RDL).

[0014] Processing module 20 may be disposed above and electrically connected to substrate 110. In some arrangements, processing module 20 includes processing element 210, one or more decoupling elements 220, and at least one integrated element 230. Decoupling elements 220 and integrated element 230 may be disposed above processing element 210. Processing element 210 may have surface 2101 and surface 2102 opposite to surface 2101. Surface 2101 may be an active surface, and surface 2102 may be a back-side surface or a passive surface. In some arrangements, surface 2102 of processing module 20 (also referred to as the “first side”) is configured to receive an electrical signal (also referred to as the “first electrical signal”). Surface 2012 may be configured to receive power (e.g., a power signal). In some arrangements, surface 2101 (or active surface) of processing module 20 is configured to receive an electrical signal different from the electrical signal received by surface 2102 (also referred to as the “second electrical signal”).

[0015] In some arrangements, processing element 210 has a surface (e.g., surface 2102) configured to receive power (e.g., electrical signals). Processing element 210 may be a processing chiplet. In some arrangements, processing element 210 includes a CPU chiplet, MCU chiplet, GPU chiplet, ASIC chiplet, or the like. In some arrangements, processing element 210 includes conductive pads 210a and 210b, and processing element 210 is electrically connected to substrate 110 via conductive pad 210b, connection element 71, and conductive pad 110c2. Protective element 71u may further encapsulate conductive pad 210b, connection element 71, and conductive pad 110c2. Protective element 71u may be or include an underfill. The underfill may include an epoxy resin with filler, a molding compound (e.g., epoxy molding compound or other molding compound), polyimide (PI), a phenolic compound or material, a polymeric material in which silicone is dispersed, or a combination thereof. The connecting element 71 may include conductive bumps, which may be or may include Ag, Al, Cu, another metal, solder alloy, or a combination thereof.

[0016] In some arrangements, decoupling element 220 is configured to decouple noise from electrical signals. Decoupling element 220 and power conditioning module 30 may be configured to decouple noise of different frequencies. Decoupling element 220 may be configured to decouple noise from power signals. In some arrangements, decoupling element 220 is configured to decouple noise from power signals and transmit power signals to processing element 210. Decoupling element 220 may include decoupling capacitors. Decoupling element 220 may be referred to as a decoupling element. In some arrangements, decoupling element 220 is or includes a power distribution network (PDN) element. In some arrangements, decoupling element 220 includes conductive structure 220c (also referred to as a "circuit layer"), conductive pads 220a and 220b, and conductive vias 220v1 and 220v2. In some arrangements, conductive structure 220c includes portions 220c1 and 220c2. Section 220c1 may further include multiple capacitor structures 220t, such as deep trench capacitors (DTC). In some arrangements, the density distribution of capacitor structures 220t in section 220c1 is greater than that in section 220c2. In some arrangements, section 220c1 is configured to decouple noise from the power signal and transmit the power signal to the processing element 210. In some arrangements, a conductive via 220v1 is connected to section 220c1 and configured to transmit the power signal. In some arrangements, section 220c2 is configured to provide electrical communication between the processing element 210 and the storage module 50. In some arrangements, section 220c2 is configured to transmit an electrical signal (e.g., a command signal) from the processing element 210 to control access to the storage module 50. In some arrangements, a conductive via 220v2 is connected to section 220c2 and configured to transmit an electrical signal from the processing element 210 to control access to the storage module 50. Part 220c1 may be referred to as the decoupling section, and part 220c2 may be referred to as the signal transmission section. In some arrangements, the width of the conductive via 220v1 is greater than the width of the conductive via 220v2. In some arrangements, the decoupling element 220 is electrically connected to the processing element 210 via conductive pad 220b, connecting element 72, and conductive pad 210a. The processing element 210 may be configured to access the storage module 50 through the conductive via 220v2 and part 220c2. In some arrangements, the processing element 210 is configured to transmit an electrical signal (e.g., a command signal) through a path P5B passing through the conductive via 220v2 and part 220c2 to control access to the storage module 50. The protective element 72u may further encapsulate the conductive pad 220b, connecting element 72, and conductive pad 210a. The protective element 72u may be or include an underfill. The connecting element 72 may include conductive bumps, which may be or may include Ag, Al, Cu, another metal, solder alloy, or a combination thereof.

[0017] In some arrangements, integrated element 230 includes memory cells and active components. For example, integrated element 230 includes cache cells and analog circuitry. Integrated element 230 may be a chiplet. In some arrangements, the wafer node of processing element 210 is smaller than the wafer node of integrated element 230. In some arrangements, processing element 210 includes a set of transistors, integrated element 230 includes a set of transistors, and the gate length of each set of transistors in processing element 210 is smaller than the gate length of each set of transistors in integrated element 230. In some arrangements, the wafer node of processing element 210 may be approximately 2nm or 3nm, and the wafer node of integrated element 230 may be approximately 7nm or 9nm. In some arrangements, the manufacturing process of processing element 210 is more advanced than the manufacturing process of integrated element 230. In some arrangements, processing element 210 and integrated element 230 are separated from monolithic processing components (e.g., CPU components, MCU components, GPU components, ASIC components). In some arrangements, processing element 210 and integrated element 230 together provide full functionality of a standalone processing component or semiconductor chip (e.g., CPU chip, MCU chip, GPU chip, ASIC chip). In some arrangements, integrated element 230 includes conductive pad 230b, and integrated element 230 is electrically connected to decoupling element 220 via conductive pad 230b, connection element 73, and conductive pad 220a. Protective element 73u may further encapsulate conductive pad 230b, connection element 73, and conductive pad 220a. Protective element 73u may be or include underfill. Connection element 73 may include conductive bumps, which may be or include Ag, Al, Cu, another metal, solder alloy, or a combination thereof. As used herein, the term “gate length” refers to the length of the gate along a direction extending between the two source / drain regions or defined by said length. Nanometer (nm) may be a unit of measurement used to measure gate length. As used herein, the term "wafer node" refers to parameters and design rules in a particular semiconductor manufacturing process. For example, a wafer node, as used herein, can be defined by the minimum gate width of a chip. Smaller wafer nodes correspond to smaller feature sizes, which in turn correspond to smaller transistors.

[0018] The power conditioning module 30 may be positioned adjacent to the processing module 20. In some arrangements, the power conditioning module 30 is positioned above and electrically connected to the substrate 110. In some arrangements, the power conditioning module 30 is configured to transmit electrical signals and decouple noise from electrical signals received by electrical contacts 81. The power conditioning module 30 may be configured to transmit power signals and decouple noise from power signals. In some arrangements, the power conditioning module 30 is configured to decouple noise from power signals and transmit power signals to the processing module 20. In some arrangements, the power conditioning module 30 is configured to decouple noise from power signals and transmit power signals to the storage module 50. The power conditioning module 30 may be referred to as an integrated module that includes signal transmission and decoupling functions.

[0019] In some arrangements, the power conditioning module 30 includes a first portion (also referred to as a "decoupling portion") configured to decouple noise from the power signal and transmit the power signal to the back surface (e.g., surface 2102) of the processing element 210. In some arrangements, the power conditioning module 30 further includes a second portion (also referred to as a "signal transmission portion") configured to transmit the power signal to the storage module 50. In some arrangements, the first portion is positioned closer to the processing element 210 than the second portion. In some arrangements, the power conditioning module 30 further includes a third portion (also referred to as a "memory access control portion") configured to provide electrical communication between the processing element 210 and the storage module 50. In some arrangements, the third portion is configured to transmit an electrical signal from the processing element 210 to the storage module 50. In some arrangements, the third portion is configured to transmit an electrical signal from the processing element 210 to control access to the storage module 50. The electrical signal may be a command signal configured to control access to the storage module 50. In some arrangements, the first part is positioned closer to the processing element 210 than the third part.

[0020] In some arrangements, the power conditioning module 30 includes decoupling elements and conductive elements (also referred to as "connection elements"). The decoupling elements can be configured to decouple noise from electrical signals (or power signals). The conductive elements can be configured to transmit electrical signals (or power signals). The electrical signals can be power signals transmitted to processing module 20, power signals transmitted to storage module 50, or a combination thereof. The decoupling elements can be electrically coupled to the conductive elements such that noise signals can bypass the decoupling elements while the power signals continue to propagate along the conductive elements.

[0021] In some arrangements, the power conditioning module 30 includes a substrate 30s, dielectric layers 30d1 and 30d2 on opposite surfaces of the substrate 30s, conductive structures 30c1 and 30c2 (also referred to as "replacement layers (RDL)" or "circuit layers"), conductive vias 30v1 and 30v2 (also referred to as "conductive vias"), and conductive pads 30a and 30b. In some arrangements, conductive structures 30c1 and 30c2 are located in dielectric layers 30d1 and 30d2, respectively, and conductive vias 30v1 and 30v2 penetrate the substrate 30s and are electrically connected to conductive structures 30c1 and 30c2. In some arrangements, conductive pads 30a and 30b are electrically connected to conductive structures 30c1 and 30c2, respectively. In some arrangements, conductive vias 30v1 and 30v2 may be or contain conductive elements configured to transmit electrical signals. In some arrangements, conductive structures 30c1 and 30c2 include decoupling elements configured to decouple noise from electrical signals. In some arrangements, the power conditioning module 30 is electrically connected to the substrate 110 via conductive pad 30b, connection element 76, and conductive pad 110c2. Connection element 76 may include conductive bumps, which may be or may include Ag, Al, Cu, another metal, solder alloy, or a combination thereof.

[0022] In some arrangements, the conductive structure 30c1 includes portions 30c11, 30c12, and 30c13. Portion 30c11 may further include multiple capacitor structures 30t, such as deep trench capacitors (DTC). In some arrangements, the density distribution of capacitor structures 30t in the region closer to the processing element 210 (e.g., portion 30c11) is greater than the density distribution of capacitor structures 30t in the region farther from the processing element 210 (e.g., portion 30c12). In some arrangements, the density distribution of capacitor structures 30t in the region closer to the processing element 210 (e.g., portion 30c11) is greater than the density distribution of capacitor structures 30t in the region farther from the processing element 210 (e.g., portion 30c13). Portion 30c11 may be referred to as a first portion or decoupling portion, portion 30c12 may be referred to as a second portion or signal transmission portion, and portion 30c13 may be referred to as a third portion of the memory access control portion. In some arrangements, conductive via 30v1 is configured to transmit a power signal to processing element 210 and / or storage module 50, and conductive via 30v2 is electrically connected to portion 30c13. In some arrangements, the width of conductive via 30v1 is greater than the width of conductive via 30v2. In some arrangements, portion 30c11 is configured to decouple noise from the power signal and transmit the power signal to processing element 210. In some arrangements, the power signal may be further decoupled by decoupling element 220 before being transmitted to processing element 210. Portion 30c11 and decoupling element 220 may decouple noise of different frequencies from the power signal received by electrical contact 81 and transmitted to processing element 210. In some arrangements, portion 30c12 is configured to transmit a power signal to storage module 50. In some arrangements, portion 30c12 is configured to decouple noise from the power signal and transmit the power signal to storage module 50. Processing element 210 may be configured to access storage module 50 through conductive via 30v2 and portion 30c13. In some arrangements, processing element 210 is configured to transmit electrical signals (e.g., command signals) through path P5A through substrate 110 (or fan-out RDL), conductive via 30v2, and portion 30c13 to control access to storage module 50.

[0023] Encapsulation 120 may encapsulate processing module 20 and power conditioning module 30. In some arrangements, encapsulation 120 connects substrates 110 and 130. Encapsulation 120 may be or contain epoxy resin with filler, molding compound (e.g., epoxy molding compound or other molding compound), PI, phenolic compound or material, polymer material in which silicone is dispersed, or a combination thereof.

[0024] Substrate 130 is electrically connected to and above processing module 20 and power conditioning module 30. In some arrangements, substrate 130 includes a dielectric layer 130d, conductive pads 130c1 and 130c2, one or more conductive layers (or circuit layers or RDL), and a conductive via 130v electrically connecting conductive pads 130c1 and 130c2 to the conductive layers and conductive vias. In some arrangements, conductive pad 130c2 is electrically connected to conductive pads 220a and 30a. Conductive pads 130c1 and 130c2, conductive layers, and conductive vias may contain conductive materials such as metals or metal alloys. Examples include Au, Ag, Al, Cu, or alloys thereof. Substrate 130 may be referred to as RDL.

[0025] Substrate 150 may be electrically connected to and over substrate 130. In some arrangements, substrate 150 includes a dielectric layer 150d, conductive pads 150c1 and 150c2, one or more conductive layers (or circuit layers or RDLs), and conductive vias (not shown) electrically connecting conductive pads 150c1 and 150c2 to the conductive layers and conductive vias. In some arrangements, substrate 150 is electrically connected to substrate 130 via conductive pads 150c1, electrical contacts 83, and conductive pads 130c2. Conductive pads 150c1 and 150c2, the conductive layers, and the conductive vias may comprise conductive materials such as metals or metal alloys. Examples include Au, Ag, Al, Cu, or alloys thereof. Substrate 130 may be referred to as an RDL. Electrical contacts 83 may comprise solder balls or solder bumps.

[0026] Storage module 50 may be disposed above processing module 20. In some arrangements, storage module 50 is disposed above and electrically connected to substrate 150. In some arrangements, storage module 50 includes a plurality of memory dies and logic dies (e.g., dies 510, 520, and 530) stacked on top of each other and electrically connected to each other via connection element 75. One or more of the dies may include conductive vias 50v electrically connected to connection element 75. Conductive vias 50v may penetrate opposite surfaces of the dies. In some arrangements, conductive pad 530b of die 530 is electrically connected to conductive pad 520a of die 520 via connection element 75. In some arrangements, conductive pad 520b of die 520 is electrically connected to conductive pad 510a of die 310 via connection element 75. Connection element 75 may include conductive bumps, which may be or may include Ag, Al, Cu, another metal, solder alloy, or a combination thereof. In some arrangements, the conductive pad 510b of die 510 is electrically connected to the conductive pad 150c1 of substrate 150 via connection element 75. The die may contain memory components or memory elements (e.g., dies 520 and 530) and optionally include logic dies (e.g., die 510). The logic die may be configured to generate control signals to access the memory die in response to command signals sent by processing element 210. Storage module 50 may be or include high-bandwidth memory (HBM).

[0027] Encapsulation 160 may be disposed over substrate 150 and encapsulate storage module 50. Encapsulation 160 may be or contain epoxy resin with filler, molding compound (e.g., epoxy molding compound or other molding compound), PI, phenolic compound or material, polymer material wherein silicone is dispersed, or a combination thereof.

[0028] Electrical contacts 81 may be located beneath substrate 110. In some arrangements, electrical contacts 81 are electrically connected to substrate 110. Electrical contacts 81 may include solder balls. Electrical contacts 81 may be or include controlled collapse chip interconnect (C4) bumps, ball grid array (BGA), or connection disk grid array (LGA).

[0029] The encapsulation structure 1 may include a path P1A configured to provide an electrical signal to the processing module 20 and a path P2A configured to provide an electrical signal to the storage module 50. In some arrangements, path P1A is configured to decouple noise from the electrical signal and transmit the electrical signal to the processing module 20, and path P2A is configured to decouple noise from the electrical signal and transmit the electrical signal to the storage module 50. In some arrangements, path P1A is configured to provide power (e.g., a power signal) to the processing module 20, and path P2A is configured to provide power (e.g., a power signal) to the storage module 50.

[0030] In some arrangements, path P1A is configured to transmit a power signal to processing module 20. Path P1A may pass through a portion 30c11 of the conductive structure 30c1 of power conditioning module 30 and is configured to transmit the power signal. In some arrangements, path P1A includes a vertical segment configured to transmit the power signal toward power conditioning module 30. In some arrangements, path P1A passes vertically through power conditioning module 30 and then extends horizontally toward surface 2102 (or back side) of processing module 20. As the initial power signal passes through power conditioning module 30, some noise signals bypass the decoupling elements of power conditioning module 30 while the power signal continues to be transmitted along path P1A and by the conductive elements of power conditioning module 30, such that these noise signals are decoupled from the transmitted power signal. After the noise signals are decoupled by power conditioning module 30, the power signal may subsequently be transmitted horizontally along path P1A toward surface 2102 (or back side) of processing module 20 by the conductive layer (not shown) of substrate 130.

[0031] In some arrangements, path P1A may further include another vertical segment configured to transmit power signals through decoupling element 220 and toward processing element 210. Noise signals (e.g., noise signals having a different frequency than those that bypass power conditioning module 30) may bypass the decoupling capacitor of decoupling element 220, which allows these noise signals to be further decoupled from the transmitted power signals transmitted to processing element 210.

[0032] In some arrangements, path P2A is configured to transmit a power signal to storage module 50. Path P2A may pass through a portion 30c12 of the conductive structure 30c1 of power conditioning module 30 and is configured to transmit a power signal. In some arrangements, path P2A includes a vertical segment configured to transmit a power signal toward power conditioning module 30. In some arrangements, path P2A passes vertically through power conditioning module 30 and is configured to transmit a power signal to storage module 50. As the initial power signal passes through power conditioning module 30, some noise signals bypass the decoupling elements (e.g., portion 30c12) of power conditioning module 30, while the power signal continues to propagate along path P2A and is transmitted by conductive elements (e.g., conductive via 30v1) of power conditioning module 30, such that these noise signals are decoupled from the transmitted power signal. After the noise signals are decoupled by power conditioning module 30, the power signal may subsequently be transmitted vertically along path P2A toward storage module 50 by electrical contact 83. In some arrangements, path P2A further passes through a portion of substrate 130 and a portion of substrate 150.

[0033] Currently, the package structure may include a lower substrate (or lower fan-out RDL), a processing component disposed above the lower substrate with an active surface facing the lower substrate, a decoupling capacitor disposed below the lower substrate for decoupling noise from the power signal transmitted to the processing component, an upper substrate (or upper fan-out RDL) above the back surface of the processing component, and conductive pillars adjacent to the processing component and electrically connecting the lower substrate to the upper substrate. The power signal is transmitted along a path that passes through a portion of the lower substrate for noise bypassing the decoupling capacitor, through the conductive pillars to transmit the decoupled power signal to the upper substrate, and then through a portion of the upper substrate to reach the back surface of the processing component. With this design, the power path is relatively long, and therefore the power loss is relatively high.

[0034] According to some arrangements of this disclosure, both the processing module 20 and the power conditioning module 30, configured to transmit and decouple the power signals transmitted to the processing module 20, are disposed above the substrate 110 and encapsulated by the encapsulant 120. Power paths (e.g., paths P1A, P1B, P1C, P1D, and P1E) do not pass through the substrate 110 and instead pass vertically along the lateral side of the processing module 20 to provide the decoupled power signals to the back side (e.g., surface 2102) of the processing module 20. Therefore, the power paths are relatively short, resulting in relatively low power loss or consumption and thus improved power efficiency.

[0035] Furthermore, according to some arrangements of this disclosure, the power conditioning module 30 is positioned relatively close to the processing module 20 or the processing element 210. Therefore, the path length or wiring length between the decoupling element and the processing element 210 is relatively short, resistance can be reduced, power transmission losses can be reduced, and the number or quantity of decoupling capacitors in the power conditioning module 30 can be reduced. This, in turn, reduces the size of the power conditioning module 30 and increases the stability of the power supply (especially for high power applications).

[0036] Furthermore, according to some arrangements of this disclosure, the power conditioning module 30 integrates decoupling elements for decoupling power signals and conductive elements for transmitting power signals. Therefore, the size of the power conditioning module 30 is relatively small compared to the total size of the decoupling capacitors and conductive posts, each independently housed in the package structure. Consequently, the size of the package structure 1 is further reduced.

[0037] Furthermore, according to some arrangements of this disclosure, the processing element 210 and the integrated element 230 have different nodes. Therefore, the integrated element 230 can be manufactured using a less advanced manufacturing process than that used for the processing element 210, and thus the processing element 210 and the integrated element 230 can be manufactured independently and then assembled into the processing module 20. Therefore, the manufacturing process of the processing module 20 and the packaging structure 1 becomes more flexible, and production volume can also be increased.

[0038] Figure 2 This is a cross-section of the packaging structure 2 according to some arrangements of this disclosure. The packaging structure 2 is similar to... Figure 1 The encapsulation structure 1 in the text is described below, and the differences between them are described below.

[0039] The package structure 2 may further include a connecting element 74 and a conductive post 120P.

[0040] In some arrangements, processing module 20 further includes power management element 240. In some arrangements, decoupling element 220, integrated element 230, and power management element 240 are stacked above and electrically connected to processing element 210. In some arrangements, decoupling element 220, integrated element 230, and power management element 240 are stacked above and electrically connected to surface 2102 (or back side) of processing element 210.

[0041] In some arrangements, processing element 210 includes conductive vias 210v1, 210v2, 210v3, and 210v4. In some arrangements, conductive vias 210v1 and 210v2 are configured to transmit one or more electrical signals (e.g., power signals) to power conditioning module 30. In some arrangements, conductive vias 210v3 and 210v4 are configured to transmit one or more electrical signals (e.g., power signals) to power management element 240.

[0042] In some arrangements, power management element 240 is configured to manage power signals to be supplied to or transmitted to processing module 20 and storage module 50. Power management element 240 may be or include a power management IC (PMIC). In some arrangements, power management element 240 includes conductive pads 240a and 240b. In some arrangements, power management element 240 is electrically connected to processing element 210 via conductive pad 240b, connection element 74, and conductive pad 210a, and power management element 240 is electrically connected to substrate 130 via conductive pads 240a and 130b. Connection element 74 may include conductive bumps, which may be or include Ag, Al, Cu, another metal, solder alloy, or a combination thereof.

[0043] In some arrangements, the power conditioning module 30 is stacked above and electrically connected to the processing element 210. In some arrangements, the power conditioning module 30 is stacked above and electrically connected to the surface 2102 (or back side) of the processing element 210. In some arrangements, the power conditioning module 30 is closer to the surface 2102 (or back side) of the processing module 20 than to the surface 2101 (or active surface). In some arrangements, the power conditioning module 30 is electrically connected to the processing element 210 via a conductive pad 30b, a connecting element 76, and a conductive pad 210a.

[0044] In some arrangements, the storage module 50 is positioned above the processing module 20, and the power regulation module 30 is located between the storage module 50 and the processing element 210.

[0045] In some arrangements, the conductive post 120P is encapsulated by encapsulant 120. In some arrangements, the substrate 110 is electrically connected to the substrate 130 via the conductive post 120P. The conductive post 120P may comprise a conductive material such as a metal or metal alloy. Examples include Au, Ag, Al, Cu, or alloys thereof.

[0046] The encapsulation structure 2 may include paths P1B, P1C, and P1D configured to provide electrical signals to the processing module 20, and paths P2B and P2C configured to provide electrical signals to the storage module 50. In some arrangements, paths P1B, P1C, and P1D are configured to decouple noise from the electrical signals and transmit the electrical signals to the processing module 20, and paths P2B and P2C are configured to decouple noise from the electrical signals and transmit the electrical signals to the storage module 50. In some arrangements, paths P1B, P1C, and P1D are configured to provide power (e.g., power signals) to the processing module 20, and paths P2B and P2C are configured to provide power (e.g., power signals) to the storage module 50.

[0047] In some arrangements, path P1B is configured to transmit a power signal to processing module 20. Path P1B may pass through power conditioning module 30 and is configured to transmit a power signal. In some arrangements, path P1B includes a vertical segment configured to transmit a power signal toward power conditioning module 30. In some arrangements, path P1B vertically passes through conductive via 210v2 of processing element 210 of processing module 20 and conductive via 30v1 of power conditioning module 30. When the initial power signal passes through conductive via 210v2 of processing element 210 and then through a portion 30c11 of conductive structure 30c of power conditioning module 30, some noise signals bypass the decoupling element of power conditioning module 30 while the power signal continues to propagate along path P1B and is transmitted by conductive element of power conditioning module 30, thus decoupling these noise signals from the transmitted power signal. After the noise signal is decoupled by the power conditioning module 30, the power signal can then be transmitted vertically along the path P1B from the conductive via 30v1 of the power conditioning module 30 toward the surface 2102 (or back side) of the processing element 210 of the processing module 20.

[0048] In some arrangements, path P1C is configured to transmit a power signal to processing module 20. Path P1C may be electrically coupled to power conditioning module 30 and configured to transmit a power signal. In some arrangements, path P1C includes a vertical segment configured to transmit a power signal through conductive post 120P. In some arrangements, path P1C passes vertically through conductive post 120P. As the initial power signal passes through conductive post 120P and then through the substrate 130 electrically coupled to power conditioning module 30, some noise signals bypass the decoupling elements (e.g., portion 30c11) of power conditioning module 30, while the power signal continues to propagate along path P1C and is transmitted by the conductive elements of power conditioning module 30, such that these noise signals are decoupled from the transmitted power signal. After the noise signals are decoupled by power conditioning module 30, the power signal may subsequently be transmitted vertically along path P1C towards the surface 2102 (or back side) of processing element 210 of processing module 20 via conductive via 30v1 of power conditioning module 30. In some arrangements, the conductive post 120P is encapsulated by encapsulant 120 and configured to transmit electrical signals to the surface 2102 of the processing element 210 along the path P1C through the power conditioning module 30.

[0049] In some arrangements, path P1D is configured to transmit a power signal to processing module 20. Path P1D may pass through conductive via 210v4 of processing element 210, power management element 240, and decoupling element 220, and is configured to transmit the power signal. In some arrangements, path P1D includes a vertical segment configured to transmit the power signal toward power management element 240. When the initial power signal passes through conductive via 210v4 and is subsequently transmitted to power management element 240, the initial power signal may be processed by power management element 240, for example, selecting a power signal from the supplied power signal, adjusting the voltage of the power signal, stabilizing the power signal, or other power management functions. The power signal transmitted from power management element 240 is then transmitted to a portion 220c1 of conductive structure 220c of decoupling element 220, where some noise signals bypass the decoupling element of decoupling element 220 while the power signal continues to propagate along path P1D, thus decoupling these noise signals from the transmitted power signal. After the noise signal is decoupled by the decoupling element 220, the power signal can then be transmitted vertically along the path P1D toward the surface 2102 (or back side) of the processing element 210 of the processing module 20.

[0050] In some arrangements, path P2B is configured to transmit a power signal to storage module 50. Path P2B passes through the conductive via 210v1 of processing element 210 and power conditioning module 30 and is configured to transmit a power signal. In some arrangements, path P2B includes a vertical segment configured to transmit a power signal toward power conditioning module 30. In some arrangements, path P2B passes vertically through conductive via 210v1 and power conditioning module 30 and is configured to transmit a power signal to storage module 50. As the initial power signal passes through power conditioning module 30, some noise signals bypass the decoupling elements of power conditioning module 30 while the power signal continues to propagate along path P2B and is transmitted by the conductive elements of power conditioning module 30, thus decoupling these noise signals from the transmitted power signal. After the noise signals are decoupled by power conditioning module 30, the power signal can then be transmitted vertically along path P2B toward storage module 50 by electrical contact 83.

[0051] In some arrangements, path P2C is configured to transmit a power signal to storage module 50. Path P2C may pass through conductive via 210v3 of processing element 210 and power management element 240, be electrically coupled to power conditioning module 30, and be configured to transmit a power signal to storage module 50. When the initial power signal passes through conductive via 210v3 and is subsequently transmitted to power management element 240, the initial power signal may be processed by power management element 240, for example, selecting a power signal from the supplied power signal, adjusting the voltage of the power signal, stabilizing the power signal, or other power management functions. The power signal transmitted from power management element 240 is then transmitted to a portion of substrate 130 electrically coupled to power conditioning module 30. Some noise signals bypass the decoupling element of power conditioning module 30 while the power signal continues to be transmitted along path P2C and horizontally by a portion of substrate 130, such that these noise signals are decoupled from the transmitted power signal. After the noise signals are decoupled by power conditioning module 30, the power signal may then be transmitted along path P2C toward storage module 50.

[0052] According to some arrangements of this disclosure, the power conditioning module 30 is positioned above the processing element 210, and the power signal decoupled by the power conditioning module 30 can be directly transmitted to the processing element 210 via paths (e.g., paths P1B and P1C) without any horizontal paths, and thus the power path can be further reduced. Therefore, power loss or power consumption is further reduced, and thus power efficiency is significantly improved.

[0053] Furthermore, according to some arrangements of this disclosure, the power path can pass through the conductive post 120P to transmit a relatively high-power power signal for increasing transmission speed, and then through the power conditioning module 30 to decouple noise from the high-power signal. Therefore, the power path is relatively short, which is beneficial for increasing power efficiency and also improves power distribution.

[0054] Furthermore, according to some arrangements of this disclosure, decoupling elements 220 for decoupling noise from the power signal transmitted to the processing module 20 are stacked on top of the processing element 210 and electrically connected to the processing element 210 via connecting elements 72. Therefore, the path length or wiring length between the decoupling capacitors in the decoupling element 220 and the processing element 210 is relatively short, resulting in almost no voltage drop or only a very small voltage drop in the power signal transmitted between the decoupling element 220 and the processing element 210. Thus, the power loss transmitted can be reduced, and the number or quantity of decoupling capacitors in the decoupling element 220 can be reduced, which in turn reduces the size of the decoupling element 220 and increases the stability of the power supply (especially for high power).

[0055] Figure 3 This is a cross-section of the packaging structure 3 according to some arrangements of this disclosure. The packaging structure 3 is similar to... Figure 1 The encapsulation structure 1 in the text is described below, and the differences between them are described below.

[0056] In some arrangements, decoupling element 220 includes conductive vias 220v2, 220v3, and 220v4. In some arrangements, conductive via 220v1 is configured to transmit an electrical signal (e.g., a power signal) to power conditioning module 30. In some arrangements, conductive via 220v2 is configured to transmit an electrical signal (e.g., a command signal) from processing element 210 to control access to storage module 50. In some arrangements, processing element 210 is configured to send an electrical signal (e.g., a command signal) via path P5C through conductive vias 220v2, 30v2, and portion 30c13 to control access to storage module 50. In some arrangements, conductive vias 220v3 and 220v4 are configured to transmit one or more electrical signals (e.g., power signals) to power management element 240.

[0057] In some arrangements, decoupling element 220 is configured to decouple noise from electrical signals (e.g., power signals) and is stacked between processing element 210 and power management element 240. In some arrangements, decoupling element 220 further includes a conductive pad 130c1 electrically connected to substrate 130 for transmitting electrical signals to conductive pillars 220p of substrate 130. In some arrangements, power management element 240 and power conditioning module 30 are stacked above decoupling element 220 and electrically connected to the decoupling element.

[0058] The encapsulation structure 3 may include a path P1E configured to provide an electrical signal to the processing module 20 and paths P2D and P2E configured to provide an electrical signal to the storage module 50. In some arrangements, path P1E is configured to decouple noise from the electrical signal and transmit the electrical signal to the processing module 20, and paths P2D and P2E are configured to decouple noise from the electrical signal and transmit the electrical signal to the storage module 50. In some arrangements, path P1E is configured to provide power (e.g., a power signal) to the processing module 20, and paths P2D and P2E are configured to provide power (e.g., a power signal) to the storage module 50.

[0059] In some arrangements, path P1E is configured to transmit a power signal to processing module 20. Path P1E may pass through conductive vias 220v4 of decoupling element 220, conductive vias 210v4 of processing element 210, power management element 240, and subsequent decoupling element 220, and is configured to transmit the power signal. In some arrangements, path P1E includes a vertical segment configured to transmit the power signal toward power management element 240. As the initial power signal passes through conductive vias 210v4 and 220v4 to power management element 240, the initial power signal may be processed by power management element 240, for example, selecting a power signal from the supplied power signal, adjusting the voltage of the power signal, stabilizing the power signal, or other power management functions. The power signal transmitted from power management element 240 is then transmitted to decoupling element 220, where some noise signals bypass the decoupling element of decoupling element 220 while the power signal continues to propagate along path P1E, thus decoupling these noise signals from the transmitted power signal. After the noise signal is decoupled by the decoupling element 220, the power signal can then be transmitted vertically along the path P1E toward the surface 2102 (or back side) of the processing element 210 of the processing module 20.

[0060] In some arrangements, path P2D is configured to transmit a power signal to storage module 50. Path P2D may pass through conductive via 210v2 of processing element 210, conductive via 2240v2 of decoupling element 220, and power conditioning module 30, and is configured to transmit a power signal. In some arrangements, path P2D includes a vertical segment configured to transmit a power signal toward power conditioning module 30. In some arrangements, path P2D vertically passes through conductive via 210v2, conductive via 220v2, and a portion 30c12 of conductive structure 30c1 of power conditioning module 30, and is configured to transmit a power signal to storage module 50. When the initial power signal passes through power conditioning module 30, some noise signals bypass the decoupling element of power conditioning module 30, while the power signal continues to propagate along path P2D and is transmitted by the conductive element of power conditioning module 30, thus decoupling these noise signals from the transmitted power signal. After the noise signal is decoupled by the power conditioning module 30, the power signal can then be transmitted vertically along the path P2D towards the storage module 50 via the electrical contact 83.

[0061] In some arrangements, path P2E is configured to transmit a power signal to storage module 50. Path P2E may pass through conductive vias 210v3 of processing element 210, conductive vias 220v3 of decoupling element 220, and power management element 240, be electrically coupled to power regulation module 30, and be configured to transmit a power signal to storage module 50. When the initial power signal passes through conductive vias 210v3 and 220v3 and then to power management element 240, the initial power signal can be processed by power management element 240, for example, selecting a power signal from the supplied power signal, adjusting the voltage of the power signal, stabilizing the power signal, or other power management functions. The power signal transmitted from the power management element 240 is then transmitted to a portion of the substrate 130 electrically coupled to the power conditioning module 30. Some noise signals bypass the decoupling elements of the power conditioning module 30 (e.g., portion 30c12 of the conductive structure 30c1), while the power signal continues to propagate along path P2E and horizontally by the portion of the substrate 130, thus decoupling these noise signals from the transmitted power signal. After the noise signals are decoupled by the power conditioning module 30, the power signal can then be transmitted along path P2E toward the storage module 50.

[0062] According to some arrangements of this disclosure, the power management element 240 is stacked above the decoupling element 220 and electrically connected to the decoupling element 220 via the connecting element 74. Therefore, the path length or wiring length between the power management element 240 and the decoupling element 220 is further reduced, resulting in almost no voltage drop or only a very small voltage drop in the power signal transmitted between the power management element 240 and the decoupling element 220. Consequently, the power loss transmitted can be reduced, and the number or amount of decoupling capacitors in the decoupling element 220 can be reduced, which in turn reduces the size of the decoupling element 220 and increases the stability of the power supply (especially for high power).

[0063] Figure 4 This is a cross-section of the packaging structure 4 according to some arrangements of this disclosure. The packaging structure 4 is similar to... Figure 1 The encapsulation structure 1 in the text is described below, and the differences between them are described below.

[0064] In some arrangements, the processing element 210 includes portions R1 and R2 configured to perform different functions. For example, portions R1 and R2 may be sensitive to noise at different frequencies.

[0065] In some arrangements, processing module 20 includes decoupling elements 220 and 220' above processing element 210. In some arrangements, decoupling elements 220 and 220' are configured to decouple a first noise and a second noise of different frequencies, respectively. In some arrangements, power conditioning module 30 is configured to transmit a power signal to processing element 210. In some arrangements, decoupling element 220 is above portion R1 and configured to decouple the first noise from the power signal and transmit the power signal to portion R1. In some arrangements, decoupling element 220' is above portion R2 and configured to decouple the second noise from the power signal and transmit the power signal to portion R2. In some arrangements, path P1A is configured to transmit a power signal from power conditioning module 30. In some arrangements, path P1A can be split into paths P1A1 and P1A2. Path P1A1 can be configured to transmit a power signal to decoupling element 220, whereby decoupling element 220 decouples the power signal from a first noise, and then the power signal is transmitted to a portion R1 of processing element 210. Path P1A2 can be configured to transmit a power signal to decoupling element 220', whereby decoupling element 220' decouples the power signal from a second noise, and then the power signal is transmitted to a portion R2 of processing element 210. In some arrangements, portion R1 is more sensitive to the first noise, and a second portion R2 is more sensitive to the second noise.

[0066] Unless otherwise specified, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” and “below” are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not compromised by such arrangement.

[0067] As used herein, the terms “approximately,” “generally,” “roughly,” “about,” and “approximately” are used to describe and explain minor variations. When used in conjunction with an event or situation, these terms may refer to examples where the event or situation occurred precisely or very approximately. For example, when used in conjunction with a numerical value, these terms may refer to a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first value is within a range of variation less than or equal to ±10% of a second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, the first value may be considered “generally” the same as or equal to the second value. For example, "roughly" vertical can refer to an angle variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0068] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0069] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may contain a plural or multiple indicators.

[0070] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials are those that offer little or no resistance to the flow of electric current. A unit of measurement for conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m, for example, at least 10 5 S / m or at least 10 6 A material with conductivity of S / m. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0071] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be flexibly interpreted as including not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0072] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and alternative equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, the process reproduction in this disclosure may differ from actual equipment. Other embodiments may exist that are not specifically described in this disclosure. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are considered to be included within the scope of the appended claims. Although the disclosed methods have been described herein with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A package structure comprising: a processing module comprising a processing element having a first side configured to receive power; a storage module; and a power conditioning module disposed adjacent to the processing module, wherein the power conditioning module comprises: a first portion configured to decouple a first noise from a first power signal and transmit the first power signal to the first side of the processing element; and a second portion configured to transmit a second power signal to the storage module.

2. The package structure of claim 1, wherein the first portion is closer to the processing element than the second portion.

3. The package structure of claim 1, wherein the power conditioning module further comprises a third portion configured to provide electrical communication between the processing element and the storage module.

4. The package structure of claim 3, wherein the first portion is closer to the processing element than the third portion.

5. The package structure of claim 3, wherein the third portion is configured to transmit an electrical signal from the processing element to control access to the storage module.

6. The package structure of claim 3, wherein the power conditioning module comprises a first conductive via configured to transmit the first power signal and a second conductive via electrically connected to the third portion, and a width of the second conductive via is less than a width of the first conductive via.

7. The package structure of claim 1, wherein the second portion is configured to decouple a second noise from the second power signal and transmit the second power signal to the storage module.

8. The package structure of claim 1, wherein the power conditioning module comprises a plurality of capacitor structures, and a distribution density of the capacitor structures in a first region closer to the processing element is greater than a distribution density of the capacitor structures in a second region farther from the processing element.

9. The package structure of claim 1, wherein the power conditioning module is stacked between the storage module and the processing module.

10. The package structure of claim 9, wherein the processing module further comprises: a decoupling element configured to decouple a second noise from the first power signal, wherein the first noise and the second noise have different frequencies.

11. A package structure comprising: a processing module comprising: a processing element having a first side; and a decoupling element configured to decouple a first noise from a first power signal and transmit the first power signal to the first side of the processing element; a storage module over the processing module; and a power conditioning module disposed adjacent to the processing module and configured to transmit a first signal to the storage module.

12. The package structure of claim 11, wherein the power conditioning module comprises a conductive via configured to transmit the first signal to the storage module. ​ ​ 13. The package structure of claim 11, wherein the decoupling element comprises a first portion configured to decouple the first noise from the first power signal and a second portion configured to provide electrical communication between the processing element and the memory module.

14. The package structure of claim 13, wherein the decoupling element comprises a first conductive via connected to the first portion and configured to transmit the first power signal.

15. The package structure of claim 14, wherein the decoupling element comprises a second conductive via connected to the second portion and configured to transmit an electrical signal from the processing element to control access to the memory module.

16. The package structure of claim 15, wherein a width of the second conductive via is less than a width of the first conductive via.

17. The package structure of claim 11, further comprising an encapsulant encapsulating the processing module and the power regulation module.

18. A package structure comprising: a processing module comprising a processing element having a first side configured to receive electrical power; and a power regulation module disposed adjacent to the processing module, wherein the power regulation module is configured to transmit a power signal, and a power path is configured to transmit the power signal by extending vertically through the power regulation module and horizontally toward the first side of the processing element.

19. The package structure of claim 18, wherein the processing module comprises first and second decoupling elements over the processing element and configured to decouple first and second noises of different frequencies, respectively.

20. The package structure of claim 19, wherein the processing element comprises first and second portions configured to perform different functions, the first decoupling element is over the first portion and configured to decouple the first noise from the power signal and transmit the power signal to the first portion, and the second decoupling element is over the second portion and configured to decouple the second noise from the power signal and transmit the power signal to the second portion.

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