High-voltage capacitor isolators and their manufacturing methods
By inserting a floating conductor ring with a fluctuating potential inside the high-voltage capacitor isolator, the premature failure point problem caused by the edge electric field effect is solved, the electric field distribution is optimized and the edge electric field strength is reduced, thereby improving the reliability of the device and the signal quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG ELECTRONICS (SHAOXING) CORP
- Filing Date
- 2026-02-04
- Publication Date
- 2026-05-26
Smart Images
Figure CN121645907B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of microelectronic device technology, and in particular to a high-voltage capacitor isolator and its manufacturing method. Background Technology
[0002] HV capacitor (HVCAP) is a high-voltage capacitor isolator that blocks DC and allows AC to pass. It is widely used for connections between the front and rear stages of a circuit and can be directly designed on-chip. By using different layers of metal as the top and bottom plates, and using SiO2 as the insulating medium between the top and bottom plates, a high-voltage capacitor is formed by the interlayer of metals.
[0003] In the Time-Dielectric-Diffusion Breakdown (TDDB) test, due to the edge electric field effect of the parallel plate capacitor, the edge electric field distribution of the upper and lower plates of the internal metal layer of the HVCAP will be distorted, and the peak edge electric field strength E edge This exponential increase leads to localized media breakdown, causing an early fail problem, such as... Figure 2 , Figure 3 , Figure 4 As shown.
[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to provide a high-voltage capacitor isolator and its manufacturing method to solve the problem of premature failure.
[0006] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a high-voltage capacitor isolator, comprising:
[0007] A lower electrode plate is grown on the substrate surface, and a first dielectric layer is deposited on top of the lower electrode plate;
[0008] A second metal layer is deposited on the first dielectric layer, and the second metal layer is etched to form a floating conductor ring;
[0009] A second dielectric layer and a third metal layer are sequentially deposited on the floating conductor ring, and the third metal layer is etched to form an upper electrode. The potential of the floating conductor ring is free to float, and its projection on the substrate overlaps at least partially with the projection of the upper or lower electrode on the substrate, in order to counteract the electric field divergence at the edge of the electrode.
[0010] A passivation layer and a protective layer are sequentially formed on the top of the upper electrode plate, and the passivation layer and the protective layer are etched to form an opening that exposes the top surface of the upper electrode plate.
[0011] Preferably, growing the lower electrode on the substrate surface includes: depositing a first metal layer on the substrate and forming the lower electrode by photolithography and etching, as well as a first peripheral metal layer located around the lower electrode.
[0012] Preferably, after depositing the first dielectric layer, the first dielectric layer is further etched to form a first connection hole.
[0013] Preferably, when etching the second metal layer to form a floating conductor ring, a second peripheral metal layer is also formed around the floating conductor ring, and the first peripheral metal layer and the second peripheral metal layer are connected through the first connecting hole.
[0014] Preferably, after depositing the second dielectric layer and before etching the third metal layer, the second dielectric layer is also etched to form a second connection hole.
[0015] Preferably, when etching the third metal layer to form the upper electrode plate, a third peripheral metal layer is also formed around the upper electrode plate, and the third peripheral metal layer and the second peripheral metal layer are connected through a second connecting hole.
[0016] Preferably, the outer edge dimension of the floating conductor ring is the same as the outer edge dimension of the upper electrode plate.
[0017] Preferably, the outer edge dimension of the floating conductor ring is the same as the outer edge dimension of the lower electrode plate.
[0018] Preferably, the material of the second metal layer includes aluminum, the material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer includes silicon oxide, silicon oxynitride, and silicon nitride.
[0019] A high-voltage capacitor isolator, manufactured using the method described above, includes:
[0020] The lower electrode plate is mounted on the substrate.
[0021] A first dielectric layer covers the lower electrode plate;
[0022] A second dielectric layer covers the first dielectric layer;
[0023] The upper electrode plate is located on top of the second dielectric layer;
[0024] A floating conductor ring is disposed between the first dielectric layer and the second dielectric layer. The potential of the floating conductor ring is free to float, and its projection on the substrate at least partially overlaps with the projection of the upper or lower electrode on the substrate, in order to counteract the electric field divergence at the edge of the electrode.
[0025] In the manufacturing method of the high voltage capacitor isolator provided by the present invention, a floating conductor ring with free potential is inserted between the internal plates of the capacitor. The upper and lower surfaces of the floating conductor ring generate equal and opposite charges due to electrostatic induction. The induced charges form new electric field sources on both sides, which cancel the electric field divergence at the edge of the original plate, thereby optimizing the edge electric field distribution and improving the HVCAP premature failure point problem.
[0026] The high-voltage capacitor isolator provided by this invention and the manufacturing method of the high-voltage capacitor isolator provided by this invention belong to the same inventive concept. Therefore, the high-voltage capacitor isolator provided by this invention has at least all the advantages of the manufacturing method of the high-voltage capacitor isolator provided by this invention, which will not be repeated here. Attached Figure Description
[0027] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0028] Figure 1 This is a schematic diagram of the cross-section of an existing HVCAP capacitor isolator;
[0029] Figure 2 This is the electric field distribution of the upper and lower metal plates in the existing HVCAP technology;
[0030] Figure 3 This is an existing HVCAP premature death point chart;
[0031] Figure 4 This is a schematic diagram of the early death point problem of HVCAP in existing technologies;
[0032] Figure 5 This is a schematic diagram of the lower electrode plate structure according to an embodiment of the present invention;
[0033] Figure 6 This is a schematic diagram of the structure for preparing the first connecting hole according to an embodiment of the present invention;
[0034] Figure 7 This is a schematic diagram of the structure for preparing a floating conductor ring according to an embodiment of the present invention;
[0035] Figure 8 This is a schematic diagram of the structure for preparing the second dielectric layer according to an embodiment of the present invention;
[0036] Figure 9 This is a schematic diagram of the structure for preparing the upper electrode plate according to an embodiment of the present invention;
[0037] Figure 10 This is a schematic diagram of the structure for preparing the passivation layer and protective layer according to an embodiment of the present invention;
[0038] Figure 11 This is a schematic diagram showing the morphology and electric field distribution of two floating conductor rings made of Al material according to the present invention and an existing capacitor isolator.
[0039] Figure 12 These are schematic diagrams showing the morphology and electric field distribution of two types of floating conductor rings made of Cu material according to the present invention and existing capacitor isolators;
[0040] Figure 13 This is a flowchart of an embodiment of the present invention.
[0041] In the attached image:
[0042] 100. Lower electrode plate; 101. First dielectric layer; 102. First connecting hole; 103. Floating conductor ring; 104. Second dielectric layer; 105. Second connecting hole; 106. Upper electrode plate; 107. Passivation layer; 108. Protective layer; 200. First peripheral metal layer; 201. Second peripheral metal layer; 202. Third peripheral metal layer. Detailed Implementation
[0043] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0044] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0045] Studies have found that, for example Figure 2 The electric field distribution of the upper and lower plates is shown. The electric field lines are densely distributed near the plates, but they converge at the edges. The electric field strength peaks at the edges, a phenomenon known as the edge electric field effect. This edge effect can cause premature failures in TDDB tests. Figure 3 The Weibull Distribution for TDDB test is shown below. Figure 4 The diagram shown illustrates the problem of premature death.
[0046] Based on this, the core idea of the present invention is to optimize the structural design of HVCAP by inserting a floating conductor ring with a free-floating potential between the internal plates of the capacitor. The upper and lower surfaces of the floating conductor ring generate equal amounts of opposite charges due to electrostatic induction. The induced charges form new electric field sources on both sides, which cancel the electric field divergence at the edge of the original plate, thereby optimizing the edge electric field distribution and improving the premature failure point problem of HVCAP.
[0047] For details, please refer to Figures 5-13 This is a schematic diagram of an embodiment of the present invention. Figure 13 As shown, a method for manufacturing a high-voltage capacitor isolator includes:
[0048] A lower electrode 100 is grown on the surface of a substrate (not shown), and a first dielectric layer 101 is deposited on top of the lower electrode 100;
[0049] A second metal layer is deposited on the first dielectric layer 101, and the second metal layer is etched to form a floating conductor ring 103;
[0050] A second dielectric layer 104 and a third metal layer are sequentially deposited on the floating conductor ring 103. The third metal layer is etched to form an upper electrode 106. The potential of the floating conductor ring 103 is free to float, and its projection on the substrate overlaps at least partially with the projection of the upper electrode 106 or the lower electrode 100 on the substrate, in order to counteract the electric field divergence at the edge of the electrode.
[0051] A passivation layer 107 and a protective layer 108 are sequentially formed on the top of the upper electrode plate 106, and the passivation layer 107 and the protective layer 108 are etched to form an opening that exposes the top surface of the upper electrode plate 106.
[0052] In one embodiment, a floating conductor ring 103, meaning it is ungrounded and free to float, is inserted between the upper and lower plates. Equal but opposite charges are generated on the upper and lower surfaces of the conductor ring due to electrostatic induction. These induced charges form new electric field sources on both sides, canceling out the electric field divergence at the edges of the original plates. Theoretical formulas show that without the floating conductor ring 103, the peak electric field strength E at the edge is... edge ≈2.5E0; When there is a floating conductor ring 103, the peak electric field strength at the edge is E edge ≈1.2-1.5E0, where E0 is the ideal electric field strength in the central region. The edge electric field distribution was optimized, and the peak edge electric field strength was reduced by about 40%, thus improving the early failure point problem of HVCAP.
[0053] First, growing the lower electrode 100 on the substrate surface includes: depositing a first metal layer on the substrate, forming the lower electrode 100 by photolithography and etching, and a first peripheral metal layer 200 located around the lower electrode 100.
[0054] like Figure 5 As shown, a first metal layer is first deposited, and a lower electrode 100 and a first peripheral metal layer 200 are formed by photolithography and etching. For example, the width of the lower electrode 100 is 120µm-160µm.
[0055] like Figure 6As shown, a first dielectric layer 101 is deposited on the lower electrode 100. After depositing the first dielectric layer 101, the first dielectric layer 101 is etched to form a first connection hole 102. The first dielectric layer 101 is made of silicon oxide and has a thickness of 6.3µm-7.7µm. A photoresist layer is formed on the first dielectric layer 101. The desired photoresist pattern is formed by photolithography of the photoresist layer. The exposed area is used to etch the first dielectric layer 101 to form the first connection hole 102, and a metal material is filled into the first connection hole 102.
[0056] Next, a second metal layer is deposited on the first dielectric layer 101. While etching the second metal layer to form the floating conductor ring 103, a second peripheral metal layer 201 is also formed around the floating conductor ring 103. The first peripheral metal layer 200 and the second peripheral metal layer 201 are connected through the first connecting hole 102. Figure 7 As shown.
[0057] By forming a photoresist layer on the second metal layer, and by photolithography of the photoresist layer to form the desired photoresist pattern, the exposed area is etched to form a floating conductor ring 103 and a second peripheral metal layer 201.
[0058] More preferably, the floating conductor ring 103 is made of the same material as the upper and lower plates, such as copper or aluminum. The edge of the floating conductor ring 103 is rounded, with an outer corner radius R ≥ 30µm. The second outer metal layer 201 and the floating conductor ring 103 have the same material and thickness. The thickness of the second outer metal layer 201 and the floating conductor ring 103 is D = 4.5µm, and the width of the floating conductor ring 103 is W = 10µm-60µm. The size of the floating conductor ring 103 varies slightly depending on its placement. The floating conductor ring 103 is located below the edge region of the upper plate 106 or above the edge region of the lower plate 100. When the floating conductor ring 103 is projected perpendicularly onto the substrate along with the upper plate 106 and the lower plate 100, there is a partial overlap between the floating conductor ring 103 and the upper plate 106 or the lower plate 100, especially at the edge of the upper plate 106 or the lower plate 100.
[0059] In one embodiment, the outer edge dimension of the floating conductor ring 103 is the same as the outer edge dimension of the upper electrode plate 106. For example... Figure 11 As shown, the floating conductor ring 103 (i.e. Figure 11 The size of the floating conductor ring 103 is the same as that of the upper electrode plate 106. The outer edge of the floating conductor ring 103 coincides with the projection of the outer edge of the upper electrode plate 106 onto the substrate. The length of the outer edge of the floating conductor ring 103 is L = 100µm-140µm.
[0060] In one embodiment, the outer edge dimension of the floating conductor ring 103 is the same as the outer edge dimension of the lower electrode plate 100. For example... Figure 10 As shown, the dimensions of the floating conductor ring 103 are the same as those of the lower electrode plate 100. The outer edge of the floating conductor ring 103 coincides with the projection of the outer edge of the lower electrode plate 100 onto the substrate. The length L of the outer edge of the floating conductor ring 103 is 120µm-160µm.
[0061] like Figure 8 As shown, after depositing the second dielectric layer 104 and before etching the third metal layer, the second dielectric layer 104 is also etched to form a second connection hole 105. The thickness of the second dielectric layer 104 is 6.3µm-7.7µm. The second connection hole 105 is formed by photolithography and etching through a photoresist layer, and the second connection hole 105 is also filled with metal material.
[0062] The deposition of the third metal layer continues, and the third metal layer is etched to form the upper electrode plate 106. During the etching process, a third peripheral metal layer 202 is also formed around the upper electrode plate 106. The third peripheral metal layer 202 is connected to the second peripheral metal layer 201 via a second connecting hole 105. Figure 9 As shown.
[0063] The upper electrode 106 and the third peripheral metal layer 202 are formed by photolithography and etching of the photoresist layer and the third metal layer. The width of the upper electrode 106 is 100µm-140µm.
[0064] The second metal layer is made of aluminum, the first dielectric layer 101 is made of silicon oxide, and the second dielectric layer 104 is made of silicon oxide, silicon oxynitride, and silicon nitride. The first, second, and third metal layers are all made of aluminum or all of copper. Similarly, the first peripheral metal layer 200, the second peripheral metal layer 201, the third peripheral metal layer 202, the upper electrode 106, the lower electrode 100, and the floating conductor ring 103 are made of the same material, such as all of aluminum or all of copper. Figure 11 and Figure 12 As shown, the morphology and electric field distribution of two floating conductor rings 103 made of Al and Cu materials and an existing capacitor isolator are illustrated. The floating conductor ring 103 made of copper has excellent conductivity and electromagnetic shielding capabilities.
[0065] Generally, to address electromagnetic interference or parasitic interference from surrounding traces on the upper and lower plates of an isolation capacitor, a shielding ring resembling a "running track" is often designed around the isolation capacitor. This shielding ring is composed of multiple layers of metal wires to shield external electromagnetic signals. No traces of the same layer are placed inside the "running track" to prevent signals from surrounding metal layers from affecting the isolation capacitor. The potential of the shielding ring is the same as the substrate, providing a "clean" ground and avoiding interference from surrounding noise. Its cross-sectional view is shown below. Figure 1 As shown, there is an upper electrode plate, a lower electrode plate, connecting holes (WTV0 and WTV1), a passivation layer (PA) and polyimide (PI), and shielding rings (TM1, M1TM and TTM2). The upper electrode plate is connected by wire bond.
[0066] In this invention, the stacked first peripheral metal layer 200, second peripheral metal layer 201, and third peripheral metal layer 202 constitute a shielding ring structure around the capacitor, preventing signals from the surrounding metal layers from affecting the isolation capacitor. The potential of the shielding ring is consistent with the substrate, providing a "clean" ground and avoiding interference from surrounding noise.
[0067] Finally, a passivation layer 107 and a protective layer 108 are deposited on the upper electrode 106, and the passivation layer 107 and the protective layer 108 are etched to expose the surface of the upper electrode 106 and the surface of the third peripheral metal layer 202 for connecting external devices, such as... Figure 10 As shown. The passivation layer 107 is made of silicon oxide and silicon nitride, and the protective layer 108 is made of polyimide (PI).
[0068] Based on the same technical concept, the present invention also provides a high-voltage capacitor isolator, which is manufactured using the manufacturing method of the high-voltage capacitor isolator described above, comprising:
[0069] The lower electrode plate 100 is disposed on the substrate;
[0070] A first dielectric layer 101 covers the lower electrode plate 100;
[0071] The second dielectric layer 104 covers the first dielectric layer 101;
[0072] The upper electrode plate 106 is located on top of the second dielectric layer 104;
[0073] A floating conductor ring 103 is disposed between the first dielectric layer 101 and the second dielectric layer 104. The potential of the floating conductor ring 103 is free to float, and its projection on the substrate at least partially overlaps with the projection of the upper electrode 106 or the lower electrode 100 on the substrate, in order to counteract the electric field divergence at the edge of the electrode.
[0074] The high-voltage capacitor also includes a first outer peripheral metal layer 200, a second outer peripheral metal layer 201, and a third outer peripheral metal layer 202. The first outer peripheral metal layer 200 and the second outer peripheral metal layer 201 are connected through a first connecting hole 102, and the third outer peripheral metal layer 202 and the second outer peripheral metal layer 201 are connected through a second connecting hole 105.
[0075] In the high-voltage capacitor isolator and its manufacturing method provided by this invention, a floating conductor ring with free potential is inserted between the internal plates of the capacitor. The four corners of the floating conductor ring are rounded, and the angle is consistent with that of the upper and lower plates. This adjusts the edge electric field distribution. The upper and lower surfaces of the floating conductor ring generate equal amounts of opposite charges due to electrostatic induction. The induced charges form new electric field sources on both sides, which cancel the electric field divergence at the edge of the original plates, thereby optimizing the edge electric field distribution. The peak edge field strength is reduced by about 40%, improving the HVCAP premature failure point problem. The stacked outer metal layer shields external interference and improves signal purity. The HVCAP performance can be further improved by adjusting the position and size of the floating conductor ring.
[0076] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. A method for manufacturing a high-voltage capacitor isolator, characterized in that, include: A lower electrode plate is grown on the substrate surface, and a first dielectric layer is deposited on top of the lower electrode plate; A second metal layer is deposited on the first dielectric layer, the second metal layer is etched to form a floating conductor ring, and a second peripheral metal layer is also formed around the floating conductor ring; A second dielectric layer and a third metal layer are sequentially deposited on the floating conductor ring, and the third metal layer is etched to form an upper electrode. The potential of the floating conductor ring is free to float, and its projection on the substrate overlaps at least partially with the projection of the upper or lower electrode on the substrate, in order to counteract the electric field divergence at the edge of the electrode. A passivation layer and a protective layer are sequentially formed on the top of the upper electrode plate, and the passivation layer and the protective layer are etched to form an opening that exposes the top surface of the upper electrode plate.
2. The manufacturing method of the high-voltage capacitor isolator according to claim 1, characterized in that, Growing a lower electrode on the substrate surface includes: depositing a first metal layer on the substrate, forming the lower electrode by photolithography and etching, and a first peripheral metal layer located around the lower electrode.
3. The method for manufacturing a high-voltage capacitor isolator according to claim 2, characterized in that, After depositing the first dielectric layer, the first dielectric layer is etched to form a first connection hole.
4. The manufacturing method of the high-voltage capacitor isolator according to claim 3, characterized in that, The first peripheral metal layer and the second peripheral metal layer are connected through the first connecting hole.
5. The method for manufacturing a high-voltage capacitor isolator according to claim 4, characterized in that, After depositing the second dielectric layer and before etching the third metal layer, the second dielectric layer is also etched to form a second connection hole.
6. The method for manufacturing a high-voltage capacitor isolator according to claim 5, characterized in that, When etching the third metal layer to form the upper electrode plate, a third peripheral metal layer is also formed around the upper electrode plate. The third peripheral metal layer and the second peripheral metal layer are connected through a second connecting hole.
7. The method for manufacturing a high-voltage capacitor isolator according to claim 1, characterized in that, The outer edge dimension of the floating conductor ring is the same as the outer edge dimension of the upper electrode plate.
8. The method for manufacturing a high-voltage capacitor isolator according to claim 1, characterized in that, The outer edge dimension of the floating conductor ring is the same as the outer edge dimension of the lower electrode plate.
9. The method for manufacturing a high-voltage capacitor isolator according to claim 1, characterized in that, The material of the second metal layer includes aluminum, the material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer includes silicon oxide, silicon oxynitride, and silicon nitride.
10. A high-voltage capacitor isolator, characterized in that, The high-voltage capacitor isolator is manufactured using the manufacturing method of any one of claims 1-9, comprising: The lower electrode plate is mounted on the substrate. A first dielectric layer covers the lower electrode plate; A second dielectric layer covers the first dielectric layer; The upper electrode plate is located on top of the second dielectric layer; A floating conductor ring is disposed between the first dielectric layer and the second dielectric layer. The potential of the floating conductor ring is free to float, and its projection on the substrate at least partially overlaps with the projection of the upper or lower electrode on the substrate, in order to counteract the electric field divergence at the edge of the electrode.