Semiconductor structure and forming method thereof
By introducing a high-stress layer into the HBT device and performing annealing, the problem of long carrier transit time was solved, the frequency performance and common-emitter amplification factor of the device were improved, and the high-frequency and high-power application capabilities of the device were enhanced.
Patent Information
- Application Number
- CN202411263002.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2026-03-10
AI Technical Summary
The carrier transit time in existing HBT devices is relatively long, which affects the high-frequency and high-power performance of the devices.
In HBT devices, a high-stress layer is formed and compressive stress is introduced through an annealing process to improve the stress matching between the base and emitter.
It improves carrier transit time, enhances device frequency performance and common-emitter amplification factor, and strengthens the device's high-frequency and high-power application capabilities.
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Figure CN121645914A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND
[0002] As a core device of radio frequency integrated circuits, HBT (heterojunction bipolar transistor) has high gain, speed and frequency response, making it more competitive in technical fields requiring high speed and high frequency response. With the evolution of technology, the cutoff frequency (fT) and maximum oscillation frequency (fmax) of silicon-based active devices gradually enter the terahertz (THz) frequency band. It is urgent to develop new bipolar device structures suitable for high frequency and high power applications.
[0003] Therefore, it is necessary to provide a more effective and reliable technical solution to improve the carrier transit time in the HBT device and thus improve the device performance. SUMMARY
[0004] The present application provides a semiconductor structure and a forming method thereof, which can improve the carrier transit time of the base and emitter in the HBT device and thus improve the device performance.
[0005] One aspect of the present application provides a forming method of a semiconductor structure, comprising: providing a semiconductor substrate; sequentially forming a first dielectric layer and a second dielectric layer on the surface of the semiconductor substrate, and a collector in the first dielectric layer and the second dielectric layer; sequentially forming a third dielectric layer, a polysilicon layer and a fourth dielectric layer on the surface of the collector and the second dielectric layer, and a first opening penetrating through the fourth dielectric layer and the polysilicon layer and a second opening penetrating through the third dielectric layer, the width of the second opening being greater than the width of the first opening; forming a base at the bottom and sidewall of the second opening; forming an emitter filling the first opening and the second opening and covering the surface of the fourth dielectric layer on the surface of the base; etching the emitter, the fourth dielectric layer, the polysilicon layer, the third dielectric layer and the second dielectric layer to expose part of the first dielectric layer; forming a high stress layer covering the top and sidewall of the emitter, the fourth dielectric layer, the polysilicon layer, the third dielectric layer and the second dielectric layer; performing an annealing process to make the high stress layer shrink so that the base is subjected to a compressive stress of the emitter reaching a first preset value.
[0006] In some embodiments of the present application, the first preset value is 2 to 5 GPa.
[0007] In some embodiments of the present application, the shrinkage of the high stress layer also makes the base subjected to a compressive stress of the polysilicon layer reaching a second preset value, and the second preset value is 2 to 5 GPa.
[0008] In some embodiments of the present application, the material of the high stress layer includes silicon nitride.
[0009] In some embodiments of this application, the method for forming the high-stress layer includes PECVD, wherein the process parameters of the PECVD include: process gases including SiH4, NH3 and N2, process temperature of 400-500 degrees Celsius, and process pressure of 25-133 Pa.
[0010] In some embodiments of this application, the annealing process is millisecond-level annealing.
[0011] In some embodiments of this application, the process parameters of the annealing process include: an annealing temperature of 1000 to 1100 degrees Celsius and an annealing type of millisecond-level Spike annealing.
[0012] Another aspect of this application provides a semiconductor structure, comprising: a semiconductor substrate, wherein a first dielectric layer and a second dielectric layer and a collector electrode located in the first dielectric layer and the second dielectric layer are sequentially formed on the surface of the semiconductor substrate; a third dielectric layer, a polysilicon layer and a fourth dielectric layer are sequentially formed on the surface of the collector electrode and the second dielectric layer, and a first opening penetrating the fourth dielectric layer and the polysilicon layer and a second opening penetrating the third dielectric layer are formed therethrough, wherein the width of the second opening is greater than the width of the first opening; a base electrode is formed at the bottom and sidewall of the second opening; an emitter electrode is formed on the surface of the base electrode, filling the first opening and the second opening and covering the surface of the fourth dielectric layer, wherein the base electrode is subjected to a compressive stress of the emitter electrode reaching a first preset value; and a high-stress layer is formed on the top and sidewall of the emitter electrode, the fourth dielectric layer, the polysilicon layer, the third dielectric layer and the second dielectric layer.
[0013] In some embodiments of this application, the first preset value is 2 to 5 GPa.
[0014] In some embodiments of this application, the base electrode is subjected to a compressive stress of the polycrystalline silicon layer that reaches a second preset value, the second preset value being 2 to 5 GPa.
[0015] This application provides a semiconductor structure and a method for forming the same, which increases the stress conducted from the emitter to the base, thereby improving the carrier transit time of the base and emitter in HBT devices and thus improving device performance. Attached Figure Description
[0016] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0017] in:
[0018] Figures 1 to 14 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation
[0019] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0020] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.
[0021] Figures 1 to 14 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.
[0022] refer to Figure 1 As shown, a semiconductor substrate 100 is provided, wherein a well region 101 and an isolation structure 102 located on both sides of the well region 101 are also formed in the semiconductor substrate 100.
[0023] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.
[0024] In some embodiments of this application, the semiconductor substrate 100 is a P-type substrate with a crystal orientation of (100) and a boron-doped resistivity of 10-50 Ωcm.
[0025] In some embodiments of this application, the well region 101 is formed by an ion implantation process. The implantation dose of the well region 101 is 5e15 / cm². 2 The injected energy is 50 keV. The material of the isolation structure 102 includes insulating materials such as silicon oxide. The depth of the isolation structure 102 is 3500 angstroms.
[0026] refer to Figures 2 to 12As shown, a heterojunction bipolar transistor structure is formed on the surface of the semiconductor substrate 100. The heterojunction bipolar transistor includes a collector, a base, and an emitter sequentially stacked on the surface of the semiconductor substrate. Heterojunction bipolar transistors are conventional devices in the semiconductor field, therefore, this application will not elaborate on them further. Those skilled in the art will understand that they can be any type of heterojunction bipolar transistor in the semiconductor field.
[0027] Specifically, refer to Figure 2 As shown, a first dielectric layer 110 and a second dielectric layer 120, as well as a collector electrode 121 located in the first dielectric layer 110 and the second dielectric layer 120, are sequentially formed on the surface of the semiconductor substrate 100.
[0028] In some embodiments of this application, the material of the first dielectric layer 110 comprises silicon oxide insulating material formed by a thermal oxidation process. The thickness of the first dielectric layer 110 is, for example, 200 angstroms.
[0029] In some embodiments of this application, the material of the second dielectric layer 120 comprises silicon nitride. The thickness of the second dielectric layer 120 is, for example, 1300 angstroms.
[0030] In some embodiments of this application, the top surface of the collector 121 is flush with the top surface of the second dielectric layer 120. The material of the collector 121 is, for example, silicon or doped silicon epitaxially grown from the semiconductor substrate 100.
[0031] In some embodiments of this application, a method for sequentially forming a first dielectric layer 110 and a second dielectric layer 120 and a collector electrode 121 located in the first dielectric layer 110 and the second dielectric layer 120 on the surface of the semiconductor substrate 100 includes: sequentially forming a first dielectric layer 110 and a second dielectric layer 120 on the surface of the semiconductor substrate 100; sequentially forming a third opening penetrating the second dielectric layer 120 and a fourth opening penetrating the first dielectric layer located at the bottom of the third opening, wherein the width of the third opening is smaller than the width of the fourth opening; epitaxially growing the collector electrode 121 in the third opening and the fourth opening using the semiconductor substrate 100 as a substrate, wherein the width of the collector electrode 121 located in the first dielectric layer 110 is larger than the width of the collector electrode 121 located in the second dielectric layer 120.
[0032] refer to Figures 3 to 7 As shown, a third dielectric layer 130, a polysilicon layer 140, and a fourth dielectric layer 150 are sequentially formed on the surfaces of the collector 121 and the second dielectric layer 120, as well as a first opening 141 penetrating the fourth dielectric layer 150 and the polysilicon layer 140 and a second opening 131 penetrating the third dielectric layer 130. The width of the second opening 131 is greater than the width of the first opening 141.
[0033] refer to Figure 3 As shown, a third dielectric layer 130, a polysilicon layer 140, and a fourth dielectric layer 150 are sequentially formed on the surfaces of the collector 121 and the second dielectric layer 120.
[0034] In some embodiments of this application, the material of the third dielectric layer 130 includes silicon oxide. The thickness of the third dielectric layer 130 is, for example, 1000 angstroms.
[0035] In some embodiments of this application, the polysilicon layer 140 is made of polysilicon or doped polysilicon. The thickness of the polysilicon layer 140 is, for example, 1000 angstroms. The dopant ions in the polysilicon layer 140 are, for example, boron. The doping concentration of the polysilicon layer 140 is 1e10. 20 cm -3 .
[0036] In some embodiments of this application, the material of the fourth dielectric layer 150 includes silicon oxide. The thickness of the fourth dielectric layer 150 is, for example, 2000 angstroms.
[0037] refer to Figure 4 As shown, a first opening 141 is formed that penetrates the fourth dielectric layer 150 and the polysilicon layer 140.
[0038] refer to Figure 5 As shown, a sacrificial layer 151 is formed on the sidewall of the first opening 141. The material of the sacrificial layer 151 is, for example, silicon nitride. The thickness of the sacrificial layer 151 is, for example, 300 angstroms.
[0039] refer to Figure 6 As shown, an ion implantation process is used to form a collector implantation region 111 in the collector 121, with the third dielectric layer 130 as a protection. The implantation energy of the collector implantation region 111 is 110 keV. The implantation dose of the collector implantation region 111 is 10 keV. 14 / cm 2 The injected ions are, for example, phosphorus ions.
[0040] refer to Figure 7 As shown, a second opening 131 is formed through the third dielectric layer 130 to expose the collector 121, and the width of the second opening 131 is greater than the width of the first opening 141.
[0041] refer to Figure 8 As shown, a base 160 is formed at the bottom and sidewall of the second opening 131. The base 160 is electrically connected to the collector 121 and the polysilicon layer 140. The base 160 is also referred to as the inner base region, corresponding to the outer base region represented by the polysilicon layer 140.
[0042] In some embodiments of this application, the method of forming the base 160 includes selectively epitaxially growing the base 160 on the substrate of the collector 121 and the polysilicon layer 140. The material of the base 160 is, for example, silicon germanium or doped silicon germanium, such as doped with boron ions.
[0043] In some embodiments of this application, the inner sidewall of the base 160 is flush with the inner sidewall of the polysilicon layer 140 and the fourth dielectric layer 150.
[0044] refer to Figure 9 As shown, the sacrificial layer 151 is removed.
[0045] refer to Figure 10 As shown, sidewalls 161 are formed on the sidewalls of the first and second openings 141. The material of the sidewalls 161 includes silicon oxide or silicon nitride. The sidewalls 161 can be a single-layer structure or a multi-layer composite structure.
[0046] refer to Figure 11 As shown, an emitter 170 is formed on the surface of the base 160, filling the first and second openings and covering the surface of the fourth dielectric layer 150. The top surface of the emitter 170 has a V-shaped notch.
[0047] In some embodiments of this application, the emitter 170 is made of, for example, polycrystalline silicon or doped polycrystalline silicon. The doping type of the emitter 170 is, for example, N. The thickness of the emitter 170 is, for example, 5000 angstroms. The doping concentration of the emitter 170 is, for example, 3 × 10⁻⁶. 20 cm -3 The method for forming the emitter 180 includes chemical vapor deposition or physical vapor deposition processes, etc.
[0048] refer to Figure 12 As shown, etching of the emitter 170, the fourth dielectric layer 150, the polysilicon layer 140, the third dielectric layer 130, and the second dielectric layer 120 exposes a portion of the first dielectric layer 110.
[0049] refer to Figure 13 As shown, a high-stress layer 180 is formed covering the top and sidewalls of the emitter 170, the fourth dielectric layer 150, the polysilicon layer 140, the third dielectric layer 130, and the second dielectric layer 120 (i.e., covering the heterojunction bipolar transistor structure).
[0050] In some embodiments of this application, the high-stress layer 180 is made of silicon nitride material having high stress and high shrinkage rate, and the thickness of the high-stress layer 180 is 500 to 1000 angstroms.
[0051] In some embodiments of this application, the method for forming the high-stress layer 180 includes LPCVD, wherein the process parameters of the LPCVD include: process gases including SiH4, NH3 and N2, process temperature of 400-500 degrees Celsius, and process pressure of 25-133 Pa.
[0052] After the high-stress layer 180 is formed, an annealing process is performed to shrink the high-stress layer 180 so that the base 160 is subjected to the compressive stress of the emitter 170 to reach a first preset value.
[0053] In some embodiments of this application, the first preset value is 2 to 5 GPa.
[0054] In some embodiments of this application, the shrinkage of the high-stress layer 180 further causes the base 160 to experience a second preset value of compressive stress from the polysilicon layer 140, the second preset value being 2 to 5 GPa.
[0055] In some embodiments of this application, the annealing process is millisecond-level annealing, and the process parameters of the annealing process include: an annealing temperature of 1000 to 1100 degrees Celsius, and an annealing type of millisecond-level Spike annealing.
[0056] In the technical solution of this application, the compressive stress on the emitter by the base is increased by forming the high-stress layer and annealing. Under the action of high-stress, the carrier velocity increases, the transit time of the base region decreases, and the frequency performance of the device is improved.
[0057] In some embodiments, the common-emitter amplification factor of the SiGe HBT device increased from 84 to 106, an increase of 26%, and the maximum frequency fmax increased by 20 GHz, an increase of 13%.
[0058] refer to Figure 14 As shown, the high-stress layer 180 is etched to retain only the high-stress layer 180 located on the sidewalls of the emitter 170, the fourth dielectric layer 150, the polysilicon layer 140, the third dielectric layer 130, and the second dielectric layer 120.
[0059] In some embodiments of this application, the method for forming the semiconductor structure further includes: etching away a portion of the exposed first dielectric layer 110; and forming a self-aligned metal silicide on the surface of the emitter 170, the surface of the polysilicon layer 140, and the surface of the semiconductor substrate 100 for subsequent electrical connection.
[0060] The technical solution of this application improves the frequency performance of an HBT device by depositing a layer of high-stress silicon nitride on the device and then performing high-temperature annealing. This nitride film introduces uniaxial compressive stress into the base region, thereby reducing the effective mass of charge carriers and increasing their mobility. It should be noted that the technical solution of this application can be used for any HBT device formed by any process method, and is not limited to the structure shown in the embodiments of this application.
[0061] This application provides a method for forming a semiconductor structure, which increases the stress conducted from the emitter to the base, thereby improving the carrier transit time of the base and emitter in the HBT device and thus improving device performance.
[0062] This application also provides a semiconductor structure, referenced... Figure 13 As shown, it includes: a semiconductor substrate 100, on which a heterojunction bipolar transistor structure is formed.
[0063] The heterojunction bipolar transistor structure includes a first dielectric layer 110 and a second dielectric layer 120 sequentially located on the surface of the semiconductor substrate 100, and a collector 121 located in the first dielectric layer 110 and the second dielectric layer 120; a third dielectric layer 130, a polysilicon layer 140, and a fourth dielectric layer 150 are sequentially formed on the surfaces of the collector 121 and the second dielectric layer 120, and a first opening 141 penetrating the fourth dielectric layer 150 and the polysilicon layer 140 and a second opening 131 penetrating the third dielectric layer 130. The width of the second opening 131 is greater than the width of the first opening 141; a base 160 is formed on the bottom and sidewall of the second opening 131; an emitter 170 is formed on the surface of the base 160, which fills the first and second openings and covers the surface of the fourth dielectric layer 150; the base 160 is subjected to a compressive stress of the emitter 170 that reaches a first preset value; a high-stress layer 180 is formed on the top and sidewall of the emitter 170, the fourth dielectric layer 150, the polysilicon layer 140, the third dielectric layer 130, and the second dielectric layer 120.
[0064] In some embodiments of this application, a well region 101 and an isolation structure 102 located on both sides of the well region 101 are also formed in the semiconductor substrate 100.
[0065] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.
[0066] In some embodiments of this application, the semiconductor substrate 100 is a P-type substrate with a crystal orientation of (100) and a boron-doped resistivity of 10-50 Ωcm.
[0067] In some embodiments of this application, the well region 101 is formed by an ion implantation process. The implantation dose of the well region 101 is 5e15 / cm². 2 The injected energy is 50 keV. The material of the isolation structure 102 includes insulating materials such as silicon oxide. The depth of the isolation structure 102 is 3500 angstroms.
[0068] In some embodiments of this application, the material of the first dielectric layer 110 comprises silicon oxide insulating material formed by a thermal oxidation process. The thickness of the first dielectric layer 110 is, for example, 200 angstroms.
[0069] In some embodiments of this application, the material of the second dielectric layer 120 comprises silicon nitride. The thickness of the second dielectric layer 120 is, for example, 1300 angstroms.
[0070] In some embodiments of this application, the top surface of the collector 121 is flush with the top surface of the second dielectric layer 120. The material of the collector 121 is, for example, silicon or doped silicon epitaxially grown from the semiconductor substrate 100.
[0071] In some embodiments of this application, the width of the collector 121 located in the first dielectric layer 110 is greater than the width of the collector 121 located in the second dielectric layer 120.
[0072] In some embodiments of this application, the material of the third dielectric layer 130 includes silicon oxide. The thickness of the third dielectric layer 130 is, for example, 1000 angstroms.
[0073] In some embodiments of this application, the polysilicon layer 140 is made of polysilicon or doped polysilicon. The thickness of the polysilicon layer 140 is, for example, 1000 angstroms. The dopant ions in the polysilicon layer 140 are, for example, boron. The doping concentration of the polysilicon layer 140 is 1e10. 20 cm -3 .
[0074] In some embodiments of this application, the material of the fourth dielectric layer 150 includes silicon oxide. The thickness of the fourth dielectric layer 150 is, for example, 2000 angstroms.
[0075] In some embodiments of this application, a collector injection region 111 is formed in the collector 121. The injection energy of the collector injection region 111 is 110 keV. The injection dose of the collector injection region 111 is 10 keV. 14 / cm 2The injected ions are, for example, phosphorus ions.
[0076] In some embodiments of this application, the base 160 is electrically connected to the collector 121 and the polysilicon layer 140. The base 160 is also referred to as the inner base region, corresponding to the outer base region represented by the polysilicon layer 140.
[0077] In some embodiments of this application, the base 160 is made of silicon germanium or doped silicon germanium, such as doped boron ions.
[0078] In some embodiments of this application, the inner sidewall of the base 160 is flush with the inner sidewall of the polysilicon layer 140 and the fourth dielectric layer 150.
[0079] In some embodiments of this application, the first opening and the second opening 141 are formed with sidewalls 161. The material of the sidewalls 161 includes silicon oxide or silicon nitride. The sidewalls 161 can be a single-layer structure or a multi-layer composite structure.
[0080] In some embodiments of this application, the top surface of the emitter 170 has a V-shaped notch.
[0081] In some embodiments of this application, the material of the emitter 170 is, for example, doped single-crystal silicon. The doping type of the emitter 170 is, for example, N. The thickness of the emitter 170 is, for example, 5000 angstroms. The doping concentration of the emitter 170 is, for example, 3 × 10⁻⁶. 20 cm -3 The method for forming the emitter 180 includes chemical vapor deposition or physical vapor deposition processes, etc.
[0082] In some embodiments of this application, the high-stress layer 180 is made of silicon nitride material having high stress and high shrinkage rate, and the thickness of the high-stress layer 180 is 500 to 1000 angstroms.
[0083] In some embodiments of this application, the first preset value is 2 to 5 GPa.
[0084] In some embodiments of this application, the base 160 is subjected to a compressive stress of the polysilicon layer 140 reaching a second preset value, the second preset value being 2 to 5 GPa.
[0085] In the technical solution of this application, the compressive stress on the emitter by the base is increased by forming the high-stress layer and annealing. Under the action of high-stress, the carrier velocity increases, the transit time of the base region decreases, and the frequency performance of the device is improved.
[0086] In some embodiments, the common-emitter amplification factor of the SiGe HBT device increased from 84 to 106, an increase of 26%, and the maximum frequency fmax increased by 20 GHz, an increase of 13%.
[0087] The technical solution of this application improves the frequency performance of an HBT device by depositing a layer of high-stress silicon nitride on the device and then performing high-temperature annealing. This nitride film introduces uniaxial compressive stress into the base region, thereby reducing the effective mass of charge carriers and increasing their mobility. It should be noted that the technical solution of this application can be used for any HBT device formed by any process method, and is not limited to the structure shown in the embodiments of this application.
[0088] This application provides a semiconductor structure and a method for forming the same, which increases the stress conducted from the emitter to the base, thereby improving the carrier transit time of the base and emitter in HBT devices and thus improving device performance.
[0089] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0090] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0091] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0092] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0093] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method of forming a semiconductor structure, characterized by, The method comprises: forming a semiconductor substrate; forming a heterojunction bipolar transistor structure on the semiconductor substrate, the heterojunction bipolar transistor comprising a collector, a base and an emitter successively stacked on a surface of the semiconductor substrate; forming a high stress layer covering the heterojunction bipolar transistor structure; performing an annealing process to shrink the high stress layer.
2. The method of forming a semiconductor structure of claim 1, wherein, The method of forming a heterojunction bipolar transistor structure on a semiconductor substrate comprises: forming a first dielectric layer and a second dielectric layer successively on a surface of the semiconductor substrate and a collector in the first dielectric layer and the second dielectric layer; forming a third dielectric layer, a polysilicon layer and a fourth dielectric layer successively on a surface of the collector and the second dielectric layer and a first opening through the fourth dielectric layer and the polysilicon layer and a second opening through the third dielectric layer, the second opening having a width greater than that of the first opening; forming a base on a bottom and a sidewall of the second opening; forming an emitter filling the first opening and the second opening and covering a surface of the fourth dielectric layer on a surface of the base; etching the emitter, the fourth dielectric layer, the polysilicon layer, the third dielectric layer and the second dielectric layer to expose a portion of the first dielectric layer; forming a high stress layer covering a top and a sidewall of the emitter, the fourth dielectric layer, the polysilicon layer, the third dielectric layer and the second dielectric layer.
3. The method of forming a semiconductor structure of claim 2, wherein, The annealing process shrinks the high stress layer so that the base is subjected to a compressive stress of the emitter reaching a first preset value.
4. The method of forming a semiconductor structure of claim 3, wherein, The first preset value is 2-5 GPa.
5. The method of forming a semiconductor structure of claim 3, wherein, The shrinkage of the high stress layer also causes the base to be subjected to a compressive stress of the polysilicon layer reaching a second preset value, the second preset value being 2-5 GPa.
6. The method of forming a semiconductor structure of claim 1, wherein, The material of the high stress layer comprises silicon nitride.
7. The method of forming a semiconductor structure of claim 6, wherein, The method of forming the high stress layer comprises PECVD, the process parameters of the PECVD comprising: process gas comprising SiH4, NH3 and N2, process temperature being 400-500 degrees Celsius, process pressure being 25-133 Pa.
8. The method of forming a semiconductor structure of claim 1, wherein, The annealing process is a millisecond annealing process.
9. The method of forming a semiconductor structure of claim 8, wherein, The process parameters of the annealing process comprise: annealing temperature being 1000-1100 degrees Celsius, annealing time being 1-9 seconds.
10. A semiconductor structure, characterized by The method comprises: forming a semiconductor substrate; forming a heterojunction bipolar transistor structure on the semiconductor substrate, the heterojunction bipolar transistor comprising a collector, a base and an emitter successively stacked on a surface of the semiconductor substrate, a portion of a surface of the heterojunction bipolar transistor structure being formed with a high stress layer.
11. The semiconductor structure of claim 10, wherein, The heterojunction bipolar transistor structure comprises: a first dielectric layer and a second dielectric layer successively on a surface of the semiconductor substrate and a collector in the first dielectric layer and the second dielectric layer; a third dielectric layer, a polysilicon layer and a fourth dielectric layer successively on a surface of the collector and the second dielectric layer and a first opening through the fourth dielectric layer and the polysilicon layer and a second opening through the third dielectric layer, the second opening having a width greater than that of the first opening; a base on a bottom and a sidewall of the second opening; an emitter filling the first opening and the second opening and covering a surface of the fourth dielectric layer on a surface of the base; The emitter, the fourth dielectric layer, the polysilicon layer, the third dielectric layer and the second dielectric layer top and sidewall are formed with the high stress layer.
12. The semiconductor structure of claim 11, wherein, The base is subjected to a compressive stress of the emitter to a first preset value.
13. The semiconductor structure of claim 12, wherein, The first preset value is 2-5 GPa.
14. The semiconductor structure of claim 11, wherein, The base is subjected to a compressive stress of the polysilicon layer to a second preset value, and the second preset value is 2-5 GPa.