Semiconductor structure and forming method thereof
By employing the Certas chemical gas etching method and a two-step etching process to remove the mixed oxide layer of silicon and silicon-germanium stacked layers, the shape of the recesses and inner sidewalls in the gate ring device structure is optimized, solving the problem of unsatisfactory morphology in the prior art and improving the performance and reliability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2026-03-10
AI Technical Summary
In existing technologies, when fabricating gate-around device structures, it is difficult to effectively remove the mixed oxide layer on the sidewalls of the fins of the silicon and silicon-germanium stacked layers, resulting in an undesirable recess morphology that affects device performance and reliability.
The Certas chemical gas etching method is used to first remove the mixed oxide layer through a two-step etching process, and then form a rectangular recess and inner sidewall in an oxygen-free environment to optimize the shape of the recess and inner sidewall.
This improves device performance and reliability, avoids the blocking effect of mixed oxide layers, and ensures precise morphological control of recesses and inner sidewalls.
Smart Images
Figure CN121645925A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] In fabricating gate-all-around (GAA) device structures, lateral etching is performed on the stacked silicon and silicon-germanium layers to form recesses, within which inner spacers are formed. The inner spacers primarily function to regulate the parasitic capacitance and resistance of the device, significantly impacting its performance. Low-dielectric-constant materials such as silicon nitride are typically used for the inner spacers. The inner spacers mainly reduce leakage current between the gate and the source / drain. If the inner spacers are too thin, they increase the parasitic capacitance between the gate and the source / drain; if they are too thick, they increase the parasitic resistance, significantly affecting the conduction current. The inner spacers also act as a barrier layer during subsequent channel relief, controlling the effective gate length and preventing etching from extending into the source / drain region.
[0003] Inner spacer cavity etching (ISCE) is one of the front-end processes that affects the morphology of the inner sidewalls. Due to the presence of a mixed oxide layer on the sidewalls of the silicon and silicon-germanium stacked layers that hinders etching, as well as the unevenness of the epitaxial process of the front-end germanium-silicon sacrificial layer, the sacrificial layer etching process not only causes significant silicon loss in the channel layer but also forms crescent-shaped recesses, thus creating crescent-shaped inner sidewalls. This type of inner sidewall morphology degrades device performance. Currently, the mixed oxide layer on the sidewalls of the silicon and germanium-silicon stacked layers in current gate-around device structures is mainly removed by hydrofluoric acid wet cleaning and BreakThrough etching. However, this pre-cleaning method cannot effectively remove germanium-silicon oxide and germanium oxide from the mixed oxide layer; it can only remove silicon oxide. The residual germanium-silicon oxide and germanium oxide after pre-cleaning and BreakThrough etching still hinder the main etching step of the sacrificial layer. Furthermore, there is still a risk of re-oxidation in the fin area before entering the sacrificial layer etching chamber after pre-clean wet cleaning.
[0004] Therefore, this invention proposes a two-step etching method based on Certas chemical gas etching. By adjusting process parameters, a first etching process removes the fin mixing barrier layer and part of the silicon-germanium-silicon stack layer. The silicon-germanium-silicon stack layer without any mixing barrier layer is then fully exposed to the second etching process, which etches the sacrificial layer. Optimizing the recess and inner sidewall shape reduces silicon loss in the channel layer, thereby improving device performance and reliability. Summary of the Invention
[0005] This application provides a semiconductor structure and a method for forming the same, which can optimize the shape of the recess and inner sidewall in the gate ring device structure, thereby improving device performance and reliability.
[0006] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a fin is formed on the surface of the semiconductor substrate, the fin comprising a plurality of sequentially stacked sacrificial layers and channel layers, and a mixed oxide layer is formed on the sidewalls of the fin; performing a first etching process to remove the mixed oxide layer; performing a second etching process to etch the sacrificial layer to form recesses on both sides of the sacrificial layer, the recesses being rectangular; forming inner sidewalls in the recesses; forming source / drain layers on the semiconductor substrate surfaces on both sides of the fin; removing the sacrificial layer and forming a metal gate at the location of the sacrificial layer.
[0007] In some embodiments of this application, the first etching process also etches away a portion of the sidewall of the fin.
[0008] In some embodiments of this application, the first etching process has the same etching selectivity for the fins and the mixed oxide layer.
[0009] In some embodiments of this application, the channel layer is made of silicon, the sacrificial layer is made of silicon-germanium, the mixed oxide layer is made of silicon oxide, germanium oxide, and germanium-silicon oxide, and the first etching process has the same etching selectivity for the silicon, silicon-germanium, silicon oxide, germanium oxide, and germanium-silicon oxide.
[0010] In some embodiments of this application, the process parameters of the first etching process include: the etching gas includes a fluorine-based gas and an inert gas, wherein the volume ratio of the fluorine-based gas to the inert gas is 1:10; the etching temperature is 20 to 30°C; the etching pressure is 250 to 350 mTor r; and the etching time is 10 to 20 s.
[0011] In some embodiments of this application, the first etching process and the second etching process are performed in the same etching equipment.
[0012] In some embodiments of this application, the depth of the recess is 5 to 10 nanometers.
[0013] Another aspect of this application provides a semiconductor structure, comprising: a semiconductor substrate, wherein a fin is formed on the surface of the semiconductor substrate, the fin comprising a plurality of sequentially stacked metal gates and channel layers, wherein recesses are formed on both sides of the metal gates, the recesses being rectangular; an inner wall located in the recesses; and source / drain layers located on the semiconductor substrate surfaces on both sides of the fins.
[0014] In some embodiments of this application, the material of the channel layer includes silicon.
[0015] In some embodiments of this application, the depth of the recess is 5 to 10 nanometers.
[0016] This application provides a semiconductor structure and a method for forming the same. The mixed oxide layer on the sidewall of the fin is removed before the recess is formed, which can optimize the shape of the recess and inner sidewall in the gate ring device structure and improve device performance and reliability. Attached Figure Description
[0017] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0018] in:
[0019] Figures 1 to 7 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation
[0020] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0021] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.
[0022] Figures 1 to 7 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.
[0023] refer to Figure 1 As shown, a semiconductor substrate 100 is provided, and a fin 110 is formed on the surface of the semiconductor substrate 100. The fin 110 includes a plurality of sequentially stacked sacrificial layers 111 and channel layers 112, and a mixed oxide layer 130 is formed on the sidewall of the fin 110.
[0024] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.
[0025] In some embodiments of this application, the semiconductor structure is, for example, a GAA gate-around device.
[0026] In some embodiments of this application, a plurality of fins 110 may be formed on the semiconductor substrate 100. For the purpose of simplicity, only one fin 110 is shown as an example in this embodiment.
[0027] In some embodiments of this application, the sacrificial layer 111 is made of silicon-germanium, and the channel layer 112 is made of silicon.
[0028] In some embodiments of this application, the number of sacrificial layers 111 and channel layers 112 is multiple. In this embodiment, only three sacrificial layers 111 and three channel layers 112 are used as an example.
[0029] In conventional processes, subsequent etching of the sidewalls of the fin 110 to form recesses results in crescent-shaped recesses and significant silicon loss in the channel layer. This undesirable recess and channel layer morphology is primarily due to the failure to effectively remove the mixed oxide layer on the fin sidewalls before the main etching. Existing solutions mainly employ hydrofluoric acid wet cleaning or plasma cyclic oxidation etching to reduce the crescent-shaped recesses. However, the applicant of this application discovered through experiments and testing that the sidewalls of the fin 110 are oxidized when exposed to air before the recess process. The materials of the sacrificial layer 111 and the channel layer 112 (containing silicon and oxygen atoms) are oxidized to form oxides such as silicon oxide, germanium oxide, and germanium silicon oxide. These oxides form the mixed oxide layer 130 on the sidewalls of the fin 110. Furthermore, the silicon oxide, germanium oxide, and germanium silicon oxide in the mixed oxide layer 130 do not exhibit a clear distribution pattern; that is, they are mixed together. The morphology of the recess cannot be precisely controlled because the mixed oxide layer 130 blocks the etching process of the recess, resulting in an unsatisfactory morphology.
[0030] In some embodiments of this application, a gate structure 120 is further formed on the top of the fin 110. The gate structure 120 includes a gate oxide layer, a gate layer, a mask layer, and a sidewall layer located sequentially on the surface of the fin 110.
[0031] refer to Figure 2As shown, the first etching process is performed to remove the mixed oxide layer 130. The technical solution of this application removes the mixed oxide layer 130 before forming the recess, thus avoiding the influence of the mixed oxide layer 130 and forming a recess with an ideal morphology.
[0032] In some embodiments of this application, the first etching process exhibits similar etching selectivity for germanium oxide, germanium-silicon, and silicon. Since the mixed oxide layer 130 contains germanium-oxygen, germanium-silicon, and silicon-silicon bond energies that are close, Certas chemical etching using the first etching process can effectively remove germanium oxide, germanium-silicon, and silicon, while BT etching based on the Certas principle can effectively remove silicon oxide. Conventional BT etching can only remove silicon oxide from the mixed oxide layer and cannot remove germanium oxide and germanium-silicon oxide, resulting in residual germanium oxide in the mixed oxide layer 130 that blocks the main etching of the sacrificial layer.
[0033] In some embodiments of this application, the etching selectivity of the first etching process for the mixed oxide layer 130 and the fin 110 is close. That is, the etching rate of the first etching process for silicon oxide, germanium oxide, and germanium-silicon oxide is close to the etching rate of the first etching process for silicon and silicon-germanium, and the sidewalls of the mixed oxide layer 130 and the fin 110 are completely removed by controlling the etching time of the first etching process. The lost critical dimensions of the fin can be compensated for in the front-end process.
[0034] Figure 3 This is a schematic diagram of the structure after the first etching process in some other embodiments of this application.
[0035] refer to Figure 3 As shown, in some embodiments of this application, the first etching process further etches away a portion of the sidewalls of the fin 110, making the width of the fin 110 slightly smaller than the width of the gate structure 120. This approach is also to further ensure the complete removal of the mixed oxide layer 130. The first etching process penetrates deep into the sidewalls of the fin 110 to ensure the cleanliness of the sidewalls of the fin 110.
[0036] In some embodiments of this application, the first etching process has the same etching selectivity for both the fin 110 and the mixed oxide layer 130. In this approach, both the fin 110 and the mixed oxide layer 130 are etched, therefore their etching selectivity can be the same. It should be noted that the statement in this application regarding the same etching selectivity can also be understood as having similar etching selectivity, because it is unrealistic to have exactly the same selectionivity, and a reasonable margin of error is permissible.
[0037] In some embodiments of this application, the first etching process has the same etching selectivity for the silicon, silicon-germanium, silicon oxide, germanium oxide, and germanium-silicon oxide.
[0038] In some embodiments of this application, the process parameters of the first etching process include: based on the Certas chemical dry etching principle, the main etching gas is a fluorine-based gas (F*Gas), and the inert gas includes, but is not limited to, nitrogen (N2), argon (Ar), and helium (He). The ratio of the main etching gas to the inert gas is 1:10, the temperature is 20-30℃, the etching pressure is 300mTorr, and the etching time is selected as 10-20s according to the previous conditions.
[0039] refer to Figure 4 As shown ( Figure 2 (In subsequent steps), a second etching process is performed to etch the sacrificial layer 111, forming recesses 140 on both sides of the sacrificial layer 111. The recesses 140 are rectangular. Due to the absence of interference from the mixed oxide layer, the second etching process can form ideal rectangular recesses. It should be noted that the recesses 140 are not necessarily perfectly rectangular; the edges and corners of the recesses 140 may have undulations or rounded corners caused by the etching process itself. The technical solution of this application requires that the top and bottom surfaces of the sacrificial layer 111 are also etched and recessed, without forming a crescent shape.
[0040] In some embodiments of this application, the first etching process and the second etching process are performed in the same etching apparatus, and the etching apparatus is an oxygen-free environment. Performing the first etching process and the second etching process in an oxygen-free environment and in the same apparatus is to prevent the sidewall of the fin 110 from being re-oxidized before the second etching process after the mixed oxide layer 130 has been removed by the first etching process.
[0041] In some embodiments of this application, the etching selectivity ratio of the second etching process for the sacrificial layer 111 and the channel layer 112 is greater than 10:1.
[0042] In some embodiments of this application, the process parameters of the second etching process include: based on the Certas chemical dry etching principle, the main etching gas is a fluorine-based gas (F*Gas), and the inert gas includes, but is not limited to, nitrogen (N2), argon (Ar), and helium (He). The ratio of the main etching gas to the inert gas is 1:3, the temperature is 30°C, the etching pressure is 400 mTorr, and the etching time is selected as a short-second multi-cycle etching mode based on the previous conditions.
[0043] In some embodiments of this application, the depth of the recess 140 is 5 to 10 nanometers.
[0044] In some embodiments of this application, the method of forming the semiconductor structure further includes forming an inner sidewall in the recess 140. The material of the inner sidewall includes silicon nitride.
[0045] refer to Figure 5As shown, an inner sidewall 150 is formed in the recess 140.
[0046] In some embodiments of this application, the material of the inner sidewall 150 includes insulating materials such as silicon oxide or silicon nitride.
[0047] In some embodiments of this application, the method of forming an inner sidewall 150 in the recess 140 includes: forming a sidewall material layer on the surface of the semiconductor substrate 100, the sidewall of the fin 110, and the sidewall and top of the hard mask layer 120; removing the sidewall material layer other than the recess 140, and retaining only the sidewall material layer located in the recess 140 as the inner sidewall 140.
[0048] refer to Figure 6 As shown, source / drain layers 160 are formed on the surface of semiconductor substrates 100 on both sides of the fin 110.
[0049] In some embodiments of this application, the method of forming the source / drain layer 160 includes: forming the source / drain layer 160 using an in-situ doped epitaxial growth process on the surface of the semiconductor substrate 100 as a substrate.
[0050] In some embodiments of this application, the source / drain layer 160 is made of doped silicon-germanium material.
[0051] refer to Figure 7 As shown, the sacrificial layer 111 is removed and a metal gate 113 is formed at the location of the sacrificial layer 111.
[0052] In some embodiments of this application, the method for removing the sacrificial layer 111 includes a wet etching process.
[0053] In some embodiments of this application, the material of the metal gate 113 includes at least one or more of titanium, titanium nitride, copper, or aluminum.
[0054] This application provides a method for forming a semiconductor structure, which involves first removing the mixed oxide layer from the sidewall of the fin and then forming the recess, thereby optimizing the shape of the recess and inner sidewall in the gate ring device structure and improving device performance and reliability.
[0055] Embodiments of this application also provide a semiconductor structure, referencing Figure 4 As shown, it includes: a semiconductor substrate 100, on the surface of which a fin 110 is formed, the fin 110 including a plurality of sequentially stacked metal gates 113 and channel layers 112, the metal gates 113 having recesses on both sides, the recesses being rectangular; an inner sidewall 150 located in the recesses; and a source / drain layer 160 located on the surface of the semiconductor substrate 100 on both sides of the fin 110.
[0056] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.
[0057] In some embodiments of this application, the semiconductor structure is, for example, a GAA gate-around device.
[0058] In some embodiments of this application, the semiconductor structure may be formed by the aforementioned semiconductor structure formation method.
[0059] In some embodiments of this application, a plurality of fins 110 may be formed on the semiconductor substrate 100. For the purpose of simplicity, only one fin 110 is shown as an example in this embodiment.
[0060] In some embodiments of this application, the material of the metal gate 113 includes at least one or more of titanium, titanium nitride, copper or aluminum, and the material of the channel layer 112 is silicon.
[0061] In some embodiments of this application, the number of metal gate 113 and channel layer 112 is multiple. In this embodiment, only three-layer metal gate 113 and three-layer channel layer 112 are used as examples.
[0062] In some embodiments of this application, a gate structure 120 is further formed on the top of the fin 110. The gate structure 120 includes a gate oxide layer, a gate layer, a mask layer, and a sidewall layer located sequentially on the surface of the fin 110.
[0063] refer to Figure 3 As shown, in some other embodiments of this application, the width of the fin 110 is slightly smaller than the width of the gate structure 120.
[0064] In some embodiments of this application, the depth of the recess 140 is 5 to 10 nanometers.
[0065] In some embodiments of this application, the semiconductor structure further includes an inner sidewall 160 formed in the recess 140. The material of the inner sidewall includes silicon nitride.
[0066] In some embodiments of this application, the source / drain layer 160 is made of doped silicon-germanium material.
[0067] This application provides a semiconductor structure and a method for forming the same. The mixed oxide layer on the sidewall of the fin is removed before the recess is formed, which can optimize the shape of the recess and inner sidewall in the gate ring device structure and improve device performance and reliability.
[0068] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0069] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0070] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0071] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0072] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method of forming a semiconductor structure, characterized by, The application relates to a semiconductor substrate manufacturing method. The method comprises the following steps: providing a semiconductor substrate, a fin is formed on the surface of the semiconductor substrate, the fin comprises a plurality of sequentially stacked sacrificial layers and channel layers, and a mixed oxide layer is formed on the sidewall of the fin; performing a first etching process to remove the mixed oxide layer; performing a second etching process to etch the sacrificial layer and form a recess on both sides of the sacrificial layer, the recess is rectangular; forming an inner sidewall in the recess; forming a source-drain layer on the surface of the semiconductor substrate on both sides of the fin; 2. The method of forming a semiconductor structure of claim 1, wherein, removing the sacrificial layer and forming a metal gate in the position of the sacrificial layer.
3. The method of forming a semiconductor structure of claim 2, wherein, The first etching process also etches and removes part of the sidewall of the fin.
4. The method of forming a semiconductor structure of claim 3, wherein, The etching selectivity of the first etching process on the fin and the mixed oxide layer is the same.
5. The method of forming a semiconductor structure of claim 4, wherein, The material of the channel layer comprises silicon, the material of the sacrificial layer comprises silicon germanium, the material of the mixed oxide layer comprises silicon oxide, germanium oxide and germanium silicon oxide, and the etching selectivity of the first etching process on the silicon, silicon germanium, silicon oxide, germanium oxide and germanium silicon oxide is the same.
6. The method of forming a semiconductor structure of claim 1, wherein, The process parameters of the first etching process comprise the following steps: the etching gas comprises fluorine-based gas and inert gas, the volume ratio of the fluorine-based gas and the inert gas is 1:10; the etching temperature is 20-30 DEG C; the etching pressure is 250-350 mTor r; and the etching time is 10-20 s.
7. The method of forming a semiconductor structure of claim 1, wherein, The first etching process and the second etching process are completed in the same etching equipment.
8. A semiconductor structure, characterized by The depth of the recess of the sacrificial layer is 5-10 nanometers. The application relates to a semiconductor substrate manufacturing method. The method comprises the following steps: providing a semiconductor substrate, a fin is formed on the surface of the semiconductor substrate, the fin comprises a plurality of sequentially stacked sacrificial layers and channel layers, and a mixed oxide layer is formed on the sidewall of the fin; 9. The semiconductor structure of claim 8, wherein, performing a first etching process to remove the mixed oxide layer; 10. The semiconductor structure of claim 8, wherein, performing a second etching process to etch the sacrificial layer and form a recess on both sides of the sacrificial layer, the recess is rectangular; forming an inner sidewall in the recess; forming a source-drain layer on the surface of the semiconductor substrate on both sides of the fin; removing the sacrificial layer and forming a metal gate in the position of the sacrificial layer. The first etching process also etches and removes part of the sidewall of the fin. The first etching process also etches and removes part of the sidewall of the fin. The etching selectivity of the first etching process on the fin and the mixed oxide layer is the same. The material of the channel layer comprises silicon, the material of the sacrificial layer comprises silicon germanium, the material of the mixed oxide layer comprises silicon oxide, germanium oxide and germanium silicon oxide, and the etching selectivity of the first etching process on the silicon, silicon germanium, silicon oxide, germanium oxide and germanium silicon oxide is the same. The process parameters of the first etching process comprise the following steps: the etching gas comprises fluorine-based gas and inert gas, the volume ratio of the fluorine-based gas and the inert gas is 1:10; the etching temperature is 20-30 DEG C; the etching pressure is 250-350 mTor r; and the etching time is 10-20 s. The first etching process and the second etching process are completed in the same etching equipment. The depth of the recess of the sacrificial layer is 5-10 nanometers. The application relates to a semiconductor substrate manufacturing method. The method comprises the following steps: providing a semiconductor substrate, a fin is formed on the surface of the semiconductor substrate, the fin comprises a plurality of sequentially stacked sacrificial layers and channel layers, and a mixed oxide layer is formed on the sidewall of the fin; performing a first etching process to remove the mixed oxide layer; performing a second etching process to etch the sacrificial layer and form a recess on both sides of the sacrificial layer, the recess is rectangular; forming an inner sidewall in the recess; forming a source-drain layer on the surface of the semiconductor substrate on both sides of the fin; removing the sacrificial layer and forming a metal gate in the position of the sacrificial layer. The first etching process also etches and removes part of the sidewall of the fin. The first etching process also etches and removes part of the sidewall of the fin. The etching selectivity of the first etching process on the fin and the mixed oxide layer is the same. The material of the channel layer comprises silicon. The depth of the recess is 5-10 nanometers.