Preparation method of thin film transistor

Abstract

The invention discloses a preparation method of a thin film transistor. The core of the preparation method is to construct a quasi-double-channel structure. Taking an insulating layer of the thin film transistor as a first metal oxide, and processing the surface of the insulating layer to obtain an oxygen-deficient surface; depositing a second metal oxide on the anoxic surface as a channel layer; a metal-oxygen bond of the insulating layer is higher than a metal-oxygen bond of the channel layer; and after the deposition of the second metal oxide is finished, a two-dimensional oxygen-deficient surface is spontaneously formed on the contact surface of the insulating layer and the channel layer through annealing treatment, so that the thin film transistor with the quasi-double-channel structure is obtained. Compared with a traditional thin film transistor, the thin film transistor has the advantages that the positive bias voltage stability and the negative bias voltage stability are obviously improved, and meanwhile, the mobility is greatly improved. The invention has the characteristics of high carrier mobility, small threshold voltage drift and high long-term working reliability, and is simple in preparation process and low in cost. The quasi-double-channel structure is expected to be widely applied to oxide thin film transistors.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and microelectronic devices, and specifically relates to a thin-film transistor and its manufacturing method. Background Technology

[0002] Thin-film transistors (TFTs) are widely used in logic circuits, memory, and display devices. In recent years, metal-oxide-slim TFTs (MO TFTs) have received increasing attention and research due to their high electron mobility and excellent optical transparency. In mainstream display technologies such as liquid crystal displays (LCDs), organic light-emitting diode displays (OLEDs), and emerging micro-LED displays (Micro-OLEDs / Micro-LEDs), TFTs play a crucial role in pixel driving, signal transmission, and current control. Their electrical performance indicators, especially electrical stability and carrier mobility, have become the core bottleneck restricting the development of display devices towards higher resolution, higher refresh rates, lower power consumption, and greater flexibility.

[0003] On the one hand, carrier mobility directly affects the switching speed and driving capability of TFTs: high mobility devices can achieve faster signal response, reduce pixel charging time, and thus support higher screen refresh rates (such as 240Hz and above), while reducing driving voltage to achieve low power consumption design; on the other hand, electrical stability determines the long-term reliability of devices, especially in the repeated bending, high temperature and high humidity environment of flexible displays, or under long-term high voltage stress, stability problems such as threshold voltage drift and increased leakage current of TFTs will directly lead to image retention, uneven brightness or even driving failure, seriously shortening the service life of terminal products. Current mainstream TFT technology still faces the technical dilemma of balancing electrical stability and mobility, with significant performance shortcomings in each system. Among them, metal-oxide thin-film transistors (such as IGZO, IZO and other semiconductor material systems) are limited by oxygen vacancy defects and interface contact problems in the semiconductor layer, making them prone to charge trapping / releasing under bias or light stress, resulting in significant threshold voltage drift. On the other hand, Schottky barriers or interface states are easily formed at the interface between the metal electrode and the oxide semiconductor layer, which not only reduces carrier transport efficiency but also exacerbates leakage current and stability degradation during long-term use. WO2022267043A1 discloses an oxide thin-film transistor (TFT) employing a multilayer insulating oxide structure. Adjusting the density and thickness of the insulating layer effectively prevents oxygen escape and hydrogen ingress, ensuring oxygen fixation in the oxide semiconductor layer and thus improving the TFT's stability. However, this only addresses one aspect of NBS stability (preventing oxygen vacancies), failing to resolve the poor PBS stability issue, remaining hampered by the "seesaw effect," and offering no benefit to device mobility. WO2023024116A1 discloses a TFT that forms a metal oxide semiconductor crystal in the semiconductor layer, utilizing a metal-induced layer to create a crystallization interface between the oxide semiconductor and the metal. While this improves mobility, it doesn't directly resolve the PBS / NBS stability contradiction related to oxygen vacancies and interstitial oxygen. Furthermore, uneven crystallization or grain boundaries can introduce new instabilities. On the other hand, it relies on heat treatment to drive crystallization, requiring precise temperature control. CN103545377A discloses an oxide thin-film transistor that uses alternating layers of hafnium-neodymium alloy thin films and IGZO thin films to control threshold voltage and subthreshold swing. This method is complex and costly. While it reduces oxygen vacancies (beneficial for NBS), it does not explain how to address the instability of PBS under oxygen-rich conditions. The introduced metal impurities themselves may also become a new source of instability. CN107408579A discloses a transistor including an oxide semiconductor film, using a stacked structure of a first oxide semiconductor film and a second oxide semiconductor film to suppress variations in electrical characteristics. This structure is complex and difficult to manufacture. CN114122012A discloses a method to improve the mobility of oxide TFTs by controlling the oxygen vacancy content in a metal oxide insulating layer through laser irradiation, but this does not improve device stability. Furthermore, laser irradiation carries a risk of leakage current, as it may generate a large number of oxygen vacancies within the metal oxide insulating layer, thus failing to provide insulation.

[0004] In summary, there is a constraint between the device mobility and stability (negative bias stability and positive bias stability) of oxide thin-film transistors. Current thin-film transistor technology still faces significant technical bottlenecks in synergistically improving electrical stability and carrier mobility. Existing optimization schemes cannot simultaneously meet the industrialization requirements of high mobility, high stability, low cost, and large-area flexible fabrication. Therefore, developing a thin-film transistor that can simultaneously improve carrier mobility and long-term electrical stability has become a key technical problem urgently needing to be solved in this field. Summary of the Invention

[0005] Based on the technical bottlenecks of existing technologies, this invention proposes a thin-film transistor and its fabrication method, which overcomes the shortcomings of existing thin-film transistor technologies in that it is difficult to balance electrical stability (PBS / NBS) and carrier mobility. It provides a high-stability, high-mobility thin-film transistor that significantly improves the carrier mobility and electrical stability of oxide TFTs without sacrificing off-state performance.

[0006] The inventive concept of this invention is to improve performance through chemical modification of the heterojunction interface in the vertical direction, utilizing the bond energy difference between different oxides to spontaneously form a functional interface. After the insulating layer is deposited on the substrate surface, oxygen vacancies are created on the surface of the insulating layer to form an oxygen-deficient surface. Then, the channel layer is deposited on the oxygen-deficient surface. After deposition, an annealing treatment is performed, and a two-dimensional oxygen-deficient interface is naturally formed at the interface where the insulating layer and the channel layer contact. The conductivity of the two-dimensional oxygen-deficient interface is higher than that of the rest of the channel layer.

[0007] This invention provides a method for fabricating a thin-film transistor, specifically including the following steps: (a) A conductive thin film is deposited sequentially on the substrate as a gate and a first metal oxide layer as an insulating layer.

[0008] (b) The first metal oxide is treated to form an oxygen-deficient surface rich in oxygen vacancies on its surface.

[0009] (c) A second metal oxide layer is deposited on the oxygen-deficient surface as a channel layer, wherein the metal-oxygen bond energy of the first metal oxide is higher than that of the second metal oxide. For example, the second metal oxide is tantalum-doped tin oxide (TaSnO). x The first metal oxide (TTO) includes tin oxide (SnO2), indium oxide (In2O3), zinc oxide (ZnO), indium gallium zinc oxide (In-Ga-Zn-O), indium tin oxide (In-Sn-O), zinc tin oxide (Zn-Sn-O), etc. For example, the first metal oxide includes zirconium oxide, gallium oxide, aluminum oxide, or hafnium oxide.

[0010] After the second metal oxide deposition is completed, an annealing process is performed to form a two-dimensional oxygen-deficient interface at the interface between the insulating layer and the channel layer, thus constituting a quasi-dual-channel structure. Preferably, the annealing process is performed under an inert atmosphere, a reducing atmosphere, a vacuum, or an air atmosphere at a temperature of 300°C to 450°C.

[0011] (d) Deposit source and drain electrodes on the channel layer and anneal the device.

[0012] Furthermore, the oxygen-deficient surface formed in step b is achieved through one of the following methods: controlled annealing atmosphere treatment, plasma treatment, or acid etching treatment. Controlled annealing atmosphere treatment refers to annealing under a vacuum atmosphere or a reducing atmosphere, wherein the vacuum atmosphere has a pressure less than 10... -5 Torr, the reducing atmosphere is argon or a N2 / H2 mixture containing a small amount of H2, the annealing temperature is 100℃~600℃, and the time is 0.5 to 3 hours. Plasma treatment refers to placing the sample in a plasma device for physical bombardment in an inert atmosphere, or performing chemical reduction in a reducing atmosphere, with a treatment power of 50W~150W, a gas pressure of 1Pa~10Pa, and a time of 30 seconds to 5 minutes. The acid etching treatment refers to surface etching with dilute hydrofluoric acid solution or dilute hydrochloric acid for 5 seconds to 300 seconds.

[0013] Furthermore, in step a, the insulating layer is deposited using magnetron sputtering. Specific process parameters are as follows: deposition at room temperature, using a ceramic target, an oxygen / argon ratio of (0~4):(26~30) sccm, a sputtering power of 50W~200W, and a working pressure of 0.5Pa~0.6Pa. The ceramic target is at least one of zirconium oxide, gallium oxide, aluminum oxide, or hafnium oxide. Alternatively, this step can be performed using electron beam evaporation deposition or chemical vapor deposition, depending on the specific requirements.

[0014] Furthermore, step c employs magnetron sputtering to deposit the channel layer. Specific process parameters are: oxygen / argon mixed gas ratio (1~4):(26~29) sccm; working pressure 0.1~1.0 Pa; sputtering power 50W~200W; and substrate temperature controlled between room temperature and 300℃. Alternatively, electron beam evaporation deposition or chemical vapor deposition can be used for this step, depending on the specific requirements.

[0015] In some preferred embodiments, the substrate after the deposition of the source electrode and the drain electrode is performed annealing in N2 or vacuum at a temperature of 200°C to 350°C.

[0016] The source / drain electrode material is one of aluminum, titanium, indium, molybdenum, Ti / Au, Ti / Al, or indium tin oxide. Preferably, the substrate can also be a quartz wafer, in which case the gate electrode needs to be deposited on the surface of the quartz wafer first, followed by the deposition of an insulating layer, and then the above steps are followed.

[0017] This invention also provides an enhanced-channel thin-film transistor, fabricated according to the above method. The thin-film transistor has a bottom-gate top-contact structure, with a heavily doped low-resistivity silicon wafer as the substrate. An insulating layer is located above the substrate, followed by a semiconductor channel layer, and then source / drain electrodes are positioned above the semiconductor channel layer. The semiconductor channel layer has a thickness of 2 nm to 60 nm and a resistivity of 10⁻⁶. 2 ~10 3Ω·cm; insulation layer thickness 3nm~60nm.

[0018] This invention offers the following advantages: By utilizing the bond energy difference between the insulating layer (first metal oxide) and the channel layer (second metal oxide), where the metal-oxygen bond energy of the first metal oxide is higher than that of the second metal oxide, an oxygen-deficient surface is formed on the surface of the insulating layer. This allows the oxygen-deficient insulating layer (first metal oxide) to "capture" oxygen from the channel layer (second metal oxide), artificially creating a high-carrier-concentration two-dimensional oxygen-deficient conductive layer at the channel layer / insulating layer interface. This is also referred to as a two-dimensional oxygen-deficient interface. Although this two-dimensional oxygen-deficient interface itself contains oxygen vacancies, it is a "surface," not a solid entity with thickness, forming a "quasi-dual-channel" structure. Unlike traditional dual-channel structures with finite-thickness oxygen-deficient layers, it does not experience internal defect redistribution due to an electric field. Therefore, under positive bias, it effectively suppresses the electron trapping process, exhibiting significant PBS stability.

[0019] This invention employs a precise, synergistic design of "bulk oxygen enrichment + interface oxygen deficiency" through a two-dimensional oxygen-deficient interface, enabling the device to simultaneously achieve high on-state current and extremely low off-state current, resulting in a very high on / off ratio. It also solves the major challenges of PBS and NBS, achieving comprehensive stability unattainable by traditional single-channel and dual-channel methods. Compared to bulk doping methods, this interface modulation is a more refined and advanced physical mechanism, better balancing the device's various performance indicators.

[0020] Based on a unique "quasi-dual-channel" structure, the instability problem of traditional oxide thin-film transistors under positive and negative bias (PBS / NBS) is effectively overcome from a mechanistic perspective. It exhibits superior performance in mobility, on / off ratio, and threshold voltage stability, achieving long lifespan and high reliability in practical applications.

[0021] The process of this invention offers significant advantages: the core functional interface is spontaneously formed, requiring no additional photolithography steps. Compared to the complex processes added to build "stepped layers," this invention achieves high performance while being simpler and more efficient in process integration. The all-vacuum process results in higher film quality and cleaner interfaces, leading to better device performance and stability. Furthermore, it does not use any precious metals, resulting in low material costs. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the thin-film transistor of the present invention.

[0023] Figure 2 This describes the fabrication process of the thin-film transistor of this invention.

[0024] Labeling explanation: 1. Substrate; 2. Insulating layer; 3. Channel layer; 4. Source electrode; 5. Drain electrode. Detailed Implementation

[0025] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0026] In practical applications, thin-film transistors inevitably experience both positive bias (PBS) and negative bias (NBS) stresses simultaneously. If these stresses cause a shift in the threshold voltage, it may lead to non-uniformity in the display screen. Related research reports that oxygen-rich devices fabricated from amorphous oxide semiconductors (AOS), such as IGZO, exhibit high stability only under negative bias stress, while devices with insufficient oxygen content remain stable only under positive bias stress.

[0027] This invention aims to solve the bias instability problem of traditional oxide thin-film transistors. Its core technical solution is to construct a "quasi-dual-channel" structure. The formation mechanism of this structure is as follows: First, the first metal oxide, which serves as the insulating layer 2, is pretreated (e.g., high-temperature annealing) to artificially create an oxygen-deficient surface rich in oxygen vacancies on its surface.

[0028] Subsequently, a second metal oxide is deposited on this oxygen-deficient surface as the channel layer 3. Crucially, the metal-oxygen bond energy of the insulating layer 2 is designed to be higher than that of the channel layer 3. Therefore, upon contact, the insulating layer 2, with its stronger oxygen binding capacity, "steals" oxygen atoms from the adjacent channel layer 3. This process spontaneously forms a stable, oxygen-vacancy-rich thin layer (i.e., electron donor) in the region of the channel layer 3 near the interface, which we call a "two-dimensional oxygen-deficient interface."

[0029] This two-dimensional oxygen-deficient interface formed at the interface constitutes the core part with the highest conductivity in the entire conductive channel. It is not an independent conducting layer unaffected by the gate, but rather serves as the "foundation" of the entire single-function channel. When the device is turned on, the charge carriers induced by the gate electric field preferentially transport in this high-quality, high-concentration interface layer, thus achieving high mobility and low turn-on voltage. Therefore, the entire channel is a unified structure with a vertically gradient distribution of charge carrier concentration, rather than two parallel transport paths. The final annealing treatment of the entire device primarily aims to improve electrode contact and stabilize overall device performance.

[0030] It is called a "quasi-dual-channel" because it is not achieved by stacking two different channel materials, but by creating an additional conductive layer within a single channel material through ingenious interface engineering. This structure can provide a high concentration of charge carriers to significantly improve mobility, while effectively shielding and compensating for charge trapping caused by gate bias, thus solving the stability problem under both positive and negative biases.

[0031] See Figure 2 The present invention includes the following steps: cleaning the surface of substrate 1 → depositing an insulating layer 2 → creating an oxygen-deficient surface on the surface of the insulating layer 2 → depositing a channel layer 3 on the oxygen-deficient surface of the insulating layer 2 → annealing treatment → depositing a source electrode 4 and a drain electrode 5.

[0032] Preferably, the substrate 1 is selected from a heavily doped low-resistivity silicon substrate or a quartz wafer. The heavily doped low-resistivity silicon wafer serves as both the substrate and the gate. If a quartz wafer is used as the substrate 1, a conductive thin film is first deposited as the gate, and then an insulating layer 2 is deposited on the surface of the gate.

[0033] Comparative Example 1: Surface-enriched silicon dioxide serves as the insulating layer. According to existing technology, a heavily doped low-resistivity silicon wafer is used as substrate 1. After cleaning the surface of substrate 1, an insulating layer 2, a channel layer 3, a source electrode 4, and a drain electrode 5 are sequentially deposited on its surface. The insulating layer 2 is silicon oxide, and the channel layer 3 is TTO with a tantalum doping concentration of 1~3 at%. After the silicon oxide deposition, no pretreatment is performed on the insulating layer 2, meaning that the insulating layer 2 has no oxygen-deficient surface. The channel layer 3, source electrode 4, and drain electrode 5 are sequentially deposited on the silicon oxide to obtain a thin-film transistor.

[0034] Example 1, using TTO / HfO x Taking thin-film transistors as an example, the fabrication process is explained.

[0035] A schematic diagram of the thin-film transistor structure in Example 1 is shown below. Figure 1 As shown, from bottom to top, it includes: substrate 1, insulating layer 2, channel layer 3 (semiconductor material), source electrode 4, and drain electrode 5. The substrate is selected from heavily doped low-resistivity silicon wafers, and the insulating layer 2 is HfO with an oxygen-deficient surface. x Thin film. Channel layer 3 is oxygen-rich tantalum-doped tin oxide (TTO, tantalum doping concentration of 1~3 at%). Taking advantage of the fact that Hf-O bonds (801.7 kJ / mol) are significantly stronger than Sn-O bonds (531.8 kJ / mol), a two-dimensional oxygen-deficient interface is naturally formed at the interface of channel layer 3 / insulator layer 2 after annealing.

[0036] Example 1 was prepared according to the following procedure.

[0037] (a) Cleaning of the surface of substrate 1.

[0038] Before use, substrate 1 is immersed in a hydrofluoric acid aqueous solution for etching to remove the surface oxide layer. Substrate 1 is then sequentially placed in beakers containing acetone, anhydrous ethanol, and deionized water for ultrasonic cleaning for 5–15 minutes each. After cleaning, the silicon wafer surface is thoroughly dried using high-purity nitrogen gas.

[0039] (ii) An insulating layer 2 is deposited on the substrate 1, and an oxygen-deficient surface is formed on the surface of the insulating layer 2.

[0040] This step can be performed by radio frequency magnetron sputtering, or, depending on the specific requirements, by electron beam evaporation deposition or chemical vapor deposition. Taking the deposition of a 15nm thick hafnium oxide film as an example, it is deposited at room temperature using radio frequency magnetron sputtering with a pure HfO2 ceramic target at a fixed oxygen / argon ratio of (0~4):(26~30) sccm, such as 4:26 sccm, 1:29 sccm, 2:28 sccm, 3:27 sccm, etc. The sputtering power is 50W~200W, and the working pressure is 0.5Pa~0.6Pa. The insulating layer thickness is 3nm-60nm.

[0041] In this embodiment, a metal oxide with a high dielectric constant is used to fabricate the insulating layer 2. Using a high dielectric constant material as the insulating layer 2 enhances the gate's control capability. According to the capacitance formula C=(k×ɛ0×A) / d, where k is the dielectric constant, with the gate area A and the insulating layer thickness d remaining constant, a higher dielectric constant k significantly increases the gate capacitance C. A higher gate capacitance means that at the same gate voltage, more charge can be induced in the channel, i.e., the gate has stronger control over the channel, thereby reducing the device's operating voltage, decreasing gate leakage current, and increasing the transistor's switching speed and transconductance. Besides hafnium oxide in this embodiment, the first metal oxide can also be zirconium oxide, gallium oxide, aluminum oxide, or other metal oxides.

[0042] (iii) Create oxygen vacancies on the surface of insulating layer 2 to form an oxygen-deficient surface.

[0043] Next, oxygen vacancies are created on the surface of insulating layer 2 to form an oxygen-deficient surface. The purpose of forming an oxygen-deficient surface is to subsequently form a thin layer with high conductivity at the interface of insulating layer 2 / channel layer 3. This is one of the key aspects of this invention.

[0044] This embodiment uses vacuum / reducing atmosphere annealing to create an oxygen-deficient surface on the surface of the insulating layer 2. The specific steps are as follows: the sample with the deposited insulating layer 2 is placed in a tube furnace or rapid heat treatment equipment, and annealed under high vacuum (vacuum degree less than 10). -5Annealing is performed under a reducing atmosphere (such as argon or a N2 / H2 mixture containing a small amount of H2). Annealing temperatures are set between 100-600℃, for example, 100℃, 200℃, 300℃, 350℃, 400℃, and 450℃. Annealing time is 30 minutes to 1 hour. The vacuum / reducing atmosphere annealing method is simple, highly controllable, and produces good uniformity, making it suitable for large-area samples. It also creates oxygen vacancies not only on the surface but also in the near-surface region.

[0045] The oxygen-deficient surface can also be formed by plasma treatment or acid etching. Plasma treatment involves placing the sample in a plasma device for physical bombardment in an inert atmosphere, or chemical reduction in a reducing atmosphere. The treatment power is 50W–150W, the pressure is 1Pa–10Pa, and the time is 30 seconds to 5 minutes. Plasma treatment is short and efficient; it is a low-temperature process, minimizing its impact on the thermal budget of subsequent processes; and its shallow penetration depth allows for precise creation of defects only on the outermost layer of the insulation layer without affecting the insulation performance of the main body of the insulation layer. Acid etching involves surface etching with dilute hydrofluoric acid solution or dilute hydrochloric acid for 5 to 10 seconds.

[0046] (iv) Sedimentary channel layer 3.

[0047] TTO is deposited on the insulating layer 2 after the previous step by magnetron sputtering as the channel layer 3.

[0048] TTO thin films are deposited at room temperature using an RF magnetron sputtering process. The sputtering power is 50W–200W, and the operating pressure is 0.1–1.0 Pa, preferably 0.5 Pa. A ceramic target with a tin oxide to tantalum oxide molar ratio of 98:2 is used, and different oxygen / argon gas mixture ratios are adjusted. TTO thin films with thicknesses ranging from 2 nm to 60 nm are deposited.

[0049] The working pressure refers to the total pressure within the chamber, which affects the plasma density and the mean free path of sputtered particles. Excessive pressure leads to frequent particle collisions, low energy, and poor film density; insufficient pressure results in unstable plasma. This invention controls the pressure within the range of 0.1–1.0 Pa. The high oxygen partial pressure environment ensures that the deposited TTO film is fully oxidized, and the ratio of the oxygen / argon mixture is a key parameter. In this embodiment, the oxygen / argon ratio can be 1:29 sccm, 2:28 sccm, 3:27 sccm, or 4:26 sccm.

[0050] Furthermore, heating the substrate during deposition can increase the migration ability of deposited atoms on the surface, contributing to the formation of films with better crystallinity and fewer defects. Films deposited at room temperature are typically amorphous. The preferred substrate temperature is controlled between room temperature and 300°C.

[0051] (v) Annealing treatment to form a "quasi-double groove" structure After depositing the TTO film using the above steps, an annealing treatment is performed. The annealing atmosphere is air, the annealing temperature is 300-450℃, and the annealing time is 0.5-3 hours. For example, annealing temperatures of 300℃, 350℃, 400℃, and 450℃ can be selected.

[0052] (vi) Deposition source electrode 4 and drain electrode 5 After annealing, source electrode 4 and drain electrode 5 with good ohmic contact are fabricated, completing the basic structure of the transistor. A metal with a work function matching or lower than the electron affinity of channel layer 3 is selected as source electrode 4 and drain electrode 5. For n-type oxide semiconductors, metals with low work functions can be selected, such as aluminum (Al), titanium (Ti), indium (In), molybdenum (Mo), etc., or Ti / Au, Ti / Al, or indium tin oxide, etc. Ti serves as the contact layer, forming good contact with channel layer 3, while Au or Al serves as the conductive layer, reducing the resistance of the electrodes themselves. In some preferred embodiments, a 60 nm thick indium tin oxide (ITO) layer is deposited by sputtering in a pure argon atmosphere as source electrode 4 and drain electrode 5.

[0053] Before depositing the source electrode 4 and the drain electrode 5, the surface of the channel layer 3 can be subjected to plasma treatment to optimize the contact interface. By lightly bombarding the surface of the channel layer 3 with argon ions, surface contaminants and the native oxide layer are removed, and even some oxygen vacancies are created on the surface to increase the surface carrier concentration, thereby promoting the formation of ohmic contacts and effectively reducing contact resistance.

[0054] After the source electrode 4 and drain electrode 5 are deposited, an annealing treatment is performed in N2 or vacuum at a temperature of 200℃-350℃. The purpose is to promote alloying between the metal and semiconductor, repair any damage that may have been caused by plasma processing, and further reduce contact resistance. This improves the film quality, interfacial contact, and overall electrical performance of the device, stabilizing it. Thus, the quasi-dual-channel TTO / HfO... x The fabrication process of the thin-film transistor is now complete.

[0055] The electrical performance of Example 1 and Comparative Example 1 was tested, including basic electrical characteristic tests and bias stability tests. All tests were performed using a semiconductor parameter analyzer (such as a Keithley 4200-SCS) in a vacuum probe station at room temperature and in a vacuum environment (<10). 2 (Pa) and conditions without light.

[0056] Basic electrical characteristic tests extract key performance parameters by measuring the transfer characteristic curves of the device. Example 1 test conditions: With the source-drain voltage (VDS) fixed at 1.0V, the gate voltage (VGS) is scanned from -5V to +5V to obtain the results of field-effect mobility, threshold voltage, and device on / off ratio.

[0057] To evaluate the stability of the device under long-term operation, positive and negative bias tests were performed. The test procedure was as follows: First, the initial transfer characteristic curve of the device was measured. Then, a constant gate bias voltage was applied, and immediately after the test, the transfer characteristic curve was measured again. The threshold voltage drift (ΔV) was evaluated by comparing the changes in the curves before and after the test. th The positive bias (PBS) test conditions are as follows: a certain gate voltage is applied while the source and drain are grounded (VDS=0V) for 3600 seconds. The negative bias (NBS) test conditions are as follows: a certain gate voltage is applied while the source and drain are grounded (VDS=0V) for 3600 seconds.

[0058] The device prepared in Example 1 was found to have a field-effect mobility of approximately 7-10 cm⁻¹. 2 V -1 s -1 With a threshold voltage of 0.2V to 0.5V and a VDS of 1V, the device's on / off ratio is approximately 1×10⁻⁶. 6 ~5×10 7 The subthreshold swing is approximately 0.1~0.2Vdec. -1 The test results of the transfer characteristic curves showed that after 3600 seconds, the threshold voltage change of NBS and PBS was about 0.1V, or even less than 0.1V.

[0059] Comparative Example 1 underwent electrical performance testing under the same environmental conditions as Example 1. The thin-film transistor prepared in Comparative Example 1 exhibited a field-effect mobility of approximately 0.1–4 cm⁻¹. 2 V -1 s -1 With a threshold voltage of +1 to +2.8V and VDS = 10V, the device's on / off ratio is approximately 5 × 10⁻⁶. 4 ~8×10 7 After a 3600-second PBS test, ΔV th Up to +4~+8.8V; after NBS testing, ΔV th It ranges from -1 to -4V.

[0060] A comparison between Example 1 and Comparative Example 1 confirms the effectiveness and feasibility of the "quasi-dual-channel" structure of the present invention. The present invention vertically separates the functions of the channel layer 3, achieving synergistic performance improvement, including the following three aspects: (1) Achieving high mobility: by allowing the oxygen-deficient HfOx By "stealing" oxygen from TTO, a two-dimensional oxygen-deficient conductive layer with high carrier concentration is artificially created at the interface. According to the percolation model, this high-concentration electron layer fills the trapped states near the bottom of the conduction band, allowing electrons to flow more freely when the gate electric field is turned on, thereby significantly improving the field-effect mobility.

[0061] (2) Achieving high NBS stability: NBS stability is determined by the host channel. This invention specifically fabricates an oxygen-rich TTO channel. Oxygen richness means that the concentration of oxygen vacancies, which are mobile positive charge defects, in the channel is extremely low. Under negative bias, since almost no oxygen vacancies can migrate to the interface and trap electrons, the device exhibits excellent NBS stability.

[0062] (3) Achieving high PBS stability: PBS stability is determined by the interface adjacent to the gate. In the design of this invention, this interface is a two-dimensional oxygen-deficient interface with negligible thickness. The reason for the instability of PBS in conventional devices is that electrons are trapped by oxygen gaps and other traps at the interface. In the oxygen-rich main channel of this invention, oxygen gaps may exist, but they are far from the interface region with the strongest electric field. Although the two-dimensional oxygen-deficient interface of this invention itself has oxygen vacancies, it is a "surface" rather than a solid with thickness. Unlike conventional oxygen-deficient layers, it does not cause internal defect redistribution due to the electric field. Therefore, under positive bias, it can effectively suppress the electron trapping process and exhibit significant PBS stability.

[0063] Example 2: Creating an oxygen-deficient surface using an alumina insulating layer and air annealing at 350°C. In this embodiment, the insulating layer material is replaced with aluminum oxide (Al2O3). The preparation is carried out according to the process steps of Example 1, except that: an aluminum oxide thin film is deposited on the substrate by magnetron sputtering as the insulating layer, and the sample after Al2O3 deposition is placed in a vacuum annealing furnace and vacuum annealed at 350°C for 1 hour to create an oxygen-deficient surface on the surface of the aluminum oxide thin film.

[0064] The electrical performance of the device was tested under the same conditions as in Example 1. Test results: The device prepared in Example 2 exhibits a field-effect mobility of approximately 6.8 cm⁻¹. 2 V -1 s -1 With a threshold voltage of +0.4V and VDS=1V, the device's on / off ratio is approximately 1.8×10⁻⁶. 6 The subthreshold swing is approximately 0.18Vdec. -1 The results of the transfer characteristic curve test showed that after 3600 seconds, the threshold voltage changes of NBS and PBS were approximately -0.25V and +0.3V, respectively.

[0065] Example 3: Creating an oxygen-deficient surface using an alumina insulating layer and vacuum annealing at 600℃ The preparation method is basically the same as in Example 2, except that when manufacturing the oxygen-deficient surface of the insulating layer, the vacuum annealing temperature is increased to 600°C and the time is still 1 hour.

[0066] The electrical performance of the device was tested under the same conditions as in Example 1. Test results: The device prepared in Example 3 exhibits a field-effect mobility of approximately 8.5 cm⁻¹. 2 V -1 s -1 With a threshold voltage of +0.3V and VDS=1V, the device's on / off ratio is approximately 2.1×10⁻⁶. 6 The subthreshold swing is approximately 0.15Vdec. -1 The results of the transfer characteristic curve test showed that after 3600 seconds, the threshold voltage changes of NBS and PBS were approximately -0.22V and +0.26V, respectively.

[0067] The above description is merely a preferred embodiment of the present invention and does not constitute any limitation on the technical scope of the present invention. Therefore, any minor modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for fabricating a thin-film transistor, characterized in that, A two-dimensional oxygen vacancy interface is spontaneously formed at the contact surface of the insulating layer and the channel layer, and specifically comprises the following steps: Step a: depositing a conductive thin film as a gate electrode and a first metal oxide as an insulating layer on a substrate in sequence; or depositing a first metal oxide as an insulating layer on a substrate with electrical conductivity; Step b: treating the first metal oxide to form an oxygen vacancy-rich surface on the surface thereof; Step c: depositing a second metal oxide as a channel layer on the oxygen vacancy-rich surface, and performing annealing treatment after the deposition of the second metal oxide, so as to form a two-dimensional oxygen vacancy interface at the interface of the insulating layer and the channel layer, thereby forming a quasi-double channel structure; the annealing treatment is performed in an inert atmosphere, a reducing atmosphere, vacuum or air atmosphere, and the temperature is 300-450°C; wherein the metal-oxygen bond energy of the first metal oxide is higher than that of the second metal oxide; Step d: depositing a source electrode and a drain electrode on the channel layer, and performing annealing treatment on the device.

2. The production method according to claim 1, characterized by, The method for forming the oxygen vacancy-rich surface in step b is one of control annealing atmosphere treatment, plasma treatment or acid etching treatment.

3. The preparation method according to claim 2, characterized in that, In step b, the control annealing atmosphere treatment refers to annealing under a vacuum atmosphere or a reducing atmosphere, the vacuum atmosphere is an atmosphere with a pressure less than 10 Torr, the reducing atmosphere is argon or N2 / H2 mixed gas containing a small amount of H2, the annealing temperature is 100-600℃, and the time is 0.5-3 hours. -5 Torr, the reducing atmosphere is argon or N2 / H2 mixed gas containing a small amount of H2, the annealing temperature is 100-600℃, and the time is 0.5-3 hours.

4. The preparation method according to claim 2, characterized in that, In step b, the plasma treatment refers to placing the sample in a plasma device for physical bombardment in an inert atmosphere or chemical reduction in a reducing atmosphere, and the treatment power is 50-150W, the gas pressure is 1-10Pa, and the time is 30 seconds to 5 minutes.

5. The preparation method according to claim 2, characterized in that, In step b, the acid etching treatment refers to surface corrosion with a dilute hydrofluoric acid solution or a dilute hydrochloric acid for 5-300 seconds.

6. The method of claim 1, wherein, The annealing temperature in step d is 200-350°C.

7. The preparation method according to claim 1, characterized in that, In step a, the deposition is performed by magnetron sputtering, and the specific process parameters are as follows: deposition at room temperature, ceramic target material, oxygen / argon ratio (0-4):(26-30) sccm, sputtering power 50-200W, and working pressure 0.5-0.6Pa; the ceramic target material is at least one of zirconium oxide, gallium oxide, aluminum oxide or hafnium oxide.

8. The method of claim 1, wherein, In step c, the channel layer is deposited by magnetron sputtering, and the specific process parameters are as follows: oxygen / argon mixed gas ratio (1-4):(26-29) sccm; working pressure 0.1-1.0Pa, sputtering power 50-200W, and substrate temperature controlled at room temperature-300°C.

9. The method of claim 1, wherein, The second metal oxide is at least one of tantalum-doped tin oxide, tin oxide, indium oxide, zinc oxide, indium gallium zinc oxide, indium tin oxide and zinc tin oxide; and the first metal oxide comprises at least one of zirconium oxide, gallium oxide, aluminum oxide or hafnium oxide.

10. The enhanced channel thin film transistor prepared by the method of any one of claims 1 to 9, wherein the thin film transistor is of a bottom-gate top-contact structure, and the substrate is a heavily doped low-resistance silicon wafer, and an insulating layer is on the substrate, and a semiconductor channel layer is on the insulating layer, and source / drain electrodes are on the semiconductor channel layer; wherein, Semiconductor channel layer thickness 2 nm to 60 nm, resistivity 10 2 ~ 10 3 Ω-cm; insulating layer thickness 3 nm to 60 nm.

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