Normally-closed wide bandgap semiconductor device

Abstract

The invention provides a normally-off type wide bandgap semiconductor device, which comprises an n-type semiconductor layer, an n-type semiconductor layer, an n-type semiconductor layer, an n-type semiconductor layer, an n-type semiconductor layer and an n-type semiconductor layer, the trench gate structure comprises a gate trench extending inwards from the first main surface of the n-type semiconductor layer and a gate electrode embedded in the gate trench through a gate dielectric layer, and the gate electrode comprises a p-type conductive or metal electrode material; a source trench extending inward from the first main surface of the n-type semiconductor layer, located between adjacent gate trenches, and having a width of 30 nm to 440 nm with respect to the n-type semiconductor layer between the gate trenches; the source electrode comprises two parts, the first part is in contact with the n-type semiconductor layer along the side wall and the bottom of the source electrode groove to form Schottky contact, and the second part is located on the first part and is in contact with the n-type semiconductor layer along the side wall of the source electrode groove to form ohmic contact; a drain electrode in ohmic contact with the second main surface of the n-type semiconductor layer; when the device is turned on, the conductive channel is an accumulation channel formed in the n-type semiconductor layer. According to the invention, on-resistance can be reduced and reverse recovery can be improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor devices, and particularly relates to a normally-off wide-bandgap semiconductor device. BACKGROUND

[0002] Silicon carbide (SiC) is a wide-bandgap semiconductor material, which has the advantages of high breakdown field strength, good thermal stability and high carrier saturation drift velocity, and has application advantages in high-voltage, large-current and high-temperature working environments. In some power electronic application fields, it gradually replaces the traditional silicon (Si) material.

[0003] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a widely used semiconductor power device. Taking an n-type MOS with a vertical structure as an example, the semiconductor layer of a conventional trench-type MOSFET device is usually provided with an n+ type substrate layer, an n- type drift layer, a p-type body region layer, and an n+ type source region layer from bottom to top, wherein the doping type of the p-type body region layer is different from those of the other semiconductor layers. Due to the existence of the p-type body region layer, the MOSFET is a normally-off device. Under the action of a proper gate bias, electrons are gathered to form a conductive channel in the interface region of the p-type body region layer close to the gate dielectric layer, which connects the n- type drift layer and the n+ type source region layer, so that the MOSFET can be turned on. As shown in the conventional pn junction trench-type MOSFET device shown in the accompanying drawings, it comprises a drain electrode 11, an n+ type substrate layer 211, an n- type drift layer 212, a p-type body region layer 311, an n+ type source region layer 213, a gate trench extending from top to bottom through the n+ type source region layer 213, the p-type body region layer 311 and into the n- type drift layer 212, the gate trench comprising a gate dielectric layer 41 and a gate electrode 13, and a gate top dielectric layer 42 covering the top of the gate electrode 13, and the n+ type source region layer 213 is electrically connected with a source electrode 12. The working mode of the device is described as follows: when the device is in a blocking state, the pn junction formed by the p-type body region layer 311 and the n- type drift layer 212 is in a reverse bias state, and there are almost no electrons in the p-type body region layer 311, so the electrons cannot flow from the n+ type source region layer 213 to the n- type drift layer 212, and the conductive channel between the source electrode 12 and the drain electrode 11 is blocked; when a voltage greater than the threshold value is applied to the gate electrode 13, a high-concentration electron layer is gathered and formed at the interface of the p-type body region layer 311 close to the gate dielectric layer 41, forming a reverse channel, at this time, the electrons can flow from the n+ type source region layer 213 to the n- type drift layer 212 through the reverse channel in the p-type body region layer 311, and the conductive channel between the source electrode 12 and the drain electrode 11 is connected. Figure 1

[0004] ​However, for wide band gap semiconductor material silicon carbide (SiC), the trench type MOSFET device with the inversion layer conductive channel has the following problems: 1. The carrier mobility in the inversion layer is low, mainly affected by the following two factors: ① The p-type doping of silicon carbide (SiC) material requires high-energy ion implantation and high-temperature annealing, which will cause damage to the semiconductor crystal quality; ② The interface state density between the p-type body layer 311 and the gate dielectric layer 41 is large. These two points will reduce the carrier mobility of the inversion layer, thereby increasing the channel resistance; 2. In a wide band gap semiconductor MOSFET device, the channel resistance accounts for a large proportion, which makes the electric field between the source and the drain more concentrated in the channel region when the wide band gap semiconductor MOSFET device is in the reverse blocking state, thereby increasing the risk of breakdown of the gate dielectric layer near the channel region; 3. The pn junction body diode has a high on-state voltage drop and a long reverse recovery time, thereby increasing the switching loss. SUMMARY

[0005] Therefore, the technical problem to be solved by the present application is to provide a normally-off wide band gap semiconductor device that can reduce the channel resistance and also achieve protection of the gate dielectric and improvement of the reverse recovery characteristics.

[0006] To solve the above technical problems, the embodiment of the normally-off wide band gap semiconductor device provided by the present application has the following technical solutions:

[0007] A normally-off wide band gap semiconductor device, comprising:

[0008] An n-type semiconductor layer having a material band gap width > 2.0 eV, having a first main surface on one side and a second main surface on the other side opposite to the first main surface;

[0009] A trench gate structure, the trench gate structure comprising a gate trench extending inwardly from the first main surface of the n-type semiconductor layer, and a gate electrode embedded in the gate trench via a gate dielectric layer, the gate electrode comprising a p-type conductive electrode material or a metal electrode material;

[0010] A source trench extending inwardly from the first main surface of the n-type semiconductor layer, the source trench being located between adjacent gate trenches, and the width of the n-type semiconductor layer between the gate trench and the source trench being 30 nm to 440 nm;

[0011] The source electrode includes a first part and a second part. The first part of the source electrode contacts the n-type semiconductor layer along the sidewall and bottom of the source trench and forms a Schottky contact therewith. The second part of the source electrode is located above the first part of the source electrode and contacts the n-type semiconductor layer along the sidewall of the source trench to form an ohmic contact.

[0012] A drain electrode, wherein the drain electrode forms an ohmic contact with the second main surface of the n-type semiconductor layer;

[0013] When the wide bandgap semiconductor device is turned on, the conductive channel is an accumulation channel formed in the n-type semiconductor layer.

[0014] Preferably, the material of the n-type semiconductor layer is one of silicon carbide, gallium nitride, and gallium oxide.

[0015] Preferably, the n-type semiconductor layer comprises, in sequence from its second principal surface to its first principal surface, an n+ type substrate layer, an n- type drift layer, and an n+ type source region layer.

[0016] Furthermore, the n-type drift layer comprises two n-type semiconductor layers with different doping concentrations.

[0017] Furthermore, the doping concentration of the n+ type substrate layer is 10. 18 cm -3 ~10 20 cm -3 The doping concentration of the n-type drift layer is 10. 14 cm -3 ~10 18 cm -3 The doping concentration of the n+ type source region is

[0018] 10 18 cm -3 ~10 20 cm -3 .

[0019] Furthermore, the n+ type source region layer and the second part of the source electrode form an ohmic contact.

[0020] Preferably, the depth of the source trench exceeds the depth of the gate trench.

[0021] Preferably, the bottom region of the source trench forms a p-type well region to protect the gate dielectric layer at the bottom region of the gate trench.

[0022] Preferably, the bottom region of the gate trench forms a p-type well region to protect the gate dielectric layer at the bottom region of the gate trench.

[0023] Preferably, the first portion of the source electrode and the second portion of the source electrode respectively correspond to different metals or alloys.

[0024] Preferably, the material of the gate electrode includes p-type conductive polysilicon.

[0025] Further, the material of the gate electrode is one of metals Ti, Ni, Au, Co, W, and Pt.

[0026] Preferably, the gate dielectric layer includes a dielectric material with a dielectric constant greater than that of SiO2.

[0027] Further, the material of the gate dielectric layer is one of silicon oxynitride (SiNO), silicon nitride (Si3N4), aluminum oxide (Al2O3), and hafnium oxide (HfO2).

[0028] The normally-off wide-bandgap semiconductor device of the present application has the following beneficial effects:

[0029] (1) The normally-off wide-bandgap semiconductor device of the present application has no p-type body region layer, and utilizes the Schottky contact barrier formed by the second portion of the source electrode and the n-type semiconductor layer to deplete the electron carriers in the n-type semiconductor layer between the adjacent gate trench and the source trench, block the conduction channel between the source and the drain, and realize the normally-off function.

[0030] (2) When the normally-off wide-bandgap semiconductor device of the present application is turned on, the conduction channel is an accumulation channel formed in the n-type semiconductor layer, rather than an inversion channel, and the carrier mobility in the accumulation channel is higher, so the channel resistance is lower, thereby improving the power handling capability and efficiency of the semiconductor device.

[0031] (3) After the channel resistance of the normally-off wide-bandgap semiconductor device of the present application is lower, the proportion of the channel resistance is reduced, and when the device is in the reverse blocking state, the electric field distribution in the bottom region of the gate trench can be optimized, and the risk of breakdown of the gate dielectric layer near the channel region is reduced.

[0032] (4) The normally-off wide-bandgap semiconductor device of the present application integrates a Schottky body diode in the source trench region, eliminates the parasitic pn junction body diode in the traditional pn junction MOS, avoids bipolar degradation, and can also significantly reduce the on-state voltage drop of the body diode and shorten the reverse recovery time of the body diode, thereby reducing the loss caused by the parasitic body diode in circuit applications.

[0033] (5) The normally-off wide bandgap semiconductor device of the embodiment of the present application, by additionally providing a p-type well region at the bottom region of the source trench or the bottom region of the gate trench, can utilize the lateral depletion effect of the p-type well region to optimize the electric field distribution at the bottom region of the gate trench, and further reduce the risk of breakdown of the gate dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a vertical sectional view of a conventional pn junction trench gate MOSFET;

[0035] Figure 2 is a vertical sectional view of a conventional SiC-based pn junction double-trench MOSFET;

[0036] Figure 3 is a vertical sectional view of a first embodiment of the MOSFET to which the embodiment of the present application relates;

[0037] Figure 4 is a vertical sectional view of a second embodiment of the MOSFET to which the embodiment of the present application relates;

[0038] Figure 5 is a vertical sectional view of a third embodiment of the MOSFET to which the embodiment of the present application relates;

[0039] The technical features corresponding to the reference signs in the drawings are as follows:

[0040] 11 drain electrode

[0041] 12 source electrode

[0042] 121 first part of source electrode

[0043] 122 second part of source electrode

[0044] 13 gate electrode

[0045] 211 n+ type substrate layer

[0046] 212 n- type drift layer

[0047] 213 n+ type source region layer

[0048] 311 p-type body region layer

[0049] 312 p-type well region

[0050] 313 p+ type source region layer

[0051] 41 gate dielectric layer

[0052] 42 gate top dielectric layer

[0053] 43 field dielectric layer DETAILED DESCRIPTION

[0054] In order to make the skilled in the art better understand the technical solutions of the application, the technical solutions of the application will be described in detail below in combination with the drawings and specific embodiments, but the embodiments of the application are not limited thereto.

[0055] It should be noted that the terms "comprising" and "having" and any variations thereof described in the specification and claims of the present application are intended to cover non-exclusive inclusion, for example, a series of layers, regions or process steps described as being included do not have to be limited to only those clearly listed, but can include layers, regions or process steps not clearly listed or inherent to these structures.

[0056] In addition, the embodiments in the present application and the features therein can be combined with each other without conflict.

[0057] Figure 1 A vertical cross-sectional view of a conventional pn-junction trench-gate MOSFET. The MOSFET has a drain electrode 11, an n+ substrate layer 211, an n- drift layer 212, a p body region layer 311, an n+ source region layer 213, a gate trench extending inwardly from the upper surface of the n+ source region layer 213 into the n- drift layer 212, which includes a gate electrode 13, and a gate dielectric layer 41 and a gate top dielectric layer 42 which form a surround for the gate electrode 13, a source contact hole extending inwardly from the upper surface of the n+ source region layer 213 into the p body region layer 311, and a source electrode 12 which partially extends into the source contact hole and forms an ohmic contact with the n+ source region layer.

[0058] Figure 1 The MOSFET shown operates as follows: when the device is in a high voltage blocking state, the pn junction formed between the p body region layer 311 and the n- drift layer 212 is in a reverse biased state, there are almost no electrons in the p body region layer 311, and electrons cannot flow from the n+ source region layer 213 to the n- drift layer 212, and the conduction path between the source electrode 12 and the drain electrode 11 is blocked; when a voltage greater than the threshold value is applied to the gate electrode 13, a high concentration of electron layer is gathered at the interface of the p body region layer 311 near the gate dielectric layer 41, forming an inversion layer, at which time electrons can flow from the n+ source region layer 213 to the n- drift layer 212 through the inversion layer in the p body region layer 311, and the conduction path between the source electrode 12 and the drain electrode 11 is connected, and the device is in a conducting state at this time.

[0059] For Figure 1As shown in the MOSFET, when the material of the n-type semiconductor layer is silicon carbide (SiC) and the gate dielectric layer 41 is a gate oxide layer made by a thermal oxidation process, interface state defects are easily formed at the interface between SiC and the gate oxide layer due to the discontinuity of atomic arrangement and the difference in chemical bonds, which seriously affects the quality and reliability of the gate oxide layer and significantly increases the risk of breakdown of the gate oxide layer at a high electric field. Therefore, appropriate measures need to be taken to protect the gate oxide layer to improve the voltage withstand capability of the device.

[0060] Figure 2 A vertical sectional view of a conventional SiC-based pn junction double-trench MOSFET is shown. The MOSFET has a drain electrode 11, an n+ type substrate layer 211, an n- type drift layer 212, a p-type body region layer 311, an n+ type source region layer 213, a p+ type source region layer 313, a gate trench extending inward from the upper surface of the n+ type source region layer 213 into the n- type drift layer 212, which includes a gate electrode 13, and a gate dielectric layer 41 and a gate top dielectric layer 42 forming a surround for the gate electrode 13, a source trench extending inward from the upper surface of the p+ type source region layer 313 into the n- type drift layer 212, a p-type well region 312 located below the p-type body region layer 311 and forming a surround for the source trench, a field dielectric layer 43 covering the inner surface of the source trench, a source electrode 12 partially extending into the source trench and separated from the p-type well region 312 by the field dielectric layer 43, and the source electrode 12 being in ohmic contact with the p+ type source region layer 313 and the n+ type source region layer 213.

[0061] Figure 2 As shown in the MOSFET, the clever design of the double-trench structure can effectively protect the gate dielectric layer 41 and reduce the risk of breakdown of the gate dielectric layer 41 at a high electric field, thereby improving the voltage withstand capability of the device. The principle is as follows: when the device is in a high-voltage blocking state, the p-type well region 312 electrically connected to the p-type body region layer 311 will have a certain lateral depletion effect on the electron carriers in the n-type drift layer 212 at the bottom region of the gate dielectric layer 41, thereby weakening the electric field intensity at the bottom of the gate dielectric layer 41 and reducing the risk of breakdown of the gate dielectric.

[0062] For Figure 2 As shown in the MOSFET, the clever design of the double-trench structure can effectively protect the gate dielectric layer 41, but it still has the following problems: (1) Figure 2 As shown in the SiC-based MOSFET, the conductive channel of the inversion layer is formed in the p-type body region layer 311 when it is turned on. In SiC, the carrier mobility in the inversion layer is very low, which increases the channel resistance and thus increases the on-state loss; (2) Figure 2 The pn junction body diode provided in the SiC-based MOSFET has a high on-state voltage drop and a long reverse recovery time, which increases the switching loss during the reverse recovery process; (3)Figure 2 The pn junction body diode of the SiC-based MOSFET shown in the figure has a bipolar degradation effect, which will affect the service life and long-term reliability of the device during use.

[0063] Figure 3 is a vertical sectional view of a first embodiment of the MOSFET involved in the embodiment of the present application. The MOSFET has: a drain electrode 11, an n+ type substrate layer 211, an n- type drift layer 212, an n+ type source region layer 213, a gate trench extending inward from the upper surface of the n+ type source region layer 213 into the n- type drift layer 212, which includes a gate electrode 13 composed of a p-type conductive electrode material or metal electrode material and a gate dielectric layer 41 and a gate top dielectric layer 42 forming a surround for the gate electrode 13, a source trench extending inward from the upper surface of the n+ type source region layer 213 into the n- type drift layer 212, a first portion 121 of the source electrode contacting the n- type drift layer 212 along the sidewall and bottom of the source trench and forming a Schottky contact therewith, and a second portion 122 of the source electrode located above the first portion 121 of the source electrode and contacting the n+ type source region layer 213 along the sidewall of the source trench to form an ohmic contact therewith.

[0064] Since both the first portion 121 of the source electrode and the gate electrode 13 have a lateral depletion effect on the electron carriers in the n- type drift layer 212 between the gate trench and the source trench, under the combined action of both the first portion 121 of the source electrode and the gate electrode 13, Figure 3 The width of the n- type drift layer 212 between the gate trench and the source trench is spaced apart, i.e. Figure 3 The width of the n- type semiconductor layer between the gate trench and the source trench marked as W is designed to be 30 nm to 440 nm, which can deplete the electron carriers in the n- type drift layer 212 between the adjacent gate trench and source trench without gate bias, close the channel, block the conduction path between the second portion 122 of the source electrode and the drain electrode 11, and achieve Figure 3 The MOSFET shown is a normally-off device.

[0065] In addition, Figure 3 The MOSFET shown can also take the following technical means in detail in specific implementation:

[0066] (1) The material of the gate electrode includes p-type conductive polysilicon;

[0067] (2) The materials of the n+ type substrate layer 211, the n- type drift layer 212, and the n+ type source region layer 213 are silicon carbide;

[0068] (3) The doping concentration of the n- type drift layer 212 is 10 14 cm -3 ~ 1018 cm -3 , the doping concentration of the n+ type source region layer 213 is 10 18 cm -3 ~ 10 20 cm -3 ;

[0069] (4) The first part 121 of the source electrode and the second part 122 of the source electrode use different metals, for example, the first part 121 of the source electrode uses metal Ni, and the second part 122 of the source electrode uses metal Ti. The use of different metals for the two parts of the source electrode can provide more space for adjusting the electrical performance, for example, the first part 121 of the source electrode uses metal Ni, which forms a larger Schottky barrier with the n- type drift layer 212, and has a stronger lateral depletion effect on the electron carriers;

[0070] (5) The gate electrode 13 uses a conductive material with a work function higher than that of the n- type drift layer 212, for example, one of the metals Ti, Ni, and Au, for example, the gate electrode 13 uses metal Ni, which also forms a lateral depletion effect on the electron carriers in the n- type drift layer 212 on the side of the gate dielectric layer 41;

[0071] (6) The material of the gate dielectric layer 41 is silicon dioxide, and the material of the gate dielectric layer 41 can also be at least one of silicon nitride, silicon oxynitride, aluminum oxide, and hafnium oxide in addition to silicon dioxide.

[0072] Figure 3 The MOSFET structure shown does not have a p- type body region layer, and does not require the multiple high-energy ion implantation processes and ultra-high temperature annealing processes required to form the p- type body region layer, which can reduce the damage to the crystal quality caused by high-energy ion implantation processes and can also simplify the process appropriately.

[0073] Figure 3 The MOSFET shown, when a voltage above the threshold voltage is applied to the gate electrode 13, will accumulate a high concentration of electron layers in the n- type drift layer 212 on both sides of the gate dielectric layer 41 and form an accumulation channel, which connects the conductive channel between the second part 122 of the source electrode and the drain electrode 11, thereby turning on the device. Compared with devices with inversion layer channels, accumulation channels have higher carrier mobility, so the on-resistance of the device can be greatly reduced.

[0074] Figure 3In the MOSFET shown, the self-integrated Schottky body diode formed by the Schottky junction between the first part 121 of the source electrode and the n-type drift layer 212 can integrate a Schottky body diode in the device to serve as a freewheeling diode without increasing the device area, can improve reverse recovery, reduce losses caused by body diode freewheeling; at the same time, there is no bipolar degradation effect, which can improve the long-term reliability of the device.

[0075] Figure 3 The MOSFET shown can further adopt the following technical means in specific implementation to obtain more beneficial effects:

[0076] (1) The materials of the n+ substrate layer 211, the n-type drift layer 212, and the n+ source region layer 213 are selected to be silicon carbide, and the depth of the source trench is greater than the depth of the gate trench. When the device is in a high-voltage blocking state, the Schottky contact barrier between the first part 121 of the source electrode and the n-type drift layer 212 will be reverse biased to widen the depletion layer, so as to produce a lateral depletion effect on the electron carriers in the n-type drift layer 212 at the bottom region of the gate dielectric layer 41, and further weaken the electric field intensity at the bottom of the gate dielectric layer 41, thereby reducing the risk of breakdown of the gate dielectric;

[0077] (2) The n-type drift layer 212 adopts two n-type semiconductor layers with different doping concentrations, for example, a relatively lower upper layer and a relatively higher lower layer. By adjusting the doping concentration difference and the thickness of the upper and lower layers, the on-resistance and off-state leakage current can be moderately optimized.

[0078] Figure 4 is a vertical sectional view of a second embodiment of the MOSFET involved in the embodiments of the present application. Compared with Figure 3 the MOSFET shown, Figure 4 The MOSFET shown adds a p-type well region 312 at the bottom region of the source trench. The introduction of the p-type well region 312 can also produce a lateral depletion effect on the electron carriers in the n-type drift layer 212 at the bottom region of the gate dielectric layer 41 to protect the gate dielectric and improve the breakdown voltage. In addition, the depletion layer formed by the lateral depletion effect will extend to the bottom region of the gate trench, which will also reduce the feedback capacitance between the gate electrode 13 and the drain electrode 11. In this way, the depth of the source trench can be greater than, equal to, or close to the depth of the gate trench, or shallower than the depth of the gate trench. The depth of the source trench relative to the depth of the gate trench has greater flexibility, which further provides more adjustment windows for the electrical performance of the device and the process of the device.

[0079] Figure 5 is a vertical sectional view of a third embodiment of the MOSFET involved in the embodiments of the present application. Compared withFigure 3 the MOSFET shown, Figure 5 The MOSFET shown also has a p-type well region 312 added to the bottom region of the gate trench, which also has a lateral depletion effect on the electron carriers in the n-type drift layer 212 in the bottom region of the gate dielectric layer 41 to protect the gate dielectric and improve the breakdown voltage. In addition, the depletion layer formed by the lateral depletion of the p-type well region 312 will be verified in the bottom region of the gate trench, which will also reduce the feedback capacitance between the gate electrode 13 and the drain electrode 11. In this way, the depth of the source trench relative to the gate trench has greater flexibility in design, which provides more adjustment windows for the electrical performance of the device and the device process.

[0080] It should be noted that the MOSFET shown in each embodiment of the present application is based on the structural innovation of the Schottky junction MOSFET, which is not only suitable for silicon carbide (SiC) based semiconductor materials, but is especially suitable for using other types of semiconductor materials, such as gallium nitride (GaN), gallium oxide (Ga2O3), and tin oxide (SnO2), etc. In these materials, the p-type diffusion, implantation and activation process is difficult to complete and control.

[0081] It should be understood that the above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A normally-off wide bandgap semiconductor device, characterized by, The wide band gap semiconductor device comprises: an n-type semiconductor layer having a material band gap > 2.0 eV, having a first main surface on one side and a second main surface on the other side opposite to the first main surface; a trench gate structure comprising gate trenches extending inwardly from the first main surface of the n-type semiconductor layer, and gate electrodes embedded in the gate trenches via a gate dielectric layer, the gate electrodes comprising a p-type conductive electrode material or a metal electrode material; source trenches extending inwardly from the first main surface of the n-type semiconductor layer, the source trenches being located between adjacent gate trenches, the n-type semiconductor layer between the gate trenches and the source trenches having a width of 30 nm to 440 nm; a source electrode comprising a first portion of the source electrode and a second portion of the source electrode, the first portion of the source electrode contacting the n-type semiconductor layer along the sidewalls and the bottom of the source trenches and forming a Schottky contact therewith, the second portion of the source electrode being located on the first portion of the source electrode and contacting the n-type semiconductor layer along the sidewalls of the source trenches and forming an Ohmic contact therewith; a drain electrode contacting the second main surface of the n-type semiconductor layer and forming an Ohmic contact therewith; when the wide band gap semiconductor device is turned on, a conductive channel is formed in the n-type semiconductor layer as an accumulation channel.

2. The off-state wide bandgap semiconductor device of claim 1, wherein, The material of the n-type semiconductor layer is one of silicon carbide, gallium nitride, gallium oxide.

3. The off-state wide bandgap semiconductor device of claim 1, wherein, The n-type semiconductor layer comprises, in order from the second main surface to the first main surface thereof, an n+ type substrate layer, an n- type drift layer, and an n+ type source region layer.

4. The off-state wide bandgap semiconductor device of claim 3, wherein, The n- type drift layer comprises two n-type semiconductor layers having different doping concentrations.

5. The off-state wide bandgap semiconductor device of claim 3, wherein the first and second semiconductor layers are formed of a same material. The n+ type substrate layer has a doping concentration of 10 18 cm -3 ~ 10 20 cm -3 , the n- type drift layer has a doping concentration of 10 14 cm -3 ~ 10 18 cm -3 , and the n+ type source region layer has a doping concentration of 10 18 cm -3 ~ 10 20 cm -3 .

6. The off-state wide bandgap semiconductor device of claim 3, wherein, The n+ type source region layer contacts the second portion of the source electrode and forms an Ohmic contact therewith.

7. The off-state wide bandgap semiconductor device of claim 1, wherein the first and second semiconductor layers are each a gallium nitride based semiconductor layer. The depth of the source trenches exceeds the depth of the gate trenches.

8. The off-state wide bandgap semiconductor device of claim 1, wherein, The bottom region of the source trenches forms a p-type well region, and the gate dielectric layer protects the bottom region of the gate trenches.

9. The off-state wide bandgap semiconductor device of claim 1, wherein, The bottom region of the gate trenches forms a p-type well region, and the gate dielectric layer protects the bottom region of the gate trenches.

10. The off-state wide bandgap semiconductor device of claim 1, wherein, The first portion of the source electrode and the second portion of the source electrode respectively correspond to different metals or alloys.

11. The off-state wide bandgap semiconductor device of claim 1, wherein, The material of the gate electrodes comprises p-type conductive polysilicon.

12. The off-state wide bandgap semiconductor device of claim 1, wherein, The material of the gate electrodes is at least one of metal Ti, Ni, Au, Co, W, and Pt.

13. The off-state wide bandgap semiconductor device of claim 1, wherein, The gate dielectric layer comprises a dielectric material having a dielectric constant greater than that of SiO2.

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