Power semiconductor device

Abstract

The invention relates to the technical field of power semiconductors, particularly provides a power semiconductor device, and aims to solve the problem of how to effectively improve the dynamic performance of the power semiconductor device. In order to achieve the purpose, the power semiconductor device comprises a doped region with the same conduction type as a well region, the doped region is arranged in an epitaxial layer and at least surrounds the side wall of one side of a trench gate structure, and the top of the doped region is directly connected with the bottom surface of the well region; by means of the arrangement, an efficient low-resistance extraction path can be provided for minority carriers generated in the switching process of the device, and the dynamic performance of the power semiconductor device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor, and particularly provides a power semiconductor device. BACKGROUND

[0002] With the development of power electronics technology towards high frequency, high efficiency and high power density, the dynamic characteristics of power semiconductor devices have become a key factor determining the performance of the entire system. The dynamic characteristics can be reflected by dynamic parameters. The dynamic parameters of power semiconductor devices such as silicon-based IGBT (Insulated Gate Bipolar Transistor), silicon-based MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), SiC MOSFET, GaN HEMT (High Electron Mobility Transistor) are the characteristic parameters exhibited in the switching transient process, which are the key indicators representing the switching transient behavior of the device and can be used to describe the transient behavior of the device when switching between "on" and "off" states, directly determining the efficiency, power density and reliability of the power electronic system.

[0003] The dynamic characteristics affect the power loss and safety of the device. Taking energy loss, current change rate (di / dt), voltage change rate (dv / dt), energy loss and Miller capacitance as examples, the energy loss in the switching process directly determines the total power loss of the device at high frequency, and a high-efficiency system design must balance the conduction loss (determined by the on-resistance) and the switching loss; extremely high current change rate (di / dt) and voltage change rate (dv / dt) are the main sources of electromagnetic interference, which can generate oscillation and overvoltage peak on the circuit parasitic inductance and capacitance, threatening the safety of the device; the Miller capacitance is easy to cause the device to be mistakenly turned on. Therefore, how to effectively improve the dynamic performance of the power semiconductor device has become a problem to be solved. SUMMARY

[0004] The present application aims to solve the above technical problems and provides a power semiconductor device to effectively improve the dynamic performance of the power semiconductor device.

[0005] To achieve the above-mentioned purpose, the power semiconductor device provided by the present application comprises: a semiconductor substrate comprising an epitaxial layer of a first conductivity type, the epitaxial layer having opposite first and second surfaces; a well region of a second conductivity type, the well region being disposed in the epitaxial layer and close to the first surface; the second conductivity type being different from the first conductivity type; a source region of a first conductivity type disposed in the well region and located on a side of the well region away from the second surface; a trench gate structure extending through the source region and the well region and into the epitaxial layer in a first direction, the first direction being a direction of thickness of the semiconductor substrate; a doped region of a second conductivity type disposed in the epitaxial layer and at least surrounding a sidewall of one side of the trench gate structure, a top of the doped region being directly connected to a bottom surface of the well region on a side close to the second surface.

[0006] In some embodiments, a local region of the doped region has a doping concentration less than that of the well region, the local region being a region of the doped region directly connected to the well region.

[0007] In some embodiments, the doped region has a doping concentration less than that of the well region.

[0008] In some embodiments, the doped region only surrounds one side of the trench gate structure in a third direction; alternatively, the doped region surrounds one side of the trench gate structure in the third direction and a bottom of the trench gate structure; alternatively, the doped region surrounds one side of the trench gate structure in the third direction, a bottom of the trench gate structure, and another side of the trench gate structure in the third direction, and in a state of applying a gate-source reverse bias between gate oxides, a spacing distance between a depletion layer formed by the doped region surrounding the other side of the trench gate structure and a depletion layer formed by the well region on a side close to the second surface is greater than zero; the third direction being a direction of width of the trench gate structure, the third direction being parallel to the first surface and perpendicular to the first direction.

[0009] In some embodiments, the doped region also surrounds a partial sidewall of the other side of the trench gate structure in the third direction, the doped region of the partial sidewall on the other side being spaced apart from the well region, and in a state of applying a gate-source reverse bias between gate oxides, a spacing distance between a depletion layer formed and a depletion layer formed by the well region on a side close to the second surface is greater than zero.

[0010] In some embodiments, the trench gate structure and the doped region are each provided in a plurality, the plurality of the trench gate structures being spaced apart in the third direction, and the doped regions being provided in one-to-one correspondence with the trench gate structures.

[0011] In some embodiments, the plurality of the trench gate structures are equally spaced apart in the third direction, and the plurality of the doped regions are provided in the same manner.

[0012] In some embodiments, at least part of the plurality of doped regions are arranged differently.

[0013] In some embodiments, two-by-two of the plurality of doped regions form a doped group, different doped groups are arranged in the same way, and two doped regions in the same doped group are arranged at least partially surrounding different sides of the trench gate structure and symmetrically about the center line between two adjacent trench gate structures.

[0014] In some embodiments, in a state where a gate-source reverse bias is applied between the gate oxides, in the third direction, the spacing distance between the depletion layers formed by any two adjacent doped regions is greater than zero.

[0015] In some embodiments, in the first direction, the size of the doped region is greater than the size of the depletion layer of the well region, and in a state where a gate-source reverse bias is applied between the gate oxides, the depletion layer of the well region is formed on the side of the well region close to the second surface.

[0016] The power semiconductor device provided by the present application includes a doped region having the same conductivity type as the well region, which is arranged in the epitaxial layer and at least surrounds the sidewall of one side of the trench gate structure, and the top of the doped region is directly connected to the bottom surface of the well region. This arrangement can provide an efficient low-resistance extraction path for the minority carriers generated during the switching process of the device, thereby improving the dynamic performance of the power semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0017] The preferred embodiments of the present application will be described below with reference to the accompanying drawings, in which: Figure 1 is a schematic diagram of the cross-sectional structure of a power semiconductor device provided by an embodiment of the present application; Figure 2 is a schematic diagram of the cross-sectional structure of a power semiconductor device provided by another embodiment of the present application; Figure 3 is a schematic diagram of the cross-sectional structure of a power semiconductor device provided by another embodiment of the present application; Figures 4 to 6 is a schematic diagram of the intermediate structure of a power semiconductor device obtained after performing different steps in the process of manufacturing Figure 2 the power semiconductor device shown; Figure 7 is a schematic diagram of the structure of the power semiconductor device shown in a state where no gate-source reverse bias is applied between the gate oxides. Figure 2 DETAILED DESCRIPTION

[0018] ​To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the described embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] The terms “first,” “second,” “third,” and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “connection” are not limited to mechanical connections, but can include electrical connections.

[0020] Figure 1 and Figure 2 These are cross-sectional structural schematic diagrams of the power semiconductor devices provided in two embodiments of this application, see below. Figure 1 and Figure 2 As shown, the power semiconductor device provided in this application embodiment may include: a semiconductor substrate, including an epitaxial layer 11 of a first conductivity type, the epitaxial layer 11 having a first surface S1 and a second surface S2 opposite to each other; a well region 12 of a second conductivity type, disposed in the epitaxial layer 11 and close to the first surface S1; the second conductivity type is different from the first conductivity type; a source region 13 of the first conductivity type, disposed in the well region 12 and located on the side of the well region 12 away from the second surface S2; a trench gate structure 14, in a first direction, the trench gate structure 14 penetrates the source region 13 and the well region 12 and extends into the epitaxial layer 11, the first direction being the direction of the semiconductor substrate thickness; and a doped region (15, 15') of the second conductivity type, the doped region (15, 15') being disposed in the epitaxial layer 11 and at least surrounding one sidewall of the trench gate structure 14, the top of the doped region (15, 15') being directly connected to the well region 12.

[0021] In some embodiments, such as Figure 1 and Figure 2 As shown, the top of the doped region (15,15') can be directly connected to the surface of the well region 12 near the second surface S2.

[0022] In the doped region (15,15'), the doping concentration in a local area is lower than that in the well region 12. This local area refers to the region within the doped region (15,15') that is directly connected to the well region 12. By setting the doping concentration in this local area to be lower than that in the well region 12, the impact on device performance parameters such as the threshold voltage can be reduced. In a more preferred embodiment, the overall doping concentration of the doped region (15,15') is lower than that of the well region 12.

[0023] In the power semiconductor device provided in the embodiments of this application, by setting a doped region (15,15') of the second conductivity type, the doped region (15,15') is disposed in the epitaxial layer 11 and at least surrounds the sidewall of one side of the trench gate structure 14, and at least the top of the doped region (15,15') is directly connected to the well region 12, an efficient low-resistance extraction path can be provided for minority carriers generated during the switching process of the device, thereby improving the dynamic performance of the power semiconductor device.

[0024] In this embodiment, the power semiconductor device can be a trench MOSFET. The semiconductor substrate may consist only of the epitaxial layer 11, or it may include the epitaxial layer 11 and a semiconductor substrate 10 disposed on the second surface S2 of the epitaxial layer 11. The inclusion of a substrate can be chosen based on factors such as the device type and product heat dissipation requirements. In the following description, an example will be provided where the semiconductor substrate includes the epitaxial layer 11 and a semiconductor substrate 10 disposed on the second surface S2 of the epitaxial layer 11. The semiconductor substrate 10 can be made of semiconductor materials such as silicon or silicon carbide. For a silicon substrate, the corresponding epitaxial layer can be lightly doped silicon; for a silicon carbide substrate, homoepitaxial growth such as 4H-SiC or heteroepitaxial growth can be used.

[0025] In some embodiments, the region in the epitaxial layer 11 located on the side of the well region 12 near the second surface S2 can be used as a drift region. When a reverse bias voltage is applied between the gate and the source, the free carriers in a portion of the drift region will be depleted, forming a depletion layer (space charge region).

[0026] The trench gate structure 14 may include a trench, a gate dielectric layer conformally covering the trench, and a gate conductive material filling the trench. In some embodiments, the gate conductive material may be doped polysilicon.

[0027] The second conductivity type is different from the first conductivity type, or in other words, they are opposites; for example, if the first conductivity type is N-type, then the second conductivity type is P-type; or if the first conductivity type is P-type, then the second conductivity type is N-type.

[0028] Taking the trench MOSFET with N-type as the first conductivity type and P-type as the second conductivity type as an example, by setting the doped region (15, 15'), the dynamic performance of the device can be improved in the following aspects: (1) Significantly reduce turn-off loss (Eoff) and improve switching speed: During the turn-on of the trench MOSFET, the N-type epitaxial layer 11 is filled with minority carriers—holes—generated by electron injection. When the device is turned off, these stored charges must be removed before the depletion layer can be established, thereby blocking the voltage. This process takes time and is manifested as the "current tail" phenomenon in the turn-off waveform. Without a low-resistance minority carrier (i.e., the aforementioned holes) extraction path, the holes can only be slowly discharged through thermal recombination or through the high-resistance body resistance, which is slow and generates additional power consumption. However, due to the addition of a low-resistance channel, the stored charge is quickly cleared, the current tail is significantly reduced or disappears, the turn-off process is faster, and the overlap area of ​​current and voltage (i.e., the power loss range) is greatly reduced. This is crucial for high-frequency switching applications such as switched-mode power supplies (SMPS), which can directly improve system efficiency. Furthermore, since the charge extraction is extremely rapid during turn-off, there is more room to optimize the gate drive resistor without worrying about the problem of slow turn-off. Using a smaller gate resistor (Rg) can further accelerate the turn-on and turn-off speeds, reduce switching time, and thus be suitable for higher frequency applications. This can form a virtuous cycle, namely, fast internal charge extraction allows for the use of a smaller external Rg, thereby achieving a faster overall switching speed. (2) Enhance dv / dt tolerance and prevent false turn-on: The root cause of false turn-on is the Miller capacitance effect. When the trench MOSFET is in the off state, the drain voltage rises rapidly (high dv / dt), which will generate a displacement current I_disp = Cgd *dv / dt through the Miller capacitance (Cgd). This current will flow into the gate drive circuit. If the drive impedance is low, it will be absorbed. However, if the drive impedance is high, it may raise the gate voltage, causing the device to turn on falsely (even without a gate drive signal). Furthermore, this displacement current also flows into the body region. If the body resistance is high, the current will generate a voltage across it, which may trigger a parasitic BJT or cause partial conduction. In the solution provided in this application, by setting a doped region (15, 15'), an additional low-impedance discharge channel can be provided for the displacement current, so that most of the displacement current will choose to flow directly to the source through this low-impedance discharge channel, rather than raising the gate voltage or body potential, thus improving the reliability of the device in bridge circuits (such as half-bridge and full-bridge).

[0029] In the embodiments of this application, such as Figure 1 and Figure 2As shown, in the first direction, the extension depth of the trench gate structure 14 within the epitaxial layer 11 is greater than the extension depth of the well region 12 within the epitaxial layer 11; the trench gate structure 14 extends along the second direction (not shown in the figure) and has a preset width in the third direction. Here, the second direction refers to the direction of the trench length, and the third direction refers to the direction of the trench width; both the second direction and the third direction are parallel to the first surface S1, and the second direction is perpendicular to the third direction; obviously, both are perpendicular to the first direction. The preset width can be flexibly set according to actual needs.

[0030] See Figure 1 and Figure 2 As shown, the doped region (15, 15') is located below the well region 12, meaning that compared to the well region 12, the doped region (15, 15') is closer to the second surface S2, and the top of the doped region (15, 15') is directly connected to the side surface of the well region 12 closest to the second surface S2 (i.e., the bottom surface of the well region 12). In some embodiments, such as... Figure 1 As shown, the doped region 15 is located entirely on one side of the trench gate structure 14. The top of the doped region 15 is in direct contact with the bottom surface of the well region 12, and the bottom of the doped region 15 extends toward the second surface S2 but does not exceed the bottom of the trench gate structure 14. The entire doped region 15 is approximately "I" shaped. In other embodiments, such as... Figure 2 As shown, the doped regions 15' are located on both sides of the trench gate structure 14. The top of the doped regions 15' is in direct contact with the bottom surface of the well region 12, and the bottom of the doped regions 15' surrounds the bottom of the trench gate structure 14. The bottom of the doped regions 15' is spaced apart from the well region 12, and the entire doped region 15' is approximately a "J"-shaped structure. By setting the doped regions 15' to further surround the bottom of the trench gate structure 14, the dynamic performance of the power semiconductor device can be improved, the electric field distribution can be optimized, and the gate oxide breakdown voltage characteristics at the bottom of the trench gate structure 14 can be improved.

[0031] In some embodiments, the doping concentration of the remaining regions in the doped regions (15, 15') other than the local regions may be the same as or different from that of the local regions. When the doping concentration of the remaining regions is different from that of the local regions, the doping concentration of the remaining regions may be less than, equal to or greater than that of the well region 12.

[0032] In some embodiments, the overall doping concentration of the doped regions (15, 15') is lower than that of the well region 12, so as to minimize the impact on device performance such as the threshold voltage Vth.

[0033] In some embodiments, such as Figure 1As shown, the doped region 15' surrounds the sidewalls on both sides of the trench gate structure 14. The doped region 15' located on one sidewall is directly connected to the well region 12. The doped region 15' located on the other sidewall is spaced apart from the well region 12. When a gate-source reverse bias voltage is applied between the gate and the oxide, the distance between the depletion layer 16 formed by the doped region 15' on this side and the depletion layer 16' formed at the bottom surface of the well region 12 is greater than zero, so as to ensure the normal turn-on of the power semiconductor device.

[0034] It should be noted that, Figure 2 and Figure 2 Both diagrams show a schematic of a power semiconductor device under a gate-source reverse bias applied between the gate and oxide. The depletion layer (16, 16') shown is a space charge region dynamically formed under the application of the gate-source reverse bias, clearly demonstrating the internal electric field and carrier distribution of the power semiconductor device under bias conditions, rather than a physical structure layer formed by the fabrication process. The state of applying the gate-source reverse bias between the gate and oxide can be achieved by applying a reverse voltage drop between the gate and source formed in the gate conductive material. Unless otherwise specified, this patent refers to the reverse bias between the gate and source.

[0035] In some embodiments, see Figure 1 or Figure 2 As shown, in the first direction, the size of the doped region (15, 15') is larger than the size of the depletion layer 16' of the well region 12, which can ensure that the Miller capacitance (Cgd) is sufficiently reduced and also makes the consistency of the threshold voltage Vth better.

[0036] In some embodiments, such as Figure 1 and Figure 2 As shown, multiple trench gate structures 14 and doped regions (15, 15') are provided. Multiple trench gate structures 14 are arranged at intervals in the third direction, and the doped regions (15, 15') are arranged in a one-to-one correspondence with the trench gate structures 14.

[0037] In some embodiments, such as Figure 1 and Figure 2 As shown, multiple trench gate structures 14 can be equally spaced in the third direction, and multiple doped regions (15, 15') adopt the same arrangement. The multiple doped regions (15, 15') adopting the same arrangement can mean that the doping concentration, doping concentration distribution, structure, size, and relative position to their respective corresponding trench gate structures 14 are all the same. Figure 1 As shown, multiple doped regions 15 are located to the right of their respective corresponding trench gate structures 14. This arrangement is beneficial for more uniform current distribution and better device performance.

[0038] In other embodiments, at least some of the multiple doped regions (15, 15') adopt different arrangements. For example, some of the multiple doped regions (15, 15') may be arranged in an "I" shape, while the rest may be arranged in a "J" shape. Alternatively, the multiple doped regions (15, 15') may all adopt the same structure and size, but their relative positions with respect to their respective corresponding trench gate structures 14 may differ. See [link to relevant documentation] for details. Figure 2 And the following description.

[0039] Figure 1 This is a cross-sectional structural schematic diagram of a power semiconductor device provided in another embodiment of this application, see below. Figure 3 As shown, this embodiment is similar to Figure 3 The main difference in the corresponding embodiment is that each pair of doped regions 15' is a doping group, and different doping groups are set in the same way. The two doped regions 15' in the same doping group at least partially surround different sides of the trench gate structure 14 and are symmetrically arranged about the center line (not shown in the figure) between the two adjacent trench gate structures 14.

[0040] In some embodiments, such as Figure 3 As shown, with a gate-source reverse bias applied between the gate and oxide, in the third direction, the spacing between any two doped regions (15,15') forming the depletion layer 16 is greater than zero.

[0041] See Figure 2 As shown, X1 and X3 represent the dimensions of the doped regions located on the two sidewalls of the trench gate structure 14 in the third direction, respectively. The values ​​of X1 and X3 are determined by the energy and dose of ion implantation when forming the doped regions (15, 15'), and can be set according to actual needs. In some embodiments, X1 can be equal to X3. X2 and X4 represent the dimensions of the depletion layer 16 formed between the doped regions on the two sidewalls of the trench gate structure 14 and the epitaxial layer 11 in the third direction when a reverse bias voltage is applied between the gate and the source. The values ​​of X2 and X4 are determined by the doping concentration of the doped regions 15 and the epitaxial layer 11 and the bias voltage between the gate and the source. X represents the trench pitch. When multiple trench gate structures 14 are equally spaced, that is, the trench pitch X of any two adjacent trench gate structures 14 is the same. In some cases, the depletion layers corresponding to adjacent trench gate structures 14 are not connected when a forward bias voltage is applied between the gate and the source, but the depletion layers can be connected when a reverse bias voltage is applied.

[0042] Y1 represents the thickness of the depletion layer 16' formed between the well region 12 and the epitaxial layer 11 in the first direction. The value of Y1 can be determined by the doping concentration of the well region 12 and the epitaxial layer 11. Y2 represents the extension dimension of the doped region located on one sidewall of the trench gate structure 14 (i.e., the doped region on the side directly connected to the well region 12) in the first direction. Y3 represents the distance between the depletion layer 16 formed on the other side of the trench gate structure 14 (i.e., the doped region not connected to the well region 12) and the depletion layer 16' formed in the well region 12 in the first direction. Y4 represents the distance between the depletion layer 16' formed on the other side of the trench gate structure 14 (i.e., the doped region not connected to the well region 12) and the bottom corner of the trench in the first direction. The value of Y4 can be determined by the doping concentration of this part of the region, the implantation depth in the first direction, the gate-source reverse bias voltage between the gate and oxide, and the doping concentration of the epitaxial layer 11.

[0043] In the first direction, the size of the doped region (15,15') is larger than the size of the depletion layer 16' of the well region 12, that is, Y2 > Y1 must be satisfied, and its extension size Y2 in the first direction must also ensure that it does not affect the threshold voltage of the device. Sufficient margin is required. This margin can be determined by the well region 12, the epitaxial layer 11 and the doped region (15,15') together to ensure that the channel between the doped region (15,15') and the well region 12 does not open during normal device operation.

[0044] like Figures 1 to 3 and Figures 1 to 3 As shown, in order to ensure that the region in the doped region 15' located on the side where the trench gate structure 14 and the well region 12 are not connected, the spacing between the depletion layer 16 formed under the condition of applying a reverse bias voltage between the gate and the source and the depletion layer 16' formed in the well region 12 near the second surface S2 is greater than zero, that is, Y3 > 0 must be guaranteed.

[0045] Y4 can be greater than or equal to zero. When Y4 is equal to zero, the doped region 15' can surround the sidewall of the trench gate structure 14 on the third-direction upward side and the bottom corner of the trench gate structure 14. When Y4 is greater than zero, it means that the doped region 15' can also surround the sidewall of the trench gate structure 14 on the other side on the third-direction upward side, that is, it surrounds the sidewalls on both sides of the trench gate structure 14. The corresponding power semiconductor device structure is as follows: Figure 2 As shown. Y represents the distance between the corner of the trench gate structure 14 and the depletion layer 16' of the well region 12 in the first direction.

[0046] In the third direction, the spacing between any two doped regions (15, 15') forming the depletion layer 16 is greater than zero. Figure 3For example, it is necessary to ensure that (X1+X2+X3+X4) < X, or as follows Figure 2 As shown, it is necessary to ensure that 2*(X3+X4)<X and 2*(X1+X2)<X.

[0047] In some embodiments, such as Figure 2 As shown, the power semiconductor device may further include: an insulating dielectric layer 17 and a first metal layer 18 disposed on the first surface S1 of the epitaxial layer 11, and a second metal layer 19 disposed on the semiconductor substrate opposite to the first surface S1 of the epitaxial layer 11; the first metal layer 18 includes a metal wiring layer covering the insulating dielectric layer 17 and a metal plug (not shown) penetrating the insulating dielectric layer 17 and the source region 13, the metal wiring layer being electrically connected to the well region 12 through the metal plug. Furthermore, the lead-out structure of the gate conductor structure in the trench gate structure 14 is omitted in the figure.

[0048] In some embodiments, epitaxial growth, photolithography, ion implantation, and etching steps can be performed sequentially and repeated multiple times to form the epitaxial layer 11 and the doped region (15, 15'). The following will describe the formation of... Figure 3 Taking the power semiconductor device shown as an example, its fabrication steps are described as follows: Step 1: On the semiconductor substrate 10, a first epitaxial layer is first formed using an epitaxial process. Then, by repeatedly performing epitaxy, photolithography, ion implantation, and etching steps, a second epitaxial layer is obtained. The second epitaxial layer has multiple spaced doped regions 15' serving as buried layers. Next, a third epitaxial layer is formed on the surface of the second epitaxial layer, resulting in... Figures 1 to 3 The intermediate structure shown. The aforementioned first to third epitaxial layers are all of the first conductivity type, and the three together constitute epitaxial layer 11. Epitaxial layer 11 has a first surface S1 and a second surface S2, wherein the second surface S2 is in contact with the semiconductor substrate 10; the doped region 15' is of the second conductivity type.

[0049] Step 2: Pattern the epitaxial layer 11 to form multiple trenches, the positions of which correspond one-to-one with the positions of the doped regions 15'; grow a gate dielectric layer within the trenches; and deposit the gate conductive material and perform back etching to obtain the desired result. Figure 2 The trench grid structure 14 shown.

[0050] In some embodiments, a hard mask may first be formed covering the surface of the epitaxial layer 11, and then plasma etching may be performed on the epitaxial layer 11 to form a plurality of spaced trenches at predetermined locations in the epitaxial layer 11. Subsequently, an oxide layer may be grown in the trenches using a high-temperature diffusion method. In some embodiments, such as Figure 4As shown, the oxide layer covers not only the sidewalls and bottom wall of the trench, but also the first surface S1 of the epitaxial layer 11, wherein the oxide layer covering the inner wall of the trench serves as the gate dielectric layer. Subsequently, a gate conductive material, such as doped polysilicon, is deposited in the trench using methods such as low-pressure chemical vapor deposition. The doped polysilicon on the first surface S1 of the epitaxial layer 11 is removed using methods such as chemical mechanical polishing and etch-back, ensuring that the gate conductive material in the trench does not exceed the top of the trench or the first surface S1 of the epitaxial layer 11.

[0051] Step 3: A second conductivity type well region 12 is formed in the epitaxial layer 11 by ion implantation and high-temperature annealing, and a first conductivity type source region 13 is formed on the side of the well region 12 away from the second surface S2 of the epitaxial layer 11, to obtain the intermediate structure shown in 6.

[0052] In this case, the region of the doped region 15' located on one side wall of the trench gate structure 14 is directly connected to the well region 12, and the doping concentration of the local region of the doped region 15' near the well region 12 is less than the doping concentration of the well region 12.

[0053] Step 4: Remove the oxide layer on the first surface S1 of the epitaxial layer 11, and deposit an insulating dielectric layer 17; form a plurality of through holes penetrating the insulating dielectric layer 17 and the source region 13, extending to the well region 12; and deposit a first metal layer 18 on the insulating dielectric layer 17 and perform patterning processing to obtain metal plugs filling the through holes and a metal wiring layer covering the insulating dielectric layer 17, thus obtaining... Figure 5 Figure 5 Figure 7 The power semiconductor device shown is further described below. Subsequent processes may include wafer thinning, back-side metallization, etc. Depending on the device requirements, thinning may remove part or all of the substrate 10, and then a second metal layer 19 is formed on the back side of the wafer. Furthermore, for FS IGBTs (Field-Stop Insulated Gate Bipolar Transistors), back-side implantation can also be performed. These are all existing technologies and will not be elaborated further.

[0054] The technical solutions of this application have been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.

Claims

1. A power semiconductor device, characterized by, Comprise: a semiconductor substrate comprising an epitaxial layer of a first conductivity type, the epitaxial layer having opposite first and second surfaces; a well region of a second conductivity type disposed within the epitaxial layer and proximate to the first surface; the second conductivity type being different from the first conductivity type; a source region of the first conductivity type disposed within the well region and on a side of the well region distal from the second surface; a trench gate structure extending in a first direction through the source region and the well region and into the epitaxial layer, the first direction being a direction of thickness of the semiconductor substrate; a doped region of the second conductivity type disposed within the epitaxial layer and at least surrounding a sidewall of a side of the trench gate structure, a top of the doped region being directly connected to a bottom surface of a side of the well region proximate to the second surface.

2. The power semiconductor device according to claim 1, characterized in that, A local region of the doped region has a doping concentration less than a doping concentration of the well region, the local region being a region of the doped region directly connected to the well region.

3. The power semiconductor device according to claim 2, characterized in that, The doping concentration of the doped region is less than the doping concentration of the well region.

4. The power semiconductor device according to any one of claims 1 to 3, wherein: the doped region surrounds only one side of the trench gate structure in a third direction; or, the doped region surrounds one side of the trench gate structure in the third direction and a bottom of the trench gate structure; or, the doped region surrounds one side of the trench gate structure in the third direction, a bottom of the trench gate structure, and another side of the trench gate structure in the third direction, and in a state in which a gate-source reverse bias is applied between gate oxides, a spacing distance between a depletion layer formed by the doped region surrounding the other side of the trench gate structure and a depletion layer formed by the well region proximate to the second surface is greater than zero; the third direction is a direction of width of the trench gate structure, the third direction being parallel to the first surface and perpendicular to the first direction.

5. The power semiconductor device according to claim 4, characterized in that, The trench gate structure and the doped region are each provided in a plurality, the plurality of trench gate structures being provided at intervals in the third direction, and the plurality of doped regions being provided in one-to-one correspondence with the plurality of trench gate structures.

6. The power semiconductor device according to claim 5, characterized in that, The plurality of doped regions are provided in the same manner.

7. The power semiconductor device according to claim 5, characterized in that, At least some of the plurality of doped regions are provided in different manners.

8. The power semiconductor device according to claim 7, characterized in that, The plurality of doped regions are each provided in a doped group, different doped groups being provided in the same manner, and two doped regions in the same doped group at least partially surrounding different sides of the trench gate structure and being symmetrically provided about a center line between two adjacent trench gate structures.

9. The power semiconductor device according to any one of claims 6 to 8, characterized in that, In a state in which a gate-source reverse bias is applied between gate oxides, a spacing distance between depletion layers formed by any two adjacent doped regions in the third direction is greater than zero.

10. The power semiconductor device according to any one of claims 1 to 9, characterized in that, In the first direction, a size of the doped region is greater than a size of a depletion layer of the well region, and in a state in which a gate-source reverse bias is applied between gate oxides, the depletion layer of the well region is formed on a side of the well region proximate to the second surface.

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