Shield gate power semiconductor device and preparation method thereof

Abstract

The invention relates to a power semiconductor device and a preparation method thereof, in particular to a shield gate power semiconductor device and a preparation method thereof. According to the technical scheme provided by the invention, the shielding gate power semiconductor device comprises a semiconductor substrate; the active region is distributed in the central region of the semiconductor substrate and comprises a plurality of SGT cells which are distributed in parallel, the SGT structures in the SGT cells adopt left and right structures, the SGT cells comprise shielding grids which are vertically distributed in cell grooves, and the shielding grids are arranged in the SGT cells. The shielding grid comprises a shielding first unit body and a shielding second unit body connected with the shielding first unit body, and the contact connection between the shielding first unit body and the shielding second unit body forms a T shape on the cross section of the SGT cell. The method can effectively improve the withstand voltage of the SGT structure of the left-right structure, is compatible with the prior art, and is safe and reliable.

Description

Technical Field

[0001] This invention relates to a power semiconductor device and its fabrication method, and more particularly to a shielded gate power semiconductor device and its fabrication method. Background Technology

[0002] SGT (Shielded Gate Trench) power devices are a new type of power semiconductor device that offers advantages such as low conduction losses and low switching losses compared to traditional power semiconductor devices. SGT power devices can include SGT MOSFET devices and SGT IGBT (Insulated Gate Bipolar Transistor) devices. Among them, SGT MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices are widely used as switching devices and can achieve excellent power control performance.

[0003] The cell of an existing SGT power device typically consists of a shield gate and a control gate. When the SGT power device is turned on, the drain current flows along the longitudinal sidewalls of the SGT trench, forming an inversion layer channel on the surface of the body region. When a forward bias is applied to the source, electrons travel from the source region to the drain region along the inversion layer channel. After passing through the channel from the source region, the electrons enter the epitaxial region at the bottom of the trench gate and then spread across the entire width of the active region.

[0004] The SGT structure of power devices can be either top-bottom or left-right. In particular, for left-right SGT structures, how to effectively improve the withstand voltage of power devices is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a shielded gate power semiconductor device and its fabrication method, which can effectively improve the voltage withstand capability of the left and right SGT structures, is compatible with existing processes, and is safe and reliable.

[0006] According to the technical solution provided by the present invention, a shielded gate power semiconductor device is provided, the power semiconductor device comprising: Semiconductor substrate; The active region, located in the central region of the semiconductor substrate, comprises several parallel SGT cells, and the SGT structures within each SGT cell adopt a left-right structure. The SGT cell includes a shielding grid vertically distributed within the cell grooves. The shielding grid includes a first shielding unit and a second shielding unit interconnected with the first shielding unit. On the cross-section of the SGT cell, the contact connection between the first shielding unit and the second shielding unit forms a T-shape.

[0007] The length directions of the shielded first unit and the shielded second unit are consistent with the depth direction of the trench in the cell. Within the cell trench, the second shielding unit is located below the first shielding unit, and the lower end of the second shielding unit is adjacent to the bottom of the cell trench. The width of the first shielding unit is greater than the corresponding width of the second shielding unit.

[0008] Control grids are provided on both sides of the upper end of the first shielding unit, and the bottom of the control grids is located above the joint between the first shielding unit and the second shielding unit. Within the cell trench, the height of the shielding first unit is 20% to 50% of the depth of the cell trench.

[0009] The control grid is vertically or obliquely distributed on the outside of the shielding first unit body; The control gate is insulated from the sidewall of the cell trench by the control gate oxide layer, and the control gate is insulated from the shielding gate in the cell trench by the shielding gate oxide layer. The shielding gate oxide layer encapsulates the shielding gate, and the thickness of the shielding gate oxide layer is greater than the thickness of the control gate oxide layer.

[0010] Within the cell trench, when the control gates are distributed at an angle, the two control gates form a figure-eight shape.

[0011] When the control grid is vertically distributed, the length direction of the control grid is parallel to the length direction of the shielding grid; The vertically distributed control grid is columnar or T-shaped. When the control grid is T-shaped, it includes a first grid body and a second grid body connected to the first grid body. The second gate is located below the first gate, and the width of the second gate is smaller than the width of the first gate.

[0012] The width of all regions of the shielding first unit is consistent; Alternatively, the width of the groove opening of the adjacent cell of the shielding first unit is smaller than the width of the rest of the shielding first unit. Alternatively, along the direction from the first shielding unit to the second shielding unit, the width of the first shielding unit decreases in a stepped manner.

[0013] The semiconductor substrate includes a first conductivity type drift region and a first conductivity type substrate adjacent to the first conductivity type drift region, wherein, The doping concentration is the same in different regions within the first conductivity type drift region, or the first conductivity type drift region exhibits a variable doping state; When the first conductivity type drift region is in a variable doping state, the first conductivity type drift region includes at least a drift first doped region and a drift second doped region; The first doped region of the drift region is adjacent to the substrate of the first conductivity type, and the doping concentration of the first doped region of the drift region is higher than the corresponding concentration of the second doped region of the drift region; The first drift doped region at least covers the bottom of the cell trench.

[0014] A method for fabricating a shielded gate power semiconductor device, used to fabricate the shielded gate power semiconductor described above, wherein the fabrication method includes: A semiconductor substrate is provided, and a front-side cell process is performed on the front side of the semiconductor substrate to fabricate the desired active region within the semiconductor substrate after the front-side cell process. The active region is distributed in the central region of the semiconductor substrate and includes several SGT cells arranged in parallel, wherein the SGT structure within the SGT cell adopts a left-right structure. The SGT cell includes a shielding grid vertically distributed within the cell grooves. The shielding grid includes a first shielding unit and a second shielding unit interconnected with the first shielding unit. On the cross-section of the SGT cell, the contact connection between the first shielding unit and the second shielding unit forms a T-shape.

[0015] The front-side cell process includes: Cell trenches are formed on the front side of a semiconductor substrate, wherein the cell trenches extend vertically within the semiconductor substrate. A trench insulating oxide layer is prepared in the above-mentioned cell trench, the trench insulating oxide layer covers the inner wall of the cell trench, and a shielding grid first filling hole is formed in the cell trench; The shielding grid is filled into the first filling hole of the shielding grid to form a second shielding unit, the height of which is less than the depth of the cell trench. A shielding first unit cell is prepared within the aforementioned cell trench, and the shielding first unit cell is made to contact and connect with the shielding second unit cell. A control gate unit is fabricated within the aforementioned cell trench, the control gate unit comprising control gates distributed on both sides of the shielding first unit body.

[0016] Advantages of the present invention: The SGT cell includes a shielding grid vertically distributed within the cell trenches. The shielding grid includes a first shielding unit and a second shielding unit interconnected with the first shielding unit. On the cross-section of the SGT cell, the contact connection between the first shielding unit and the second shielding unit forms a T-shape. Because the width of the first shielding unit is relatively wide, and the thickness of the narrower shielding gate oxide layer will result in a larger field oxide layer capacitance, the electric field direction of the depleted charge in part of the semiconductor substrate will turn to the corner of the junction between the first shielding unit and the second shielding unit. Thus, the electric field can be shared by the shielding gate, so that the power semiconductor device has a more uniform depletion electric field, and thus can have a higher withstand voltage.

[0017] In the blocking state, the lower end of the shielding first unit not only shares the bottom electric field intensity, but also plays a good shielding role for the electric field near the top control gate, thereby preventing the power semiconductor device from breaking down prematurely at the bottom of the gate oxide. Therefore, the shielding gate of the present invention can also effectively reduce the electric field intensity at the bottom of the control gate oxide layer, preventing the power semiconductor device from breaking down prematurely at the bottom of the control gate oxide layer during the blocking process. Attached Figure Description

[0018] Figure 1 This is a cross-sectional view of a first embodiment of the shielded gate power semiconductor device of the present invention.

[0019] Figure 2 This is a cross-sectional view of a second embodiment of the shielded gate power semiconductor device of the present invention.

[0020] Figure 3 This is a cross-sectional view of a third embodiment of the shielded gate power semiconductor device of the present invention.

[0021] Figure 4 This is a cross-sectional view of the fourth embodiment of the shielded gate power semiconductor device of the present invention.

[0022] Figure 5 This is a cross-sectional view of the fifth embodiment of the shielded gate power semiconductor device of the present invention.

[0023] Figure 6 This is a cross-sectional view of the sixth embodiment of the shielded gate power semiconductor device of the present invention.

[0024] Figure 7 This is a cross-sectional view of the seventh embodiment of the shielded gate power semiconductor device of the present invention.

[0025] Figures 8-14 This is a schematic flowchart illustrating an embodiment of the fabrication of a shielded gate power semiconductor device according to the present invention, wherein, Figure 8This is a cross-sectional view of one embodiment of the cell trenches prepared according to the present invention.

[0026] Figure 9 This is a cross-sectional view of one embodiment of the present invention after the first filling hole of the shielding grid has been prepared.

[0027] Figure 10 This is a cross-sectional view of one embodiment of the shielded second unit body prepared according to the present invention.

[0028] Figure 11 This is a cross-sectional view of one embodiment of the present invention after obtaining the shielded second filling hole.

[0029] Figure 12 This is a cross-sectional view of one embodiment of the shielded first unit body prepared according to the present invention.

[0030] Figure 13 This is a cross-sectional view of an embodiment of the present invention after dry etching to obtain a control gate filling hole.

[0031] Figure 14 This is a cross-sectional view of one embodiment of the present invention after the control gate oxide layer is prepared by an oxidation process.

[0032] Explanation of reference numerals in the attached figures: 1-N-type drift region, 2-cell trench, 3-shielded second unit cell, 4-shielded first unit cell, 5-control gate, 6-shielded gate oxide layer, 7-N+ substrate, 8-control gate oxide layer, 9-drift first doped region, 10-drift second doped region, 11-first gate body, 12-drift third doped region, 13-second gate body, 14-trench insulating oxide layer, 15-shielded first filling via, 16-shielded second filling via, 17-control gate filling via. Detailed Implementation

[0033] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0034] To effectively improve the withstand voltage of the SGT structure with left and right sides, this invention provides a shielded gate power semiconductor device. Specifically, the power semiconductor device includes: Semiconductor substrate; The active region, located in the central region of the semiconductor substrate, comprises several parallel SGT cells, and the SGT structures within each SGT cell adopt a left-right structure. The SGT cell includes a shielding grid vertically distributed within the cell trench 2. The shielding grid includes a first shielding unit 4 and a second shielding unit 4 interconnected with the first shielding unit 3. On the cross-section of the SGT cell, the contact connection between the first shielding unit 4 and the second shielding unit 3 forms a T-shape.

[0035] It should be noted that the shielded gate power semiconductor device can be any of the commonly used device types, such as MOSFETs or IGBTs. The type of shielded gate power semiconductor device can be selected as needed, and will not be listed here. Similar to existing shielded gate power semiconductor devices, the shielded gate power semiconductor device of the present invention should include a semiconductor substrate and an active region fabricated in the central region of the semiconductor substrate. The semiconductor substrate can be of commonly used types, such as silicon substrates. The active region serves as the functional region of the power semiconductor device, and should include a plurality of SGT cells arranged in parallel. In the present invention, the SGT structure within the SGT cell should be a left-right structure.

[0036] Similar to existing SGT structures with a left-right configuration, the SGT cells of this invention should include a shielding gate vertically distributed within the cell trench 2. The function of the shielding gate is consistent with existing structures; for example, when the power semiconductor device is a MOSFET, the shielding gate is electrically connected to the source metal on the front side of the semiconductor substrate to form the source electrode of the MOSFET. Other cases will not be described in detail here. Unlike existing SGT structures with a left-right configuration, the shielding gate of this invention includes a first shielding unit 4 and a second shielding unit 3, which are interconnected.

[0037] Figures 1-7 ,as well as Figures 12-14 An embodiment of the shielding grid is shown in the figure. As can be seen from the figure, the contact connection between the first shielding unit 4 and the second shielding unit 3 of the present invention forms a T-shape. As can be seen from the figure, the corresponding length directions of the first shielding unit 4 and the second shielding unit 3 are consistent with the depth direction of the cell trench 2. In the cell trench 2, the second shielding unit 3 is located below the first shielding unit 4, and the lower end of the second shielding unit 3 is adjacent to the bottom of the cell trench 2, while the upper end of the second shielding unit 3 is connected to the lower end of the first shielding unit 4.

[0038] In one embodiment of the present invention, on the cross-section of the SGT cell, the width of the first shielding unit 4 is greater than the corresponding width of the second shielding unit 3. That is, when forming a T-shape, the width of the first shielding unit 4 should be greater than the corresponding width of the second shielding unit 3. Here, the width refers to the width on the cross-section of the SGT cell. Figures 1-7 as well as Figures 12-14 The width of the corresponding illustration.

[0039] It should be noted that when the contact connection between the first shielding unit 4 and the second shielding unit 3 forms a T-shape, the electric field strength between the semiconductors can be effectively adjusted, making the electric field distribution in the semiconductor substrate more uniform. This allows the power semiconductor device to obtain a higher withstand voltage under the same resistivity conditions. The principle of improving the withstand voltage of power semiconductor devices will be explained below.

[0040] In one embodiment of the present invention, control gates 5 are provided on both sides of the upper end of the shielding first unit body 4, and the bottom of the control gates 5 is located above the junction of the shielding first unit body 4 and the shielding second unit body 3. Within the cell trench 2, the height of the shielding first unit 4 is 20% to 50% of the depth of the cell trench 2.

[0041] Similar to existing SGT structures with a left-right configuration, the SGT structure of this invention should also include a control gate 5. Generally, the control gate 5 should be distributed on both sides of the shielding gate. When the SGT cell is elongated, both the control gate 5 and the shielding gate are elongated in the top view of the SGT cell. In one embodiment of this invention, the control gate 5 is distributed on both sides of the shielding first unit 4, and the bottom of the control gate 5 is located above the junction of the shielding first unit 4 and the shielding second unit 3. Similar to the prior art, the control gate 5 in each cell trench 2 should generally be electrically connected to the metal on the front side of the semiconductor substrate. If the power semiconductor device is a MOSFET, the control gate 5 should be electrically connected to the gate metal on the front side of the semiconductor substrate. It should be understood that the present invention... Figures 1-14 The source metal and gate metal on the front side of the semiconductor substrate are not shown in the diagram.

[0042] In one embodiment of the present invention, the control gate 5 is insulated from the sidewall of the cell trench 2 by the control gate oxide layer 8, and the control gate 5 is insulated from the shielding gate in the cell trench 2 by the shielding gate oxide layer 6. The shielding gate oxide layer 6 encloses the shielding gate, and the thickness of the shielding gate oxide layer 6 is greater than the thickness of the control gate oxide layer 8.

[0043] Similar to existing technologies, the control gate 5 should be insulated from the sidewalls of the cell trench 2 via the control gate oxide layer 8. The control gate 5 is generally made of conductive polysilicon. Similarly, the shielding first unit 4 and the shielding second unit 3 within the shielding gate are also generally made of conductive polysilicon. The control gate oxide layer 8 is generally a silicon dioxide layer. The control gate 5 is insulated from the shielding gate via the shielding gate oxide layer 6, meaning the control gate 5 is insulated from the shielding first unit 4 and the shielding second unit 3 via the shielding gate oxide layer 6.

[0044] Figures 1-7In this design, the shielding gate oxide layer 6 covers all areas except for the control gate oxide layer 8, and it can enclose both the first shielding unit 4 and the second shielding unit 3. Therefore, the first shielding unit 4 and the second shielding unit 3 can be insulated from the inner wall of the cell trench through the shielding gate oxide layer 6. It is understood that because the widths of the first shielding unit 4 and the second shielding unit 3 are different, the thickness of the shielding gate oxide layer 6 between the first shielding unit 4 and the sidewall of the cell trench 2 is different from the thickness of the shielding gate oxide layer between the second shielding unit 3 and the sidewall of the cell trench 2.

[0045] In the prior art, for SGT cells with a left-right structure, the shielding gate is long and straight, meaning the width of the shielding gate is basically equal and does not form a T-shape. When the power semiconductor device with the long and straight shielding gate is in reverse blocking state, the highest region of the electric field exists only in the depletion region near the bottom of the cell trench 2. This is because within the semiconductor substrate, the electric field direction of the depleted charge points towards the shielding gate at the corner of the cell trench 2, resulting in electric field concentration.

[0046] In the case of the shielding gate of the present invention, since the width of the shielding first unit body 4 is relatively wide, the thickness of the narrower shielding gate oxide layer 6 will result in a larger field oxide layer capacitance. At this time, the electric field direction of the depleted charge in part of the semiconductor substrate will turn to the corner of the junction between the shielding first unit body 4 and the shielding second unit body 3. Thus, the electric field can be shared by the shielding gate, so that the power semiconductor device has a more uniform depletion electric field, and thus can have a higher withstand voltage.

[0047] In the blocking state, the lower end of the shielding first unit 4 not only shares the bottom electric field intensity, but also plays a good shielding role for the electric field near the top control gate 5, thereby preventing the power semiconductor device from breaking down prematurely at the bottom of the gate oxide. Therefore, the shielding gate of the present invention can also effectively reduce the electric field intensity at the bottom of the control gate oxide layer 8, preventing the power semiconductor device from breaking down prematurely at the bottom of the control gate oxide layer 8 during the blocking process.

[0048] In order to effectively utilize the shielding grid to share the electric field, it is necessary to control the position of the joint between the first shielding unit 4 and the second shielding unit 3. In one embodiment of the present invention, the height of the first shielding unit 4 is 20% to 50% of the depth of the groove 2 of the cell. Specifically, the height of the first shielding unit 4 refers to the distance between the two ends of the first shielding unit 4. The two ends of the first shielding unit 4 are the upper end and the lower end, respectively. As can be seen from the above description, the lower end of the first shielding unit 4 is in contact with the second shielding unit 3, and the upper end of the first shielding unit 4 corresponds to the groove opening of the groove 2 of the cell.

[0049] In one embodiment of the present invention, the control gate 5 is vertically or obliquely distributed on the outside of the shielding first unit body 4; Within the cell trench 2, when the control gates 5 are distributed at an angle, the two control gates 5 form a figure-eight shape.

[0050] In practice, each control grid 5 can be vertically or obliquely distributed. Figure 1 , Figure 2 , Figures 4-7 The image shows an embodiment where the control gates 5 are vertically distributed. Figure 3 The diagram shows an embodiment where the control gate 5 is obliquely distributed, by Figure 3 It can be seen that when both control gates 5 are tilted, the two control gates 5 are in a figure-eight shape. At this time, the contact area between the two capacitor plates of the control gate 5 and the shield gate can be reduced, thereby reducing the input capacitance Ciss of the power semiconductor device.

[0051] In one embodiment of the present invention, when the control gate 5 is vertically distributed, the length direction of the control gate 5 is parallel to the length direction of the shielding gate; The vertically distributed control grid 5 is columnar or T-shaped. When the control grid 5 is T-shaped, it includes a first grid body 11 and a second grid body 13 connected to the first grid body 11. The second gate 13 is located below the first gate 11, and the width of the second gate 13 is smaller than the width of the first gate 11.

[0052] Figure 1 , Figure 2 as well as Figures 5-7 The illustration shows an embodiment in which the control gates 5 are vertically distributed and each control gate 5 is columnar, in which case the width of the control gates 5 is the same. Figure 4 The diagram illustrates an embodiment where the control gate 5 is T-shaped. In this embodiment, the control gate 5 includes a first gate body 11 and a second gate body 13 interconnected with the first gate body 11. The thickness of the control gate oxide layer 8 between the second gate body 13 and the sidewall of the cell trench 2 is greater than the thickness between the first gate body 11 and the sidewall of the cell trench 2. By adjusting the thickness of the control gate oxide layer 8 between the second gate body 13 and the cell trench 2, the electric field strength in the gate channel region under the blocking state can be effectively reduced, further improving the reliability of the power semiconductor device.

[0053] In one embodiment of the present invention, the width of all regions of the shielding first unit 4 is consistent; Alternatively, the width of the groove 2 of the adjacent cell of the shielding first unit 4 is smaller than the width of the rest of the shielding first unit 4. Alternatively, along the direction from the first shielding unit 4 to the second shielding unit 3, the width of the first shielding unit 4 decreases in a stepped manner.

[0054] In practice, the width or shape of the shielding first unit 4 can be adjusted according to actual needs. Figure 1 , Figure 3 and Figure 4 In the middle, the width of the first shielding unit 4 is the same. Figure 2 and Figure 5 In the shielding first unit 4, the width of the groove opening of the adjacent cell 2 is smaller than the width of the rest of the shielding first unit 4. Figure 6 and Figure 7 In the design, the width of the first shielding unit 4 decreases in a stepped manner. By varying the width of the first shielding unit 4, different process requirements can be accommodated.

[0055] When the conductivity type of the semiconductor substrate is N-type or P-type, the following description uses N-type conductivity as an example. In one embodiment of the present invention, the semiconductor substrate includes an N-type drift region 1 and an N+ substrate 7 adjacent to the N-type drift region 1, wherein... The doping concentration is the same in different regions within the N-type drift region 1, or the N-type drift region 1 exhibits a variable doping state; When the N-type drift region 1 is in a variable doping state, the N-type drift region 1 includes at least a first drift doping region 9 and a second drift doping region 10; The first doped region 9 of the drift region is adjacent to the N+ substrate 7, and the doping concentration of the first doped region 9 is higher than the corresponding concentration of the second doped region 10 of the drift region. The first doped region 9 of the drift at least covers the bottom of the cell trench 2.

[0056] Generally, the doping concentration of the N+ substrate 7 is greater than that of the N-type drift region 1. The aforementioned cell trenches 2 are fabricated within the N-type drift region 1, and the bottom of the cell trenches 2 typically does not extend into the N+ substrate 7. In specific implementations, the doping concentration of the N-type drift region 1 can be selected as needed, such as having the same doping concentration in different regions within the N-type drift region 1, or exhibiting a variable doping state within the N-type drift region 1. Figures 1-4 The example shown illustrates an embodiment where a single doping concentration exists within the N-type drift region 1. Figures 5-7 The diagram shows that several different doping concentrations can exist within the N-type drift region 1.

[0057] Figure 5 and Figure 6 In the N-type drift region 1, there are at least two drift regions: a first doped region 9 and a second doped region 10. Figure 7In this process, a third drift doping region 12 is provided between the first drift doping region 9 and the second drift doping region 10. The third drift doping region 12 is adjacent to both the first drift doping region 9 and the second drift doping region 10. The doping concentration of the third drift doping region 12 should generally be greater than that of the first drift doping region 9, and the doping concentration of the first drift doping region 9 should also generally be greater than that of the second drift doping region 10.

[0058] In specific implementation, when the N-type drift region 1 contains the first drift doped region 9, the second drift doped region 10, and the third drift doped region 12, the first drift doped region 9 covers the bottom of the cell trench 2. In addition, the junction of the third drift doped region 12 and the first drift doped region 9 should be located below the corresponding junction of the shielding first unit body 4 and the shielding second unit body 3.

[0059] When the N-type drift region 1 adopts a variable doping state, the device resistance in the on-state can be reduced. Since the high-concentration doped region has more depletion charge during the blocking process, the resulting electric field strength will be greater. Therefore, by setting different doping concentrations, the electric field distribution can be further changed. Combined with the effect of the shielding gate in adjusting the electric field distribution, the electric field distribution in the power semiconductor device can be made more uniform, while the overall electric field integral is larger, thereby obtaining a higher breakdown voltage.

[0060] The power semiconductor device described above can be prepared through the following process steps. This invention provides a method for preparing a shielded gate power semiconductor device, specifically, for preparing the aforementioned shielded gate power semiconductor, wherein the preparation method includes: A semiconductor substrate is provided, and a front-side cell process is performed on the front side of the semiconductor substrate to fabricate the desired active region within the semiconductor substrate after the front-side cell process. The active region is distributed in the central region of the semiconductor substrate and includes several SGT cells arranged in parallel, wherein the SGT structure within the SGT cell adopts a left-right structure. The SGT cell includes a shielding grid vertically distributed within the cell trench 2. The shielding grid includes a first shielding unit 4 and a second shielding unit 4 interconnected with the first shielding unit 3. On the cross-section of the SGT cell, the contact connection between the first shielding unit 4 and the second shielding unit 3 forms a T-shape.

[0061] Specifically, the semiconductor substrate can be referred to the above description. When fabricating the shielded gate power semiconductor device, the front cell process should generally be performed first, followed by the back cell process. When the semiconductor substrate adopts the above-described combination of N-type drift region 1 and N+ substrate 7, the corresponding surface of N-type drift region 1 forms the front side of the semiconductor substrate, and the corresponding surface of N+ substrate 7 forms the back side of the semiconductor substrate. The front and back sides of the semiconductor substrate are consistent with the prior art and will not be described again here.

[0062] After the frontal cell process, at least the above-mentioned active region can be prepared. The preparation of the active region is described above and will not be repeated here. In one embodiment of the present invention, the frontal cell process includes: Cell trench 2 is formed on the front side of a semiconductor substrate, wherein the cell trench 2 extends vertically within the semiconductor substrate. A trench insulating oxide layer 14 is prepared in the above-mentioned cell trench 2. The trench insulating oxide layer 14 covers the inner wall of the cell trench 2 and forms a shielding grid first filling hole 15 in the cell trench 2. The shielding grid is filled in the first filling hole 15 of the shielding grid to form the second shielding unit 3. The height of the second shielding unit 3 is less than the depth of the cell trench 2. A shielding first unit body 4 is prepared in the aforementioned cell trench 2, and the shielding first unit body 4 is made to contact and connect with the shielding second unit body 3. A control gate unit is fabricated within the aforementioned cell trench 2, the control gate unit comprising control gates 5 distributed on both sides of the shielded first unit body 4.

[0063] In practical implementation, during the frontal cell process, it is necessary to first prepare cell trenches 2. The method for preparing cell trenches 2 can be consistent with existing technologies. Figure 8 The figure shows an embodiment of the cell trench 2, in which the opening of the cell trench 2 corresponds to the front side of the semiconductor substrate, and the bottom of the cell trench 2 is adjacent to the N+ substrate 7.

[0064] After the cell trench 2 is prepared, the trench insulating oxide layer 14 can be prepared by thermal oxidation or oxide layer deposition. Figure 9 The figure shows an embodiment of preparing a trench insulating oxide layer 14. In the figure, the trench insulating oxide layer 14 does not completely fill the cell trench 2. At this time, a shielding grid first filling hole 15 can be formed in the cell trench 2.

[0065] The second shielding unit 3 can be prepared by filling the first filling hole 15 of the shielding grid. Figure 10As shown in the figure, the height of the second shielding unit 3 is less than the depth of the cell trench 2. The height of the second shielding unit 3 can be selected and determined according to the filling process.

[0066] Figure 11 and Figure 12 The figure shows an embodiment of preparing the first shielding unit 4. Specifically, after preparing the second shielding unit 3, the trench insulating oxide layer 14 can be etched to form the second filling hole 16 of the shielding grid. In the figure, the second shielding unit 3 extends into the second filling hole 16 of the shielding grid, and the width of the second filling hole 16 of the shielding grid is greater than the width of the second shielding unit 3.

[0067] It is understandable that after etching to form the second filling hole 16 of the shielding gate, it is mainly to prepare for filling to form the first shielding unit 4. Therefore, when etching to form the second filling hole 16 of the shielding gate, the thickness of the etching trench insulating oxide layer 14 is critical. When the thickness of the etching trench insulating oxide layer 14 is too thick, the electric field will be concentrated at the wide shielding gate, causing the power semiconductor device to break down prematurely. If the etching thickness is too thin, the electric field sharing effect will be very weak.

[0068] In specific implementation, when etching the trench insulating oxide layer 14, the thickness between one side of the shielding second unit 3 and the corresponding sidewall of the cell trench 2 is used as a reference, and the thickness of the trench insulating oxide layer 14 etched away is between 20% and 60% of the reference thickness.

[0069] After the second filling hole 16 of the shielding grid is formed, the first shielding unit 4 can be prepared through processes such as filling, for example... Figure 12 As shown in the figure, the first shielding unit 4 and the second shielding unit 3 are in contact and connected. Generally, the first shielding unit 4 and the second shielding unit 3 are made of the same material, such as conductive polycrystalline silicon.

[0070] In order to fabricate control gates on both sides of the shielding first unit 4, the trench insulating oxide layer 14 on both sides of the shielding first unit 4 should be etched to form control gate filling holes 17. The etching method of the trench insulating oxide layer 14 can be selected as needed, such as dry etching or wet etching. Figure 13 The diagram illustrates an embodiment employing wet etching, in which the trench insulating oxide layer 14 between the shielding first unit cell 4 and the corresponding cell trench 2 sidewall is etched; subsequently, a gate oxide process is performed to form the control gate oxide layer 8. Gate oxide processes often employ thermal oxidation processes; when thermal oxidation is used, the shielding first unit cell 4 is thermally oxidized to form… Figure 14 The diagram illustrates this situation. It should be noted that by controlling the temperature during thermal oxidation, the oxidation state of the shielding first unit 4 can be adjusted to form... Figure 2 , Figure 5 , Figure 6 and Figure 7 In the corresponding situations, the temperature of thermal oxidation can be selected as needed, which is well known to those skilled in the art and will not be elaborated here.

[0071] After obtaining the control gate oxide layer 8, it can be filled into the control gate filling holes 17 to form the control gate 5. Of course, if it is necessary to form... Figure 3 and Figure 4 When forming the corresponding control gate 5, the corresponding process steps need to be adjusted, specifically to ensure that the corresponding control gate 5 can be formed. Of course, if it is necessary to form... Figure 6 and Figure 7 When the corresponding shielding first unit 4 is formed, the above-mentioned process steps for forming the second filling hole 16 of the shielding grid should be adjusted. The specific process steps should be based on the ability to form the corresponding shielding first unit 4. Examples will not be given here.

[0072] After performing the front cell process, the back electrode process should be performed on the back side of the semiconductor substrate. The back electrode process can be consistent with the existing technology, and the specific details should be based on the ability to prepare the required power semiconductor device. These details will not be elaborated here.

Claims

1. A shielded gate power semiconductor device, characterized by, The power semiconductor device comprises: a semiconductor substrate; an active region distributed in a central region of the semiconductor substrate, comprising a plurality of SGT cells arranged side by side, and a SGT structure in the SGT cell adopts a left-right structure, wherein the SGT cell comprises a shield gate vertically arranged in the cell trench, and the shield gate comprises a shield first unit and a shield second unit connected with the shield first unit, on a cross section of the SGT cell, the contact connection between the shield first unit and the shield second unit forms a T shape.

2. The shielded gate power semiconductor device of claim 1, wherein: The length direction of the shield first unit and the shield second unit is consistent with the depth direction of the cell trench. In the cell trench, the shield second unit is located below the shield first unit, and the lower end of the shield second unit is adjacent to the bottom of the cell trench. The width of the shield first unit is greater than the corresponding width of the shield second unit.

3. The shielded gate power semiconductor device of claim 2, wherein the shield gate electrode is formed on the semiconductor body. The control gate is arranged on both sides of the upper end of the shield first unit, and the bottom of the control gate is located above the joint of the shield first unit and the shield second unit. In the cell trench, the height of the shield first unit is 20% to 50% of the depth of the cell trench.

4. The shielded gate power semiconductor device of claim 3, wherein: The control gate is vertically arranged or obliquely arranged outside the shield first unit. The control gate is insulated and isolated from the sidewall of the cell trench through a control gate oxide layer, and the control gate is insulated and isolated from the shield gate in the cell trench through a shield gate oxide layer. The shield gate oxide layer wraps the shield gate, and the thickness of the shield gate oxide layer is greater than the thickness of the control gate oxide layer.

5. The shielded gate power semiconductor device of claim 4, wherein: When the control gate is obliquely arranged, the two control gates form an eight-character shape.

6. The shielded gate power semiconductor device of claim 4, wherein: When the control gate is vertically arranged, the length direction of the control gate is parallel to the length direction of the shield gate. The vertically arranged control gate is columnar or T-shaped, wherein when the control gate is T-shaped, the control gate comprises a first gate body and a second gate body connected with the first gate body, the second gate body is located below the first gate body, and the width of the second gate body is less than the width of the first gate body.

7. The shielded gate power semiconductor device according to any one of claims 1 to 6, characterized in that: The width of all regions of the shield first unit is consistent. Alternatively, the width of the shield first unit adjacent to the cell trench opening is less than the width of the remaining regions of the shield first unit. Alternatively, along the direction of the shield first unit pointing to the shield second unit, the width of the shield first unit decreases in a stepped manner.

8. The shielded gate power semiconductor device according to any one of claims 1 to 6, characterized in that: The semiconductor substrate comprises a first conductive type drift region and a first conductive type substrate adjacent to the first conductive type drift region, wherein the doping concentration of different regions in the first conductive type drift region is the same, or the first conductive type drift region is in a variable doping state; when the first conductive type drift region is in a variable doping state, the first conductive type drift region comprises at least a drift first doped region and a drift second doped region; the drift first doped region is adjacent to the first conductive type substrate, and the doping concentration of the drift first doped region is higher than the corresponding concentration of the drift second doped region; the drift first doped region at least covers the bottom of the cell trench.

9. A method of fabricating a shielded gate power semiconductor device, characterized by, The method for preparing the shield gate power semiconductor in any one of claims 1 to 8 comprises: The semiconductor substrate is provided and a front surface cell process is performed on the front surface of the semiconductor substrate to prepare a required active region in the semiconductor substrate after the front surface cell process, wherein The active region is distributed in a central region of the semiconductor substrate and includes a plurality of parallelly distributed SGT cells, and the SGT structure in the SGT cell adopts a left-right structure. The SGT cell includes a shielding gate vertically distributed in a cell trench, and the shielding gate includes a shielding first unit body and a shielding second unit body connected with the shielding first unit body. On a cross section of the SGT cell, the contact connection between the shielding first unit body and the shielding second unit body forms a T shape.

10. The method of fabricating a shielded gate power semiconductor device according to claim 9, wherein The front surface cell process includes: A cell trench is prepared on the front surface of the semiconductor substrate, wherein the cell trench vertically extends in the semiconductor substrate; A trench insulation oxide layer is prepared in the cell trench, the trench insulation oxide layer covers the inner wall of the cell trench and forms a shielding gate first filling hole in the cell trench; Shielding gate filling is performed in the shielding gate first filling hole to form a shielding second unit body, and the height of the shielding second unit body is less than the depth of the cell trench; A shielding first unit body is prepared in the cell trench, and the shielding first unit body is in contact with the shielding second unit body; A control gate unit is prepared in the cell trench, and the control gate unit includes a control gate distributed on both sides of the shielding first unit body.

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