Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, an epitaxial layer located above the substrate, an isolation layer located in the substrate or the epitaxial layer, and a deep trench isolation piece which extends downwards in the epitaxial layer and is connected with the isolation layer. The isolation layer is located in the second region of the semiconductor structure, but does not extend to the first region of the semiconductor structure. The semiconductor structure also includes a first device in the first region and a second device in the second region. Further, the substrate may act as a drain region of the first device. The second device is located in an isolation region defined by the deep trench isolation piece and the isolation layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor structures and methods of fabricating the same, and more particularly to semiconductor structures and methods of fabricating the same that integrate different types of semiconductor devices on the same substrate. BACKGROUND

[0002] The semiconductor industry continues to improve the integration density of different electronic components by continuously reducing the minimum feature size, allowing more components to be integrated into a given area. Attempts have also been made to integrate different types of semiconductor devices on the same substrate. However, as the requirements for the electrical performance of semiconductor devices continue to increase, the complexity of integrating semiconductor devices also increases.

[0003] For example, lateral diffusion metal oxide semiconductor (LDMOS) devices can meet the requirements of high output power and gate-source breakdown voltage greater than 60 volts, and are mainly used in high-end audio amplifiers and radio power amplifiers for wireless cellular networks. The driving current of LDMOS devices is in the planar direction. Vertical devices such as vertical diffusion metal oxide semiconductor (VDMOS) devices have high voltage resistance characteristics and are widely used in power switch devices. The driving current of VDMOS devices flows in the vertical direction. Currently, integrating LDMOS devices and VDMOS devices with different driving current directions on a substrate increases the complexity of the formation method, and the electrical performance of each device in operation is easily affected by other different types of devices and cannot meet the application requirements. Therefore, although existing semiconductor devices are generally appropriate and sufficient for their intended purposes individually, they are not completely satisfactory in terms of integrated fabrication. SUMMARY

[0004] Some embodiments of the present disclosure provide a semiconductor structure including a substrate, an epitaxial layer above the substrate, an isolation layer in the substrate or in the epitaxial layer, and a deep trench isolation extending downward in the epitaxial layer and connected to the isolation layer. The isolation layer is located in a second region of the semiconductor structure but does not extend to a first region of the semiconductor structure. The semiconductor structure further includes a first device in the first region and a second device in the second region. Furthermore, the substrate includes a dopant that serves as a drain region of the first device. The second device is located in an isolation region defined by the deep trench isolation and the isolation layer.

[0005] Some embodiments of the present disclosure also provide a method for fabricating a semiconductor structure, including providing a substrate; forming an epitaxial layer over the substrate; forming an isolation layer in the substrate or in the epitaxial layer, wherein the isolation layer is located in a second region of the semiconductor structure but does not extend to a first region of the semiconductor structure; forming a deep trench isolation in the epitaxial layer extending downward, and the deep trench isolation is connected with the isolation layer; forming a first device in the first region, and the substrate serves as a drain region of the first device; and forming a second device in the second region, and the second device is located in an isolation region defined by the deep trench isolation and the isolation layer.

[0006] According to the semiconductor structure and the method for fabricating the same of some embodiments of the present disclosure, the configuration of the isolation structure can integrate different types of semiconductor devices, especially semiconductor devices with different current directions, on the same substrate. According to some embodiments, a locally-extended isolation layer is arranged in the substrate or the epitaxial layer, and one or more isolation regions are defined by the deep trench isolation and the isolation layer. Non-vertical semiconductor devices are arranged in the isolation regions, and vertical semiconductor devices are arranged in regions without the isolation layer. By arranging the local isolation layer, the influence of the conductive substrate on the electrical performance of the non-vertical semiconductor devices can be reduced, so that the integrated vertical and non-vertical semiconductor devices can achieve good electrical performance. Therefore, according to the application of the embodiments of the present disclosure, BCD (including Bipolar devices, CMOS devices and DMOS devices) and VDMOS devices can be integrated on the same wafer, so as to comprehensively solve the design problems of complex and high-power applications.

[0007] In addition, according to the method for fabricating the same of some embodiments of the present disclosure, the locally-extended isolation layer and the integrated semiconductor devices including different types of semiconductor devices can be manufactured in the substrate or the epitaxial layer by simple and compatible processes. When integrating different semiconductor devices, similar components can be manufactured together in the same process, so as to save processes, for example, multiple deep trench isolations can be formed in the same process, and wells or heavily doped regions of the same conductivity type can be formed in the same process. Therefore, the process of the embodiments is simple and does not significantly increase additional manufacturing costs. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a cross-sectional schematic view of a semiconductor structure at an intermediate fabrication stage according to some embodiments of the present disclosure.

[0009] Figure 2A 、 Figure 2B 、 Figure 2C is a partial cross-sectional schematic view of a semiconductor structure at multiple intermediate fabrication stages according to some embodiments of the present disclosure.

[0010] Figure 3A 、Figure 3B , Figure 3C This is a partial cross-sectional schematic diagram of a semiconductor structure at multiple intermediate manufacturing stages, according to some other embodiments of this disclosure.

[0011] Figure 4 This is a schematic cross-sectional view of a semiconductor structure at an intermediate manufacturing stage, according to some embodiments of this disclosure.

[0012] Figure 5A , Figure 5B for Figure 4 A magnified view of a portion of the semiconductor structure.

[0013] Symbol Explanation

[0014] 1,2: Semiconductor Structure

[0015] 11: First Device

[0016] 12: Second device

[0017] 13: Third device

[0018] 14: Fourth Device

[0019] 100: Substrate

[0020] 1030: Local region of oxygen ions

[0021] 104: Isolation Layer

[0022] 1040: Silicon oxide layer

[0023] 114: Deep trench isolation component

[0024] 114L: Lower part

[0025] 1142: First deep trench isolation component

[0026] 1143: Second deep trench isolation component

[0027] 1144: Third deep trench isolation component

[0028] 120: Epitaxial layer

[0029] 102: First epitaxial material layer

[0030] 112: Second epitaxial material layer

[0031] 16: Gate Structure

[0032] 31L: Lining

[0033] 311: Insulation layer

[0034] 313: Dielectric layer

[0035] 314: insulating portion

[0036] 31G: gate

[0037] 312: bottom gate

[0038] 316: top gate

[0039] 321, 331, 341: N-type well

[0040] 330, 340: P-type well

[0041] 331B, 340B: base region

[0042] 322, 324, 325, 332, 334, 335, 342, 344, 345, 3321, 3322, 3341, 3342, 3361, 3362, 3421, 3422, 3441, 3442, 3461, 3462: heavily doped portion

[0043] 326, 336, 346, 3361, 3362, 3461, 3462: gate structure

[0044] 100a, 102a, 104a, 112a, 114a, 120a, 1040a: top surface

[0045] 104b, 114b: bottom surface

[0046] 104S1, 104S2, 1031, 1032, 1041, 1042: opposite side

[0047] 720: mask

[0048] 722: opening

[0049] 800: local implantation of oxygen ions

[0050] d4, d5: distance

[0051] d10, d11, d12, S1, S2: spacing

[0052] W1, W2: width

[0053] A1: first region

[0054] A2: second region

[0055] A3: third region

[0056] A4: fourth region

[0057] D1: first direction

[0058] D2: second direction

[0059] D3: third direction DETAILED DESCRIPTION

[0060] The following description provides many examples and specific implementations of the various devices provided by the present disclosure. These examples and implementations are described in sufficient detail to provide a thorough understanding of embodiments of the present disclosure. Indeed, the concepts can have been and can be practiced within a variety of situations and environments. The descriptions are not meant to limit the different ways in which concepts described herein can be practiced. For example, the descriptions contain specific implementation details, such as particular devices, components, techniques, etc., that should not be construed as

[0061] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of describing one device or component's or other element's relationship to another device or component's or other element's orientation as the illustrations can be. The spatially relative terms are intended to encompass different orientations of the device in use or operation, for example, dependent on the position of the device relative to the other device(s) or element(s). The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0062] Some variations of the embodiments described below are provided. In the various drawings and descriptions of the embodiments, like-numbers refer to like- elements throughout. It will be appreciated that additional steps can be provided before, during, and / or after the steps described, and that some of these described steps can be replaced or eliminated, for example, for further embodiments of the method.

[0063] The present disclosure provides semiconductor structures and methods of fabricating the same. The embodiments of the present disclosure provide isolation structures, such as local isolation layers and deep trench isolation, to integrate different types of semiconductor devices, particularly semiconductor devices with different current flow directions, on the same substrate, such as a wafer. The embodiments of the present disclosure provide semiconductor devices with good electrical performance. The embodiments of the present disclosure provide methods of fabricating semiconductor structures with simple processes and without expensive manufacturing costs.

[0064] Applications of the embodiments include integrating multiple semiconductor devices with different current directions during operation on a single substrate. These semiconductor devices are, for example, metal-oxide-semiconductor (MOS) devices, including complementary MOS (CMOS), lateral-diffused MOS (LDMOS), double-diffused MOS (DMOS), vertical-diffused MOS (VDMOS), or other MOS devices. For example, a VDMOS device with a vertical current direction and an LDMOS device, CMOS device, or other semiconductor device with a horizontal current direction can be integrated on the same substrate. However, this disclosure is not limited to the aforementioned devices.

[0065] Figure 1 This is a simplified cross-sectional view of a semiconductor structure 1 at an intermediate manufacturing stage, according to some embodiments of the present disclosure. According to embodiments, multiple semiconductor devices of different types can be integrated on a substrate 100. An isolation region is formed by forming a locally extended isolation layer, such as a silicon-on-insulator (SOI) layer, in the substrate or epitaxial layer, and forming deep trench isolation members connected to the isolation layer. This provides a placement area for semiconductor devices with horizontally oriented operating currents, while semiconductor devices with vertically oriented operating currents can be placed in areas outside the isolation layer.

[0066] According to an embodiment, at least one semiconductor device with a vertical current direction and at least one semiconductor device with a horizontal current direction are integrated on substrate 100. This example illustrates the integration of one semiconductor device with a vertical current direction and three semiconductor devices with horizontal current directions.

[0067] like Figure 1 As shown in this example, a first device 11, a second device 12, a third device 13, and a fourth device 14 are respectively disposed in the first region A1, the second region A2, the third region A3, and the fourth region A4 of the semiconductor structure 1 to form the semiconductor structure 1. The first device 11, the second device 12, the third device 13, and the fourth device 14 are laterally separated (e.g., in the first direction D1).

[0068] In this example, the first device 11 is a vertical metal-oxide-semiconductor device, such as a VDMOS device, in which a split trench gate (SGT) structure is used as the gate structure 16 of the VDMOS device. However, the disclosure is not limited to this. In some other embodiments, the first device 11 can include a general trench gate structure. The second device 12, the third device 13, and the fourth device 14 are non-vertical metal-oxide-semiconductor devices, such as NMOS devices, LDPMOS devices, and LDNMOS devices, respectively. However, the semiconductor devices that can be integrated by the disclosure are not limited to the above types.

[0069] Further, for the purpose of clearly illustrating the content of the embodiments, Figure 1 The detailed structures of these setting devices are omitted from being shown and described. Some applicable configurations of the first device 11 to the fourth device 14 and related components will be described later (e.g., with reference to Figure 4 、 Figure 5A 、 Figure 5B ) for illustrative but non-limiting purposes.

[0070] According to some embodiments, the semiconductor structure 1 further includes an epitaxial layer 120 and a partially extended isolation layer 104. The epitaxial layer 120 is located above the substrate 100. In some embodiments, the isolation layer 104 is located in the epitaxial layer 120 (as shown in Figure 1 、 Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 4 、 Figure 5A 、 Figure 5B shown). In some embodiments, the isolation layer 104 is located in the substrate 100 (as shown in Figure 2A 、 Figure 2B 、 Figure 2C ).

[0071] Referring to Figure 1 , in this example, the isolation layer 104 is located in the epitaxial layer 120 and outside the first region A1. Further, the isolation layer 104 is partially formed above the substrate 100 and spaced apart from the substrate 100 by a distance. As shown in Figure 1 , the bottom surface 104b of the isolation layer 104 is spaced apart from the top surface 100a of the substrate 100 by a distance d10 in a vertical direction (e.g., the third direction D3).

[0072] Further, the isolation layer 104 extends continuously (e.g., along the first direction D1) in the second region A2, the third region A3, and the fourth region A4, for example, but does not extend to the first region A1. Although Figure 1The cross-section shows an elongated isolation layer 104 extending in the first direction D1, but when viewed from above the substrate 100 (not shown), this locally disposed isolation layer 104 also extends in the second direction D2.

[0073] According to some embodiments, the material of the isolation layer 104 includes a single layer or multiple layers of insulating material, such as silicon oxide, germanium oxide, other suitable semiconductor oxide materials, or combinations thereof. Furthermore, the isolation layer 104 may contain suitable dopants or may not contain any dopants. In some non-limiting examples, the isolation layer 104 is a silicon oxide layer.

[0074] In some embodiments, the substrate 100 is a substrate doped with a high concentration of a first conductivity type, such as a silicon wafer. In applications where a vertical metal-oxide-semiconductor device is used as the first device 11, since the first region A1 does not contain the isolation layer 104, the substrate 100 with the first conductivity type can serve as the drain region of the first device 11, allowing the drive current to flow in the vertical direction (e.g., the third direction D3). In some embodiments, a back-side conductor layer (not shown) is also formed below the substrate 100 to contact the bottom surface of the substrate 100, and the back-side conductor layer forms the drain terminal of the first device 11. In some embodiments, the first conductivity type is n-type, so the substrate 100 is, for example, a highly doped n-type substrate. However, this disclosure is not limited to this; in some other embodiments, the first conductivity type can also be p-type, which is the opposite conductivity type.

[0075] In some embodiments, the epitaxial layer 120 has the same conductivity type as the substrate 100. In this example, both the substrate 100 and the epitaxial layer 120 have a first conductivity type, such as (but not limited to) n-type. Furthermore, the doping concentration of the substrate 100 is greater than the doping concentration of the epitaxial layer 120.

[0076] Furthermore, the epitaxial layer 120 can be a single-layer or multi-layer structure. For example... Figure 1 As shown, in this example, the epitaxial layer 120 includes a first epitaxial material layer 102 and a second epitaxial material layer 112. In some embodiments, a partially disposed isolation layer 104 is located in the first epitaxial material layer 102, and the isolation layer 104 extends continuously in the second region A2, the third region A3, and the fourth region A4. Since the isolation layer 104 in this example is embedded in the first epitaxial material layer 102, the second epitaxial material layer 112 directly contacts the first epitaxial material layer 102 and is spaced apart from the underlying isolation layer 104 by a distance. For example Figure 1As shown, a top surface 104a of the isolation layer 104 is spaced apart from a top surface 102a of the first epitaxial material layer 102 (also a bottom surface of the second epitaxial material layer 112) in a vertical direction (e.g., the third direction D3) by a distance d11.

[0077] Generally, the epitaxial layer 120 of the multi-layer structure can adjust the breakdown voltage. The thicker the epitaxial layer 120, the higher the breakdown voltage. Further, the structure of the epitaxial layer 120 can also be selected according to the actual application of other components and the epitaxial layer 120. For example, when the doping concentration of the substrate 100 is very high, the epitaxial layer 120 with a multi-layer structure (e.g., including the first epitaxial material layer 102 and the second epitaxial material layer 112) is formed. When the doping concentration of the substrate 100 is not very high, the epitaxial layer 120 of a single layer (e.g., not including the first epitaxial material layer 102) can be formed. Therefore, whether to form the epitaxial layer 120 of a single layer or a multi-layer structure can be determined according to the actual application, and the present disclosure does not have a particular limitation thereon.

[0078] According to some embodiments, the semiconductor structure 1 further includes a deep trench isolation 114 extending downward in the epitaxial layer 120 and connected to the isolation layer 104. For example, the deep trench isolation 114 extends from the top surface 120a of the epitaxial layer 120 toward the substrate 100, e.g., along the third direction D3.

[0079] In some embodiments, the bottom of the deep trench isolation 114 can not exceed the bottom of the isolation layer 104. In some other embodiments, the bottom of the deep trench isolation 114 can exceed the bottom of the isolation layer 104. Accordingly, the bottom of the deep trench isolation 114 can be at substantially the same level as the bottom of the isolation layer 104, or can be at different levels. The present disclosure does not have a particular limitation thereon, and appropriate design and adjustment can be made according to the actual process.

[0080] In some examples, the deep trench isolation 114 can extend through the second epitaxial material layer 112 to the isolation layer 104. For example, a lower portion 114L of the deep trench isolation 114 can be located in or pass through the isolation layer 104. As shown in FIG. 1B, the lower portion 114L of the deep trench isolation 114 extends from the top surface 104a of the isolation layer 104 to the bottom surface 104b of the isolation layer 104. Figure 1 As shown, the lower portion 114L of the deep trench isolation 114 extends from the top surface 104a of the isolation layer 104 to the bottom surface 104b of the isolation layer 104.

[0081] It is worth noting that, although Figure 1 The cross-sectional view shows that two long strip cross-sections (extending in the third direction D3) of the deep trench isolation 114 are formed in the second region A2, the third region A3, and the fourth region A4, respectively, but if viewed from above the substrate 100, these deep trench isolations 114 are, for example, a closed ring, respectively, surrounding the periphery of the subsequently formed device.

[0082] According to some embodiments, the isolation structure formed by the locally formed isolation layer 104 and the deep trench isolation 114 can define an isolation region, such that the semiconductor devices (e.g., the second device 12 / the third device 13 / the fourth device 14) disposed in the isolation region can be well electrically isolated from the semiconductor devices (e.g., the first device 11) outside the isolation region. In particular, in some examples where the first device 11 is a VDMOS device, the substrate 100, which serves as the drain of the first device 11, is connected to a drain operating voltage, and the operation of the first device 11 does not affect the electrical performance of the other integrated devices (e.g., the second device 12 / the third device 13 / the fourth device 14) on the substrate 100 in the isolation region.

[0083] Further, in some embodiments, the semiconductor structure 1 includes independently formed deep trench isolations 114, which, in combination with the isolation layer 104, can define different isolation regions. In particular, as shown in FIG. 1, the semiconductor structure 1 includes a first deep trench isolation 1142, a second deep trench isolation 1143, and a third deep trench isolation 1144, which are in combination with the isolation layer 104, and are laterally (e.g., in the first direction D1) spaced apart by appropriate distances. Figure 1

[0084] In some examples, the second device 12 is disposed in an isolation region defined by the first deep trench isolation 1142 and the isolation layer 104, where the first deep trench isolation 1142, for example, encloses the periphery of the second device 12. The third device 13 is disposed in an isolation region defined by the second deep trench isolation 1143 and the isolation layer 104, where the second deep trench isolation 1143, for example, encloses the periphery of the third device 13. The fourth device 14 is disposed in an isolation region defined by the third deep trench isolation 1144 and the isolation layer 104, where the third deep trench isolation 1144, for example, encloses the periphery of the fourth device 14.

[0085] Further, the first deep trench isolation 1142 and the second deep trench isolation 1143 are laterally spaced apart by a distance d4, and the second deep trench isolation 1143 and the third deep trench isolation 1144 are laterally spaced apart by a distance d5. The distance d4 and the distance d5 can be the same or different, and their actual values can be appropriately selected and adjusted according to the desired integrated device pattern.

[0086] ​Furthermore, in the example where a vertically diffused metal-oxide-semiconductor (VDMOS) device is used as the first device 11, the bottom of its gate structure 16 (e.g., a trench gate structure) may be higher or lower than the isolation layer 104, or approximately at the same horizontal level as the isolation layer 104; this disclosure does not impose any particular limitation on this. Generally, the closer the bottom of the gate structure 16 is to the substrate 100 (which has a first conductivity type (e.g., n-type) dopant) serving as the drain region, the better the electrical performance of the VDMOS device. Therefore, the depth of the gate structure 16 can adjust the vertical current of the VDMOS. However, the bottom surface of the gate structure 16 of the VDMOS device does not contact the substrate 100 serving as the drain region; that is, it needs to be separated from the substrate 100 by a distance. In addition, in some embodiments where horizontal devices such as N / PMOS and LDMOS are used as the second device 12, the third device 13, and the fourth device 14, in addition to the good electrical isolation between the multiple devices being achieved by the configuration of the locally disposed isolation layer 104 and the deep trench isolation member 114, the farther the second device 12, the third device 13, and the fourth device 14 are from the substrate 100, the more the influence of the conductive substrate 100 (e.g., an n-type substrate) on the horizontal MOS devices such as the second device 12, the third device 13, and the fourth device 14 can be reduced.

[0087] The following illustrations, with reference to the accompanying drawings, illustrate methods for forming isolation structures (including partial isolation layers 104 and deep trench isolation members 114) according to some embodiments of this disclosure. It should be noted that the details of the following related content are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, other known methods may also be applied to fabricate the isolation structures of the embodiments.

[0088] Figure 2A , Figure 2B , Figure 2C This is a partial cross-sectional schematic diagram of a semiconductor structure at multiple intermediate manufacturing stages according to some embodiments of this disclosure. This example uses a single-layer epitaxial layer 120 as an example (but not a limitation).

[0089] Reference Figure 2A According to some embodiments, a substrate 100 is provided, and a mask 720 is provided over the substrate 100. This mask 720 has, for example, a specific pattern to correspond to the location of an isolation layer 104 to be subsequently formed. The mask 720 has, for example, an opening 722 that exposes a portion of the top surface 100a of the substrate 100. In this example, local isolation regions can be formed in the substrate 100 by means of the mask 720 and ion local implantation.

[0090] For example, in some embodiments, a mask material (not shown) is formed on the substrate 100. The mask material is, for example, a hard mask material, which can include an oxide, other suitable material, or combination thereof. The mask material can be a single layer or multiple layers of material. For simplicity, the mask material is illustrated as a single layer in the figures. In some embodiments, an oxide hard mask material, such as silicon dioxide (SiO2), can be deposited on the substrate 100.

[0091] Thereafter, a suitable lithography process can be performed on the mask material to form the mask 720 having the desired pattern. For example, in some embodiments, a patterned photoresist (not shown) corresponding to the locations of the isolation layer 104 can be formed on the mask material (e.g., oxide hard mask material). The patterned photoresist has, for example, a plurality of openings (not shown) to expose the top surface of the underlying mask material. The openings of the patterned photoresist correspond to the locations of the openings 722 to be formed later.

[0092] Further, the patterned photoresist can be formed by, for example, coating (e.g., spin coating), soft baking, mask aligning, exposing, post-exposure baking, developing, cleaning, and drying (e.g., hard baking), other suitable processes, or combination thereof.

[0093] Thereafter, the mask material is etched according to the patterned photoresist to form the mask (e.g., oxide hard mask) 720. The openings 722 of the mask 720 expose portions of the top surface 100a of the substrate 100.

[0094] After the mask 720 is formed, the patterned photoresist is removed.

[0095] Thereafter, referring back to Figure 2A According to some embodiments, a partial implantation process is performed on the substrate 100 according to the mask 720, such as a partial implantation of oxygen ions 800 through the openings 722 to form a partial region of oxygen ions 1030 in the substrate 100.

[0096] According to some embodiments, the partial region of oxygen ions 1030 is formed to correspond to the openings 722, and the maximum width W2 of the partial region of oxygen ions 1030 is greater than the width Wl of the openings 722. In this example, the maximum width W2 of the partial region of oxygen ions 1030 is defined according to the maximum distance between the opposite sides 1031 and 1032 of the partial region of oxygen ions 1030 in the first direction Dl.

[0097] After the partial region of oxygen ions 1030 is formed, referring back to Figure 2BAccording to some embodiments, the mask 720 is removed. According to some embodiments, the mask 720 can be removed by an ashing process, a wet etching process (e.g., acid etching), or other acceptable processes. After the mask 720 is removed, a cleaning process can be optionally performed to remove residue.

[0098] Afterwards, according to some embodiments, an annealing process is performed to react the oxygen ions in the oxygen ion local region 1030 with the material of the substrate 100 to form a silicon-containing oxide layer 1040, such as a SiO2layer.

[0099] Due to the thermal energy of the annealing process, the dopants are activated and driven to diffuse outward, the silicon-containing oxide layer 1040 can have a slightly larger area than the oxygen ion local region 1030. Figure 2B Figure 10B shows the silicon-containing oxide layer 1040 after the annealing process, which has opposite sides 1041 and 1042. According to some embodiments, the distance between the opposite sides 1041 and 1042 of the silicon-containing oxide layer 1040 in the first direction is slightly larger than the distance between the opposite sides 1031 and 1032 of the oxygen ion local region 1030 in the first direction (i.e., the width W2of Figure 10A). Further, according to some embodiments, the top surface 1040a of the silicon-containing oxide layer 1040 is spaced apart from the top surface 100a of the substrate 100 by a distance S1. Figure 2A

[0100] Afterwards, referring to Figure 2C According to some embodiments, an epitaxial layer 120 is formed over the substrate 100, and the deep trench isolation 114 is formed in the epitaxial layer 120 to connect the isolation layer 104 in the substrate 100.

[0101] In some embodiments, an epitaxial material is formed over the substrate 100. Since the silicon-containing oxide layer 1040 of this example is embedded in the substrate 100, the silicon-containing oxide layer 1040 does not contact the epitaxial material. As shown in Figure 10D, the silicon-containing oxide layer 1040 is spaced apart from the top surface 100a of the substrate 100 by a distance d12. This distance d12 is substantially equal to the distance S1 Figure 2C Figure 2B

[0102] Afterwards, a suitable lithography process can be performed to define the location of the deep trench isolation 114.

[0103] ​​​According to some embodiments, a mask (not shown) can be formed over the epitaxial material, and the mask has openings corresponding to locations where the deep trench isolation 114 is to be formed. In some embodiments, the mask is a patterned photoresist formed from a photoresist material. In some other embodiments, the mask can be a hard mask (HM) composed of an oxide layer and a nitride layer. In some examples where a patterned photoresist is used as the mask, the photoresist process includes coating (e.g., spin coating), soft baking, mask aligning, exposure, post-exposure baking, developing, cleaning, and drying (e.g., hard baking), other suitable processes, or combinations thereof, to form the openings of the mask.

[0104] Then, portions of the epitaxial material (e.g., through the epitaxial material) and portions of the substrate 100 are removed according to the openings of the mask to form deep trenches (not shown). The deep trenches are connected to the isolation layer 104.

[0105] In some embodiments, portions of the silicon-containing oxide layer 1040 are also removed when the deep trenches are formed, such as portions of the opposite sides 1041 and 1042 of the silicon-containing oxide layer 1040. The remaining portions of the epitaxial material 1200 form the epitaxial layer 120, and the remaining portions of the silicon-containing oxide layer 1040 form the isolation layer 104. Thus, in this example, the deep trenches expose the epitaxial layer 120, the substrate 100, and the isolation layer 104 from top to bottom at the sidewalls adjacent to the isolation layer 104.

[0106] Then, the deep trenches are filled with a suitable material, and portions of the material are removed by a suitable planarization process to form the deep trench isolation 114 in the epitaxial layer 120. As shown, the deep trench isolation 114 extending downward from the top surface 120a of the epitaxial layer 120 connects the opposite sides 104S1 and 104S2 of the isolation layer 104. Figure 2C

[0107] The planarization process can be, for example, a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etch-back process, other suitable processes, or combinations thereof. According to some embodiments, after the planarization process, the top surface 114a of the deep trench isolation 114 is substantially coplanar with the top surface 120a of the epitaxial layer 120.

[0108] ​In some embodiments, each deep trench isolation 114 includes an insulating material. In some embodiments, each deep trench isolation 114 includes an insulating material (not shown) and a conductive material (not shown), where the insulating material coats the sidewalls and the bottom of the conductive material. The insulating material includes, for example and without limitation, silicon oxide, germanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, hafnium aluminum oxide, silicon hafnium oxide, silicon aluminum hafnium oxide, silicon aluminum hafnium nitride oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, other suitable materials, or combinations thereof. In some embodiments, the conductive material includes amorphous silicon, polysilicon, other suitable materials, or combinations thereof. In some examples, the insulating material includes silicon oxide and the conductive material includes polysilicon.

[0109] Accordingly, after forming the deep trench isolation 114 connected to the isolation layer 104, the fabrication of the isolation structure of the embodiments is completed.

[0110] Although Figure 2A , Figure 2B , Figure 2C In some embodiments, the epitaxial layer 120 can include multiple layers of epitaxial material.

[0111] Figure 3A , Figure 3B , Figure 3C According to some embodiments of the present disclosure, a semiconductor structure at various intermediate fabrication stages is shown in FIGS. 1A-1E. In this example, a multi-layer epitaxial layer 120 is used for illustrative (but not limiting) purposes. Further, Figure 3A , Figure 3B , Figure 3C In some embodiments, the epitaxial layer 120 can include multiple layers of epitaxial material. Figure 2A , Figure 2B , Figure 2C , Figure 1 The same or similar components in FIGS. 1A-1E are designated by the same or similar reference numbers for ease of illustration.

[0112] Unlike the embodiments of FIGS. 1A-1E, the embodiments of FIGS. 2A-2E form the isolation layer 104 in the substrate 100 first, and then form the epitaxial layer 120 on the substrate 100, Figure 2A , Figure 2B , Figure 2C Unlike the embodiments of FIGS. 1A-1E, the embodiments of FIGS. 2A-2E form the isolation layer 104 in the substrate 100 first, and then form the epitaxial layer 120 on the substrate 100, Figure 3A , Figure 3B , Figure 3C Unlike the embodiments of FIGS. 1A-1E, the embodiments of FIGS. 2A-2E form the isolation layer 104 in the substrate 100 first, and then form the epitaxial layer 120 on the substrate 100,

[0113] Unlike the embodiments of FIGS. 1A-1E, the embodiments of FIGS. 2A-2E form the isolation layer 104 in the substrate 100 first, and then form the epitaxial layer 120 on the substrate 100, Figure 3AAs shown, according to some embodiments, a substrate 100 is provided, and a first epitaxial material layer 102 is formed on the substrate 100. A mask 720 is then formed on the first epitaxial material layer 102. The mask 720, for example, has an opening 722 that exposes a portion of the top surface 100a of the substrate 100.

[0114] Subsequently, according to some embodiments, oxygen ion local implantation 800 can be performed on the first epitaxial material layer 102 through the opening 722 of the mask 720 to form an oxygen ion local region 1030 in the first epitaxial material layer 102.

[0115] about Figure 3A For details regarding the configuration, materials, and manufacturing methods of the first epitaxial material layer 102, the mask 720, and the oxygen ion local region 1030, please refer to the above. Figure 2A The relevant descriptions of the epitaxial layer 120, the mask 720, and the oxygen ion local region 1030 will not be repeated here.

[0116] After that, as Figure 3B As shown, according to some embodiments, the mask 720 is removed and an annealing process is performed so that the oxygen ions in the oxygen ion local region 1030 react with the material of the first epitaxial material layer 102 to form a silicon oxide layer 1040, such as a SiO2 layer.

[0117] Because the silicon oxide layer 1040 in this example is embedded in the first epitaxial material layer 102, the silicon oxide layer 1040 does not contact the substrate 100. Figure 3B As shown, the top surface 1040a of the silicon oxide layer 1040 and the top surface 102a of the first epitaxial material layer 102 are separated by a distance S2.

[0118] about Figure 3B For details regarding the configuration, materials, and fabrication method of the silicon oxide layer 1040, please refer to the above. Figure 2B The relevant descriptions of the silicon oxide layer 1040 are not repeated here.

[0119] After that, as Figure 3C As shown, according to some embodiments, a second epitaxial material layer 112 is formed above the first epitaxial material layer 102. Furthermore, a deep trench spacer 114 is formed in the epitaxial layer 120 to connect the spacer layer 104 in the first epitaxial material layer 102. The deep trench spacer 114, for example, connects opposite sides 104S1 and 104S2 of the spacer layer 104.

[0120] According to some embodiments, the deep trench isolation 114 extends downward from a top surface 112a of the second epitaxial material layer 112 (i.e., a top surface 120a of the epitaxial layer 120) to pass through the second epitaxial material layer 112 and a portion of the first epitaxial material layer 102 to connect with the isolation layer 104. As shown in Figure 3C the top surface 104a of the isolation layer 104 is spaced apart from the top surface 102a of the first epitaxial material layer 102 above by a distance d11. The distance d11 is substantially equal to the distance S2 (as described above). Figure 3B ) above.

[0121] Further, according to some embodiments, as shown in Figure 3C the bottom surface 114b of the deep trench isolation 114 connected with the isolation layer 104 is, for example but not limited to, substantially coplanar with a bottom surface 104b of the isolation layer 104. Further, since the isolation layer 104 is buried in the first epitaxial material layer 102 in this example, the bottom surface 114b of the deep trench isolation 114 is covered by the first epitaxial material layer 102. As shown in Figure 3C the bottom surface 114b of the deep trench isolation 114 is spaced apart from the top surface 100a of the substrate 100 by a distance d10 in the vertical direction (e.g., the third direction D3).

[0122] Details regarding the configuration, materials, and fabrication of the second epitaxial material layer 112, the deep trench isolation 114, and the isolation layer 104 in Figure 3C may refer to the related descriptions of the epitaxial layer 120, the deep trench isolation 114, and the isolation layer 104 in Figure 2C above, which are not repeated here.

[0123] In this example, as shown in Figure 3C the first epitaxial material layer 102 and the second epitaxial material layer 112 can be collectively referred to as the epitaxial layer 120. According to embodiments as described above, the isolation layer 104 is formed in the epitaxial layer 120, for example, in the first epitaxial material layer 102, and there can be an epitaxial material layer (e.g., a portion of the first epitaxial material layer 102) of the epitaxial layer 120 between the isolation layer 104 and the substrate 100. Figure 3C

[0124] In addition to the steps of ion implantation and annealing described above to fabricate the isolation layer 104, other ways can be used to form the isolation layer 104, which are not limited in the present disclosure.

[0125] According to the fabrication method described above, a locally-extended isolation layer 104 can be formed in some regions of the semiconductor structure, and a deep trench isolation 114 connected with the isolation layer 104 can be formed to define regions in which one or more semiconductor devices with a driving current in the horizontal direction can be disposed. Regions without the isolation layer 104 are used to dispose semiconductor devices with a driving current in the vertical direction.​

[0126] The following is an example of a semiconductor structure 2 used in device integration, which integrates VDMOS devices, N / P-type MOS devices, P-type LDMOS devices, and N-type LDMOS devices. However, the semiconductor devices that can be integrated in this disclosure are not limited to the above combinations.

[0127] Figure 4 This is a schematic cross-sectional view of a semiconductor structure 2 at an intermediate manufacturing stage, according to some embodiments of the present disclosure. Figure 5A , Figure 5B for Figure 4 A magnified view of a portion of semiconductor structure 2. Figure 4 , Figure 5A , Figure 5B and Figure 1 Identical or similar components use the same or similar reference numbers, and the content regarding the multiple components in the above embodiments can be referred to, which will not be repeated in this example.

[0128] like Figure 4 As shown, in some embodiments, the semiconductor structure 2 includes a plurality of VDMOS devices disposed in the first region A1 as the first device 11, and in the example, a separated trench gate (SGT) structure is used as the gate structure 16 of the VDMOS device, but this disclosure is not limited thereto.

[0129] In some embodiments, the semiconductor structure 2 further includes an N / P-type MOS device disposed in the second region A2 as an example of the second device 12; a P-type LDMOS device disposed in the third region A3 as an example of the third device 13; and an N-type LDMOS device disposed in the fourth region A4 as an example of the fourth device 14. According to some embodiments, the isolation layer 104 in the semiconductor structure 2 is locally formed above the substrate 100, for example, in the first epitaxial material layer 102. Furthermore, the isolation layer 104 is not in direct contact with the upper second epitaxial material layer 112 and the lower substrate 100. Moreover, according to some embodiments, the isolation layer 104 extends continuously along the first direction D1 in the second region A2, the third region A3, and the fourth region A4, but does not extend to the first region A1.

[0130] Reference Figure 4 , Figure 5A According to some embodiments, in one example where a VDMOS device is used as the first device 11, each first device 11 includes a gate structure 16 and a heavily doped portion (not shown) adjacent to one side of the gate structure 16 and extending downward from the top surface 120a of the epitaxial layer 120, serving as the source region of the first device 11. The substrate 100 (e.g., n-type) serves as the drain region of the first device 11.

[0131] In some embodiments, a heavily doped portion (not shown) of the source region of the first device 11 and the epitaxial layer 120 have the same conductivity type, and the heavily doped portion has a higher doping concentration than the epitaxial layer 120.

[0132] In some embodiments, the substrate 100, the epitaxial layer 120, and the heavily doped portion of the source region of the first device 11 have a first conductivity type, such as, but not limited to, n-type. Further, the substrate 100 has a higher doping concentration than the epitaxial layer 120.

[0133] In some embodiments, the location of the gate structure 16 of the first device 11 can be defined by a suitable photolithography process. For example, a mask can be formed over the epitaxial layer 120, and a recess (not shown) can be formed in the epitaxial layer 120 (e.g., in the second epitaxial material layer 112) through the mask. Then, the insulating layer 311 and the dielectric layer 313 can be formed on the sidewalls of the recess, and the bottom gate 312 and the top gate 316 can be formed in the recess, separated by the insulating portion 314, to form the gate structure 16.

[0134] The insulating layer 311 and the dielectric layer 313 together form a liner 31L in the recess, and the bottom gate 312 and the top gate 316 together form a gate 31G. The gate structure 16 includes, for example, the liner 31L, the insulating portion 314, and the gate 31G. However, the disclosure is not limited to this example structure.

[0135] According to some examples, the mask is a patterned photoresist formed from a photoresist material. In some other embodiments, the mask can be a hard mask (HM) composed of an oxide layer and a nitride layer. In some examples where a patterned photoresist is used as the mask, the photolithography process includes coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, development, cleaning, and drying (e.g., hard baking), other suitable processes, or a combination thereof, to form a plurality of openings (not shown) in the mask. The openings expose a top surface 120a of the epitaxial layer 120. In this example, the openings expose a top surface 112a of the second epitaxial material layer 112.

[0136] According to some examples, after the mask is formed, one or more etching processes are performed through the openings of the mask to remove portions of the epitaxial layer 120 and form a recess in the epitaxial layer 120. The etching processes include, for example, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.

[0137] In some examples, the locations of the recesses correspond to the openings of the mask and are located below the openings. Thus, the formed recesses are, for example, contiguous with the openings of the mask and are in communication with each other. Although in Figure 4 In some examples, the depth (e.g., along the third direction D3) of the recesses used to form the gate structures 16 is less than the depth (e.g., along the third direction D3) of the deep trench isolation 114. However, the depth of the recesses in the embodiment in the epitaxial layer 120 can be greater than, less than, or equal to the depth of the deep trench isolation 114 in the epitaxial layer 120. The size, shape, and location of the recesses can depend on the size, shape, and location of the gate structures 16 to be formed in the actual application, and the present disclosure does not limit the same.

[0138] According to some examples, after the recesses are formed in the epitaxial layer 120, the mask can be removed by an ashing process, a wet etching process (e.g., acid etching), or other acceptable processes. After the mask is removed, a cleaning process can be optionally performed to remove residues.

[0139] Subsequently, according to some examples, a shielding insulating layer is formed on the sidewalls of the recesses. The shielding insulating layer can be, for example, silicon oxide, germanium oxide, other suitable semiconductor oxide materials, or combinations thereof. The shielding insulating layer can be formed on the sidewalls and bottom surface of the recesses and on the top surface 120a of the epitaxial layer 120 by an oxidation process. The oxidation process can be, for example, a thermal oxidation process, a radical oxidation process, or other suitable processes. In some examples, the shielding insulating layer can be optionally subjected to a thermal process, such as a rapid thermal annealing (RTA) process, to increase the density of the shielding insulating layer.

[0140] According to some examples, a bottom gate 312 is formed in the lower portion of the recesses, wherein the bottom gate 312 is located on the shielding insulating layer. The bottom gate 312 can be a single-layer or multi-layer structure and can be formed of, for example, amorphous silicon, polysilicon, other suitable conductive materials, or combinations thereof.

[0141] In some examples, a gate electrode material (not shown) can be deposited on the shielding insulating layer by a deposition process, and the gate electrode material fills the space in the recesses other than the shielding insulating layer. The deposition process can be, for example, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or combinations thereof. In some examples, the gate electrode material can be optionally subjected to a thermal process, such as an annealing process.

[0142] Next, portions of the gate electrode material are removed to form a bottom gate 312 as shown in Figure 4 , Figure 5A In one example, the excess portions of the deposited gate electrode material can be removed by a planarization process, such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable process, or a combination thereof. Thereafter, the portions of the gate electrode material in the recesses are etched back to recess the gate electrode material to a certain depth to form the bottom gate 312 in the recesses.

[0143] In some examples, the bottom gate 312 can optionally include dopants of the second conductivity type, such as p-type dopants. In some examples, the dopants of the bottom gate 312 can be boron difluoride (BF2) or other suitable dopants. In addition to reducing the gate-drain capacitance (Cgd) to improve the switching characteristics of the semiconductor device, the bottom gate 312 separating the trench gate structures can further enhance the reduced surface field (RESURF) effect with the bottom gate 312 of the second conductivity type.

[0144] According to some examples, after the bottom gate 312 is formed, an etching process can be performed to remove the upper portions of the masking insulating layer, leaving the remaining portions of the masking insulating layer to form an insulating layer 311 on the sidewalls and the bottom surface of the lower portion of the recess. The etching process can be, for example, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable process, or a combination thereof. Further, the top surface of the insulating layer 311 can be higher than, lower than, or substantially coplanar with the top surface of the bottom gate 312 with a slight dishing phenomenon.

[0145] Thereafter, a dielectric layer 313 is formed on the insulating layer 311 and the bottom gate 312 to serve as a gate dielectric layer for a top gate 316 of an electrode to be subsequently formed.

[0146] In some examples, a dielectric layer 313 can be conformally deposited by a suitable deposition process to extend from the top surface 120a of the epitaxial layer 120 to the upper portion of the recess and cover the top surface of the insulating layer 311 and the top surface of the bottom gate 312. The dielectric layer 313 does not fill the recess. The deposition process can include, for example, a PVD process, a CVD process, an atomic layer deposition (ALD) process, other suitable deposition process, or a combination thereof.

[0147] The dielectric layer 313 includes, for example, silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, hafnium aluminum oxide alloy, silicon hafnium oxide, silicon hafnium nitride oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, other suitable high-k dielectric materials, or a combination thereof. In some examples, the material of the dielectric layer 313 is different from the material of the underlying insulating layer 311. In some other examples, the material of the dielectric layer 313 is the same as the material of the insulating layer 311.

[0148] Further, according to some examples, when the dielectric layer 313 is formed, the bottom gate 312 is also oxidized, and a thicker insulating portion 314 is formed on top of the bottom gate 312. The insulating portion 314 includes, for example, insulating oxide. After the top gate electrode 316 is subsequently formed, this insulating portion 314 is located between the bottom gate 312 and the top gate 316, and can serve as an electrical isolation between the bottom gate 312 and the top gate 316.

[0149] Subsequently, according to some examples, the top gate 316 is formed in the upper portion of the recess. For example, a gate electrode material can be deposited on the dielectric layer 313 and fill the space in the upper portion of the recess other than the dielectric layer 313 by a deposition process, including PVD, CVD, other suitable processes, or a combination thereof, and the gate electrode material can be optionally subjected to a thermal process, such as an annealing process. Subsequently, excess portions of the gate electrode material can be removed by a planarization process, including a CMP process, a mechanical polishing process, an etching process, other suitable processes, or a combination thereof, to form the top gate 316.

[0150] As shown in FIGS. 3A and 3B, the top gate 316 is located on the dielectric layer 313 and is separated from the underlying bottom gate 312 by the insulating portion 314. The top gate 316 can be a single layer or a multi-layer structure. Figure 4 , Figure 5A As shown in FIGS. 3A and 3B, the top gate 316 is located on the dielectric layer 313 and is separated from the underlying bottom gate 312 by the insulating portion 314. The top gate 316 can be a single layer or a multi-layer structure.

[0151] In some examples, the top gate 316 is formed of amorphous silicon, polysilicon, one or more metals, metal nitride, metal silicide, conductive metal oxide, or a combination thereof. In some examples, the metal can include, but is not limited to, molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), or hafnium (Hf). The metal nitride can include, but is not limited to, molybdenum nitride (MoN), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN). The metal silicide can include, but is not limited to, tungsten silicide (WSi x ). The conductive metal oxide can include, but is not limited to, ruthenium metal oxide (Ru02) and indium tin oxide (ITO). Further, the material used to form the top gate 316 and the bottom gate 312 can be the same or different.

[0152] Accordingly, fabrication of some example gate structures 16, including the liner 31L, the insulating portion 314, and the gate 31G, is completed. The liner 31L includes the insulating layer 311 and the dielectric layer 313, and the bottom gate 312 and the top gate 316 can be collectively referred to as the gate 31G. The insulating portion 314 is located between the bottom gate 312 and the top gate 316. However, the disclosure is not limited to the example gate structure 16.

[0153] In addition, in an example in which the VDMOS device is the first device 11, the bottom of the gate structure 16 can be closer to the substrate 100 having the first conductivity type (e.g., n-type) to serve as the drain region, which can further improve the electrical performance of the VDMOS device. According to some examples, the bottom of the gate structure 16 can be close to the bottom surface of the second epitaxial material layer 112 or extend into the first epitaxial material layer 102, but the gate structure 16 does not directly contact the substrate 100.

[0154] Referring back to Figure 4 , Figure 5A According to some embodiments, in an example in which the PMOS device is the second device 12, an N-type well 321 can be formed in the isolation region defined by the first deep trench isolation 1142 and the isolation layer 104, and heavily doped portions 322, 324, and 325 can be formed in the N-type well 321. The heavily doped portions 322, 324, and 325 can be separated from each other by an appropriate distance.

[0155] In this example, the heavily doped portion 322 and the heavily doped portion 324 can be the source region and the drain region, respectively, of the subsequently formed PMOS device (the second device 12). The heavily doped portion 325 is the base region of the PMOS device. Further, in this example, the heavily doped portion 322 and the heavily doped portion 324 have the same conductivity type, such as (but not limited to) p-type. The heavily doped portion 325 has a different conductivity type from the heavily doped portions 322 and 324, such as (but not limited to) n-type.

[0156] Further, in some embodiments, a gate structure 326 of the PMOS device (the second device 12) is formed over the N-type well 321. The gate structure 326 is located on the epitaxial layer 120 and between the heavily doped portion 322 (the source region) and the heavily doped portion 324 (the drain region). The gate structure 326 includes, for example, a gate dielectric layer (not shown) and a gate electrode over the gate dielectric layer.

[0157] Furthermore, in this example, a portion of the second epitaxial material layer 112 and a portion of the first epitaxial material layer 102 are also included between the N-type well 321 and the underlying isolation layer 104, so as to achieve better electrical isolation between the formed PMOS device (second device 12) and the substrate 100 (e.g., n-type conductivity type), and reduce the possible impact of the conductive substrate 100 on the PMOS device when the first device 11 is operating.

[0158] Reference Figure 4 , Figure 5B According to some embodiments, in one example where a P-type LDMOS device is used as the third device 13, an N-type well 331 and a P-type well 330 can be formed in the isolation region defined by the second deep trench isolation member 1143 and the isolation layer 104. One N-type well 331 is located between the two P-type wells 330, and the bottom surfaces of the N-type well 331 and the P-type well 330 are covered by a portion of the epitaxial layer 120 (e.g., the second epitaxial material layer 112).

[0159] An N-type well 331 and a P-type well 330 can be formed in the epitaxial layer 120 (e.g., in the second epitaxial material layer 112 in this example) by an ion implantation process. The N-type well 331 and the P-type well 330 extend downward from the top surface 120a of the epitaxial layer 120 into the epitaxial layer 120.

[0160] According to some examples, a P-type LDMOS device also includes a heavily doped region 332 (source region), a heavily doped region 334 (drain region), a heavily doped region 335 (base region), and a gate structure 336. The heavily doped regions 332 and 334 have the same second conductivity type, such as p-type. The heavily doped region 335 has a first conductivity type, such as n-type.

[0161] More specifically, such as Figure 5B As shown, the gate structure 336 includes gate structures 3361 and 3362 disposed over the P-type well 330 and the N-type well 331.

[0162] The heavily doped portion 332 (source region) includes a heavily doped portion 3321 adjacent to the gate structure 3361 and a heavily doped portion 3322 adjacent to the gate structure 3362. The heavily doped portions 3321 and 3322 are located in the N-type well 331.

[0163] The heavily doped portion 334 (drain region) includes a heavily doped portion 3341 adjacent to the gate structure 3361 and a heavily doped portion 3342 adjacent to the gate structure 3362. The heavily doped portions 3341 and 3342 are located in two P-type wells 330, respectively.

[0164] The heavily doped portion 335 (base region) is located in the N-type well 331 and is disposed between the two heavily doped portions 3321 and 3322 (source regions).

[0165] Further, according to some examples, an N-type body region 331B is also formed in the N-type well 331. The heavily doped portion 335 (base region) and the heavily doped portions 3321, 3322 (source regions) are formed in the N-type body region 331B.

[0166] Further, according to some examples, the N-type well 331 has a doping concentration less than that of the heavily doped portions 332 (including 3321 and 3322; source regions) and the heavily doped portions 334 (including 3341 and 3342; drain regions). The N-type body region 331B has a doping concentration less than that of the heavily doped portions 332 and the heavily doped portions 334.

[0167] Further, in this example, the N-type well 331 and the P-type well 330 are also covered by a portion of the epitaxial layer 120, such as a portion of the second epitaxial material layer 112 and a portion of the first epitaxial material layer 102, so that the formed P-type LDMOS device (the third device 13) can be well electrically isolated from the substrate 100 (e.g., n-type), reducing the possible impact of the conducting substrate 100 on the third device 13 when the first device 11 is operating.

[0168] Further referring to Figure 4 , Figure 5B According to some embodiments, in an example of the N-type LDMOS device as the fourth device 14, a P-type well 340 and two N-type wells 341 can be formed in the isolation region defined by the third deep trench isolation 1144 and the isolation layer 104. The P-type well 340 is located between the two N-type wells 341, and the bottom surfaces of the P-type well 340 and the N-type wells 341 are covered by a portion of the epitaxial layer 120 (e.g., the second epitaxial material layer 112).

[0169] The N-type wells 341 and the P-type well 340 can be formed in the epitaxial layer 120 (e.g., the second epitaxial material layer 112 in this example) by an ion implantation process. The N-type wells 341 and the P-type well 340 extend downward from the top surface 120a of the epitaxial layer 120 into the epitaxial layer 120.

[0170] According to some examples, the N-type LDMOS device further includes a heavily doped portion 342 (source region), a heavily doped portion 344 (drain region), a heavily doped portion 345 (base region), and a gate structure 346. The heavily doped portions 342 and 344 have the same first conductivity type, such as n-type. The heavily doped portion 335 has a second conductivity type, such as p-type.

[0171] More specifically, as Figure 5BAs shown, the gate structure 346 includes gate structures 3461 and 3462 disposed over the N-type well 341 and the P-type well 340.

[0172] The heavily doped portion 342 (source region) includes a heavily doped portion 3421 adjacent to the gate structure 3461 and a heavily doped portion 3422 adjacent to the gate structure 3462. The heavily doped portions 3421 and 3422 are located in the P-type well 340.

[0173] The heavily doped portion 344 (drain region) includes a heavily doped portion 3441 adjacent to the gate structure 3461 and a heavily doped portion 3442 adjacent to the gate structure 3462. The heavily doped portions 3441 and 3442 are located in the two N-type wells 341, respectively.

[0174] The heavily doped portion 345 (base region) is located in the P-type well 340 and disposed between the two heavily doped portions 3421 and 3422 (source regions).

[0175] Further, according to some examples, a P-type base region 340B is also formed in the P-type well 340. The heavily doped portion 345 (base region) and the heavily doped portions 3421 and 3422 (source regions) are formed in the P-type base region 340B.

[0176] Further, according to some examples, the P-type well 340 has a doping concentration less than that of the heavily doped portions 342 (including 3421 and 3422; source regions) and the heavily doped portions 344 (including 3441 and 3442; drain regions). The P-type base region 340B has a doping concentration less than that of the heavily doped portions 342 and the heavily doped portions 344.

[0177] Further, in this example, the N-type well 341 and the P-type well 340 further include a portion of the epitaxial layer 120, such as a portion of the second epitaxial material layer 112 and a portion of the first epitaxial material layer 102, between the N-type well 341 and the P-type well 340 and the underlying isolation layer 104. This is to achieve better electrical isolation between the formed N-type LDMOS device (the fourth device 14) and the substrate 100 (e.g., n-type) and to reduce the possible impact of the conductive substrate 100 on the fourth device 14 when the first device 11 is in operation.

[0178] In forming the N-type LDMOS device (the fourth device 14) as described above, Figure 4After the formation of the components of the devices 11 / 12 / 13 / 14, an insulating layer (not shown) can be formed over the epitaxial layer 120, and the insulating layer covers the gate structures 16 / 326 / 336 / 346. Further, a plurality of contacts (not shown) can be formed in the insulating layer, and the contacts connect the gate structures 16 / 326 / 336 / 346, the drain regions 324 / 334 / 344, the source regions 322 / 332 / 342, and the base regions 325 / 335 / 345 of the respective devices 11 / 12 / 13 / 14.

[0179] In summary, the semiconductor structure and the method of fabricating the semiconductor structure according to some embodiments of the present disclosure can integrate different types of semiconductor devices, especially semiconductor devices with different current directions, on the same substrate (e.g., wafer) by configuring the isolation structure (e.g., including the local isolation layer and the deep trench isolation). In the application of the embodiments, vertical semiconductor devices, such as VDMOS devices, with vertical current directions and non-vertical semiconductor devices, such as N / PMOS and LDMOS devices, with non-vertical current directions (e.g., horizontal direction) can be integrated. According to some embodiments, the local extension isolation layer is disposed in the substrate or the epitaxial layer, and one or more isolation regions are defined by the deep trench isolation and the local extension isolation layer. The non-vertical semiconductor devices are disposed in the isolation regions, and the vertical semiconductor devices are disposed in the regions without the local extension isolation layer (i.e., outside the isolation regions). According to some embodiments, the substrate of the semiconductor structure includes a high-doped region that can be used as a drain region of the vertical semiconductor devices. By disposing the local extension isolation layer, the influence of the conductive substrate on the electrical performance of the non-vertical semiconductor devices can be reduced, and the integrated vertical and non-vertical semiconductor devices can achieve good electrical performance. Therefore, according to the application of the embodiments of the present disclosure, BCD (including Bipolar devices, CMOS devices, and DMOS devices) and VDMOS devices can be integrated on the same wafer to comprehensively solve the design problems of complex and high-power applications.

[0180] In addition, according to the method of fabricating the semiconductor structure according to some embodiments of the present disclosure, the local extension isolation layer and the integrated semiconductor devices including different types of semiconductor devices can be fabricated by simple and compatible processes. When the different types of semiconductor devices are integrated, similar components can be fabricated together in the same process, and the processes can be saved, such as the plurality of deep trench isolations can be formed in the same process, and the well regions or heavily doped regions of the same conductivity type can be formed in the same process. Therefore, the process of the embodiments is simple, and the additional manufacturing cost is not significantly increased.

[0181] While the present disclosure has been disclosed with reference to specific embodiments, it is to be understood that various other adaptations and modifications are to be considered as within the scope of the present disclosure. Therefore, additional embodiments are within the scope of the following claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; an epitaxial layer on the substrate; an isolation layer in the substrate or in the epitaxial layer, wherein the isolation layer is in a second region of the semiconductor structure but does not extend to a first region of the semiconductor structure; a deep trench isolation in the epitaxial layer extending downward and connecting with the isolation layer; a first device in the first region, and the substrate as a drain region of the first device; and a second device in the second region, and the second device in an isolation region defined by the deep trench isolation and the isolation layer. A lower portion of the deep trench isolation extends from a top surface of the isolation layer to a bottom surface of the isolation layer.

2. The semiconductor structure of claim 1, wherein, A bottom surface of the deep trench isolation is coplanar with the bottom surface of the isolation layer.

3. The semiconductor structure of claim 1, wherein, The isolation layer is embedded in the substrate, and the isolation layer is spaced apart from a top surface of the substrate by a distance.

4. The semiconductor structure of claim 1, wherein, The deep trench isolation extends through the epitaxial layer and below the top surface of the substrate.

5. The semiconductor structure of claim 4, wherein, The epitaxial layer further comprises:

6. The semiconductor structure of claim 1, wherein, a first epitaxial material layer on the substrate and extending in the first region and the second region of the semiconductor structure, wherein the isolation layer is embedded in the first epitaxial material layer; and a second epitaxial material layer on the first epitaxial material layer, wherein the deep trench isolation extends downward from a top surface of the second epitaxial material layer to pass through the second epitaxial material layer and a portion of the first epitaxial material layer to connect with the isolation layer. A top surface of the isolation layer is spaced apart from a top surface of the first epitaxial material layer by a distance.

7. The semiconductor structure of claim 6, wherein, A bottom surface of the deep trench isolation contacts the first epitaxial material layer.

8. The semiconductor structure of claim 6, wherein, Driving current of the first device flows in a direction from a top surface of the epitaxial layer to the substrate, and driving current of the second device flows in a direction along the top surface of the epitaxial layer.

9. The semiconductor structure of claim 1, wherein, The substrate and the epitaxial layer contain dopants of the same conductivity type.

10. The semiconductor structure of claim 1, wherein, A doping concentration of the substrate is greater than a doping concentration of the epitaxial layer.

11. The semiconductor structure of claim 1, wherein, The isolation layer extends continuously from the second region to a third region of the semiconductor structure, the second region being between the third region and the first region.

12. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises:

13. The semiconductor structure of claim 12, wherein, a third device in the third region, wherein driving current of the third device flows in a direction along the top surface of the epitaxial layer. The deep trench isolation is a first deep trench isolation disposed in the second region, wherein the second device is in the isolation region defined by the first deep trench isolation and the isolation layer, 14. The semiconductor structure of claim 13, wherein, The semiconductor structure further comprises: a second deep trench isolation disposed in the third region, and the second deep trench isolation and the first deep trench isolation are laterally spaced apart by a distance, wherein the third device is in another isolation region defined by the second deep trench isolation and the isolation layer. The semiconductor structure comprises:

15. A method of manufacturing a semiconductor structure, characterized by, providing a substrate; forming an epitaxial layer on the substrate; forming an isolation layer in the substrate or in the epitaxial layer, wherein the isolation layer is in a second region of the semiconductor structure but does not extend to a first region of the semiconductor structure; forming a deep trench isolation extending downward from a top surface of the epitaxial layer, and the deep trench isolation connecting with the isolation layer; forming a first device in the first region, and the substrate as a drain region of the first device; and a second device in the second region, and the second device in an isolation region defined by the deep trench isolation and the isolation layer. ​ forming a second device in the second region, and the second device is located in an isolation region defined by the deep trench isolation and the isolation layer.

16. The method of manufacturing a semiconductor structure according to claim 15, wherein forming the isolation layer in the substrate before forming the epitaxial layer on the substrate, wherein a top surface of the isolation layer is spaced apart from a top surface of the substrate above by a distance.

17. The method of manufacturing a semiconductor structure according to Claim 15, wherein forming the isolation layer in a portion of the epitaxial layer before forming the epitaxial layer on the substrate, wherein a bottom surface of the isolation layer is spaced apart from a top surface of the substrate below by a distance.

18. The method of manufacturing a semiconductor structure according to Claim 15, wherein forming the isolation layer comprises: performing a local oxygen ion implantation on the substrate or the epitaxial layer to form a local oxygen ion region in the substrate or in the epitaxial layer; performing annealing to react oxygen ions of the local oxygen ion region with materials of the substrate or the epitaxial layer to form a silicon-containing oxide layer; and forming the deep trench isolation on opposite sides corresponding to the silicon-containing oxide layer, the deep trench isolation extending downward from the top surface of the epitaxial layer and removing portions of the silicon-containing oxide layer on the opposite sides, wherein remaining portions of the silicon-containing oxide layer form the isolation layer, and the deep trench isolation connects the opposite sides of the isolation layer.

19. The method of manufacturing a semiconductor structure according to Claim 18, wherein before performing the local oxygen ion implantation, further comprising: providing a mask above the substrate or the epitaxial layer, wherein the mask has an opening, wherein the local oxygen ion implantation is performed on the substrate or the epitaxial layer through the opening, the local oxygen ion region formed corresponds to the opening, and a maximum width of the local oxygen ion region is greater than a width of the opening.

20. The method of manufacturing a semiconductor structure according to Claim 15, wherein the epitaxial layer further comprises: a first epitaxial material layer on the substrate and extending in the first region and the second region of the semiconductor structure, wherein the isolation layer is embedded in the first epitaxial material layer; and a second epitaxial material layer on the first epitaxial material layer, wherein the deep trench isolation extends downward from a top surface of the second epitaxial material layer to pass through the second epitaxial material layer and a portion of the first epitaxial material layer to connect with the isolation layer.

21. The method of manufacturing a semiconductor structure according to claim 20, wherein, a top surface of the isolation layer formed is spaced apart from a top surface of the first epitaxial material layer above by a distance.

22. The method of manufacturing a semiconductor structure according to claim 20, wherein a top surface of the isolation layer formed is spaced apart from a top surface of the first epitaxial material layer by a distance.

23. The method of manufacturing a semiconductor structure according to Claim 15, wherein a driving current of the first device flows in a direction from the top surface of the epitaxial layer to the substrate, and a driving current of the second device flows in a direction along the top surface of the epitaxial layer.

24. The method of manufacturing a semiconductor structure according to Claim 15, wherein, the isolation layer formed extends continuously from the second region to a third region of the semiconductor structure, wherein the second region is located between the third region and the first region.

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