Display substrate

Abstract

The invention discloses a display substrate, which is provided with a plurality of sub-pixels arranged in multiple rows and multiple columns, and comprises a substrate, a plurality of data lines and a plurality of first data line leads, the substrate comprises a display area and a non-display area, the sub-pixels are arranged in the display area, and the data lines are arranged on the substrate, at least located in the display area, extend in the first direction and are configured to provide data signals for the sub-pixels. The multiple first data line leads are arranged on the substrate and extend from the display area to the non-display area in the first direction, and at least parts of the multiple data lines are electrically connected with the multiple first data line leads respectively so as to obtain data signals from the non-display area; at least one of the first data line leads comprises a first lead part and a second lead part, the first lead part is located on the first conductive layer, the second lead part is located on the second conductive layer, and the first lead part and the second lead part are electrically connected through a via hole.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a display substrate. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) display devices have a series of advantages such as self-emission, high contrast, high definition, wide viewing angle, low power consumption, fast response speed, and low manufacturing cost, and have become one of the key development directions of new generation display devices, and therefore have attracted more and more attention. SUMMARY

[0003] At least one embodiment of the present disclosure provides a display substrate having a plurality of sub-pixels arranged in multiple rows and multiple columns, and comprising a substrate, a plurality of data lines, and a plurality of first data line leads; the substrate comprises a display area and a non-display area, wherein the plurality of sub-pixels are arranged in the display area, the plurality of data lines are arranged on the substrate and at least in the display area, extend along a first direction, and are configured to provide data signals to the plurality of sub-pixels, and the plurality of first data line leads are arranged on the substrate and extend from the display area to the non-display area along the first direction, wherein at least part of the plurality of data lines are respectively electrically connected to the plurality of first data line leads to obtain data signals from the non-display area, at least one of the plurality of first data line leads comprises a first lead portion and a second lead portion, the first lead portion is located in a first conductive layer, the second lead portion is located in a second conductive layer, and the first lead portion and the second lead portion are electrically connected through a via.

[0004] For example, in the display substrate provided by at least one embodiment of the present disclosure, one or two first data line leads are arranged between two adjacent data lines in a direction parallel to the substrate.

[0005] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second conductive layer is located on a side of the first conductive layer away from the substrate, and the plurality of data lines are located in the second conductive layer.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, a first insulating layer is arranged between the second conductive layer and the first conductive layer, the via comprises a first via and a second via penetrating through the first insulating layer, and two ends of the first lead portion are connected to the second lead portion through the first via and the second via, respectively.

[0007] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, for a first data line lead wire and a data line arranged adjacently, the first insulating layer further has a third via hole overlapping the data line in a direction perpendicular to the substrate base plate, and the third via hole is located between the first via hole and the second via hole in the first direction.

[0008] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, two data lines and two first data line lead wires are arranged between two columns of sub-pixels arranged adjacently, and the two data lines are located between the two first data line lead wires, or the two first data line lead wires are located between the two data lines.

[0009] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the two data lines are symmetrically arranged, and the third via holes corresponding to the two data lines are symmetrically arranged; the two first data line lead wires are symmetrically arranged, and the first via holes and the second via holes corresponding to the two first data line lead wires are symmetrically arranged.

[0010] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, two data lines and two first data line lead wires are arranged between two columns of sub-pixels arranged adjacently, and the two first data line lead wires are located between the two data lines; in the first direction, the first via holes and the second via holes corresponding to the two first data line lead wires are alternately arranged with intervals.

[0011] For example, the display substrate provided by at least one of the embodiments of the present disclosure further includes a second data line lead wire located in the first conductive layer and extending along a second direction different from the first direction, wherein at least one of the two first data line lead wires is connected to the second data line lead wire through a first adapter line, and the first adapter line is located in the first conductive layer and at least partially overlaps the at least one of the two first data line lead wires in a direction perpendicular to the substrate base plate.

[0012] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the second lead wire portions of the two first data line lead wires respectively include bending portions bent towards each other.

[0013] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, two data lines and two first data line lead wires are arranged between two columns of sub-pixels arranged adjacently, and the two first data line lead wires are located between the two data lines; in the first direction, the first via holes and the second via holes corresponding to the two first data line lead wires are located on the same straight line.

[0014] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, two data lines are arranged between two adjacent columns of sub-pixels in a direction parallel to the substrate, and a first data line lead is arranged between the two data lines. The display substrate further comprises: a second data line lead located in the first conductive layer and extending in a second direction different from the first direction. The first data line lead is connected to the second data line lead through a second adapter line. The second adapter line is located in the first conductive layer and at least partially overlaps one of the two data lines in a direction perpendicular to the substrate.

[0015] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, two data lines are arranged between two adjacent columns of sub-pixels in a direction parallel to the substrate, and two first data line leads are arranged between the two data lines, or two first data line leads are arranged between two adjacent columns of sub-pixels, and two data lines are arranged between the two first data line leads. The display substrate further comprises: a plurality of second data line leads located in the first conductive layer and extending in a second direction different from the first direction. A first data line of the two data lines is connected to a first second data line lead of the plurality of second data line leads, and the first second data line lead is connected to a first first data line lead spaced apart from the first data line by at least one sub-pixel. A second data line of the two data lines is connected to a second second data line lead of the plurality of second data line leads, and the second second data line lead is connected to a second first data line lead spaced apart from the second data line by at least one sub-pixel.

[0016] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, a first data line of the two data lines is connected to a first second data line lead of the plurality of second data line leads through a third adapter line. In a direction perpendicular to the substrate, the first data line at least partially overlaps the third adapter line. A second data line of the two data lines is connected to a second second data line lead of the plurality of second data line leads through a fourth adapter line. In a direction perpendicular to the substrate, the second data line at least partially overlaps the fourth adapter line.

[0017] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first data line of the two data lines is connected to the first second data line lead of the plurality of second data line leads through a third adapter line, and the third adapter line and the first data line lead adjacent to the first data line at least partially overlap in a direction perpendicular to the substrate.

[0018] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first second data line lead is connected to the first first data line lead spaced apart from the first data line by at least one sub-pixel through a fifth adapter line, and the fifth adapter line and the data line adjacent to the first first data line lead at least partially overlap in a direction perpendicular to the substrate.

[0019] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first second data line lead is directly connected to the first first data line lead spaced apart from the first data line by at least one sub-pixel through a fourth via; and the second second data line lead is directly connected to the second first data line lead spaced apart from the second data line by at least one sub-pixel through a fifth via.

[0020] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first data line, the first second data line lead, and the first first data line lead form a first data line net, the second data line, the second second data line lead, and the second first data line lead form a second data line net, and the second data line net is located at the periphery of the first data line net.

[0021] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the two first data line leads located between the two data lines include a disconnected portion disconnected from the first data line net and the second data line net, and the display substrate further includes a first power line, and the disconnected portion is connected to the first power line.

[0022] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, in a direction perpendicular to the substrate, the position of the disconnected portion overlaps with the first conductive layer or the second conductive layer.

[0023] For example, the display substrate provided by at least one of the embodiments of the present disclosure includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a light emitting device and a pixel driving circuit for driving the light emitting device, the light emitting device includes a first electrode connected to the pixel driving circuit, a second electrode arranged in a spaced manner with the first electrode, and a light emitting layer between the first electrode and the second electrode, and the second electrode is electrically connected to the first power supply line.

[0024] For example, the display substrate provided by at least one of the embodiments of the present disclosure includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a light emitting device and a pixel driving circuit for driving the light emitting device, the light emitting device includes a first electrode connected to the pixel driving circuit, a second electrode arranged in a spaced manner with the first electrode, and a light emitting layer between the first electrode and the second electrode, and the second electrode is electrically connected to the first power supply line.

[0025] For example, the display substrate provided by at least one of the embodiments of the present disclosure includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a light emitting device and a pixel driving circuit for driving the light emitting device, the light emitting device includes a first electrode connected to the pixel driving circuit, a second electrode arranged in a spaced manner with the first electrode, and a light emitting layer between the first electrode and the second electrode, and the second electrode is electrically connected to the first power supply line.

[0026] For example, the display substrate provided by at least one of the embodiments of the present disclosure includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a light emitting device and a pixel driving circuit for driving the light emitting device, the light emitting device includes a first electrode connected to the pixel driving circuit, a second electrode arranged in a spaced manner with the first electrode, and a light emitting layer between the first electrode and the second electrode, and the second electrode is electrically connected to the first power supply line.

[0027] For example, the display substrate provided by at least one of the embodiments of the present disclosure includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a light emitting device and a pixel driving circuit for driving the light emitting device, the light emitting device includes a first electrode connected to the pixel driving circuit, a second electrode arranged in a spaced manner with the first electrode, and a light emitting layer between the first electrode and the second electrode, and the second electrode is electrically connected to the first power supply line. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described in the following description only relate to some embodiments of the present disclosure, and are not a limitation on the present disclosure.

[0029] Figure 1 The planar schematic diagram of the display substrate provided by at least one of the embodiments of the present disclosure;

[0030] Figure 2 The planar arrangement schematic diagram of part of the wiring in the display substrate provided by at least one of the embodiments of the present disclosure;

[0031] Figure 3 In order to Figure 2 The cross-sectional schematic diagram of the wiring along the aa line in the display substrate provided by at least one of the embodiments of the present disclosure;

[0032] Figure 4 This is a schematic diagram of another planar arrangement of some traces in a display substrate provided in at least one embodiment of the present disclosure;

[0033] Figure 5A and Figure 5B They are respectively Figure 2 and Figure 4 A planar schematic diagram showing the overlap between some of the traces and the first electrode;

[0034] Figure 6 This is another planar layout diagram of some traces in a display substrate provided in at least one embodiment of the present disclosure;

[0035] Figure 7 This is a schematic diagram of the planar arrangement of a display substrate provided in at least one embodiment of the present disclosure;

[0036] Figures 8-11 A schematic diagram of various planar arrangements of some traces in a display substrate provided for at least one embodiment of the present disclosure;

[0037] Figure 12 A schematic diagram of the planar arrangement of the first data line lead in a display substrate with a 2-in-1 design, provided for at least one embodiment of the present disclosure;

[0038] Figure 13 This is a schematic diagram of another planar arrangement of the first data line lead in the display substrate provided in at least one embodiment of the present disclosure, where the first data line lead adopts a 2-in-1 design.

[0039] Figure 14 and Figure 15 A schematic diagram of the planar arrangement of the first data line lead in a display substrate with a 1-to-1 design, provided for at least one embodiment of the present disclosure;

[0040] Figure 16 for Figure 14 Enlarged view of the area within the dashed box;

[0041] Figure 17 for Figure 16 A planar schematic diagram showing the overlap between some of the traces and the first electrode;

[0042] Figure 18 A schematic diagram showing the connection of data lines, first data line leads, and second data line leads in a display substrate provided in at least one embodiment of this disclosure;

[0043] Figure 19 This is a schematic diagram showing the connection between the first data line lead and the second data line lead in a display substrate provided in at least one embodiment of the present disclosure;

[0044] Figure 20 for Figure 19 A planar schematic diagram showing the overlap between some of the traces and the first electrode;

[0045] Figure 21A A schematic diagram of connection of a data line and a second data line lead in a display substrate according to at least one embodiment of the present disclosure is provided;

[0046] Figure 21B Another schematic diagram of connection of a data line and a second data line lead in a display substrate according to at least one embodiment of the present disclosure is provided;

[0047] Figure 22 Another schematic diagram of connection of a first data line lead and a second data line lead in a display substrate according to at least one embodiment of the present disclosure is provided;

[0048] Figure 23 And Figure 24 Another schematic diagram of a first data line lead in a display substrate according to at least one embodiment of the present disclosure is provided, in which a 1-in-1 design is adopted;

[0049] Figure 25 Another schematic diagram of a first data line lead and a data line in a display substrate according to at least one embodiment of the present disclosure is provided;

[0050] Figure 26 And Figure 27 Another schematic diagram of a first data line lead in a display substrate according to at least one embodiment of the present disclosure is provided, in which a 1-in-1 design is adopted;

[0051] Figure 28 A schematic diagram of a plane in which part of a wire in Figure 27 overlaps with a first electrode is provided;

[0052] Figure 29 A schematic diagram of a partial cross section of a display substrate according to at least one embodiment of the present disclosure is provided;

[0053] Figure 30 A circuit diagram of a pixel driving circuit of a display substrate according to at least one embodiment of the present disclosure is provided;

[0054] Figure 31 A timing diagram of a pixel driving circuit in Figure 30 is provided;

[0055] Figure 32 A schematic diagram of binding of a data line and a first data line lead in a display substrate according to at least one embodiment of the present disclosure is provided;

[0056] Figure 33 Another schematic diagram of binding of a data line and a first data line lead in a display substrate according to at least one embodiment of the present disclosure is provided; and

[0057] Figure 34 And Figure 35Another schematic view of another planar arrangement of the first data line lead wire in the display substrate according to at least one embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0058] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0059] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0060] With the pursuit of narrow frame of display devices such as mobile phones, a series of design schemes aiming to shorten the frame have emerged. FIP technology (Fanout In Pixel) is a good method to narrow the frame. In the FIP technology, the space occupied by the fanout at the lower corner of the display device can be effectively reduced by the method of fanout wiring in the display area, so as to achieve the purpose of narrowing the frame.

[0061] In the display substrate, the wiring layout based on the FIP technology is an important factor to determine the display effect of the display substrate and the preparation difficulty and yield, therefore, how to optimize the wiring layout is a subject that the technicians in the field are constantly researching.

[0062] This disclosure provides at least one embodiment of a display substrate having multiple sub-pixels arranged in multiple rows and columns, and including a substrate, multiple data lines, and multiple first data line leads. The substrate includes a display area and a non-display area, wherein the multiple sub-pixels are disposed in the display area, the multiple data lines are disposed on the substrate and located in the display area, extending along a first direction and configured to provide data signals to the multiple sub-pixels, and the multiple first data line leads are disposed on the substrate and extend along the first direction from the display area to the non-display area. At least a portion of the multiple data lines is electrically connected to the multiple first data line leads to obtain data signals from the non-display area. At least one of the multiple first data line leads includes a first lead portion and a second lead portion, the first lead portion being located in a first conductive layer, the second lead portion being located in a second conductive layer, and the first lead portion and the second lead portion being electrically connected through a via.

[0063] In the embodiments of this disclosure, a first conductive layer and a second conductive layer are used for wiring the first data line lead, and the first data line lead is designed with a jumper design in the first and second conductive layers. On the one hand, compared with single conductive layer wiring, the above design can prevent electrostatic discharge (ESD) during the manufacturing process and improve the manufacturing yield of the display substrate. On the other hand, using double metal layer wiring can reduce manufacturing costs and wiring difficulty compared with more layers of wiring, and can simultaneously achieve narrow bezels and thinness of the display substrate.

[0064] The display substrate provided in this disclosure will be described below through several specific embodiments.

[0065] This disclosure provides a display substrate in at least one embodiment. Figure 1 A planar schematic diagram of the display substrate is shown. Figure 2 This diagram shows a planar layout of some traces in a display substrate. Figure 3 It shows Figure 2 A schematic diagram of the cross-section of the trace along line aa, as shown in the figure. Figures 1-3 As shown, the display substrate has multiple sub-pixels SP arranged in multiple rows and columns, and includes a substrate 10, multiple data lines Da, and multiple first data line leads DL1, etc.

[0066] like Figures 1-3As shown, the substrate 10 includes a display area AA and a non-display area NA, a plurality of sub-pixels SP are arranged in the display area AA for display. A plurality of data lines Da are arranged on the substrate 10 and at least in the display area AA, for example, in some embodiments, also extend to the non-display area NA, the plurality of data lines Da extend along the first direction R1, for example, are electrically connected with the plurality of sub-pixels SP, and are configured to provide data signals to the plurality of sub-pixels SP. A plurality of first data line leads DL1 are arranged on the substrate 10 and extend from the display area AA to the non-display area NA along the first direction R1, for example, extend to the non-display area NA below the display area AA, so that the area is bound, and connected to an integrated circuit IC (not shown in the figure). At least part of the plurality of data lines Da are respectively electrically connected to at least one of the plurality of first data line leads DL1 to obtain data signals from the non-display area NA.

[0067] For example, in some embodiments, a part of the plurality of data lines Da is connected to the first data line lead DL1 to obtain data signals from the non-display area NA, and another part of the plurality of data lines Da directly extends to the non-display area NA to obtain data signals from the non-display area NA. At this time, the plurality of first data line leads DL1 can be used to plan the position of the part of the plurality of data lines Da leading out to the non-display area NA, thereby facilitating the binding of the plurality of data lines Da for transmitting data signals and the plurality of first data line leads DL1 in the non-display area NA, for example, making the binding position more concentrated, so as to realize narrow frame.

[0068] As shown in Figure 2 and Figure 3 At least one of the plurality of first data line leads DL1 (for example, the plurality of first data line leads DL1, for example, all the first data line leads DL1) includes a first lead portion DL11 and a second lead portion DL12, the first lead portion DL11 is located in the first conductive layer M1, and the second lead portion DL12 is located in the second conductive layer M2, and the first lead portion DL11 and the second lead portion DL12 are electrically connected by a via (for example, a first via V1 and a second via V2, which will be described in detail later).

[0069] In this way, the first data line lead DL1 adopts a jumper design in the first conductive layer M1 and the second conductive layer M2, which can prevent electrostatic discharge (ESD) and other adverse phenomena during preparation, and improve the preparation yield of the display substrate.

[0070] For example, in some embodiments, at least one first data line lead DL1, for example, one or two first data line leads DL1, is arranged between two adjacent data lines Da in a direction parallel to the substrate 10, Figure 2For example, as shown in FIG. 1, two first data line leads DL1 are arranged between two adjacent data lines Da. Details will be described later.

[0071] For example, as shown in FIG. 1, two first data line leads DL1 are arranged between two adjacent data lines Da. Details will be described later. Figure 3 For example, as shown in FIG. 1, two first data line leads DL1 are arranged between two adjacent data lines Da. Details will be described later.

[0072] For example, as shown in FIG. 1, two first data line leads DL1 are arranged between two adjacent data lines Da. Details will be described later. Figure 3 For example, as shown in FIG. 1, two first data line leads DL1 are arranged between two adjacent data lines Da. Details will be described later.

[0073] For example, as shown in FIG. 1, two first data line leads DL1 are arranged between two adjacent data lines Da. Details will be described later. Figure 3 For example, as shown in FIG. 1, two first data line leads DL1 are arranged between two adjacent data lines Da. Details will be described later. Figure 29 For example, as shown in FIG. 1, two first data line leads DL1 are arranged between two adjacent data lines Da. Details will be described later.

[0074] For example, as shown in FIG. 1, two first data line leads DL1 are arranged between two adjacent data lines Da. Details will be described later. Figure 2 For example, as shown in FIG. 1, two first data line leads DL1 are arranged between two adjacent data lines Da. Details will be described later.

[0075] For example, as shown in FIG. 1, two first data line leads DL1 are arranged between two adjacent data lines Da. Details will be described later. Figure 2 For example, as shown in FIG. 1, two first data line leads DL1 are arranged between two adjacent data lines Da. Details will be described later. Figure 4As shown, two data lines Da are located between two first data line leads DL1, or the two first data line leads DL1 and the two data lines Da are arranged in sequence or alternately, for example, first data lead DL1, one data line Da, first data lead DL1, one data line Da, or one data line Da, first data lead DL1, one data line Da, first data lead DL1.

[0076] Thus, Figure 2 and Figure 4 The technical solution adopts the design that each column of sub-pixels SP corresponds to one data line Da and one first data line lead DL1, hereinafter referred to as 1-in-1 design. Compared with the design that every two columns of sub-pixels SP correspond to two data lines Da and one first data line lead DL1, hereinafter referred to as 2-in-1 design, the number of first data line leads DL1 is more in the 1-in-1 design, which facilitates wiring connection, can shorten the total length of the first data line leads DL1 and the second data line leads DL2, reduce the resistance and overlapping capacitance of the data line leads, reduce data signal loss and data line number loading. In addition, the 1-in-1 design can also increase the density of the connection lines (hereinafter part of DL0, which will be introduced later) of the first power supply line VSS, for example, by one, better reduce the voltage drop of the first power supply line VSS, and reduce the screen power consumption. In addition, the 1-in-1 design can also connect data signals through the plurality of first data line leads DL1 located in the middle of the display area AA to reduce the Fanout connection width below the display area AA, reduce the binding space of the data line Da and the first data line lead DL1 for binding and transmitting data signals in the non-display area NA below the display area AA, and realize narrow frame design (which will be described in detail later).

[0077] For example, in some embodiments, as shown in Figure 2 and Figure 4 As shown, the two data lines Da between the two adjacent columns of sub-pixels SP are symmetrically arranged, and the third via holes V3 corresponding to the two data lines Da are symmetrically arranged; for example, the two first data line leads DL1 between the two adjacent columns of sub-pixels SP are symmetrically arranged, and the first via holes V1 and the second via holes V2 corresponding to the two first data line leads DL1 are also symmetrically arranged.

[0078] For example, for the design of Figure 2 After the first electrode 1041 (for example, the anode of the light emitting device EM of the sub-pixel SP, which will be described in detail later) is made on the side of the second conductive layer M2 away from the substrate 10, as shown in Figure 5A The first electrode 1041 may overlap the first via holes V1 and the second via holes V2 corresponding to the first data line leads DL1; for the design of Figure 4the design, after the first electrode 1041 is made on the side of the second conductive layer M2 away from the substrate 10, as shown in Figure 5B illustrated, the first electrode 1041 can avoid the first via V1 and the second via V2 corresponding to the first data line lead DL1, thereby improving the flatness of the first electrode 1041.

[0079] For example, in some embodiments, the two first data line leads DL1 can also adopt other arrangements, such as asymmetric arrangements. For example, as shown in Figure 6 illustrated, in the case where the two first data line leads DL1 are located between the two data lines Da, the two first data line leads DL1 are arranged in a straight line along the first direction R1, and, in the first direction R1, the first via V1 and the second via V2 corresponding to the two first data line leads DL1 can be alternately spaced, or staggered. For example, in the first direction, from top to bottom, the first via V1 corresponding to the left first data line lead DL1, the first via V1 corresponding to the right first data line lead DL1, the second via V2 corresponding to the left first data line lead DL1, and the second via V2 corresponding to the right first data line lead DL1 are arranged in sequence. At this time, the first via V1 and the second via V2 corresponding to the two first data line leads DL1 are not symmetric left and right, and this design can reduce the horizontal arrangement space occupied by the first via V1 and the second via V2, making the arrangement of the two first data line leads DL1 more compact.

[0080] For example, in some embodiments, as shown in Figure 7 illustrated, the display substrate can further include a second data line lead DL2, the second data line lead DL2 being located in the first conductive layer M1 and extending along a second direction R2, the second direction R2 being different from the first direction R1, for example, the second direction R2 being perpendicular to the first direction R1. For example, the second data line lead DL2 can be used to connect the data line Da and the first data line lead DL1 having a certain distance in the second direction R2.

[0081] For example, as shown in Figure 7 illustrated, at least one of the two first data line leads DL1 between the two columns of adjacent sub-pixels SP is connected to the second data line lead DL2 through a first adapter line Z1, the first adapter line Z1 can be located in the first conductive layer M1, and in a direction perpendicular to the substrate 10, the first adapter line Z1 at least partially overlaps the at least one first data line lead DL1, so that the first adapter line Z1 is blocked, thereby avoiding display substrate from having a screen-off mura (an undesirable phenomenon of displaying a strip-shaped trace when the display substrate is in a screen-off state) and other undesirable phenomena.

[0082] For example, as shown in Figure 7 illustrated, the first adapter line Z1 is linear, and in the direction perpendicular to the substrate 10, the first adapter line Z1 at least partially overlaps the at least one first data line lead DL1, so that the first adapter line Z1 is blocked, thereby avoiding display substrate from having a screen-off mura (an undesirable phenomenon of displaying a strip-shaped trace when the display substrate is in a screen-off state) and other undesirable phenomena.Figure 7 In this embodiment, the first data line lead DL1 and the second data line lead DL2 are connected along the first direction R1, i.e., along the vertical direction shown in the figure. This shortens the length of the adapter cable, reduces the overlap capacitance of the adapter cable, and when both first data line leads DL1 are connected to the second data line lead DL2 through the first adapter cable Z1, the first adapter cable Z1 and the second data line lead DL2 are substantially symmetrical. Therefore, when the first electrode 1041 is fabricated on the second conductor layer M2, the flatness of the first electrode 1041 can be optimized. In addition, the first adapter cable Z1 and the first data line lead DL1 at least partially overlap, so that the first data line lead DL1 can block the first adapter cable Z1, thereby reducing screen-off mutagenesis. Figure 7 The wiring layout of the embodiment has less change compared to the wiring layout of the 2-in-1 design.

[0083] For example, in some embodiments, such as Figure 8 As shown, the second lead portion DL12 of the two first data line leads DL1 between two adjacent columns of sub-pixels SP can each include a bent portion B that bends in a direction closer to each other. Figure 6 Compared to the previous embodiment, the two first data line leads DL1 are recessed inwards towards each other, which further saves lateral space. This saved lateral space can be used to widen, for example, the second power line VDD (described in detail later), to reduce the voltage drop of the second power line VDD. For example, Figure 8 The scenarios illustrated in the examples can also be applied to... Figure 7 In the connection relationship.

[0084] For example, in some embodiments, such as Figures 9-11 As shown, in the first direction R1, the first via V1 and the second via V2 corresponding to the two first data line leads DL1 between two adjacent columns of sub-pixels SP can be located on the same straight line. This further reduces the lateral space occupied by the two first data line leads DL1 and the first via V1 and the second via V2. For example, Figures 9-11 The embodiments employed different jumper arrangement methods.

[0085] For example, in Figure 9 In the embodiments, such as Figure 9 As shown, in the first direction R1, the first vias V1 and V2 corresponding to the two first data line leads DL1 are located on a straight line extending along the first direction R1. Following a top-to-bottom direction, the first vias V1 and V2 corresponding to the left first data line lead DL1 and the first vias V1 and V2 corresponding to the right first data line lead DL1 are sequentially arranged; compared to... Figure 6 and Figure 8 Implementation examples, Figure 9In the embodiment, the first via V1 and the second via V2 are arranged more regularly and symmetrically, so that the flatness of the first electrode 1041 formed above the second conductive layer M2 can be improved; and the first lead part DL11 of the two first data line leads DL1 is also located on the same straight line, so that the transverse arrangement space of the first lead part DL11 is smaller, which is suitable for the case that there are more wirings in the first conductive layer M1, so as to facilitate the arrangement of the wirings in the first conductive layer M1.

[0086] For example, in the embodiment, the first data line lead DL1 and the data line Da can be interchanged, and the arrangement of the first data line lead DL1 and the via can also be interchanged. Figure 10 Figure 10 As shown in the figure, in the first direction R1, the first via V1 and the second via V2 corresponding to the two first data line leads DL1 are located on a straight line extending along the first direction R1, and in the direction from top to bottom, the first via V1 corresponding to the left first data line lead DL1, the first via V1 corresponding to the right first data line lead DL1, the second via V2 corresponding to the left first data line lead DL1, and the second via V2 corresponding to the right first data line lead DL1 are sequentially arranged; at this time, the first lead part DL11 and the second lead part DL12 both have a bending part, compared with the embodiment, the second lead part DL12 in the second conductive layer M2 protrudes less left and right, saves the arrangement space of the second conductive layer M2, and is suitable for the case that there are more wirings in the second conductive layer M2. Figure 9

[0087] For example, in the embodiment, the first data line lead DL1 and the data line Da can be interchanged, and the arrangement of the first data line lead DL1 and the via can also be interchanged. Figure 11 Figure 11 As shown in the figure, in the first direction R1, the first via V1 and the second via V2 corresponding to the two first data line leads DL1 are located on a straight line extending along the first direction R1, and in the direction from top to bottom, the first via V1 corresponding to the left first data line lead DL1, the first via V1 corresponding to the right first data line lead DL1, and the second via V2 corresponding to the left first data line lead DL1 are sequentially arranged; compared with the embodiments of Figure 9 and Figure 10 In the first conductive layer M1, the first lead part DL11 only protrudes to the left, and in the second conductive layer M2, the second lead part DL12 only protrudes to the right, which is suitable for the case that the plurality of sub-pixels SP are not designed symmetrically left and right.

[0088] For example, in each of the above embodiments, the positions of the first data line lead DL1 and the data line Da can be interchanged, and the arrangement of the adjacent first data line lead DL1 and the via can also be interchanged, and the embodiments of the present disclosure will not be repeated here.

[0089] ​​​In the above embodiments of the present disclosure, the first data line lead DL1 is arranged in a double-layer conductive layer, and a jumper design is adopted, so that the display substrate can avoid static discharge and other adverse phenomena during preparation, improve the preparation yield of the display substrate, and save costs; in addition, the above 1-1 design can shorten the total length of the data line lead, reduce the resistance and overlapping capacitance of the data line lead, reduce data signal loss, reduce load, narrow the frame, and reduce costs.

[0090] For example, in some embodiments, the display substrate can also adopt a 2-1 design. For example, Figure 12 A planar arrangement schematic diagram of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure is shown, which is under a 2-1 design, as shown in Figure 12 As shown, in the direction parallel to the substrate 10, two data lines Da are arranged between two adjacent columns of sub-pixels SP, and one first data line lead DL1 is arranged between the two data lines Da, that is, two data lines Da and one first data line lead DL1 are arranged corresponding to each two columns of sub-pixels SP. The data line Da and the first data line lead DL1 extend along the first direction R1.

[0091] For example, as shown in Figure 12 The display substrate can further include a second data line lead DL2, the second data line lead DL2 is located in the first conductive layer M1 and extends along the second direction R2, the second direction R2 is different from the first direction R1, for example, the second direction R2 is perpendicular to the first direction R1. For example, the second data line lead DL2 can be used to connect the data line Da and the first data line lead DL1 which have a certain distance in the second direction R2. For example, the first data line lead DL1 is connected to the second data line lead DL2 through the second jumper Z2, the second jumper Z2 is located in the first conductive layer M1, and in the direction perpendicular to the substrate 10, the second jumper Z2 at least partially overlaps with one of the two data lines Da (the data line Da on the right side of the middle in FIG. 8), so that the second jumper Z2 is blocked. Figure 12

[0092] For example, as shown in Figure 12 The first data line lead DL1 or the second data line lead DL2 can be designed with a break DS to disconnect the part of the first data line lead DL1 or the second data line lead DL2 for connecting different data lines Da, or to disconnect the part for connecting the data line Da and the part for connecting the first power line VSS, so as to prevent signal crosstalk.

[0093] For example, in some embodiments, the second data line lead DL2 is located in the first conductive layer M1, and the break DS of the second data line lead DL2 can overlap with the conductive pattern in the second conductive layer M2 to be blocked by the conductive pattern in the second conductive layer M2, for example​Figure 12 The first data line lead DL1 is blocked by the second power line VDD in the second conductive layer M2; for example, the first data line lead DL1 is located in the second conductive layer M2, and the break in the first data line lead DL1 is ( Figure 12 (Not shown) can overlap with the conductive pattern in the first conductive layer M1 so as to be blocked by the conductive pattern in the first conductive layer M1. The blocking break can prevent defects such as light leakage from the display substrate.

[0094] For example, in the above embodiment, a vertically extending first data line lead DL1 is inserted between every two columns of sub-pixels SP. The first data line lead DL1 is connected to a horizontally extending second data line lead DL2 via a second adapter Z2. The second adapter Z2 at least partially overlaps with the data line Da, thereby being blocked by the data line Da, which can prevent defects such as screen-off mura from occurring on the display substrate. At the same time, the second adapter Z2 can also avoid the source and drain electrodes SD of the transistors (described in detail later) of the pixel driving circuit of the sub-pixel SP. Figure 12 As shown. For example, the second data line lead DL2 can overlap with signal lines in other conductive layers besides the first conductive layer M1, so that it can be blocked / shielded by signal lines in other conductive layers besides the first conductive layer M1, such as reset voltage lines or scan signal lines, to prevent defects such as screen-off mura.

[0095] For example, in some embodiments, a portion of the longitudinally extending first data line lead DL1 and the laterally extending second data line lead DL2 is used to transmit data signals, i.e., connected to the data line Da, while the other portion can be used to connect to the first power line VSS to transmit a first power signal, thereby reducing the voltage drop of the first power line VSS. In this case, the portion used to transmit the data signal and the portion used to transmit the first power signal are disconnected through a break (e.g., break DS and breaks DS1, DS2, etc. mentioned below) to prevent signal crosstalk.

[0096] For example, in some embodiments, such as Figure 13 As shown, there can be two adapter wires ZS for connecting the first data line lead DL1 and the second data line lead DL2, and the two adapter wires ZS can be arranged symmetrically. When this part of the first data line lead DL1 and the second data line lead DL2 is used to connect the first power line VSS, this design can increase the access points of the first power line VSS, further reduce the voltage drop, reduce the overall power consumption, and optimize the flatness of the subsequently formed first electrode 1041.

[0097] For example, Figure 14 This is a schematic diagram of the planar arrangement of the first data line lead in a display substrate with a 1-to-1 design, provided for at least one embodiment of this disclosure. (See diagram below.) Figure 14As shown, in a 1-in-1 design, in a direction parallel to the substrate 10, two first data line leads DL1 are provided between two adjacent columns of sub-pixels SP, and two data lines Da are provided between two adjacent columns of sub-pixels SP. The two first data line leads DL1 are provided between the two data lines Da. Alternatively, in some other embodiments, the positions of data lines Da and first data line leads DL1 can be interchanged, and two data lines Da are provided between the two first data line leads DL1. The following describes... Figure 14 The following example illustrates the case where two first data line leads DL1 are set between the two data lines Da.

[0098] For example, such as Figure 14 As shown, the display substrate may further include multiple second data line leads DL2, which are located in the first conductive layer M1 and extend along the second direction R2. The first data line Da1 of the two data lines Da is connected to the first second data line lead 1DL2 of the multiple second data line leads DL2, and the first second data line lead 1DL2 is connected to the first first data line lead 1DL1 spaced at least one sub-pixel SP (two sub-pixels SP in the figure) from the first data line Da1; the second data line Da2 of the two data lines Da is connected to the second second data line lead 2DL2 of the multiple second data line leads DL2, and the second second data line lead 2DL2 is connected to the second first data line lead 2DL1 spaced at least one sub-pixel SP (two sub-pixels SP in the figure) from the second data line Da2.

[0099] For example, in Figure 14 In this embodiment, the first data line Da1 of the two data lines Da is connected to the first second data line lead 1DL2 of the plurality of second data line leads DL2 via a third adapter Z3. In the direction perpendicular to the substrate 10, the first data line Da1 and the third adapter Z3 at least partially overlap, for example, almost completely overlap, so that the third adapter Z3 is blocked. The second data line Da2 of the two data lines Da is connected to the second second data line lead 2DL2 of the plurality of second data line leads DL2 via a fourth adapter Z4. In the direction perpendicular to the substrate 10, the second data line Da and the third adapter Z3 at least partially overlap, for example, almost completely overlap, so that the fourth adapter Z4 is blocked. For example, both the third adapter Z3 and the fourth adapter Z4 are located in the first conductive layer M1. Blocking the third adapter Z3 and the fourth adapter Z4 can prevent defects such as screen-off mura from occurring on the display substrate.

[0100] For example, in Figure 14In an embodiment, the first second data line lead 1DL2 is connected to the first first data line lead 1DL1 through the fifth adapter line Z5, the first first data line lead 1DL1 being spaced apart from the first data line Da by at least one sub-pixel SP (two sub-pixels SP are spaced apart in the figure), the fifth adapter line Z5 and the data line Da (on the left side) adjacent to the first first data line lead 1DL1 at least partially overlap in a direction perpendicular to the substrate base plate 10, so that the fifth adapter line Z5 is at least partially blocked; the second second data line lead 2DL2 is connected to the second first data line lead 2DL1 through the sixth adapter line Z6, the second first data line lead 2DL1 being spaced apart from the second data line Da2 by at least one sub-pixel SP (two sub-pixels SP are spaced apart in the figure), the sixth adapter line Z6 and the data line Da (on the right side) adjacent to the second first data line lead 2DL1 at least partially overlap in a direction perpendicular to the substrate base plate 10, so that the sixth adapter line Z6 is at least partially blocked. For example, the fifth adapter line Z5 and the sixth adapter line Z6 are both located in the first conductive layer M1, and the fifth adapter line Z5 and the sixth adapter line Z6 being blocked can prevent the display substrate from having a screen-off mura and other defects.

[0101] For example, in Figure 14 an embodiment, the display substrate further comprises a first power line VSS, and part DL0 of the first data line lead DL1 and the second data line lead DL2 is used to connect the first power line VSS, at this time, the part DL0 is disconnected from the part of the first data line lead DL1 and the second data line lead DL2 used to transmit the data signal through the break DS / DS1, the part DL0 can reduce the voltage drop of the first power line VSS, thereby improving the display uniformity of the display substrate.

[0102] For example, Figure 16 An enlarged schematic view of the dashed box in Figure 14 is shown, as shown in Figure 16 , the first data line lead DL1 and the second data line lead DL2 are connected through the adapter line Z0, the two adapter lines Z0 are symmetrically arranged, and the data line Da bypasses the position of the adapter hole, thereby, as shown in Figure 17 , after the first electrode 1041 of the light-emitting device EM is formed subsequently, the data line lead, the adapter line, the adapter hole and the like under the first electrode 1041 are all symmetrically designed, thereby improving the flatness of the first electrode 1041.

[0103] For example, in Figure 14 , in order to highlight the connection relationship between the data line Da, the first data line lead DL1 and the second data line lead DL2, Figure 14 the connection of these lines is highlighted (for lines used to transmit data signals) / weakened (for lines used to transmit first power signals) to clearly show these connection relationships, and the clean version of the circuit arrangement diagram without highlighting the connection relationship is as shown in Figure 15As shown, please refer to the details. Figure 15 .

[0104] For example, such as Figure 14 As shown, the first data line Da1, the first second data line lead 1DL2, and the first first data line lead 1DL1 form a first data line mesh G1. The second data line Da2, the second second data line lead 2DL2, and the second first data line lead 2DL1 form a second data line mesh G2. The second data line mesh G2 is located around the first data line mesh G1; for example, the second data line mesh G2 surrounds the first data line mesh G1. For example, the first data line mesh G1 and the second data line mesh G2 extend to the lower non-display area NA of the display substrate near the center (shown on the right side in the figure) to be bonded in the non-display area NA. For example, the display substrate may also include more data lines located around the second data line mesh G2, these data lines being wound layer by layer and extending to the lower non-display area NA of the display substrate near the center (shown on the right side in the figure) to be bonded in the non-display area NA.

[0105] In the embodiments of this disclosure, the above-described winding method can reduce the binding width of the traces used for transmitting data signals below the display area AA, or the Fanout access width, so as to save the space occupied by binding in the non-display area NA.

[0106] For example, such as Figure 14 As shown, the two first data line leads DL1 located between the two data lines Da include a disconnected portion DL0 that is disconnected from the first data line network G1 and the second data line network G2. The disconnection point, i.e., the break, is shown by the dashed circle DS1. For example, the disconnected portion DL0 is connected to the first power line VSS to reduce the voltage drop of the first power line VSS. For example, in the direction perpendicular to the substrate 10, the disconnection point overlaps with the first conductive layer M1 or the second conductive layer M2, that is, overlaps with the conductive pattern in the first conductive layer M1 or the second conductive layer M2, or overlaps with the structure in other conductive layers, so that the break is blocked to prevent adverse phenomena such as light leakage.

[0107] For example, in some examples, when the break DS1 of the first data line lead DL1 is located in the first lead portion DL11, since the first lead portion DL11 is located in the first conductive layer M1, the break DS1 can overlap with the second conductive layer M2, that is, be blocked by the conductive pattern in the second conductive layer M2; or, when the break DS1 is located in the second lead portion DL12, the second lead portion DL12 is located in the second conductive layer M2, and the break DS1 can overlap with the first conductive layer M1, that is, be blocked by the conductive pattern in the first conductive layer M1.

[0108] For example, inFigures 14-17 In some embodiments, the first data line lead DL1 extends along the first direction R1 and has no bending portion to maximize the use of the arrangement space. Figure 17 As shown, the jumper wires Z0 bypass the source-drain electrodes SD of the transistors left and right, and each jumper wire is located in the first conductive layer M1 and can be shielded by a wire in another conductive layer. Compared with the 2-pin-1 design, the 1-pin-1 design can shorten the total length of the data line leads (including the first data line lead DL1 and the second data line lead DL2), reduce the lead resistance and the overlapping capacitance, reduce the data signal loss and the data signal load. In addition, the 1-pin-1 design can also increase the density of the connection lines (such as part of DL0) of the first power line VSS by, for example, one time, so as to better control the voltage drop of the first power line VSS and reduce the screen power consumption. Furthermore, the 1-pin-1 design can also reduce the binding width of the wires used for transmitting data signals below the display area AA and save the space occupied by the binding in the non-display area NA.

[0109] For example, Figure 32 A schematic diagram showing the binding of the data lines Da and the first data line lead DL1 in the non-display area NA in the 2-pin-1 design is shown in FIG. 6A, in which one box represents two sub-pixels P, and two data lines Da and one first data line lead DL1 are arranged corresponding to the two sub-pixels P. Figure 32 As shown, one box represents two sub-pixels P, and two data lines Da and one first data line lead DL1 are arranged corresponding to the two sub-pixels P. Figure 32 In FIG. 6B, a total of 16 data lines Da and 8 first data line leads DL1 corresponding to 16 sub-pixels P are shown, and a total of 24 signal lines need to be accessed to the lower binding area corresponding to the space of the 16 sub-pixels P, and the connection portion SL occupies a certain space vertically. Figure 33 A schematic diagram showing the binding of the data lines Da and the first data line lead DL1 in the non-display area NA in the 1-pin-1 design is shown in FIG. 7A, in which one box represents two sub-pixels P, and two data lines Da and two first data line leads DL1 are arranged corresponding to the two sub-pixels P. Figure 32 In FIG. 7B, a total of 12 data lines Da and 12 first data line leads DL1 corresponding to 12 sub-pixels P are shown, and a total of 24 signal lines need to be accessed to the lower binding area corresponding to the space of the 12 sub-pixels P; the connection portion SL occupies a relatively smaller space vertically, thereby saving the space occupied by the binding in the non-display area NA.

[0110] For example, in some other embodiments, the data line Da, the first data line lead DL1 and the second data line lead DL2 can also adopt different connection modes. For example, as shown in FIG. 8A, the data line Da and the first data line lead DL1 are connected by a jumper wire Z1, and the jumper wire Z1 is located in the first conductive layer M1 and can be shielded by a wire in another conductive layer. Figure 18As shown, data line Da can also be connected to the second data line lead DL2 via the first data line lead DL1. In this case, data line Da is first connected to the first data line lead DL1 via adapter cable Z21, and then connected to the second data line lead DL2 via adapter cable Z22. For example, as... Figure 18 As shown, the adapter cable Z21 and adapter cable Z22 used for the two adjacent data lines Da can be arranged symmetrically.

[0111] For example, such as Figure 18 As shown, the second data line lead DL2 also has a break DS to separate the portion of the second data line lead DL2 used for transmitting data signals and the portion used for transmitting the first power signal. For example, the second data line lead DL2 is located in the first conductive layer M1, and the break DS in the second data line lead DL2 at least partially overlaps with the conductive pattern in the second conductive layer M2 so as to be blocked by the conductive pattern in the second conductive layer M2, for example, blocked by the second power line VDD in the second conductive layer M2, thereby preventing defects such as light leakage from the display substrate.

[0112] For example, Figure 19 This is a schematic diagram illustrating the connection between the first data line lead and the second data line lead in a display substrate provided in at least one embodiment of the present disclosure; as shown. Figure 19 As shown, in some other embodiments, two first data line leads DL1 are provided between two adjacent columns of sub-pixels SP, and two data lines Da are provided between the two first data line leads DL1. For example, the data line Da extends in a straight line along the first direction R1, and the first data line lead DL1 has a bent portion at the position of the third via V3 of the data line Da to avoid the third via V3. The first data line lead DL1 is electrically connected to the second data line lead DL2 through the adapter hole V0 and the adapter wire Z23.

[0113] For example, Figure 19 Implementation examples and Figure 14 Compared to the previous embodiment, the positions of the first data line lead DL1 and the data line Da are interchanged, with the two data lines Da placed between the two first data line leads DL1, thereby reducing the impact of data signal transitions on surrounding signal lines; for example Figure 20 As shown, after the first electrode 1041 is provided on the second conductive layer M2, the first electrode 1041 can avoid the transition hole V0 and the third via V3, thereby improving the flatness of the first electrode 1041.

[0114] For example, in embodiments of this disclosure, data line Da can be connected to the second data line lead DL2 in different ways. Figure 21A and Figure 21B The diagram illustrates different connection scenarios for the data line Da and the second data line leads, as shown below. Figure 21AAs shown, the data line Da is electrically connected to the second data line lead DL2 through the third via V3 and the adapter Z24. The adapter Z24 is located on the first conductive layer M1 and overlaps at least partially with the data line Da and the first data line lead DL1. Thus, the adapter Z24 can be shielded by the data line Da and the first data line lead DL1 to prevent defects such as screen-off mura.

[0115] For example, such as Figure 21B As shown, data line Da is first connected to the adjacent first data line lead DL1 through the third via V3 and adapter Z25. The first data line lead DL1 is then connected to the second data line lead DL2 through the via V31 and adapter Z26. For example, adapter Z25 and adapter Z26 are both located on the first conductive layer M1, and adapter Z25 and adapter Z26 at least partially overlap with the first data line lead DL1, so that adapter Z25 and adapter Z26 can be shielded by the first data line lead DL1 to prevent defects such as screen muta.

[0116] Figure 21B Implementation examples and Figure 21A Compared to the previous embodiment, the first data line lead DL1 and the data line Da can share the same adapter cable, saving layout space. Furthermore, through the design of multiple breaks DS2, it is possible to disconnect the transmission network that transmits different signals, such as disconnecting the part used to transmit data signals and the part used to transmit the first power signal. Moreover, the adapter patterns of the two parts are not much different, which is beneficial to improving the uniformity of the film layer. Figure 21A Implementation examples and Figure 21B Compared to the previous embodiment, the data line Da has a shorter transition path, does not need to borrow a section of the first data line lead DL1, thus avoiding waste of the adjacent first data line lead DL1, and also reduces data signal loading and reduces overlapping capacitance, thereby increasing the setup density of the part used to transmit the first power signal.

[0117] For example, in other embodiments, such as Figure 22 As shown, the second data line lead DL2 can be directly connected to the first data line lead DL1 through the adapter hole V4, and... Figure 19 Compared to other embodiments, the electrical connection is no longer made using an adapter cable. In this case, it is no longer necessary to set vias in the first insulating layer 11. This reduces the length of the adapter path, eliminates the need for specially designed wiring layouts to shield the adapter cable and the break, and simplifies the arrangement of the break and the adapter line.

[0118] For example, if it is necessary to connect the second data line lead DL2 to the vertical first data line lead DL1, the adapter cable can be replaced with an adapter hole, see reference. Figure 35The adapter hole V36 retains the first conductive layer M1 and the second conductive layer M2, as well as the hole layer, i.e., the layer with the via, i.e., the first insulating layer 11, thereby saving space for the adapter cable. For example, if it is necessary for the first data line lead DL1 to be continuously connected and the second data line lead DL2 to be continuously connected, the hole layer can be removed, i.e., the adapter hole is not provided, and the conductive patterns of the first conductive layer M1 and the second conductive layer M2 are retained, as shown in the reference. Figure 35 The portion shown by the dashed circle 1; for example, if it is necessary to set the break position of the first data line lead DL1, the hole layer can be removed, that is, the adapter hole is not set, and only the conductive pattern of the first conductive layer M1 is retained, see reference. Figure 35 The portion shown by the dashed circle 3; for example, if it is necessary to set the break position of the second data line lead DL2, the hole layer can be removed, that is, the adapter hole is not set, and only the conductive pattern of the second conductive layer M2 is retained, see reference. Figure 35 The portion shown by the dashed circle 2. This reduces the length of the transition path, eliminates the need for specially designed wiring layouts to conceal the transition wires and breaks, and simplifies the arrangement of breaks and transition lines.

[0119] For example, Figure 21A , Figure 21B as well as Figure 22 The connection method can be used in the wiring layout provided in any embodiment of this disclosure.

[0120] For example, Figure 23 This is a schematic diagram of another planar arrangement of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure, using a 1-to-1 design. In some embodiments, such as... Figure 23 As shown, two first data line leads DL1 are provided between two adjacent columns of sub-pixels SP, and two data lines Da are provided between the two first data line leads DL1. For example, the first data line Da1 of the two data lines Da is connected to the first second data line lead 1DL2 of the multiple second data line leads DL2 through a third adapter Z3. In the direction perpendicular to the substrate 10, the third adapter Z3 and the first data line lead DL1 adjacent to the first data line Da1 at least partially overlap, for example, also at least partially overlap with the first data line Da1, so that the third adapter Z3 is blocked. The second data line Da2 of the two data lines Da is connected to the second second data line lead 2DL2 of the multiple second data line leads DL2 through a fourth adapter Z4. In the direction perpendicular to the substrate 10, the fourth adapter Z4 and the first data line lead DL1 adjacent to the second data line Da at least partially overlap, for example, also at least partially overlap with the second data line Da2, so that the fourth adapter Z4 is blocked.

[0121] For example, such as Figure 23As shown, the first second data line lead 1DL2 is directly connected to the first first data line lead 1DL1 through the fourth via V4, the first first data line lead 1DL1 being spaced apart from the first data line Da by at least one sub-pixel SP (two sub-pixels SP are shown in the figure); the second second data line lead 2DL2 is directly connected to the second first data line lead 2DL1 through the fifth via V5, the second first data line lead 2DL1 being spaced apart from the second data line Da by at least one sub-pixel SP (two sub-pixels SP are shown in the figure). In this way, the design and arrangement of the jumper wires are saved.

[0122] For example, as shown in Figure 23 , the first data line lead 1DL1 and the second data line lead 2DL2 also have a portion DL0 for connecting the first power signal, the portion DL0 being disconnected from the portion of the first data line lead 1DL1 and the second data line lead 2DL2 for connecting the data signal through the disconnection DS3. For example, in the embodiment of Figure 23 , in the portion DL0 of the first data line lead 1DL1 and the second data line lead 2DL2 for connecting the first power signal, the first data line lead 1DL1 and the second data line lead 2DL2 are electrically connected through the via V41.

[0123] For example, in the embodiment of Figure 23 , the first data line Da1, the first second data line lead 1DL2 and the first first data line lead 1DL1 form a first data line net G1, the second data line Da2, the second second data line lead 2DL2 and the second first data line lead 2DL1 form a second data line net G2, the second data line net G2 being located at the periphery of the first data line net G1, for example, the second data line net G2 surrounding the first data line net G1. For example, the first data line net G1 and the second data line net G2 can extend to the lower non-display area NA of the display substrate at a position close to the middle of the display substrate (shown as the right side in the figure) to be bound in the non-display area NA. For example, the display substrate can also include more data line nets located at the periphery of the second data line net G2, the data line nets being wound layer by layer and extending to the lower non-display area NA of the display substrate at a position close to the middle of the display substrate (for example, shown as the right side in the figure) to be bound in the non-display area NA.

[0124] For example, in Figure 23 , in order to highlight the connection relationship between the data line Da, the first data line lead DL1 and the second data line lead DL2, Figure 23 the connections of these wires are highlighted to clearly show the connection relationship, and the clean version circuit arrangement diagram of the highlighted connection relationship is shown in Figure 24 , which can be specifically seen in Figure 24 .

[0125] For example, in other embodiments, the display data line Da and the first data line lead DL1 may also be arranged in other ways. For example, Figure 25 This is a schematic diagram of another planar arrangement of the first data line lead and data line in the display substrate provided in at least one embodiment of the present disclosure, as shown below. Figure 25 As shown, in a direction parallel to the substrate 10, two data lines Da are provided between adjacent first column sub-pixels SP1 and second column sub-pixels SP2, and a reset voltage line Vint (described in detail later) is provided between the two data lines Da. Two first data line leads DL1 are provided between adjacent second column sub-pixels SP2 and third column sub-pixels SP3.

[0126] For example, Figure 26 This is another planar arrangement diagram of the first data line lead in the display substrate provided in at least one embodiment of the present disclosure, using a 1-to-1 design. Figure 26 The connection relationship between data line Da, first data line lead DL1, and second data line lead DL2 is shown, as follows: Figure 26 As shown, the data line Da1 (the first data line Da1 to the left of the second sub-pixel SP2) and the first data line lead DL1 (the first first data line lead DL1 to the right of the second sub-pixel SP2) adjacent to the second column sub-pixel SP2 are electrically connected through the first second data line lead DL2. For example, the first data line Da1 is electrically connected to the first second data line lead DL2 through the seventh adapter Z7, for example, the seventh adapter Z7 and the data line Da1 at least partially overlap, so that the seventh adapter Z7 is blocked; for example, the first second data line lead DL2 is electrically connected to the first first data line lead DL1 through the eighth adapter Z8, for example, the eighth adapter Z8 and the first first data line lead DL1 at least partially overlap, so that the eighth adapter Z8 is blocked. Alternatively, in other embodiments, the first second data line lead 1DL2 can also be directly electrically connected to the first data line lead DL1 through a via; or, the first data line Da1 can also be directly electrically connected to the first second data line lead 1DL2 through a via.

[0127] For example, such as Figure 26As shown, the data line Da2 (the second data line Da2 on the right side of the second column of sub-pixels SP2) adjacent to the first column of sub-pixels SP and the first data line lead DL1 (the second first data line lead 2DL1 on the left side of the third column of sub-pixels SP) adjacent to the third column of sub-pixels SP are electrically connected through the second second data line lead 2DL2. For example, the data line Da2 is electrically connected with the second second data line lead 2DL2 through the ninth adapter line Z9, for example, the ninth adapter line Z9 at least partially overlaps with the second data line Da2 so that the ninth adapter line Z9 is blocked; for example, the second second data line lead 2DL2 is electrically connected with the first data line lead DL1 through the tenth adapter line Z10, for example, the tenth adapter line Z10 at least partially overlaps with the second second data line lead 2DL2 so that the tenth adapter line Z10 is blocked. Alternatively, in other embodiments, the second second data line lead 2DL2 can also be directly electrically connected with the second first data line lead 2DL1 through a via hole; or the data line Da2 can also be directly electrically connected with the second second data line lead 2DL2 through a via hole.

[0128] For example, as shown in FIG. 1A, Figure 26 As shown, the first data line lead DL1 has a break DS1, Figure 26 As shown in FIG. 1A, the break DS1 in the first first data line lead 1DL1 disconnects the part of the first first data line lead 1DL1 for transmitting data signals from the part of the first first data line lead 1DL1 for transmitting the first power signal. For example, the disconnected part of the first first data line lead 1DL1 is the first lead part DL11, since the first lead part DL11 is located in the first conductive layer M1, at this time, the break DS1 can overlap with the second conductive layer M2, that is, be blocked by the conductive pattern in the second conductive layer M2; or the disconnected part of the first first data line lead 1DL1 is the second lead part DL12, the second lead part DL12 is located in the second conductive layer M2, at this time, the break DS1 can overlap with the first conductive layer M1, that is, be blocked by the conductive pattern in the first conductive layer M1.

[0129] For example, as shown in FIG. 1A, Figure 26 As shown, two second power lines VDD are also arranged in the adjacent second column of sub-pixels SP and third column of sub-pixels SP, that is, the second column of sub-pixels SP corresponds to one second power line VDD, the third column of sub-pixels SP corresponds to one second power line VDD, for example, the two first data line leads DL1 can be located between the two second power lines VDD.

[0130] For example, in Figure 26 In order to highlight the connection relationship between the data line Da, the first data line lead DL1 and the second data line lead DL2, Figure 26The connections of the wirings are highlighted to clearly show the connection relationship, and a clean version of the circuit arrangement diagram without the highlighted connections is as shown in Figure 27 , and details can be seen in Figure 27 .

[0131] For example, Figure 28 , a planar schematic diagram of the display substrate in an embodiment of the present disclosure is as shown in Figure 26 , and Figure 27 , a planar schematic diagram of the display substrate in an embodiment of the present disclosure is as shown in Figure 28 , the first electrode 1041 can avoid the third via V3 of the data line Da, thereby improving the flatness of the first electrode 1041.

[0132] For example, in embodiments of Figure 26 and Figure 27 , compared with embodiments of Figure 23 and Figure 24 , the positions of the two first data line leads DL1 are interchanged with the position of the reset voltage line Vint, the reset voltage line Vint is located between the two data lines Da, and the two first data line leads DL1 are located between the two second power lines VDD; thereby, the switching path between the display data line Da, the first data line lead DL1, and the second data line lead DL2 is short, the design of the break is good, and it is convenient to be shielded by other conductive layers, the via such as the third via V3 can avoid the first electrode 1041, so as to improve the flatness of the first electrode 1041.

[0133] For example, Figure 34 , another planar arrangement schematic diagram of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure under the 1-in-1 design, in some embodiments, as shown in Figure 34 , two first data line leads DL1 are arranged between two adjacent columns of sub-pixels SP, and two data lines Da are arranged between the two first data line leads DL1. For example, the first data line Da1 of the two data lines Da is connected to the first first data line lead 1DL1 and the first second data line lead 1DL2 through the switching hole V35, the switching line Z35, and the switching hole V36, at this time, the first data line Da1 is connected to the first first data line lead 1DL1 adjacent to it and located in the same sub-pixel SP.

[0134] For example, in the direction perpendicular to the substrate 10, the switching line Z35 and the first first data line lead 1DL1 at least partially overlap, so that the switching line Z35 is shielded.

[0135] For example, as shown in Figure 34As shown, in the part DL0 of the first data line lead DL1 and the second data line lead DL2 for transmitting the first power supply signal, the two first data line leads DL1 are connected with the second data line lead DL2 through two transfer holes V34 respectively, to form a transmission network of the first power supply signal.

[0136] For example, in Figure 34 , in order to highlight the connection relationship between the data line Da, the first data line lead DL1 and the second data line lead DL2, Figure 34 The connections of these traces are highlighted to clearly show the connection relationship, and the clean version of the circuit arrangement diagram without the highlighted connection relationship is as follows Figure 35 As shown, for details, please refer to Figure 35 .

[0137] For example, Figure 29 The partial cross-sectional schematic diagram of the display substrate is shown, as Figure 29 shown, each of the plurality of sub-pixels SP includes a light emitting device EM and a pixel driving circuit for driving the light emitting device EM, the light emitting device EM includes a first electrode 1041 connected with the pixel driving circuit, a second electrode 1043 arranged in a spaced manner with the first electrode 1041, and a light emitting layer 1042 between the first electrode 1041 and the second electrode 1043. For example, the first electrode 1041 is an anode of the light emitting device EM, for receiving a second power supply signal provided by a second power supply line VDD, for example, the second power supply signal is a high-level signal. For example, the second electrode 1043 is a cathode of the light emitting device EM, electrically connected with a first power supply line VSS, for receiving a first power supply signal, for example, the first power supply signal is a low-level signal.

[0138] For example, as Figure 29 shown, the pixel driving circuit includes a transistor T and a storage capacitor C, the transistor T includes an active layer 1021, a gate 1022, and a first source-drain electrode 1023 and a second source-drain electrode 1024, the first source-drain electrode 1023 is electrically connected with the first electrode 1041 through a connection electrode CEL, the first source-drain electrode 1023 and the second source-drain electrode 1024 are located in a first conductive layer M1, the first conductive layer M1 can also be an SD1 conductive layer, the connection electrode CEL is located in a second conductive layer M2, the second conductive layer M2 can also be referred to as an SD2 conductive layer.

[0139] For example, as Figure 29As shown, the display substrate may also include more conductive layers, such as a third conductive layer M3 and a fourth conductive layer M4. The fourth conductive layer M4 is disposed on the side of the third conductive layer M3 away from the substrate 10, and the first conductive layer M1 is disposed on the side of the fourth conductive layer M4 away from the substrate 10. For example, the storage capacitor C includes a first capacitor electrode C1 and a second capacitor electrode C2. For example, the first capacitor electrode C1 and the first gate 1022 are disposed on the third conductive layer M3, which may also be called the Gate 1 conductive layer, and the second capacitor electrode C2 is disposed on the fourth conductive layer M4, which may also be called the Gate 2 conductive layer.

[0140] For example, such as Figure 29 As shown, the display substrate may further include at least one barrier layer 1012 and at least one buffer layer 1013 disposed on the substrate 10. Figure 29 The diagram shows a barrier layer 1012 and a buffer layer 101 as an example. The barrier layer 1012 and the buffer layer 1013 can prevent impurities in the substrate 10 from entering the multiple functional layers on the display substrate, thereby providing protection. For example, the barrier layer 1012 and the buffer layer 1013 can be made of one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0141] For example, such as Figure 29 As shown, the display substrate may further include a first gate insulating layer GI1 disposed on the side of the active layer 1021 away from the substrate 11, a second gate insulating layer GI2 disposed on the side of the gate electrode 1022 and the first capacitor electrode C1 away from the substrate 11, and an interlayer insulating layer IDL disposed on the side of the second capacitor electrode C2 away from the substrate 11. For example, the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer IDL may be one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0142] For example, such as Figure 29 As shown, a first insulating layer 11 is disposed on the side of the first source / drain electrode 1023 and the second source / drain electrode 1024 away from the substrate 11. The first insulating layer 11 can serve as a planarization layer to planarize the pixel driving circuit, thereby forming a relatively flat surface to facilitate the placement of the light-emitting device EM. For example, the display substrate may also include a second insulating layer 12 disposed on the side of the connecting electrode CEL away from the substrate 10. The second insulating layer 12 can also serve as a planarization layer to further planarize the pixel driving circuit and the connecting electrode CEL.

[0143] For example, the display substrate may further include a pixel defining layer PDL disposed on the side of the first electrode 1041 away from the substrate 10. The pixel defining layer PDL has a plurality of sub-pixel openings OP to expose the first electrode 1041 of a plurality of sub-pixels SP and to define the light-emitting areas of the plurality of sub-pixels SP. For example, the display substrate may further include a spacer layer PS disposed on the side of the pixel defining layer PDL away from the substrate 10. The spacer layer PS has a plurality of spacers to serve as support and isolation.

[0144] For example, the first insulating layer 11, the second insulating layer, and the spacer layer PS can be made of organic insulating materials such as resin and polyimide. The pixel defining layer PDL can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride; or, in other embodiments, the pixel defining layer PDL can also be made of organic insulating materials such as resin and polyimide.

[0145] For example, such as Figure 29 As shown, the display substrate may further include an encapsulation layer EN disposed on the side of the light-emitting device EM away from the substrate 10. The encapsulation layer EN may be a composite encapsulation layer, comprising a stack of an inorganic encapsulation layer EN1 and an organic encapsulation layer EN2. The inorganic encapsulation layer EN1 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The organic encapsulation layer EN2 may be made of organic insulating materials such as resin or polyimide.

[0146] For example, in embodiments of this disclosure, the substrate 10 can be a rigid substrate such as glass or quartz, or a flexible substrate such as polyimide or resin. The active layer 1021 of each transistor can be a semiconductor layer of various forms, such as an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide semiconductor layer. For example, the polycrystalline silicon can be high-temperature polycrystalline silicon or low-temperature polycrystalline silicon, and the oxide semiconductor can be indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), or gallium zinc oxide (GZO), etc.

[0147] For example, the gate 1022 of each transistor can be made of metal materials or alloy materials such as copper (Cu), aluminum (Al), and titanium (Ti), and can be formed as a single-layer metal layer structure or a multi-layer metal layer structure, such as a titanium / aluminum / titanium multi-layer metal layer structure. The source / drain electrodes 1023 / 1024 of each transistor can be made of metal materials or alloy materials such as copper (Cu), aluminum (Al), and titanium (Ti), and can be formed as a single-layer metal layer structure or a multi-layer metal layer structure, such as a titanium / aluminum / titanium multi-layer metal layer structure.

[0148] For example, the first electrode 1041 can be made of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and gallium zinc oxide (GZO), while the second electrode 1043 can be made of metals such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag). The embodiments of this disclosure do not specifically limit the materials used in each structure.

[0149] For example, the pixel driving circuit in this embodiment can be a pixel driving circuit of various forms such as 3T1C (i.e., including 3 transistors and 1 storage capacitor), 7T1C (i.e., including 7 transistors and 1 storage capacitor), 8T1C (i.e., including 8 transistors and 1 storage capacitor) or 8T2C (i.e., including 8 transistors and 2 storage capacitors). Figure 30 This is an equivalent circuit diagram of the 8T1C pixel driving circuit provided in at least one embodiment of the present disclosure. The connection relationship and function of the transistors and signal lines in the pixel driving circuit will be explained below using the 8T1C pixel driving circuit as an example.

[0150] For example, such as Figure 30 As shown, the pixel driving circuit may include eight transistors (first transistor T1 to eighth transistor T8), one storage capacitor C, and multiple signal lines (e.g., data line Da, first scan signal line Gate, second scan signal line GateN, reset control signal line Reset, first reset voltage line INIT1, second reset voltage line INIT2, second power supply line VDD, first power supply line VSS, and light emission control signal line Em, etc.).

[0151] For example, the gate of the first transistor T1 is connected to the reset control signal line Reset, the first terminal of the first transistor T1 is connected to the second reset voltage line INIT2, and the second terminal of the first transistor T1 is connected to the fifth node N5.

[0152] For example, the gate of the second transistor T2 is connected to the first scan signal line Gate, the first terminal of the second transistor T2 is connected to the fifth node N5, and the second terminal of the second transistor T2 is connected to the third node N3.

[0153] For example, the gate of the third transistor T3 is connected to the first node N1, the first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is connected to the third node N3.

[0154] For example, the gate of the fourth transistor T4 is connected to the first scan signal line Gate, the first terminal of the fourth transistor T4 is connected to the data line Da, and the second terminal of the fourth transistor T4 is connected to the second node N2.

[0155] For example, the gate of the fifth transistor T5 is connected to the light-emitting control signal line Em, the first terminal of the fifth transistor T5 is connected to the second power supply line VDD, and the second terminal of the fifth transistor T5 is connected to the second node N2.

[0156] For example, the gate of the sixth transistor T6 is connected to the light-emitting control signal line Em, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4 (i.e., the first electrode 1041 of the light-emitting device EM).

[0157] For example, the gate of the seventh transistor T7 is connected to the first scan signal line Gate or the reset control signal line Reset, the first terminal of the seventh transistor T7 is connected to the first reset voltage line INIT1, and the second terminal of the seventh transistor T7 is connected to the fourth node N4.

[0158] For example, the gate of the eighth transistor T8 is connected to the second scan signal line GateN, the first terminal of the eighth transistor T8 is connected to the fifth node N5, and the second terminal of the eighth transistor T8 is connected to the first node N1.

[0159] For example, the first capacitor electrode C1 of the storage capacitor C is connected to the second power line VDD, and the second capacitor electrode C2 of the storage capacitor C is connected to the first node N1.

[0160] For example, the first transistor T1 to the seventh transistor T7 can be N-type thin-film transistors, and the eighth transistor T8 can be a P-type thin-film transistor; or, the first transistor T1 to the seventh transistor T7 can be P-type thin-film transistors, and the eighth transistor T8 can be an N-type thin-film transistor.

[0161] For example, the first transistor T1 to the seventh transistor T7 can be low-temperature polysilicon (LTPS) thin film transistors (TFTs), and the eighth transistor T8 can be an indium gallium zinc oxide (IGZO) thin film transistor.

[0162] In the above embodiments, indium gallium zinc oxide (IGN) thin-film transistors (LTVs) generate less leakage current compared to low-temperature polycrystalline silicon (LTPS) thin-film transistors (LTPS). Therefore, setting the eighth transistor T8 as an IGNV can significantly reduce leakage current, thereby improving the low-frequency, low-brightness flicker problem of the display panel. Furthermore, the first transistor T1 and the second transistor T2 do not need to be IGNVs. Since the size of LTPS is generally smaller than that of IGNVs, the pixel driving circuit of this embodiment occupies less space, which is beneficial for improving the resolution of the display panel.

[0163] The pixel driving circuit provided in this embodiment combines the good switching characteristics of LTPS-TFT and the low leakage current characteristics of Oxide-TFT, enabling low-frequency driving (1Hz to 60Hz) and significantly reducing the power consumption of the display screen.

[0164] In some embodiments, the second electrode 1043 of the light-emitting device EM is connected to the first power line VSS. The signal of the first power line VSS is a continuously supplied low-level signal, and the signal of the second power line VDD is a continuously supplied high-level signal. The signal of the first scan signal line Gate is the scan signal in the pixel driving circuit of this display row, and the signal of the reset control signal line Reset is the scan signal in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line Gate is Gate(n), and the reset control signal line Reset is Gate(n-1). The signal of the reset control signal line Reset of this display row and the signal of the first scan signal line Gate in the pixel driving circuit of the previous display row can be the same signal to reduce the signal lines of the display panel and achieve a narrow bezel of the display panel.

[0165] For example, Figure 31 for Figure 30 The timing diagram of the pixel driving circuit in the image is shown. Figure 31 As shown, in some embodiments, the operation of the pixel driving circuit can be divided into the following stages.

[0166] In the first stage, t1, called the reset stage, the signals of the first scan signal line Gate, the reset control signal line Reset, the second scan signal line GateN, and the light emission control signal line Em are all high-level signals, while the signal of the reset control signal line Reset is low-level. The high-level signal of the light emission control signal line Em turns off the fifth transistor T5 and the sixth transistor T6. The high-level signal of the second scan signal line GateN turns on the eighth transistor T8. The low-level signal of the reset control signal line Reset turns on the first transistor T1. Therefore, the voltage of the first node N1 is reset to the second reset voltage Vinit2 provided by the second reset voltage line INIT2. Then, the voltage of the reset control signal line Reset goes high, and the first transistor T1 turns off. Since the fifth transistor T5 and the sixth transistor T6 are off, the light-emitting device EL does not emit light in this stage.

[0167] In the second stage, t2, known as the data writing stage, the first scan signal line Gate is at a low level. Transistors T4, T2, and T7 are turned on, and data line Da outputs a data voltage. The voltage at node N4 is reset to the first reset voltage Vinit1 provided by the first reset voltage line INIT1, completing initialization. During this stage, since node N1 is low, transistor T3 is turned on. The turn-on of transistors T4 and T2 allows the data voltage output from data line Da to be supplied to node N1 via the turned-on transistors T4, N2, T3, N3, T2, N5, and T8. The sum of the data voltage output from data line Da and the threshold voltage of transistor T3 is then charged into the storage capacitor C. The light-emitting control signal line Em is at a high level, and transistors T5 and T6 are turned off, ensuring that the light-emitting device EM does not emit light.

[0168] The third stage, t3, is called the light-emitting stage. During this stage, the first scan signal line (Gate) and the reset control signal line (Reset) are both high-level signals, while the light-emitting control signal line (EM) and the second scan signal line (GateN) are both low-level signals. The high-level signal on the reset control signal line (Reset) turns off the seventh transistor (T7), and the low-level signal on the light-emitting control signal line (Em) turns on the fifth transistor (T5) and the sixth transistor (T6). The power supply voltage output from the second power supply line (VDD) provides a driving voltage to the first electrode (i.e., the fourth node N4) of the light-emitting device (EM) through the turned-on fifth transistor (T5), third transistor (T3), and sixth transistor (T6), driving the EM to emit light.

[0169] For example, Figure 25 and Figure 26 In the embodiments, the reset voltage line Vint can be the first reset voltage line INIT1 and / or the second reset voltage line INIT2 mentioned above, in order to achieve the corresponding functions.

[0170] The following points also need to be explained:

[0171] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0172] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0173] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0174] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A display substrate having a plurality of sub-pixels arranged in a plurality of rows and a plurality of columns, and comprising: a substrate comprising a display area and a non-display area, wherein the plurality of sub-pixels are disposed in the display area, a plurality of data lines disposed on the substrate and at least in the display area, extending along a first direction, configured to provide data signals to the plurality of sub-pixels, and a plurality of first data line leads disposed on the substrate and extending from the display area to the non-display area along the first direction, wherein at least part of the plurality of data lines are respectively electrically connected to the plurality of first data line leads to obtain data signals from the non-display area, at least one of the plurality of first data line leads comprises a first lead portion and a second lead portion, the first lead portion is located in a first conductive layer, the second lead portion is located in a second conductive layer, and the first lead portion and the second lead portion are electrically connected by a via. In a direction parallel to the substrate, one or two first data line leads are disposed between two adjacent data lines. The second conductive layer is located on a side of the first conductive layer away from the substrate, and the plurality of data lines are located in the second conductive layer. The second conductive layer and the first conductive layer have a first insulating layer therebetween, the via comprises a first via and a second via penetrating through the first insulating layer, and two ends of the first lead portion are connected to the second lead portion through the first via and the second via respectively. For one first data line lead and one data line disposed adjacently, the first insulating layer further has a third via overlapping the data line in a direction perpendicular to the substrate, In the first direction, the third via is located between the first via and the second via. 2.The display substrate of claim 1, wherein, Two data lines and two first data line leads are disposed between two adjacent columns of sub-pixels, 3.The display substrate of claim 1, wherein, The two data lines are located between the two first data line leads, or 4.The display substrate of any one of claims 1-3, wherein, The two first data line leads are located between the two data lines. 5.The display substrate of claim 4, wherein, The two data lines are symmetrically arranged, and the third vias corresponding to the two data lines are symmetrically arranged. The two first data line leads are symmetrically arranged, and the first vias and the second vias corresponding to the two first data line leads are symmetrically arranged. 6.The display substrate of claim 5, wherein, Two data lines and two first data line leads are disposed between two adjacent columns of sub-pixels, and the two first data line leads are located between the two data lines; In the first direction, the first vias and the second vias corresponding to the two first data line leads are alternately arranged with intervals.

9. The display substrate of claim 6 or 8, further comprising: a second data line lead located in the first conductive layer and extending along a second direction different from the first direction, wherein at least one of the two first data line leads is connected to the second data line lead by a first transition line, the first transition line is located in the first conductive layer and at least partially overlaps the at least one first data line lead in a direction perpendicular to the substrate. 7.The display substrate of claim 6, wherein, ​ ​ 8.The display substrate of claim 4, wherein, ​ ​ ​ ​ ​ 10.The display substrate of claim 8, wherein, The second lead portions of the two first data line leads respectively comprise bending portions bent towards each other. 11.The display substrate of claim 4, wherein, Two data lines and two first data line leads are arranged between two adjacent columns of sub-pixels, and the two first data line leads are located between the two data lines. In the first direction, the first via and the second via corresponding to the two first data line leads are located on the same straight line.

12. The display substrate according to any one of claims 1-3, wherein, In a direction parallel to the substrate, two data lines are arranged between two adjacent columns of sub-pixels, and a first data line lead is arranged between the two data lines, The display substrate further comprises a second data line lead located in the first conductive layer and extending in a second direction different from the first direction, The first data line lead is connected to the second data line lead through a second adapter line, and the second adapter line is located in the first conductive layer and at least partially overlaps one of the two data lines in a direction perpendicular to the substrate.

13. The display substrate according to any one of claims 1-3, wherein, In a direction parallel to the substrate, two data lines are arranged between two adjacent columns of sub-pixels, and two first data line leads are arranged between the two data lines, or two first data line leads are arranged between two adjacent columns of sub-pixels, and two data lines are arranged between the two first data line leads, The display substrate further comprises a plurality of second data line leads located in the first conductive layer and extending in a second direction different from the first direction, A first data line of the two data lines is connected to a first second data line lead of the plurality of second data line leads, and the first second data line lead is connected to a first first data line lead spaced apart from the first data line by at least one sub-pixel; A second data line of the two data lines is connected to a second second data line lead of the plurality of second data line leads, and the second second data line lead is connected to a second first data line lead spaced apart from the second data line by at least one sub-pixel. 14.The display substrate of claim 13, wherein, The first data line of the two data lines is connected to the first second data line lead of the plurality of second data line leads through a third adapter line, and the first data line at least partially overlaps the third adapter line in a direction perpendicular to the substrate; The second data line of the two data lines is connected to the second second data line lead of the plurality of second data line leads through a fourth adapter line, and the second data line at least partially overlaps the fourth adapter line in a direction perpendicular to the substrate. 15.The display substrate of claim 13, wherein, The first data line of the two data lines is connected to the first second data line lead of the plurality of second data line leads through a third adapter line, and the third adapter line and the first data line lead adjacent to the first data line at least partially overlap in a direction perpendicular to the substrate; A second data line of the two data lines is connected to a second second data line lead of the plurality of second data line leads through a fourth transition line, the fourth transition line and a first data line lead adjacent to the second data line at least partially overlap in a direction perpendicular to the substrate. 16.The display substrate of claim 13, wherein, The first second data line lead is connected to a first first data line lead spaced apart from the first data line by at least one sub-pixel through a fifth transition line, the fifth transition line and a data line adjacent to the first first data line lead at least partially overlap in a direction perpendicular to the substrate. The second second data line lead is connected to a second first data line lead spaced apart from the second data line by at least one sub-pixel through a sixth transition line, the sixth transition line and a data line adjacent to the second first data line lead at least partially overlap in a direction perpendicular to the substrate. 17.The display substrate of claim 13, wherein, The first second data line lead is directly connected to the first first data line lead spaced apart from the first data line by at least one sub-pixel through a fourth via; The second second data line lead is directly connected to the second first data line lead spaced apart from the second data line by at least one sub-pixel through a fifth via. 18.The display substrate of claim 13, wherein, The first data line, the first second data line lead and the first first data line lead form a first data line network, The second data line, the second second data line lead and the second first data line lead form a second data line network, The second data line network is located at the periphery of the first data line network.

19. The display substrate of claim 18, wherein, Two first data line leads located between the two data lines include a disconnected portion disconnected from the first data line network and the second data line network, The display substrate further includes a first power line, and the disconnected portion connects the first power line. 20.The display substrate of claim 19, wherein, In a direction perpendicular to the substrate, the disconnected position overlaps the first conductive layer or the second conductive layer. 21.The display substrate of claim 19, wherein, Each of the plurality of sub-pixels includes a light emitting device and a pixel driving circuit driving the light emitting device, the light emitting device includes a first electrode connected to the pixel driving circuit, a second electrode spaced apart from the first electrode, and a light emitting layer between the first electrode and the second electrode, and the second electrode is electrically connected to the first power line. 22.The display substrate of claim 21, wherein, The pixel driving circuit includes a transistor including a gate and a source-drain electrode, and the source-drain electrode is electrically connected to the first electrode through a connection electrode, The source-drain electrode is located in the first conductive layer, and the connection electrode is located in the second conductive layer.

23. The display substrate of any one of claims 1-3, wherein, In a direction parallel to the substrate, two data lines are provided between adjacent first and second columns of sub-pixels, a reset voltage line is provided between the two data lines, and two first data line leads are provided between adjacent second and third columns of sub-pixels.

24. The display substrate of claim 23, wherein, The data line adjacent to the second column of sub-pixels and the first data line lead are electrically connected through a first second data line lead, and the data line adjacent to the first column of sub-pixels and the first data line lead adjacent to the third column of sub-pixels are electrically connected through a second second data line lead. 25.The display substrate of claim 24, wherein, Two second power lines are further arranged in the adjacent second column of sub-pixels and the third column of sub-pixels, and the two first data line leads are located between the two second power lines.

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