Power semiconductor device with external grid resistor

Abstract

The invention discloses a power semiconductor device with an external gate resistor, and relates to the field of semiconductor devices, the power semiconductor device with the external gate resistor comprises a semiconductor substrate, and a gate bus, a first gate connection region and a second gate connection region which are arranged on the front surface of the semiconductor substrate, the second gate connection region is electrically connected with a gate bus; and providing an external gate resistor, one end of the external gate resistor being electrically connected with the first gate connection region, and the other end of the external gate resistor being electrically connected with the second gate connection region. Through the structural design, the external chip resistor is used for replacing a traditional grid built-in resistor RGint made of polycrystalline silicon, the repeated tape-out verification period caused by the improper built-in resistor can be avoided, meanwhile, due to the flexibility of the external chip resistor, the grid resistance value requirements of different application scenes can be met, and the effects of reducing cost and increasing efficiency are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, and in particular to a power semiconductor device with an external gate resistor. BACKGROUND

[0002] The design direction of power discrete semiconductor devices such as MOSFET, IGBT, etc. is usually to reduce the switching loss as much as possible while ensuring the lowest on-state loss, thereby reducing the overall power consumption and improving system efficiency. However, in some application conditions, a gate resistor RGint needs to be integrated on the gate to suppress the oscillation of the gate signal caused by noise in the circuit, and the resistance value of the built-in resistor is usually several ohms.

[0003] If the gate built-in resistor placed during chip design is too small, it may have poor suppression effect on gate oscillation, leading to failure during operation, and if the resistance value is too large, it will cause the chip to turn on too slowly, resulting in increased loss; the ideal gate resistance value is determined by the resistance, capacitance, inductance in the system circuit, and the didt, dvdt, etc. parameters of the discrete device itself. Before the finished discrete chip is produced, it can only be roughly estimated according to theory and simulation, and there is a certain difference. Changing the chip peripheral resistance or changing the driving resistance often has differences in action compared to the built-in gate resistor, making it difficult to confirm the most suitable gate built-in resistor during the first flow.

[0004] Figure 1 The appearance of a conventional MOSFET is shown, which is provided with a gate (Gate) and a source (Source) packaging bonding area on the surface, Figure 2 The chip internal gate trace is shown, and the current mainstream approach is to make a built-in resistor in the gate area of the chip through a polysilicon area during the initial engineering batch flow stage, as shown in Figure 3 As shown, the resistance value of the built-in resistor can be changed by changing the length and width of the polysilicon, as shown in Figure 4 The Gate packaging bonding area is connected to the built-in resistor by punching. This method needs to further adjust the resistance value after the flow production according to the application test results, and it may need to flow multiple times to confirm the most suitable resistance value, resulting in a longer product design cycle.

[0005] The conventional built-in resistor improvement scheme usually adjusts the gate resistance RGint of the overall chip by controlling the number of parallel built-in resistors, Figure 5The application principle diagram of the conventional built-in resistance improvement scheme (taking an IGBT device as an example) is shown, but the number of built-in resistors is limited, so the adjustment range of the overall RGint is limited in a fixed range. In order to adapt to different application needs, Rgout needs to be externally set, and a stray inductance (Lg) is included between Rgout and RGint. When the circuit has crosstalk, oscillation is usually caused inside Lg, Ccg and RGint, and increasing Rgout cannot effectively suppress it. At the same time, small built-in resistors (R1, R2 and R3) need to be connected through packaging wires on a small area, which has high requirements for the wire bonding, increases the packaging difficulty, and has low practicability. SUMMARY

[0006] The present inventors propose a power semiconductor device with an external gate resistor to solve the above problems and meet the technical needs, and the technical scheme of the present application is as follows: A power semiconductor device with an external gate resistor, comprising a semiconductor substrate and a gate bus, a first gate connection area and a second gate connection area arranged on the front surface of the semiconductor substrate, wherein the second gate connection area is electrically connected with the gate bus. An external gate resistor is provided, one end of which is electrically connected with the first gate connection area, and the other end of which is electrically connected with the second gate connection area.

[0007] Further, the second gate connection area is arranged above the gate bus, the gate bus is etched with a contact hole, the contact hole is filled with a connecting metal, and the second gate connection area is electrically connected with the gate bus through the connecting metal.

[0008] Further, the area of the second gate connection area is larger than that of the first gate connection area, and the second gate connection area is etched with a hollow area matched with the first gate connection area, the first gate connection area is arranged in the hollow area, and there is a gap between the first gate connection area and the second gate connection area.

[0009] Further, the first gate connection area and the second gate connection area are rectangular.

[0010] Further, a first gate pad is welded on the first gate connection area, and a second gate pad is welded on the second gate connection area.

[0011] Further, the two ends of the external gate resistor are connected with the first gate pad and the second gate pad through bonding wires, respectively.

[0012] Further, the material of the first gate connection area, the second gate connection area, the first gate pad, the second gate pad and the bonding wire includes copper.

[0013] Further, the first gate pad and the second gate pad have the same shape and are symmetrically distributed on the semiconductor substrate.

[0014] Further, the active area of the semiconductor substrate includes a plurality of semiconductor cells arranged side by side, and the gate bus is connected with the gate polysilicon in the semiconductor cell.

[0015] Further, the material of the gate bus includes polysilicon.

[0016] The present application has the following beneficial technical effects: The present application uses an external patch resistor to replace the traditional gate built-in resistor RGint made of polysilicon, which can avoid repeated flow verification period caused by improper built-in resistor, and can adapt to the gate resistance value requirement of different application scenarios due to the flexibility of the external patch resistor, thereby achieving the effect of cost reduction and efficiency improvement. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is the appearance diagram of the conventional power semiconductor device provided by the present application.

[0018] Figure 2 is the schematic diagram of the chip internal gate trace of the conventional power semiconductor device provided by the present application.

[0019] Figure 3 is the schematic diagram of the conventional built-in gate resistor provided by the present application.

[0020] Figure 4 is the schematic diagram of the connection mode between the conventional built-in gate resistor and the gate packaging bonding area provided by the present application.

[0021] Figure 5 is the application principle diagram of the conventional built-in resistor improvement scheme provided by the present application.

[0022] Figure 6 is the layout schematic diagram of the power semiconductor device with external gate resistor provided by the present application.

[0023] Figure 7 is the pad schematic diagram of the power semiconductor device with external gate resistor provided by the present application.

[0024] Figure 8 is the application principle diagram of the power semiconductor device with external gate resistor provided by the present application.

[0025] REFERENCE NUMERALS: 1-first gate connection area, 2-second gate connection area, 3-horizontal part, 4-vertical part, 5-bent part, 6-contact hole, 7-first gate pad, 8-second gate pad, 9-external gate resistance, 10-bonding wire, 11-first source pad, 12-second source pad. DETAILED DESCRIPTION

[0026] The specific embodiments of the present application will be further described below with reference to the accompanying drawings. It can be understood that the specific embodiments described herein are only used to explain the related content, and are not a limitation on the present disclosure.

[0027] The present application discloses a kind of external gate resistance power semiconductor devices, including semiconductor substrate and the gate bus of the front of semiconductor substrate, first gate connection area 1 And second gate connection area 2, wherein, the second gate connection area 2 is electrically connected with gate bus;Provide external gate resistance, one end of the external gate resistance is electrically connected with first gate connection area 1, the other end of the external gate resistance is electrically connected with second gate connection area 2, so that the built-in resistance made of conventional polysilicon can be removed, the effect of using external gate resistance instead of built-in resistance is realized, i.e. The working time of multiple flow piece verification can be shortened to the working time of one round of packaging test verification, the research and development cycle is greatly shortened, by flexibly configuring the resistance value of external gate resistance, different resistance values can be adapted according to different application scenarios, and the flexibility of application is improved.

[0028] Specifically, the first gate connection area 1 and the second connection area 2 are both metal layers deposited on the semiconductor substrate, wherein the second gate connection area 2 is arranged above the gate bus, the gate bus is etched with a contact hole 6, the contact hole 6 is filled with connecting metal, and the second gate connection area 2 is electrically connected with the gate bus through the connecting metal.

[0029] In a possible implementation manner, as shown in Figure 6 The first gate connection area 1 and the second gate connection area 2 are rectangular, the area of the second gate connection area 2 is greater than the area of the first gate connection area 1, and the second gate connection area 2 is etched with a hollow area matched with the first gate connection 1, the first gate connection area 1 is arranged in the hollow area, and there is a gap between the first gate connection area 1 and the second gate connection area 2 to realize the physical separation of the first gate connection area 1 and the second gate connection area 2. The shape design of the above-mentioned first gate connection area 1 and the second gate connection area 2 can ensure that the second gate connection area 2 has a larger area to contact with the connecting metal, so as to effectively guide the flow and facilitate process preparation. In specific implementation, the first gate connection area 1 and the second gate connection area 2 can be prepared by etching a metal layer as a whole through etching process.

[0030] The material of the gate bus line includes polysilicon, and those skilled in the art can know that the active region of the semiconductor substrate includes a plurality of semiconductor cells arranged in parallel, and the gate bus line is connected with the gate polysilicon in the semiconductor cell. In the embodiment, the gate bus line includes a horizontal part 3 and three vertical parts 4 parallel to each other above the horizontal part, the first and second vertical parts 4 are respectively connected perpendicularly to the two ends of the horizontal part 3, and the middle of the horizontal part 3 includes a rectangularly upwardly bent bending part 5, the contact hole 6 is arranged in the bending part 5, and the strip-shaped contact hole is formed by extending the bending part. The third vertical part 4 is arranged in parallel between the first vertical part 4 and the second vertical part 4 and is connected with the bending part 5, and the first vertical part 4 and the second vertical part 4 are symmetrical about the third vertical part. In specific implementation, the structure shape of the gate bus line and the structure shape of the first gate connection area 1 and the second gate connection area 2 can be designed according to actual conditions.

[0031] Further, the first gate connection area 1 is welded with a first gate pad 7, and the second gate connection area 2 is welded with a second gate pad 8. As shown in Figure 7 When the power semiconductor device is packaged, the two ends of the external gate resistor 9 (such as a patch resistor) are respectively connected with the first gate pad 7 and the second gate pad 8 through the bonding wire 10, so that the device is connected with the external gate resistor 9. The external gate resistor 9 can be placed near the first gate pad 7 and the second gate pad 8, and the length of the bonding wire 10 needs to be shortened as much as possible to avoid introducing more stray inductance.

[0032] The materials of the first gate connection area 1, the second gate connection area 2, the first gate pad 7, the second gate pad 8 and the bonding wire 10 include copper. The first gate pad 7 and the second gate pad 8 can have the same shape and be symmetrically distributed on the semiconductor substrate, and in the embodiment, the first gate pad 7 and the second gate pad 8 are rectangular. The first source pad 11 and the second source pad 12 are further arranged above the first gate pad 7 and the second gate pad 8, and in the embodiment, the first source pad 11 and the second source pad 12 have the same shape and are symmetrically distributed on the semiconductor substrate.

[0033] Figure 8This diagram illustrates an application principle of an embodiment of the power semiconductor device with an external gate resistor (taking an IGBT device as an example) provided by the present invention. The IGBT device, together with the power supply Vcc, inductor Lc, and diode, forms a test circuit. Inductors Ls1, Ls2, and Lg all represent circuit noise inductance, and resistor R is the external gate resistor 9. Vin represents the driving voltage. Compared with conventional improvements using built-in resistors in the prior art, the external gate resistor 9 in this application offers more flexible and convenient resistance adjustment, fundamentally avoiding multiple fabrication cycles caused by incompatibility with built-in gate resistors. Furthermore, the external gate resistor 9 has no upper or lower limit for adjustment, thus eliminating the need for external resistors and replacing Rgout. Simultaneously, the external gate resistor 9 is located within the crosstalk circuit, and increasing the resistance R effectively suppresses oscillations caused by crosstalk. Moreover, compared to conventional improvements using built-in resistors, the power semiconductor device with an external gate resistor provided by the present invention has less impact on packaging process difficulty and possesses good practicality.

[0034] In the description of this specification, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0035] The use of terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., refers to a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example, which is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0036] In the description of this application, if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0037] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0038] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A power semiconductor device with an external gate resistor, characterized by The semiconductor substrate and a gate bus, a first gate connecting area and a second gate connecting area arranged on the front surface of the semiconductor substrate, wherein the second gate connecting area is electrically connected with the gate bus; An external gate resistor is provided, one end of the external gate resistor is electrically connected with the first gate connecting area, and the other end of the external gate resistor is electrically connected with the second gate connecting area.

2. The power semiconductor device of claim 1, wherein The second gate connecting area is arranged above the gate bus, the gate bus is etched with a contact hole, the contact hole is filled with a connecting metal, and the second gate connecting area is electrically connected with the gate bus through the connecting metal.

3. The power semiconductor device of claim 1, wherein The area of the second gate connecting area is larger than that of the first gate connecting area, and the second gate connecting area is etched with a hollow area matched with the first gate connecting area, the first gate connecting area is arranged in the hollow area, and a gap exists between the first gate connecting area and the second gate connecting area.

4. The power semiconductor device of claim 3, wherein The first gate connecting area and the second gate connecting area are rectangular.

5. The power semiconductor device of claim 1, wherein A first gate pad is welded on the first gate connecting area, and a second gate pad is welded on the second gate connecting area.

6. The power semiconductor device of claim 4, wherein The two ends of the external gate resistor are respectively connected with the first gate pad and the second gate pad through bonding wires.

7. The power semiconductor device of claim 6, wherein The materials of the first gate connecting area, the second gate connecting area, the first gate pad, the second gate pad and the bonding wires include copper.

8. The power semiconductor device of claim 5, wherein The first gate pad and the second gate pad are of the same shape and symmetrically distributed on the semiconductor substrate.

9. The power semiconductor device of claim 1, wherein The active area of the semiconductor substrate includes a plurality of semiconductor cells arranged in parallel, and the gate bus is connected with gate polysilicon in the semiconductor cells.

10. The power semiconductor device of claim 1, wherein The material of the gate bus includes polysilicon.

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