Three-dimensional integrated structure and preparation method thereof

Abstract

The invention relates to a three-dimensional integrated structure and a preparation method thereof. The three-dimensional integrated structure comprises an intermediate layer, an insulating layer, a conductive filling layer, at least four chips, a buffer isolation layer, a first rewiring layer, a second rewiring layer, at least two front deep grooves, at least two back deep grooves and at least two through holes, through holes exist between the front deep grooves and the back deep grooves which are opposite in position, the insulating layers cover the surfaces of the front deep grooves, the back deep grooves and the through holes and the front face and the back face of the intermediate layer, the conductive filling layers are located in the through holes, the chips are located in the front deep grooves and the back deep grooves respectively, and conductive protruding parts of the chips are bonded with the conductive filling layers. The first redistribution layer covers one side of the front surface of the interposer, and the second redistribution layer covers one side of the back surface of the interposer. According to the technical scheme, the intermediate layer does not need to be thinned, the process steps can be reduced, the silicon material can be fully utilized, and the problems of warping and deformation of the intermediate layer cannot occur.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit packaging, in particular to a three-dimensional integrated structure and a preparation method thereof. BACKGROUND

[0002] In the related art, with the rapid development of integrated circuit technology, microelectronic packaging technology has gradually become a main factor restricting the development of semiconductor technology. In order to realize the high density of electronic packaging, obtain superior performance and lower overall cost, a series of advanced packaging technologies have been developed by technical personnel.

[0003] Among them, the three-dimensional system-in-package technology has good electrical performance and high reliability, and can realize high packaging density, and is applied to dynamic random access memory (DRAM) chip systems. The through silicon via (TSV) interposer technology is a new technology for realizing interconnection of stacked chips in three-dimensional integrated circuits, which realizes electrical interconnection between different chips by making many vertical interconnection holes and subsequent redistribution layers (RDL) on a silicon wafer. The TSV interposer technology can maximize the density of DRAM chips stacked in the three-dimensional direction, minimize the interconnection lines between chips, and minimize the size of the chip, and greatly improve the performance of chip storage density, speed and low power consumption. It is currently the most eye-catching technology in electronic packaging technology.

[0004] However, in order to meet the requirements of the overall thickness of the package, the silicon wafer is usually thinned first, then the TSV structure is made, and finally the chips are stacked in the vertical direction. The silicon wafer thinning undoubtedly increases the process complexity, and then causes waste of silicon material, and finally is prone to warping and deformation problems. SUMMARY

[0005] The technical problem solved by the present application is to provide a three-dimensional integrated structure and a preparation method thereof, which can reduce the process steps without thinning the interposer, make full use of silicon material, and the interposer will not have warping and deformation problems.

[0006] According to a first aspect of an embodiment of the present application, a three-dimensional integrated structure is provided, comprising: an interposer, the interposer comprising a front surface and a back surface, the front surface and the back surface being opposite to each other; the interposer being a silicon wafer; at least two front surface deep grooves located side by side on the front surface of the interposer; at least two back surface deep grooves located side by side on the back surface of the interposer; the at least two back surface deep grooves and the at least two front surface deep grooves are one-to-one corresponding in position; at least two through holes, each pair of positionally opposite front surface deep grooves and back surface deep grooves having one through hole therebetween; an insulating layer covering surfaces of the front-side deep trenches, surfaces of the back-side deep trenches, a surface of the through hole, a front surface of the interposer, and a back surface of the interposer; a conductive filling layer in the through hole, wrapped by the insulating layer on the surface of the through hole; at least four chips in the at least two front-side deep trenches and the at least two back-side deep trenches respectively, each of the chips being provided with a conductive bump on a first side facing the conductive filling layer, and a conductive part on a second side facing away from the conductive filling layer, the conductive bump being bonded with the conductive filling layer; a buffer isolation layer filling gaps between the chips and the insulating layer, and gaps between the chips and the conductive filling layer; on either side of the front surface and the back surface of the interposer, surfaces of the insulating layer, surfaces of the buffer isolation layer, and surfaces of the chips are substantially aligned; a first redistribution layer covering the insulating layer, the buffer isolation layer, and the chips on one side of the front surface of the interposer, and electrically connected with the conductive part of the chips; a second redistribution layer covering the insulating layer, the buffer isolation layer, and the chips on one side of the back surface of the interposer, and electrically connected with the conductive part of the chips.

[0007] In an embodiment, the material of the conductive filling layer is graphene.

[0008] In an embodiment, the chips are DRAM chips.

[0009] In an embodiment, the material of the insulating layer is SiO2, Si3N4, SiOCH, or SiOCFH.

[0010] In an embodiment, the material of the buffer isolation layer is epoxy resin.

[0011] According to a second aspect of the embodiments of the present application, a preparation method of a three-dimensional integrated structure is provided, for preparing the three-dimensional integrated structure described above, the method comprising: forming the at least two front-side deep trenches and the at least two back-side deep trenches on the interposer; forming the through hole between each pair of positionally opposite front-side deep trenches and back-side deep trenches; forming the insulating layer on surfaces of the front-side deep trenches, surfaces of the back-side deep trenches, a surface of the through hole, a front surface of the interposer, and a back surface of the interposer; forming the conductive filling layer in the insulating layer on the surface of the through hole; bonding the chip with the conductive filling layer; filling the buffer isolation layer in the gap between the chip and the insulating layer and the gap between the chip and the conductive filling layer; forming the first redistribution layer on one side of the front surface of the interposer and forming the second redistribution layer on one side of the back surface of the interposer.

[0012] In an embodiment, the forming the via between each pair of positionally opposite front deep trench and back deep trench comprises: forming a first photoresist layer in the front deep trench and defining the position of the via on the first photoresist layer by using a photoetching process; etching the interposer between each pair of positionally opposite front deep trench and back deep trench according to the position of the via by using an etching process to form the via; removing the first photoresist layer.

[0013] In an embodiment, the forming the conductive filling layer in the insulating layer on the surface of the via comprises: covering the surface of the insulating layer with conductive material and filling the conductive material in the front deep trench, the back deep trench and the via until the front deep trench, the back deep trench and the via are closed to obtain a conductive layer; etching the conductive layer until the conductive layer in the front deep trench and the back deep trench is etched away and the conductive layer in the via is retained to obtain the conductive filling layer.

[0014] In an embodiment, the etching the conductive layer until the conductive layer in the front deep trench and the back deep trench is etched away and the conductive layer in the via is retained to obtain the conductive filling layer comprises: forming a second photoresist layer on the conductive layer on one side of the front surface of the interposer and defining the position of the via on the second photoresist layer by using a photoetching process; etching the conductive layer in each pair of positionally opposite front deep trench and back deep trench according to the position of the via by using an etching process until the conductive layer in the front deep trench and the back deep trench is etched away and the conductive layer in the via is retained to obtain the conductive filling layer; removing the second photoresist layer.

[0015] In an embodiment, the material of the conductive filling layer is graphene and the material of the conductive protruding part is copper. The bonding the chip with the conductive filling layer comprises: The conductive protrusions are bonded to the conductive filler layer within a specified temperature range, which is 400~500℃.

[0016] Compared with the prior art, the beneficial effects of this application are as follows: by etching opposite deep trenches on the front and back sides of the interposer, setting vias between the opposite deep trenches on the front and back sides, forming conductive filling layers in the vias, placing the chips in the deep trenches on the front and back sides respectively, and bonding the conductive bumps of the chips to the conductive filling layers, electrical connections between the chips are achieved. In this way, there is no need to thin the interposer, and the total package thickness will not increase, which can meet the requirements of the total package thickness. It can reduce the number of process steps and make full use of silicon materials. Moreover, since the interposer is not thinned, the interposer will not have warping or deformation problems, and the deep trenches can also protect the chips from external impacts.

[0017] Through-holes are etched between the front and back deep trenches, which are positioned opposite each other. Graphene is directly filled inside the through-holes to electrically connect the two chips in the front and back deep trenches in the vertical direction. On the one hand, the high electrical conductivity and high thermal conductivity of graphene can be used to increase signal transmission speed and heat dissipation efficiency. On the other hand, the advantage of graphene's non-diffusion properties can be taken advantage of, eliminating the need for an additional diffusion barrier layer like copper interconnects, thereby reducing process complexity. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a three-dimensional integrated structure according to an exemplary embodiment.

[0019] Figure 2 This is a flowchart illustrating a method for fabricating a three-dimensional integrated structure according to an exemplary embodiment.

[0020] Figure 3 This is a schematic diagram of the intermediate structure prepared in step S201.

[0021] Figure 4 This is a flowchart illustrating a method for preparing a three-dimensional integrated structure according to another exemplary embodiment.

[0022] Figure 5 This is a schematic diagram of the intermediate structure prepared in step S2023.

[0023] Figure 6 This is a schematic diagram of the intermediate structure prepared in step S203.

[0024] Figure 7 This is a flowchart illustrating a method for preparing a three-dimensional integrated structure according to another exemplary embodiment.

[0025] Figure 8This is a schematic diagram of the intermediate structure prepared in step S2041.

[0026] Figure 9 This is a flowchart illustrating a method for preparing a three-dimensional integrated structure according to another exemplary embodiment.

[0027] Figure 10 This is a schematic diagram of the intermediate structure prepared in step S423.

[0028] Figure 11 This is a schematic diagram of the intermediate structure prepared in step S205.

[0029] Figure 12 This is a schematic diagram of the intermediate structure prepared in step S206. Detailed Implementation

[0030] Unless otherwise defined, the technical or scientific terms used in this specification and claims shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. Specific embodiments of this application will be described below in conjunction with the accompanying drawings. It should be noted that, in order to provide a concise description, this specification cannot exhaustively describe all features of the actual embodiments. Without departing from the spirit and scope of this application, those skilled in the art can modify and substitute the embodiments of this application, and the resulting embodiments are also within the protection scope of this application.

[0031] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0032] One embodiment of this application provides a three-dimensional integrated structure. Please refer to... Figure 1 The three-dimensional integrated structure may include an interposer layer 100, an insulating layer 101, a conductive filling layer 102, at least four chips 103, a buffer isolation layer 105, a first rewiring layer 106, a second rewiring layer 107, a front deep trench 108, a back deep trench 109, and at least two vias 110.

[0033] In one embodiment, the interposer 100 includes a front side F and a back side B, with the front side F of the interposer 100 and the back side B of the interposer 100 facing each other. The interposer 100 may be a silicon wafer, and the material of the silicon wafer may be monocrystalline silicon, but is not limited thereto.

[0034] like Figure 1 As shown, at least two front deep grooves 108 are located side by side on the front F of the intermediary layer 100, and at least two back deep grooves 109 are located side by side on the back B of the intermediary layer 100. Figure 1Only two front deep grooves 108 and two back deep grooves 109 are shown in the figure. In fact, the front F of the interposer layer 100 may not be limited to two front deep grooves 108, and the back B of the interposer layer 100 may not be limited to two back deep grooves 109.

[0035] like Figure 1 As shown, at least two reverse deep grooves 109 correspond one-to-one with at least two front deep grooves 108. That is, one reverse deep groove 109 is opposite to one front deep groove 108.

[0036] like Figure 1 As shown, there is a through-hole 110 between each pair of oppositely positioned front deep trenches 108 and back deep trenches 109. This through-hole 110 can be a through-silicon via (TSV).

[0037] like Figure 1 As shown, the insulating layer 101 covers the surface of the front deep groove 108, the surface of the back deep groove 109, the surface of the through hole 110, the front side of the interposer 100, and the back side of the interposer 100.

[0038] In one embodiment, the insulating layer 101 may be made of SiO2. In other embodiments, the insulating layer 101 may be made of Si3N4, or a low dielectric constant material, such as SiOCH or SiOCFH.

[0039] like Figure 1 As shown, the conductive filling layer 102 is located in the through hole 110 and is wrapped by the insulating layer 101 on the surface of the through hole 110.

[0040] In one embodiment, the conductive filling layer 102 is made of graphene. On the one hand, the high electrical conductivity and high thermal conductivity of graphene can be used to increase signal transmission speed and heat dissipation efficiency. On the other hand, the advantage of graphene's poor diffusion can be utilized, eliminating the need for an additional diffusion barrier layer on the insulating layer 101 as required for copper interconnects (when the conductive filling layer 102 is made of copper), thereby reducing process complexity.

[0041] like Figure 1 As shown, at least four chips 103 are located in at least two front deep grooves 108 and at least two back deep grooves 109, respectively. Figure 1 Only four chips 103 are shown. The four chips 103 are located in two front deep grooves 108 and two back deep grooves 109, respectively.

[0042] like Figure 1As shown, each chip 103 has a conductive protrusion 104 on its first side facing the conductive filling layer 102. The conductive protrusion 104 is bonded to the conductive filling layer 102, thereby interconnecting the two oppositely arranged chips 103 in the vertical direction. Each chip 103 has a conductive portion (not shown) on its second side facing away from the conductive filling layer 102, for electrical connection with the redistribution layer, thereby achieving interconnection in the horizontal direction.

[0043] In one embodiment, the aforementioned at least four chips 103 may be DRAM chips.

[0044] like Figure 1 As shown, the buffer isolation layer 105 fills the gap between the chip 103 and the insulating layer 101, as well as the gap between the chip 103 and the conductive filling layer 102, and plays a role in buffering and isolation.

[0045] In one embodiment, the material of the buffer isolation layer 105 may be epoxy resin, but is not limited thereto.

[0046] like Figure 1 As shown, on either the front or back side of the interposer 100, the surface of the insulating layer 101, the surface of the buffer isolation layer 105, and the surface of the chip 103 are substantially aligned, which facilitates the laying of the redistribution layer.

[0047] like Figure 1 As shown, the first redistribution layer 106 covers the insulating layer 101, the buffer isolation layer 105 and the chip 103 located on one side of the front side of the interposer layer 100, and is electrically connected to the conductive part of the chip 103 to interconnect at least two chips 103 located on one side of the front side of the interposer layer 100.

[0048] like Figure 1 As shown, the second redistribution layer 107 covers the insulating layer 101, the buffer isolation layer 105 and the chip 103 located on the opposite side of the interposer layer 100, and is electrically connected to the conductive part of the chip 103 to interconnect at least two chips 103 located on the opposite side of the interposer layer 100.

[0049] In this application, electrical connections between chips 103 are achieved by etching opposing deep trenches 108 and 109 on the front and back sides of the interposer 100, forming conductive filling layers 102 in the through-holes 110, placing chips 103 in the front and back deep trenches 108 and 109 respectively, and bonding the conductive protrusions of chips 103 to the conductive filling layers 102. In this way, there is no need to thin the interposer 100, and the total package thickness will not increase, which can meet the requirements of the total package thickness. It can reduce the number of process steps and make full use of silicon material. Moreover, since the interposer 100 is not thinned, the interposer 100 will not have warping or deformation problems, and the deep trenches can also protect the chips 103 from external impacts.

[0050] A via 110 is etched between the front deep trench 108 and the back deep trench 109, which are positioned opposite each other. At the same time, graphene is directly filled inside the via 110 to electrically connect the two chips 103 in the front deep trench 108 and the back deep trench 109 in the vertical direction. On the one hand, the advantages of graphene's high electrical conductivity and high thermal conductivity can be used to increase the signal transmission speed and heat dissipation efficiency. On the other hand, the advantage of graphene's non-diffusion properties can be used to reduce the complexity of the process, as there is no need to add an additional diffusion barrier layer like copper interconnects.

[0051] Another embodiment of this application provides a method for fabricating a three-dimensional integrated structure. Please refer to [link to relevant documentation]. Figure 2 The method for fabricating this three-dimensional integrated structure may include the following steps S201 to S207: Step S201: Form at least two front deep grooves and at least two back deep grooves on the intermediary layer.

[0052] In this step, such as Figure 3 As shown, photoresist can be spin-coated onto the front and back sides of the interposer 100 to form a third photoresist layer. The positions of the front deep trench 108 and the back deep trench 109 are then defined on the third photoresist layer using an exposure and development process (photolithography). Based on the positions of the front deep trench 108 and the back deep trench 109, a reactive ion etching process can be used to etch the front deep trench 108 and the back deep trench 109, resulting in the desired outcome. Figure 3 The intermediate structure shown.

[0053] The reactive plasma for etching the interposer 100 can be at least one of CF4 and SF6. For example, CF4, SF6, or both CF4 and SF6 can be selected.

[0054] In other embodiments, dry etching or wet etching can also be used to etch, resulting in a front deep groove 108 and a back deep groove 109. Dry etching processes can be, for example, ion milling, plasma etching, or laser ablation.

[0055] Step S202: A through hole is formed between each pair of oppositely positioned front and back deep grooves.

[0056] In this step, such as Figure 4 As shown, step S202 may include the following steps S2021 to S2023: Step S2021: A first photoresist layer is formed in the front deep trench, and the position of the via is defined on the first photoresist layer using photolithography.

[0057] In this step, photoresist can be spin-coated in the front deep trench 108 to form a first photoresist layer, and the position of the via 110 can be defined on the first photoresist layer using photolithography (exposure and development).

[0058] Step S2022: Based on the location of the via, an etching process is used to etch the interlayer between each pair of opposite front and back deep trenches to form a via.

[0059] In this step, depending on the position of the through hole 110, an etching process can be used to etch the intermediary layer 100 between each pair of opposite front deep trenches 108 and back deep trenches 109 until the intermediary layer 100 is penetrated to form the through hole 110.

[0060] The etching process can be deep reactive ion etching (DRIE), and the plasma used to etch the interposer 100 can be at least one of CF4 and SF6. For example, CF4 can be selected, SF6 can be selected, or both CF4 and SF6 can be selected.

[0061] In other embodiments, dry etching or wet etching can also be used to obtain the through hole 110. Dry etching processes can include, for example, ion milling, plasma etching, reactive ion etching, or laser ablation.

[0062] Step S2023: Remove the first photoresist layer.

[0063] In this step, the first photoresist layer can be removed by dissolving it in a solvent or by ashing, to obtain the desired result. Figure 5 The intermediate structure shown.

[0064] Step S203: An insulating layer is formed on the surface of the front deep groove, the surface of the back deep groove, the surface of the through hole, the front side of the interlayer, and the back side of the interlayer.

[0065] In this step, an insulating layer 101 can be deposited on the surface of the front deep trench 108, the surface of the back deep trench 109, the surface of the through hole 110, the front side of the interposer 100, and the back side of the interposer 100 using a chemical vapor deposition process, to obtain the following: Figure 6 The intermediate structure shown.

[0066] Step S204: A conductive filling layer is formed in the insulating layer on the surface of the through hole.

[0067] In this step, such as Figure 7 As shown, step S204 may include the following steps S2041 to S2042: Step S2041: Cover the surface of the insulating layer with conductive material, and fill the front deep groove, back deep groove and through hole with conductive material until the front deep groove, back deep groove and through hole are closed to obtain a conductive layer.

[0068] In this embodiment, the conductive material is graphene.

[0069] In this step, such as Figure 8 As shown, a layer of graphene material can be grown on the surface of the insulating layer 101 using a chemical vapor deposition process. The graphene material is then filled into the front deep trench 108, the back deep trench 109, and the through-hole 110 until the front deep trench 108, the back deep trench 109, and the through-hole 110 are closed, forming a conductive layer 801, thus obtaining the desired result. Figure 8 The intermediate structure shown.

[0070] Step S2042: Etch the conductive layer until the conductive layer in the front deep trench and the back deep trench is etched away, leaving the conductive layer in the through hole, to obtain a conductive filling layer.

[0071] In this step, such as Figure 9 As shown, step S2042 may include the following steps S421 to S423: Step S421: A second photoresist layer is formed on the conductive layer on the front side of the interposer, and the location of the via is defined on the second photoresist layer using a photolithography process.

[0072] In this step, photoresist can be spin-coated onto the conductive layer 801 on the front side F of the interposer 100 to form a second photoresist layer, and the position of the via 110 can be defined on the second photoresist layer using photolithography (exposure and development).

[0073] Step S422: Based on the location of the via, an etching process is used to etch the conductive layer in each pair of opposite front and back deep trenches until the conductive layer in the front and back deep trenches is etched away, leaving the conductive layer in the via to obtain a conductive filling layer.

[0074] In this step, based on the position of the through hole 110, an etching process can be used to etch the conductive layer in each pair of opposite front deep trenches 108 and back deep trenches 109 until the conductive layer in the front deep trenches 108 and back deep trenches 109 is etched away, leaving only the conductive layer in the through hole 110, thus obtaining the conductive filling layer 102.

[0075] In this embodiment, the etching process can be reactive ion etching, and the plasma used to etch the conductive layer (graphene) can be at least one of O2 and N2O. For example, O2, N2O, or both O2 and N2O can be selected.

[0076] In other embodiments, dry etching or wet etching can also be used to obtain the via 110. Dry etching processes can include, for example, ion milling, plasma etching, deep reactive ion etching, or laser ablation.

[0077] Step S423: Remove the second photoresist layer.

[0078] In this step, the second photoresist layer can be removed by dissolving it in a solvent or by ashing, to obtain the desired result. Figure 10 The intermediate structure shown.

[0079] Step S205: Place at least four chips in at least two front deep trenches and at least two back deep trenches respectively, and bond the chips to the conductive filling layer.

[0080] In this step, at least four chips 103 are placed in at least two front deep trenches 108 and at least two back deep trenches 109, respectively. The conductive protrusions of the chips 103 are in contact with the conductive filling layer 102. Then, the chips 103 and the conductive filling layer 102 are bonded together to obtain the following result: Figure 11 The intermediate structure shown.

[0081] In one embodiment, the conductive filler layer 102 is made of graphene, and the conductive protrusions are made of copper. The conductive protrusions and the conductive filler layer 102 can be bonded within a specified temperature range, wherein the specified temperature range is 400~500℃. For example, the conductive protrusions and the conductive filler layer 102 can be bonded within a temperature environment of 400℃, 450℃, or 500℃.

[0082] Step S206: Fill the gap between the chip and the insulating layer and the gap between the chip and the conductive filling layer with a buffer isolation layer.

[0083] In this step, such as Figure 12As shown, epoxy resin is filled into the gaps between the chip 103 and the insulating layer 101 in the front deep trench 108 and the back deep trench 109, as well as the gap between the chip 103 and the conductive filling layer 102, to form a buffer isolation layer 105, resulting in the following: Figure 12 The intermediate structure shown.

[0084] In step S207, a first routing layer is formed on one side of the front of the interposer layer, and a second routing layer is formed on one side of the back of the interposer layer.

[0085] In this step, a first redistribution layer 106 is formed on one side of the front face of the interposer layer 100, and a second redistribution layer 107 is formed on one side of the back face of the interposer layer 100, resulting in the following: Figure 1 The three-dimensional integrated structure shown.

[0086] The first wiring layer 106 enables the chip 103 on the front side of the interposer 100 to be electrically connected in the horizontal direction, and the second wiring layer 107 enables the chip 103 on the back side of the interposer 100 to be electrically connected in the horizontal direction.

[0087] In this application, electrical connections between chips 103 are achieved by etching opposing deep trenches 108 and 109 on the front and back sides of the interposer 100, forming conductive filling layers 102 in the through-holes 110, placing chips 103 in the front and back deep trenches 108 and 109 respectively, and bonding the conductive protrusions of chips 103 to the conductive filling layers 102. In this way, there is no need to thin the interposer 100, and the total package thickness will not increase, which can meet the requirements of the total package thickness. It can reduce the number of process steps and make full use of silicon material. Moreover, since the interposer 100 is not thinned, the interposer 100 will not have warping or deformation problems, and the deep trenches can also protect the chips 103 from external impacts.

[0088] A via 110 is etched between the front deep trench 108 and the back deep trench 109, which are positioned opposite each other. At the same time, graphene is directly filled inside the via 110 to electrically connect the two chips 103 in the front deep trench 108 and the back deep trench 109 in the vertical direction. On the one hand, the advantages of graphene's high electrical conductivity and high thermal conductivity can be used to increase the signal transmission speed and heat dissipation efficiency. On the other hand, the advantage of graphene's non-diffusion properties can be used to reduce the complexity of the process, as there is no need to add an additional diffusion barrier layer like copper interconnects.

[0089] The method and apparatus embodiments of this application can complement each other.

[0090] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0091] The above description of the embodiments is intended to enable those skilled in the art to understand and apply this application. It will be apparent to those skilled in the art that various modifications can be easily made to these embodiments, and the general principles described herein can be applied to other embodiments without creative effort. Therefore, this application is not limited to the embodiments described herein, and any improvements and modifications made by those skilled in the art based on the disclosure of this application without departing from the scope and spirit of this application are within the scope of this application.

Claims

1. A three-dimensional integrated structure, characterized by, The application relates to a three-dimensional integrated structure, comprising: an interposer, the interposer comprising a front surface and a back surface, the front surface and the back surface being opposite to each other; the interposer being a silicon wafer; at least two front surface deep grooves being arranged side by side on the front surface of the interposer; at least two back surface deep grooves being arranged side by side on the back surface of the interposer; the at least two back surface deep grooves corresponding to the at least two front surface deep grooves in position one by one; at least two through holes, one through hole being arranged between each pair of positionally opposite front surface deep grooves and back surface deep grooves; an insulating layer covering the surfaces of the front surface deep grooves, the surfaces of the back surface deep grooves, the surfaces of the through holes, the front surface of the interposer and the back surface of the interposer; a conductive filling layer being arranged in the through holes and being wrapped by the insulating layer on the surfaces of the through holes; at least four chips being arranged in the at least two front surface deep grooves and the at least two back surface deep grooves respectively, each chip being provided with a conductive protruding part on a first side facing the conductive filling layer, the conductive protruding part being bonded with the conductive filling layer, and being provided with a conductive part on a second side facing away from the conductive filling layer; a buffer isolation layer being filled in the gaps between the chips and the insulating layer and the gaps between the chips and the conductive filling layer; on any one side of the front surface and the back surface of the interposer, the surface of the insulating layer, the surface of the buffer isolation layer and the surface of the chip are substantially aligned; a first rewiring layer covering the insulating layer, the buffer isolation layer and the chip on one side of the front surface of the interposer and being electrically connected with the conductive part of the chip; and a second rewiring layer covering the insulating layer, the buffer isolation layer and the chip on one side of the back surface of the interposer and being electrically connected with the conductive part of the chip. The material of the conductive filling layer is graphene. The chip is a DRAM chip. The material of the insulating layer is SiO2, Si3N4, SiOCH or SiOCFH. The material of the buffer isolation layer is epoxy resin. The application further relates to a method for manufacturing the three-dimensional integrated structure, comprising: forming the at least two front surface deep grooves and the at least two back surface deep grooves on the interposer; forming the through holes between each pair of positionally opposite front surface deep grooves and back surface deep grooves; forming the insulating layer on the surfaces of the front surface deep grooves, the surfaces of the back surface deep grooves, the surfaces of the through holes, the front surface of the interposer and the back surface of the interposer; forming the conductive filling layer in the insulating layer on the surfaces of the through holes; arranging the at least four chips in the at least two front surface deep grooves and the at least two back surface deep grooves respectively and bonding the chips with the conductive filling layer; filling the buffer isolation layer in the gaps between the chips and the insulating layer and the gaps between the chips and the conductive filling layer; and forming the first rewiring layer on one side of the front surface of the interposer and forming the second rewiring layer on one side of the back surface of the interposer. The method further comprises: forming the at least two front surface deep grooves and the at least two back surface deep grooves on the interposer; forming the through holes between each pair of positionally opposite front surface deep grooves and back surface deep grooves, comprising: ​ ​ ​ ​ 2. The three-dimensional integrated structure of claim 1, wherein, ​ 3. The three-dimensional integrated structure of claim 1, wherein, ​ 4. The three-dimensional integrated structure of claim 1, wherein, ​ 5. The three-dimensional integrated structure of claim 1, wherein, ​ 6. A method of manufacturing a three-dimensional integrated structure, characterized by, ​ ​ ​ ​ ​ ​ ​ ​ 7. The method of producing a three-dimensional integrated structure according to Claim 6, wherein ​ Forming a first photoresist layer in the front deep groove, and defining the position of the via on the first photoresist layer by using a photoetching process; According to the position of the via, etching the interlayer between the front deep groove and the back deep groove opposite to each other by using an etching process to form the via; Removing the first photoresist layer.

8. The method of producing a three-dimensional integrated structure according to Claim 6, wherein The forming of the conductive filling layer in the insulating layer on the surface of the via includes: Covering the surface of the insulating layer with conductive material, and filling the conductive material in the front deep groove, the back deep groove and the via until the front deep groove, the back deep groove and the via are closed to obtain a conductive layer; Etching the conductive layer until the conductive layer in the front deep groove and the back deep groove is etched away, and the conductive layer in the via is reserved to obtain the conductive filling layer.

9. The method of producing a three-dimensional integrated structure according to Claim 8, wherein The etching of the conductive layer until the conductive layer in the front deep groove and the back deep groove is etched away, and the conductive layer in the via is reserved to obtain the conductive filling layer includes: Forming a second photoresist layer on the conductive layer on the front side of the interlayer, and defining the position of the via on the second photoresist layer by using a photoetching process; According to the position of the via, etching the conductive layer in the front deep groove and the back deep groove opposite to each other by using an etching process until the conductive layer in the front deep groove and the back deep groove is etched away, and the conductive layer in the via is reserved to obtain the conductive filling layer; Removing the second photoresist layer.

10. The method of producing a three-dimensional integrated structure according to Claim 6, wherein The material of the conductive filling layer is graphene, and the material of the conductive protruding part is copper; The bonding of the chip and the conductive filling layer includes: Bonding the conductive protruding part and the conductive filling layer in a specified temperature range, and the specified temperature range is 400-500℃.

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