System and method for testing automobile safety system error correction code (ECC) logic failure

Abstract

An error correction code (ECC) testing system and method is provided that preferably tests for failures of ECC logic prior to workload being processed upon power up. If the ECC logic does not pass the test, an interrupt indicating that the ECC logic has a fault is preferably issued, and the corresponding ECC fault feature is reported in the state register of the system as part of the integrated system report.

Description

[0001] Related technical descriptions

[0002] Computing devices and their components can experience operational failures, potentially leading to unintended results. In some types of computing devices, such as those used in safety-critical systems for autonomous vehicles, unexpected failures can result in dangerous situations for the driver or others. One of the key foundations of autonomous driving systems is their ability to continue operating even when Advanced Driver Assistance Systems (ADAS) or Autonomous Driving Systems (ADS) detect electrical / electronic (E / E) faults or other software failures. The Electronic Control Unit (ECU) is the heart of an ADAS / ADS system. It integrates vast amounts of environmental information from various sensors, such as stereo cameras, radar, and others, to process complex and computationally intensive tasks—tasks crucial for ensuring system availability—while continuously detecting and managing various faults in mission modes.

[0003] Error-correcting codes (ECCs) are widely used as a safety mechanism to detect and correct bit errors in the memory of ADAS / ADS systems. ECC checksum generation and checking are performed by digital test logic, which itself can be susceptible to random failures. If any such random failure (permanent or transient) occurs in this logic, it may produce false memory errors or fail to detect actual memory errors. If such errors occur in mission mode, they can lead to system failure, which is highly undesirable for safety-critical systems such as autonomous driving systems in vehicles.

[0004] The system needs to detect any faults in the digital test logic before executing the actual workload (i.e., during power-up). Summary of the Invention

[0005] Systems, methods, and other examples for testing ECC logic used to detect bit errors in storage devices are disclosed. A representative implementation of the ECC testing system includes fault injection logic and fault determination logic. The fault injection logic is configured to inject a first pre-selected test bit pattern into the ECC logic for processing by an ECC checksum generator logic to generate a first ECC checksum stored in a first ECC memory of the first storage device. The fault injection logic is further configured to retrieve the first ECC checksum from the first ECC memory, modify the retrieved first ECC checksum in a predetermined manner, and cause the modified first ECC checksum to be processed by ECC checker logic to generate a first fault feature recorded by an ECC recorder. The fault determination logic is configured to receive the recorded first fault feature from the ECC recorder and compare the recorded first fault feature with expected fault features to determine whether the recorded first fault feature matches the expected fault features.

[0006] Representative implementations of this method include: The fault injection logic is used to inject a first preselected test bit pattern into the ECC logic and transmit it to the ECC checksum generator logic of the ECC logic. The ECC checksum generator logic processes the injected first preselected test bit pattern to generate a first ECC checksum stored in the first ECC memory of the first storage device. The fault injection logic retrieves a first ECC checksum from a first ECC memory, modifies the first ECC checksum in a predetermined manner, and transmits the modified first ECC checksum to ECC checker logic. This ECC checker logic receives and processes the modified first ECC checksum to generate a first fault characteristic recorded by an ECC recorder. The fault determination logic compares the recorded first fault feature with the expected fault feature to determine whether the recorded first fault feature matches the expected fault feature.

[0007] A representative implementation of a computer program for testing ECC logic includes a first set of computer instructions, a second set of computer instructions, a third set of computer instructions, and a fourth set of computer instructions embodied on a non-transitory computer-readable medium. The first set of computer instructions causes fault injection logic to inject a first pre-selected test bit pattern into the ECC logic. The second set of computer instructions causes the fault injection logic to transmit the first pre-selected test bit pattern to ECC checksum generator logic of the ECC logic, which processes the first pre-selected test bit pattern to generate a first ECC checksum stored in a first ECC memory of a first storage device. The third set of computer instructions causes the fault injection logic to retrieve the first ECC checksum from the first ECC memory, modify the first ECC checksum in a predetermined manner, and transmit the modified first ECC checksum to ECC checker logic, which processes the modified first ECC checksum to generate a first fault feature recorded by an ECC recorder. The fourth set of computer instructions causes fault determination logic to compare the recorded first fault feature with expected fault features to determine whether the recorded first fault feature matches the expected fault feature.

[0008] Another representative implementation of an ECC testing system includes: A component for injecting a pre-selected test bit pattern into the ECC logic for processing by the ECC check generator logic to generate an ECC checksum stored in the first ECC memory of the first storage device. Components used to retrieve ECC checksums from the first ECC memory; A component used to modify the retrieved ECC checksum in a predetermined manner; A component for transmitting the modified ECC checksum to the ECC checker logic for processing to generate fault characteristics recorded by the ECC recorder; and A component for receiving recorded fault characteristics from an ECC recorder and for comparing the recorded fault characteristics with expected fault characteristics to determine whether the recorded fault characteristics match the expected fault characteristics.

[0009] These and other features and advantages will become apparent from the following description, drawings and claims. Attached Figure Description

[0010] In the accompanying drawings, unless otherwise indicated, similar reference numerals are used throughout the various views to refer to similar parts. For reference numerals with letter character names, such as "101a" or "101b", the letter character names distinguish two similar parts or elements present in the same figure. When the aim is to have the reference numerals cover all parts with the same reference numerals in all figures, the letter character names of the reference numerals may be omitted.

[0011] Figure 1 A block diagram illustrating an example ADAS / ADS system is provided, which includes ECC logic for performing ECC checker generation and checks.

[0012] Figure 2 A block diagram of a system for testing ECC logic for detecting bit errors in a storage device, according to an exemplary embodiment, is illustrated.

[0013] Figure 3 Examples Figure 2 The block diagram of the fault injection state machine of the system shown illustrates a representative implementation of the ECC checker logic and the ECC test logic, which is integrated with the ECC test logic of this disclosure for testing the ECC test logic.

[0014] Figure 4 This is a flowchart of a method for testing ECC logic based on a representative implementation scheme.

[0015] Figure 5 This is a flowchart of a method according to a preferred embodiment, wherein Figure 2 and Figure 3 The state machine control shown is used to test the ECC logic.

[0016] Figure 6Examples of PCDs are illustrated, such as mobile phones, smartphones, portable game consoles (such as extended reality (XR) devices, virtual reality (VR) devices, augmented reality (AR) devices, or mixed reality (MR) devices, servers, etc.), in which exemplary embodiments of systems and methods according to the principles and concepts of the present invention can be implemented.

[0017] Figure 7 An example is illustrated of a system including components of a vehicle autonomous driving system according to a representative implementation scheme, wherein the following can be employed: Figure 1 The system and GPU shown. Detailed Implementation

[0018] As indicated above, ECC checksum generation and checking are used to detect and correct bit faults in the storage devices of ADAS / ADS systems. ECC checksum generation and checking are performed by the ECC checker logic, which itself can be affected by random faults. If any such random fault (permanent or transient) occurs in this logic, it may produce false memory errors or miss actual memory errors. If such errors occur in mission mode, they can lead to system failure, which is highly undesirable for safety-critical systems such as autonomous driving systems in vehicles.

[0019] Based on the inventive principles and concepts of this disclosure, a testing system and method are provided, which preferably tests for faults in ECC checker logic upon power-up and before the workload is processed. If the ECC checker logic fails the test, an interrupt signal is preferably generated that indicates a fault in the ECC checker logic to the system, and the corresponding ECC fault characteristics are reported in the system's status register as part of a comprehensive system report.

[0020] In the following detailed description, exemplary or representative embodiments with specific details disclosed are set forth for purposes of explanation and not limitation, in order to provide a thorough understanding of embodiments according to this teaching. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” The word “representative” is used herein synonymously with “exemplary.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects. However, it will be apparent to those skilled in the art who benefit from this disclosure that other embodiments according to this teaching, departing from the specific details disclosed herein, still remain within the scope of the appended claims. Furthermore, descriptions of well-known apparatuses and methods may be omitted so as not to obscure the description of exemplary embodiments. Such methods and apparatus are clearly within the scope of this teaching.

[0021] The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting. The defined terms are supplementary to their technical and scientific meanings as generally understood and accepted in the technical field of this teaching content.

[0022] Unless the context clearly indicates otherwise, the terms “a,” “an,” and “the” as used in the specification and appended claims include both singular and plural references. Thus, for example, “an apparatus” includes one apparatus and multiple apparatuses.

[0023] Relative terms are used to describe the relationships between individual elements, as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, these relative terms are intended to cover different orientations of the equipment and / or elements.

[0024] It should be understood that when an element is described as being "connected to," "coupled to," or "electrically coupled to" another element, the element may be directly connected or coupled, or there may be intermediate elements present.

[0025] As used herein, the terms "memory" or "memory device" are intended to refer to a non-transitory, computer-readable storage medium capable of storing computer instructions or computer code for execution by one or more processors. References to "memory" or "memory device" herein should be interpreted as one or more memories or memory devices. For example, memory may refer to multiple memories within the same computer system. Memory may also refer to multiple memories distributed across multiple computer systems or computing devices.

[0026] The term "processor" (as used herein) encompasses an electronic component capable of executing computer programs or computer instructions. References to systems including "processor" herein should be interpreted as one or more processors. A processor may, for example, be a multi-core processor comprising multiple processing cores, each of which may include multiple processing stages in a processing pipeline. A processor may also refer to a collection of processors within a single computer system or distributed across multiple computer systems.

[0027] Computing devices may include multiple subsystems, cores, or other components. Such computing devices may be, for example, PCDs, such as laptops or handheld computers, cellular or smartphones, portable digital assistants, portable game consoles, automotive safety systems for autonomous vehicles, server chips, etc.

[0028] Figure 1 A block diagram illustrating an example ADAS / ADS system 100 is provided, which includes ECC logic for performing ECC checksum generation and checking. Figure 1 In the example shown, system 100 does not include the ECC test logic of this disclosure. The following will describe... Figure 1This example demonstrates how the current ECC logic performs ECC checksum generation and checking. In this exemplary system 100, the ECC logic is implemented in the graphics processing unit (GPU) 101 of the SoC 102. The ECC logic 104 is integrated into the storage devices 1031-103 of the GPU 101. N In each storage device, N is a positive integer greater than or equal to one. ECC logic 104 includes ECC checksum generation logic 105 and ECC checker logic 106. Storage devices 1031-103 N Each memory address in each storage device includes data memory 107 and ECC memory 108 that are co-located or contiguous with each other. For ease of illustration, Figure 1 The diagram shows a single data memory 107 and an associated ECC memory 108.

[0029] System 100's Application Processor Subsystem (APSS) 109 communicates with Functional Safety Control and Status Register Logic (FuSA Logic) 111, which is configured to operate according to the International Organization for Standardization (ISO) 26262 standard. FuSA Logic 111 is configured to initiate an ECC test by asserting one or more bits in its registers, causing FuSA Logic 111 to generate a write enable signal, a write address signal, and a write data signal to allow data to be written to storage devices 1031-103. N A specific address is specified in one of them. This allows the ECC checksum to be generated by the ECC checksum generation logic 105 and written to the ECC memory 108. Data is written to the data memory 107. The ECC checksum generation logic 105 processes the data bits according to a predefined ECC algorithm to generate an ECC checksum or checksum, and then stores the ECC checksum or checksum in the ECC memory 108.

[0030] FUSA logic 111 is then followed by the same storage devices 1031-103 that were just written to. NA read enable signal is generated at the same address in the memory. ECC checker logic 106 reads data and ECC checksums from data memory 107 and ECC memory 108, respectively. ECC checker logic 106 processes the data bits to generate an ECC checksum according to the same predefined ECC algorithm used by ECC checksum generation logic 105, and then compares this ECC checksum with the ECC checksum read from ECC memory 108 to determine if they match. If they do not match, it indicates that the data read from that memory location has one or more bit errors. In this case, ECC checker logic 106 records the association between the error and the memory location where the error occurred in ECC recorder 112. This recorded information is accessible by system 100 and can be used by system 100 as a security mechanism to detect and correct errors from storage devices 1031-103. N There is a bit error in the data being read.

[0031] References above Figure 1 In the example of the described ECC logic and method, data memory 107 and ECC memory 108 are configured for inline ECC, meaning that data memory 107 and ECC memory 108 are co-located in the same storage device. In other words, the actual data and the associated ECC code are stored together in a block of contiguous memory. A sideband ECC configuration can also be used, where the actual data and ECC code are stored in different storage devices. The inventive principles and concepts of this disclosure apply to both types of configurations. For ease of discussion and illustration, this document will assume that the inventive principles and concepts used for testing ECC logic are applied to an inline ECC logic configuration, although the inventive principles and concepts are equally applicable to a sideband ECC configuration.

[0032] As indicated above, a system and methods are needed to test the ECC logic to determine whether it operates properly. References will now be made. Figures 2 to 7 To describe the logic used for testing ECC (such as Figure 1 Exemplary or representative implementations of the system and method shown in ECC logic 104).

[0033] Figure 2 A block diagram of a system 200 according to an exemplary implementation for testing ECC logic is shown. For ease of illustration and discussion, it is assumed that system 200 is used for testing. Figure 1The ECC logic 104 shown is illustrated, but the principles and concepts of the invention are not limited to testing this particular ECC logic configuration. According to this exemplary embodiment, system 200 is implemented in GPU 201 of SoC 202. However, it should be noted that system 200 can be implemented in any processor or in any system using memory that stores bits that can become faulty or corrupted, such as a central processing unit (CPU), neural processing unit (NPU), digital signal processor (DSP), etc.

[0034] According to this implementation scheme, the ECC testing system disclosed herein includes storage devices 2031-203 connected to GPU 201. N The fault injection logic 210 is integrated into the ECC logic 104 in each storage device, and into storage devices 2031-203. N External fault injection and evaluation state machine 220. See below for reference. Figure 3 In detail, fault injection logic 210 and ECC logic 104 can be integrated into storage devices 2031 to 203. N In the memory package. As used herein, the term "memory package" refers to each storage device 2031-203 N The memory bank integrates fault injection logic 210 and part of ECC checker logic 104.

[0035] According to this embodiment, APSS 204 of system 200 is configured to communicate with FuSA logic 205 configured to operate according to ISO 26262, although the inventive principles and concepts of this disclosure are not limited to system 200 conforming to ISO 26262 or any other standard. Preferably, FuSA logic 205 is configured by APSS 204 such that an ECC test system including logic 210 and state machine 220 of this disclosure performs tests on ECC logic 104 during runtime prior to the execution of the workload.

[0036] According to a representative implementation, APSS 204 initiates the test by asserting one or more bits in the register of FuSa logic 205 to assert the Fault_Injection_Enable signal 212. The asserted Fault_Injection_Enable signal 212 is received by ECC logic 104, injection logic 210, and state machine 220. Upon power-up, state machine 220 enters an idle state and remains in the idle state until it receives the asserted Fault_Injection_Enable signal 212 from FuSa logic 205. Receiving the asserted Fault_Injection_Enable signal causes state machine 220 to enter a WRITE TO MEMORY state. In this state, state machine 220 generates a write enable signal, a write address signal, and a write data signal to write or inject the preselected test bit pattern into storage devices 2031-203. N A specific address within one of them. (See the reference above.) Figure 1 As described, this enables the ECC checksum of ECC logic 104 to generate logic 105 ( Figure 1 The preselected test bit pattern is processed to generate an ECC checksum, which is then written to the ECC memory 108 at a specific memory address in the ECC logic 104. Figure 1 This also causes the pre-selected test bit pattern to be written into the data memory 107 at a specific memory address in the ECC logic 104 (). Figure 1 ).

[0037] State machine 220 then enters the "GENERATE READ" state, in which the state machine is for the same storage device 2031-203 that was just written to. N The same address in the data memory generates a read enable signal. The fault injection logic 210 of this disclosure includes modification logic that modifies the test bit pattern read from the data memory 107 in a predetermined manner to simulate a fault. ECC logic 104 includes ECC checker logic 106 (…). Figure 1 The modified test bit pattern is then processed to generate an ECC code, which is compared with the ECC code read from the ECC memory 108, and a fault feature is output, which is recorded in the ECC recorder 112.

[0038] State machine 220 then enters the "GET LOG DATA" state, in which it obtains fault characteristics from ECC recorder 112. When ECC recorder 112 records a fault characteristic, an interrupt is issued by the ECC recorder, causing state machine 220 to obtain the recorded fault characteristics, exit the "GET LOG DATA" state, and enter the "COMPARE" state. In the "COMPARE" state, the state machine compares the recorded fault characteristics with expected fault characteristics. State machine 220 is pre-configured with intelligence that notifies it of expected fault characteristics. If the recorded fault characteristics match the expected fault characteristics, state machine 220 re-enters the "Write to Memory" state and writes to the next address in memory, reads that memory address in the "Read from Memory" state, obtains the corresponding recorded fault characteristics in the "GET LOG DATA" state, and compares them with the expected fault characteristics in the "COMPARE" state. This process is repeated until all storage devices 2031-203 are accessed. N All addresses have been written to, read from, and checked. If no fault is detected in the "compare" state at the end of the entire process, this notifies System 200 that ECC logic 104 is functioning correctly.

[0039] If state machine 220 determines in the "COMPARE" state that the recorded fault characteristics do not match the expected fault characteristics, state machine 220 enters the "Catch Fault" state. In this state, it adds the erroneous fault characteristics to the ECC fault characteristic register of FuSa logic 205 and issues a GPU_ECC_Fault_IRQ interrupt signal 213. This signal indicates the specific storage devices 2031-203 to system 200 and possibly to systems outside system 200. N The ECC logic 104 malfunctioned, and the interrupt that was just issued was cleared. Then state machine 220 re-entered the "write to memory" state and repeated the process until all storage devices 2031-203... N All addresses have been written to, read from, and checked.

[0040] Figure 3 The following is illustrated based on a representative implementation scheme. Figure 2 The block diagram of system 200 shown includes fault injection logic 210 comprising selection logics 210a and 210b, a portion of the control selection logics 210a and 210b of state machine 220, and bit modification logic 210c. According to this representative embodiment, selection logics 210a and 210b respectively include a first multiplexer (MUX) and a second MUX, and bit modification logic 210c includes an inverter. For illustrative purposes, Figure 1 The ECC logic 105-108 shown is in Figure 3 As shown, however, it should be understood that the principles and concepts of the present invention are not limited to testing ECC logic with that particular ECC logic configuration.

[0041] When the Fault_Injection_Enable signal 212 output by FuSa logic 205 remains unasserted, MUX 210a selects logic 0 input FUNC_CTRL as the output of MUX 210a. This ensures that ECC checker generator logic 105 and checker logic 106 are as described above. Figure 1 The described normal operating procedure is used to check the storage device 2031-203. N Bit errors in the data bits of the memory. When the Fault_Injection_Enable signal 212 remains unasserted, the fault injection and evaluation state machine 220 remains in an "idle" state. While state machine 220 remains in an "idle" state, FuSa logic 205 bypasses state machine 220 and is coupled to the logic 0 input of MUX 210a. APSS 204 enables FuSa logic 205 to write to and read from memory devices 2031-203. N The address can be used to initiate normal ECC checksum generation and checker operations by the FuSa logic 205 to check the accuracy of bits stored in memory addresses (such as in data memory element 107). The APSS 204 can also enable normal memory write and read operations to write to and read from data memory element 107.

[0042] During the normal operation of ECC checker logic 105 and ECC checker logic 106 when state machine 220 is in the "idle" state, ECC checker logic 105 uses error correction codes, combined with data output from MUX 210a, to generate an ECC checksum stored in ECC memory element 108. Because the Fault_Injection_Enable signal is deasserted at this time, logic 0 input of MUX 210b is selected as output of MUX 210b, which causes the values ​​stored in data memory 107 and ECC memory 108 to be transferred to ECC checker logic 106 without modification. ECC checker logic 106 is referenced above. Figure 1 These values ​​are processed in a manner described to determine whether the data stored in data memory 107 contains one or more bit errors. This information is then transmitted to ECC recorder 112, which records the information and outputs the ECC-recorded entry to FuSa logic 205.

[0043] When the Fault_Injection_Enable signal 212 output by FuSa logic 205 is asserted to test ECC checksum generator logic 105 and checker logic 106, MUX 210a selects logic 1 input FI_CTRL as the output of MUX 210a, and MUX 210b selects logic 1 input. During the "Write to Memory" state of fault injection state machine 220, ECC checksum generator logic 105 receives the preselected test bit pattern output by MUX 210a and processes it as described above to generate a predefined checksum stored in ECC memory 108.

[0044] When the state machine enters the "Read Memory" state, the values ​​stored in data memory 107 and ECC memory 108 are read and inverted by inverter 210c, and then transmitted to ECC checker logic 106. Because the values ​​are inverted, ECC checker logic 106 generates a fault characteristic, which is recorded by ECC logger 112 and transmitted by ECC logger 112 to fault injection state machine 220, which is now in the "Get Log Data" state. State machine 220 then enters the "Compare" state. This process is then referred to above. Figure 2 The description continues until all storage devices 2031-2032 are included. N All addresses have been checked. Any detected fault is captured, reported, and a GPU_ECC_FAULT_IRQ interrupt 213 is issued in the "Catch Fault" state. For each reported fault, the report will typically include fault characteristics, storage device identifier, memory address location, and fault type (e.g., unit error or multi-bit error). State machine 220 includes fault determination logic that performs steps associated with the "Read Memory," "Get Log Data," "Compare," and "Catch Fault" states, all of which involve obtaining the fault characteristics of the record, evaluating the characteristics of the record, and taking one or more actions based on the evaluation.

[0045] Figure 4 This is a flowchart illustrating a method 400 for testing ECC logic according to a representative implementation, wherein the ECC logic 104 includes... Figure 1 and Figure 3The diagram shows ECC checksum generator logic 105 and ECC checker logic 106, but this method can also be used to test ECC logic with other configurations. Box 401 illustrates the step of injecting a pre-selected test bit pattern into ECC logic 104 using fault injection logic. Box 402 illustrates the step of using selection logic to transfer the injected test bit pattern to ECC checksum generator logic 105. ECC checksum generator logic 105 processes the injected test bit pattern to generate an ECC checksum, which is stored in a first ECC memory of a first storage device implementing the ECC logic.

[0046] Box 403 represents the steps of retrieving an ECC checksum from a first ECC memory element using selection logic (MUX 210b and inverter 210c), modifying the ECC checksum in a predefined manner (inverter 210c), and transmitting the modified ECC checksum to ECC checker logic 106. ECC checker logic 106 receives the modified ECC checksum and processes it as described above to generate fault characteristics recorded by the ECC recorder. Box 404 represents the steps of comparing the recorded fault characteristics with expected fault characteristics using fault determination logic (the "compare" state of state machine 220) to determine whether the recorded fault characteristics match the expected fault characteristics.

[0047] Depend on Figure 4 The flowchart representation of the process is preferably for each storage device 2031-203 of system 200. N Each memory address is used for execution. Furthermore, if any fault is detected at box 404, it is preferable to log the fault, generate or update a report to identify the fault, and issue an interrupt. If the step represented by box 404 is at storage device 2031-203 of system 200... N If no fault is detected in any of the ECC logics of system 200, then preferably, the processor (e.g., GPU 201) of system 200 can begin processing the workload. Since this process is preferably performed when processor 201 is powered on, there is currently no workload queued for GPU 201 to process.

[0048] Figure 5 This is a flowchart of method 500 according to the preferred embodiment, wherein state machine 220 is referenced above. Figure 2 and 3The described method controls the testing of the ECC logic. When system 200 is powered on, state machine 220 enters and remains in an "idle" state until the Fault_Injection_Enable signal 212 is asserted. This occurs when one or more preselected bits in one of the registers of FuSa logic 205 are asserted. When this occurs, the fault injection logic of fault injection and evaluation state machine 220 changes from the "idle" state to the "write to memory" state and transmits the preselected test bit pattern and the address to be tested in memory to ECC logic 105-108. Selection logic 210a receives the fault injection enable signal 212 and the preselected test bit pattern and transmits the preselected test bit pattern to ECC checker generator logic 105. These steps are performed by... Figure 5 The flowchart is represented by box 501.

[0049] Box 502 indicates that the fault injection and evaluation state machine 220 changes from a "write to memory" state to a "read from memory" state, and selection logic and modification logic 210b and 210c respectively cause the ECC checksum and test bit pattern to be read from ECC memory 108 and data memory 107, modified (e.g., reversed), and transmitted to ECC checker logic 106. This ECC checker logic processes the modified ECC checksum and test bit pattern to generate a checksum, compares the checksum with the checksum stored in ECC memory 108 to generate a fault feature, and causes the fault feature to be recorded by ECC logger 112. Box 503 indicates that the fault determination logic of the fault injection and evaluation state machine 220 changes from a "read from memory" state to a "get log data" state, and causes the recorded fault feature to be received by the fault determination logic of the fault injection and evaluation state machine 220.

[0050] Box 504 indicates that the fault determination logic of state machine 220 changes from the "acquire log data" state to the "compare" state, and compares the recorded fault characteristics with the expected fault characteristics to determine whether the recorded fault characteristics match the expected fault characteristics. Box 505 indicates the process by which the fault determination logic of state machine 220 determines whether these characteristics match. Box 506 indicates the process by which state machine 220 changes from the "compare" state to the "catch fault" state if, during the "compare" state, the fault determination logic determines at box 505 that the recorded fault characteristics do not match the expected fault characteristics. During the "catch fault" state, the fault determination logic of state machine 220 preferably generates an interrupt and generates or updates a report in FuSa logic 105 to indicate that a fault has been detected in the ECC checker logic. The process then proceeds to box 507.

[0051] Box 507 indicates the process by which state machine 220 determines whether all memory addresses of all storage devices have been tested. If not, the next memory address to be tested is obtained at box 508 (e.g., the memory address pointer is incremented), and then the process returns to box 501. If it is determined at box 507 that all memory addresses of all storage devices have been tested, the process proceeds to box 509, where it is determined whether any faults were detected at box 505. If not, the process proceeds to box 510, where the processor can begin processing the workload. Otherwise, the process proceeds to box 511, and the workload is not processed during task mode due to a fault in the ECC logic.

[0052] It should be noted that it is possible to Figure 5 The process represented by the flowchart undergoes numerous additions, deletions, and other modifications. Modifications to the ECC checksum made by the selection logic can be performed in different ways. Preferably, the logic 1 inputs of inverter 210c and the second MUX 210b perform this modification by inverting the ECC checksum read from ECC memory 108. This relatively low-complexity, low-cost logic configuration for modifying the ECC checksum can be implemented in a very small area of ​​SoC 202, but other logic configurations can also be used for this purpose. The fault determination logic of state machine 220 only needs to know how the ECC checksum will be modified so that it knows what the expected fault characteristics will be.

[0053] Figure 6 Examples of PCD 600 are illustrated, such as mobile phones, smartphones, portable game consoles (such as extended reality (XR) devices, virtual reality (VR) devices, augmented reality (AR) devices, or mixed reality (MR) devices, servers, etc.), in which exemplary embodiments of systems and methods according to the principles and concepts of the present invention can be implemented. PCD 600 includes Figure 2 and Figure 3 The SoC 202 shown includes... Figure 2 and Figure 3 The system 200 and GPU 201 are shown. For clarity, Figure 6 Some interconnects, signals, etc. are not shown.

[0054] SoC 202 may also include, for example, a CPU 604, an NPU 605, a DSP 607, an analog signal processor 608, a modem / modem subsystem 654, or other processors. CPU 604 may include one or more CPU cores, such as a first CPU core 6041, a second CPU core 6042, and so on up to the Mth CPU core 604. M .

[0055] Display controller 609 and touchscreen controller 612 may be coupled to CPU 604. A touchscreen display 614 external to SoC 202 may be coupled to display controller 610 and touchscreen controller 612. PCD 600 may also include a video decoder 616 coupled to CPU 604. Video amplifier 618 may be coupled to video decoder 616 and touchscreen display 614. Video port 620 may be coupled to video amplifier 618. Universal Serial Bus (“USB”) controller 622 may also be coupled to CPU 604, and USB port 624 may be coupled to USB controller 622. User identity module (“SIM”) card 626 may also be coupled to CPU 604.

[0056] One or more memory modules 628 may be coupled to the CPU 604. The one or more memory modules 628 may include both volatile and non-volatile memory. Examples of volatile memory include static random access memory (“SRAM”) and dynamic random access memory (“DRAM”). Such memory may be external to or internal to the SoC 202. The one or more memory modules 628 may include local cache memory or system-level cache memory.

[0057] A stereo audio codec 634 may be coupled to an analog signal processor 608. Additionally, an audio amplifier 636 may be coupled to the stereo audio codec 634. A first stereo speaker 638 and a second stereo speaker 640 may be coupled to the audio amplifier 636, respectively. Furthermore, a microphone amplifier 642 may be coupled to the stereo audio codec 634, and a microphone 644 may be coupled to the microphone amplifier 642. An FM radio tuner 646 may be coupled to the stereo audio codec 634. An FM antenna 648 may be coupled to the FM radio tuner 646. Additionally, a stereo headset 650 may be coupled to the stereo audio codec 634. Other devices that may be coupled to the CPU 604 include one or more digital (e.g., CCD or CMOS) cameras 652.

[0058] A modem or RF transceiver 654 may be coupled to an analog signal processor 608 and a CPU 604. An RF switch 656 may be coupled to an RF transceiver 654 and an RF antenna 658. Additionally, a keypad 660 and a mono headset 662 with a microphone may be coupled to the analog signal processor 608. The SoC 602 may have one or more internal or on-chip thermal sensors 670. A power supply 674 and a PMIC 676 may power the SoC 202.

[0059] Firmware or software may be stored in any of the aforementioned memories, or in local memory directly accessible to the processor hardware executing the software or firmware thereon. Execution of such firmware or software by system 200 may control aspects of any of the methods described above or configure aspects of any of the systems described above. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware may be an example of a "computer-readable medium," as understood in the patent dictionary.

[0060] Figure 7 A system 700, comprising components of a vehicle autonomous driving system according to a representative embodiment, is illustrated, wherein the system may employ… Figure 2 The system 200 and GPU 201 are shown. The vehicle autonomous driving system may include a processing module 710 and a drive-by-wire (DBW) system controller 736. Figure 2 The system 200 shown and Figure 2 The GPU 201 shown, or some other processors combined with system 200, may be implemented in processing module 710. Processing module 710 may be, for example, a SoC and may include additional components, such as... Figure 6 The components shown are as described. The processing module 710 may include one or more object detection elements 712 and one or more camera sensing elements 714. For example, the object detection element 712 may receive input from one or more sensors 713; and the camera sensing element 714 may receive input from one or more cameras 717.

[0061] In an exemplary embodiment, the processing module 710 may further include a positioning engine 718, a map fusion and arbitration element 722, and a route planning element 724. In an exemplary embodiment, the positioning engine 718 may receive input from a camera 717 and a positioning input 723. The positioning input 723 may be, for example, Global Positioning System (GPS) data, Inertial Measurement Unit (IMU) data, Controller Area Network (CAN) data, etc. For example, the map fusion and arbitration element 722 and the route planning element 724 may receive map input from a high-precision map element 727.

[0062] In an exemplary embodiment, the processing module 710 may further include a sensor fusion and road world model (RWM) management element 730, a motion planning and control element 732, and a behavior planning and prediction element 734. In an exemplary embodiment, the sensor fusion and road world model (RWM) management element 730 may receive input from an object detection element 712, a camera perception element 714, a map fusion and arbitration element 722, and a route planning element 724 to develop a road world model. Figure 2The GPU 201 and system 200 shown may be employed, for example, in sensor fusion and RWM management element 730, for processing data received from elements 712, 714, 722, and 724. In an exemplary embodiment, the road world model may be an intelligent world model for autonomous vehicles.

[0063] In an exemplary embodiment, sensor fusion and RWM management element 730 may provide outputs to motion planning and control element 732 and behavior planning and prediction element 734. Behavior planning and prediction element 734 may also provide outputs to motion planning and control element 732. The output of processing module 710 may be provided to drive-by-wire (DBW) system controller 736, which may provide autonomous driving commands to vehicle 740.

[0064] It should be noted that Figure 6 and Figure 7 Systems 600 and 700 shown are respectively among the systems that can be employed. Figure 2 and Figure 3 The system 200 shown is an example of a system. However, ECC checkers are used in many different applications and systems. Therefore, any application and system that can benefit from the inventive principles and concepts disclosed herein can adopt system 200. Furthermore, although system 200 has been described as being used in a SoC, it is not limited to use in a SoC.

[0065] Specific implementation examples are described in the following numbered clauses: 1. An ECC testing system for testing error correction code (ECC) logic of at least a first storage device, the ECC logic being used to check for bit errors in the memory of at least the first storage device, the ECC logic including ECC checker generator logic and ECC checker logic, the ECC testing system comprising: A fault injection logic, configured to inject a first pre-selected test bit pattern into the ECC logic for processing by the ECC checksum generator logic to generate a first ECC checksum stored in a first ECC memory of the first storage device, the fault injection logic being configured to retrieve the first ECC checksum from the first ECC memory, modify the retrieved first ECC checksum in a predetermined manner, and cause the modified first ECC checksum to be processed by the ECC checker logic to generate a first fault feature recorded by an ECC recorder; and The fault determination logic is configured to receive the recorded first fault feature from the ECC recorder and compare the recorded first fault feature with the expected fault feature to determine whether the recorded first fault feature matches the expected fault feature.

[0066] 2. The ECC test system according to Clause 1, wherein the fault injection logic includes: The write logic of the fault injection and evaluation state machine is configured to change from an "idle" state to a "write to memory" state when a fault injection enable signal is asserted, wherein during the "write to memory" state, the first preselected test bit pattern is injected into the ECC logic by the write logic; and Selection logic, configured to receive the fault injection enable signal and the first preselected test bit mode, and when the fault injection and evaluation state machine is in the "write to memory" state, to transmit the first preselected test bit mode to the ECC checksum generator logic.

[0067] 3. The ECC test system according to Clause 2, wherein the fault injection and evaluation state machine is further configured to change from the "write to memory" state to the "read to memory" state after the first ECC checksum has been stored in the first ECC memory, wherein during the "read to memory" state, the selection logic causes the first ECC checksum to be read from the first ECC memory and processed by the ECC checker logic to generate the first fault feature.

[0068] 4. The ECC test system according to Clause 3, wherein the fault injection and evaluation state machine includes the fault determination logic, and wherein the fault injection and evaluation state machine is further configured to: after the first fault feature has been recorded by the ECC recorder, change from the "read memory" state to the "get log data" state, wherein during the "get log data" state, the fault determination logic receives the recorded first fault feature.

[0069] 5. The ECC testing system according to Clause 4, wherein the fault injection and evaluation state machine is further configured to: after the recorded first fault feature has been received by the fault determination logic, change from the "get log data" state to the "compare" state, wherein during the "compare" state, the fault determination logic compares the recorded first fault feature with the expected fault feature to determine whether the recorded first fault feature matches the expected fault feature.

[0070] 6. The ECC test system according to Clause 5, wherein the fault injection and evaluation state machine is further configured to: change from the “Compare” state to a “Catch Fault” state if the fault determination logic determines during the “Compare” state that the recorded first fault feature does not match the expected fault feature, and wherein the fault determination logic is further configured to generate an interrupt during the “Catch Fault” state, the interrupt being output from the ECC test system to notify one or more systems that “a fault has been detected in the ECC logic”.

[0071] 7. The ECC test system according to Clause 5, wherein the fault injection and evaluation state machine is further configured to: change from the “Compare” state to a “Catch Fault” state if the fault determination logic determines during the “Compare” state that the recorded first fault feature does not match the expected fault feature, and wherein the fault determination logic is further configured to generate a report indicating that a fault has been detected in the ECC logic during the “Catch Fault” state.

[0072] 8. The ECC test system according to any one of Clauses 5 to 7, wherein the fault injection and evaluation state machine is further configured to: return from the "Compare" state to the "Write to Memory" state when the fault determination logic determines during the "Compare" state that the recorded first fault feature matches the expected fault feature; and wherein when the fault injection and evaluation state machine returns to the "Write to Memory" state, a second preselected test bit pattern is injected into the ECC logic by the write logic and processed by the ECC checksum generator logic to generate a second ECC checksum, the second ECC checksum being stored in a second ECC memory of the first storage device.

[0073] 9. An ECC test system according to any one of Clauses 3 to 8, wherein the fault injection logic further includes an inverter, and wherein the selection logic includes a first multiplexer (MUX) and a second MUX, each of the first MUX and the second MUX having at least a first input and a second input and an output, wherein the second input of the first MUX is electrically coupled to the fault injection logic such that when the fault injection and evaluation state machine is in the "write to memory" state, the first preselected test bit pattern is received at the second input of the first MUX and output from the output of the first MUX and input to the ECC checksum generator logic, and wherein when the fault injection and evaluation state machine is in the "write to memory" state, the first ECC checksum generated by the ECC checksum generator is stored in the first ECC memory by the fault injection logic.

[0074] 10. The ECC test system according to Clause 9, wherein the output of the second MUX is electrically coupled to the input of the ECC checker logic, and wherein the second input of the second MUX is electrically coupled to the output of the first ECC memory via the inverter, and wherein when the fault injection and evaluation state machine is in the "read memory" state, the first ECC checksum stored in the first ECC memory is inverted by the inverter, output from the output of the second MUX, and input to the ECC checker logic via the input of the ECC checker logic.

[0075] 11. A method for testing error correction code (ECC) logic of at least a first storage device, the ECC logic being used to check for bit errors in the memory of at least the first storage device, the method comprising: The fault injection logic is used to inject a first preselected test bit pattern into the ECC logic and transmit it to the ECC checksum generator logic of the ECC logic. The ECC checksum generator logic processes the injected first preselected test bit pattern to generate a first ECC checksum stored in the first ECC memory of the first storage device. The fault injection logic retrieves the first ECC checksum from the first ECC memory, modifies the first ECC checksum in a predetermined manner, and transmits the modified first ECC checksum to the ECC checker logic. The ECC checker logic receives the modified first ECC checksum and processes it to generate a first fault characteristic recorded by the ECC recorder. The fault determination logic is used to compare the recorded first fault feature with the expected fault feature to determine whether the recorded first fault feature matches the expected fault feature.

[0076] 12. The method according to Clause 11, wherein the fault injection logic includes fault injection and evaluation state machine and selection logic, the method further comprising: Using the fault injection and evaluation state machine, when the fault injection enable signal is asserted, the state changes from "idle" to "write to memory," wherein the write logic of the fault injection and evaluation state machine injects the first preselected test bit pattern into the ECC logic during the "write to memory" state; and Using the selection logic, when the fault injection and evaluation state machine is in the "write to memory" state, the fault injection enable signal and the first pre-selected test bit pattern are received, and the first pre-selected test bit pattern is transmitted to the ECC checksum generator logic. When the fault injection and evaluation state machine is in the "write to memory" state, the ECC checksum generator logic processes the first pre-selected test bit pattern to generate the first ECC checksum, and the first ECC checksum is stored in the first ECC memory.

[0077] 13. The method according to Clause 12, further comprising: Using the fault injection and evaluation state machine, after the first ECC checksum has been stored in the first ECC memory, the state changes from "write to memory" to "read from memory"; and Using the selection logic, during the "read memory" state, the first ECC checksum is read from the first ECC memory, modified by the fault injection logic in the predetermined manner, and transmitted to the ECC checker logic for processing to generate the first fault feature.

[0078] 14. The method according to Clause 13, wherein the fault injection and evaluation state machine includes the fault determination logic, and wherein the method further comprises: Using the fault injection and evaluation state machine, after the first fault characteristic has been recorded by the ECC logger, the state changes from "read memory" to "acquire log data"; and Using the fault determination logic, during the "acquire log data" state, the first fault feature recorded is received by the fault determination logic.

[0079] 15. The method according to Clause 14, further comprising: Using the fault injection and evaluation state machine, after the recorded first fault feature has been received by the fault determination logic, the state changes from "acquire log data" to "compare"; and Using the fault determination logic, during the "comparison" state, the recorded first fault feature is compared with the expected fault feature to determine whether the recorded first fault feature matches the expected fault feature.

[0080] 16. The method according to Clause 15, further comprising: Using the fault injection and evaluation state machine, during the "comparison" state, if the fault determination logic determines that the recorded first fault feature does not match the expected fault feature, it changes from the "comparison" state to the "fault capture" state; and Using the fault determination logic, during the “fault capture” state, an interrupt indicating that a fault has been detected in the ECC logic is generated.

[0081] 17. The method according to Clause 15, further comprising: Using the fault injection and evaluation state machine, during the "comparison" state, if the fault determination logic determines that the recorded first fault feature does not match the expected fault feature, it changes from the "comparison" state to the "fault capture" state; and Using the fault determination logic, during the “fault capture” state, a report indicating that a fault has been detected in the ECC checker logic is generated.

[0082] 18. The method according to any one of clauses 15 to 17, wherein the method further comprises: Using the fault injection and evaluation state machine, during the "compare" state, if the fault determination logic determines that the recorded first fault feature matches the expected fault feature, it returns from the "compare" state to the "write to memory" state; and Using the fault injection logic, when the fault injection and evaluation state machine returns to the "write to memory" state, the second preselected test bit pattern is injected into the ECC logic, so that the second preselected test bit pattern is processed by the ECC checksum generator logic to generate a second ECC checksum, and the second ECC checksum is stored in the second ECC memory element of the first storage device.

[0083] 19. The method according to any one of claims 13 to 18, wherein the fault injection logic further includes an inverter, and wherein the selection logic includes a first multiplexer (MUX) and a second MUX, each having at least a first input and a second input and an output, the second input of the first MUX being electrically coupled to the fault injection logic such that when the fault injection and evaluation state machine is in the “write to memory” state, the first preselected test bit pattern is received at the second input of the first MUX and output from the output of the first MUX and input to the ECC checksum generator, and wherein when the fault injection and evaluation state machine is in the “write to memory” state, the first ECC checksum generated by the ECC checksum generator is stored by the fault injection logic in the first ECC memory.

[0084] 20. The method according to Clause 19, wherein the output of the second MUX is electrically coupled to the input of the ECC checker logic, and the second input of the second MUX is electrically coupled to the output of the first ECC memory via the inverter, and wherein when the fault injection and evaluation state machine is in the "read memory" state, the steps of retrieving the first ECC checksum from the first ECC memory, modifying the first ECC checksum in the predetermined manner, and transmitting the modified first ECC checksum to the ECC checker logic are performed by the second MUX and the inverter.

[0085] 21. A computer program for testing error correction code (ECC) logic of at least a first storage device, the ECC logic being used to check for bit errors in the memory of at least the first storage device, the computer program comprising computer instructions for execution by a processor, the computer program being embodied on a non-transitory computer-readable medium, the computer program comprising: A first set of computer instructions, the first set of computer instructions being used to cause the fault injection logic to inject a first preselected test bit pattern into the ECC logic; The second set of computer instructions is used to cause the fault injection logic to transmit the first pre-selected test bit pattern to the ECC checksum generator logic of the ECC logic, and the ECC checksum generator logic processes the first pre-selected test bit pattern to generate a first ECC checksum stored in the first ECC memory of the first storage device. A third set of computer instructions is used to cause the fault injection logic to retrieve the first ECC checksum from the first ECC memory, modify the first ECC checksum in a predetermined manner, and transmit the modified first ECC checksum to the ECC checker logic of the ECC logic for processing the modified first ECC checksum to generate a first fault feature recorded by the ECC recorder; and The fourth set of computer instructions is used to cause the fault determination logic to compare the recorded first fault feature with the expected fault feature to determine whether the recorded first fault feature matches the expected fault feature.

[0086] 22. The computer program according to Clause 21, wherein the fault injection logic includes a fault injection and evaluation state machine, and wherein the first set of computer instructions and the fourth set of computer instructions are executed by the fault injection and evaluation state machine, wherein when the first set of computer instructions is executed, the fault injection and evaluation state machine changes from an "idle" state to a "write to memory" state when a fault injection enable signal is asserted, and wherein during the "write to memory" state, the first set of computer instructions causes the first preselected test bit pattern to be injected into the ECC logic by the write logic of the fault injection and evaluation state machine, and wherein during the "write to memory" state, the second set of computer instructions causes the fault injection logic to transmit the injected first preselected test bit pattern to the ECC checksum generator logic for generating the first ECC checksum, and causes the first ECC checksum to be stored in the first ECC memory.

[0087] 23. The computer program according to Clause 22, wherein after the first ECC checksum has been stored in the first ECC memory, the fault injection and evaluation state machine changes from the "write to memory" state to the "read from memory" state, and wherein during the "read from memory" state, the third set of computer instructions causes the fault injection logic to read the first ECC checksum from the first ECC memory, modify the read first ECC checksum in the predetermined manner, and transmit the modified first ECC checksum to the ECC checker logic for processing to generate the first fault feature.

[0088] 24. The computer program according to Clause 23, wherein after the first fault feature has been recorded by the ECC recorder, the fault injection and evaluation state machine changes from the “read memory” state to the “get log data” state, and wherein during the “get log data” state, the fourth set of computer instructions causes the fault determination logic to receive the recorded first fault feature.

[0089] 25. The computer program according to Clause 24, wherein after the recorded first fault feature has been received by the fault determination logic, the fault injection and evaluation state machine changes from the "acquire log data" state to the "compare" state, and wherein the fourth set of computer instructions causes the fault determination logic to compare the recorded first fault feature with the expected fault feature during the "compare" state to determine whether the recorded first fault feature matches the expected fault feature.

[0090] 26. The computer program according to Clause 25, wherein during the “Compare” state, if the fault injection logic determines that the recorded first fault characteristic does not match the expected fault characteristic, the fault injection and evaluation state machine changes from the “Compare” state to the “Catch Fault” state, and wherein the fourth set of computer instructions further includes computer instructions for causing the fault determination logic to perform at least one of the following operations during the “Catch Fault” state: generating an interrupt indicating that a fault has been detected in the ECC logic, and generating a report indicating that a fault has been detected in the ECC checker logic.

[0091] 27. The computer program according to Clause 25, wherein, during the “Compare” state, if the fourth set of computer instructions executed by the fault determination logic determines that the recorded first fault feature matches the expected fault feature, the fault injection and evaluation state machine returns from the “Compare” state to the “Write to Memory” state, and wherein, when the fault injection and evaluation state machine returns to the “Write to Memory” state, the first set of computer instructions causes the write logic to inject a second preselected test bit pattern into the ECC logic, and the second set of computer instructions causes the second preselected test bit pattern to be transmitted to the ECC checksum generator logic for generating a second ECC checksum, and the second set of computer instructions causes the second ECC checksum to be stored in a second ECC memory element of the first storage device.

[0092] 28. A computer program according to any one of clauses 23 to 27, wherein the fault injection logic further includes an inverter, and wherein the selection logic includes a first multiplexer (MUX) and a second MUX and an inverter, the first MUX and the second MUX each having at least a first input and a second input and an output, the second input of the first MUX being electrically coupled to the fault injection logic such that, when the fault injection and evaluation state machine is in the "write to memory" state, the first set of computer instructions causes the first preselected test bit pattern to be received at the second input of the first MUX, output from the output of the first MUX, and input by the fault injection logic to the ECC checksum generator, and wherein, when the fault injection and evaluation state machine is in the "write to memory" state, the second set of computer instructions causes the selection logic to store the first ECC checksum generated by the ECC checksum generator in the first ECC memory.

[0093] 29. The computer program according to Clause 28, wherein the output of the second MUX is electrically coupled to the input of the ECC checker logic, and the second input of the second MUX is electrically coupled to the output of the first ECC memory via the inverter, and wherein when the fault injection and evaluation state machine is in the "read memory" state, the third set of computer instructions causes the fault injection logic to retrieve the first ECC checksum from the first ECC memory, apply the retrieved first ECC checksum to the second input of the second MUX, such that the retrieved first ECC checksum is modified via the inverter and transmitted to the input of the ECC checker logic.

[0094] 30. An ECC testing system for testing error correction code (ECC) logic of at least a first storage device, the ECC logic being used to check for bit errors in the memory of at least the first storage device, the ECC logic including ECC checker generator logic and ECC checker logic, the ECC testing system comprising: A component for injecting a pre-selected test bit pattern into the ECC logic for processing by the ECC check generator logic to generate an ECC check stored in the first ECC memory of the first storage device. Components for retrieving the ECC checksum from the first ECC memory; Components for modifying the retrieved ECC checksum in a predetermined manner; Components for transmitting the modified ECC checksum to the ECC checker logic for processing to generate fault characteristics recorded by the ECC recorder; and A component for receiving the recorded fault characteristics from the ECC recorder and for comparing the recorded fault characteristics with expected fault characteristics to determine whether the recorded fault characteristics match the expected fault characteristics.

[0095] Alternative embodiments will become apparent to those skilled in the art to which this invention pertains. Therefore, although selected aspects have been illustrated and described in detail, it should be understood that various substitutions and changes may be made therein, and all such modifications are within the scope of this disclosure.

Claims

1. An error-correcting code (ECC) test system for testing ECC logic of at least a first storage device, the ECC logic for checking bit errors of a memory of at least the first storage device, the ECC logic including ECC syndrome generator logic and ECC checker logic, the ECC test system comprising: fault injection logic configured to inject a first preselected test bit pattern into the ECC logic for processing by the ECC syndrome generator logic to generate a first ECC syndrome stored in a first ECC memory of the first storage device, the fault injection logic configured to retrieve the first ECC syndrome from the first ECC memory, modify the retrieved first ECC syndrome in a predetermined manner, and cause the modified first ECC syndrome to be processed by the ECC checker logic to generate a first fault signature recorded by an ECC logger; and fault determination logic configured to receive the recorded first fault signature from the ECC logger and compare the recorded first fault signature to an expected fault signature to determine whether the recorded first fault signature matches the expected fault signature.

2. The ECC test system of claim 1, wherein the fault injection logic comprises: write logic of a fault injection and evaluation state machine configured to change from an "idle" state to a "write memory" state when a fault injection enable signal is asserted, wherein during the "write memory" state, the first preselected test bit pattern is injected into the ECC logic by the write logic; and select logic configured to receive the fault injection enable signal and the first preselected test bit pattern and cause the first preselected test bit pattern to be transferred to the ECC syndrome generator logic when the fault injection and evaluation state machine is in the "write memory" state.

3. The ECC test system of claim 2, wherein the fault injection and evaluation state machine is further configured to change from the "write memory" state to a "read memory" state after the first ECC syndrome has been stored in the first ECC memory, wherein during the "read memory" state, the select logic causes the first ECC syndrome to be read from the first ECC memory and processed by the ECC checker logic to generate the first fault signature.

4. The ECC test system of claim 3, wherein the fault injection and evaluation state machine includes the fault determination logic, and wherein the fault injection and evaluation state machine is further configured to change from the "read memory" state to a "get log data" state after the first fault signature has been recorded by the ECC logger, wherein during the "get log data" state, the fault determination logic receives the recorded first fault signature.

5. The ECC test system of claim 4, wherein the fault injection and evaluation state machine is further configured to change from the "get log data" state to a "compare" state after the first fault signature recorded has been received by the fault decision logic, wherein during the "compare" state the fault decision logic compares the first fault signature recorded to the expected fault signature to determine whether the first fault signature recorded matches the expected fault signature.

6. The ECC test system of claim 5, wherein the fault injection and evaluation state machine is further configured to change from the "compare" state to a "capture fault" state if the fault decision logic determines during the "compare" state that the first fault signature recorded does not match the expected fault signature, and wherein the fault decision logic is further configured to generate an interrupt during the "capture fault" state, the interrupt being output from the ECC test system to notify one or more systems that a fault has been detected in the ECC logic.

7. The ECC test system of claim 5, wherein the fault injection and evaluation state machine is further configured to change from the "compare" state to a "capture fault" state if the fault decision logic determines during the "compare" state that the first fault signature recorded does not match the expected fault signature, and wherein the fault decision logic is further configured to generate a report during the "capture fault" state indicating that a fault has been detected in the ECC logic.

8. The ECC test system of claim 5, wherein the fault injection and evaluation state machine is further configured to return from the "compare" state to the "write memory" state if the fault decision logic determines during the "compare" state that the first fault signature recorded matches the expected fault signature, and wherein a second preselected test bit pattern is injected into the ECC logic by the write logic and processed by the ECC syndrome generator logic to generate a second ECC syndrome when the fault injection and evaluation state machine returns to the "write memory" state, the second ECC syndrome being stored in a second ECC memory of the first storage device.

9. The ECC test system of claim 3, wherein the fault injection logic further comprises an inverter, and wherein the selection logic comprises a first multiplexer (MUX) and a second MUX, the first and second MUX each having at least a first input and a second input and an output, the second input of the first MUX electrically coupled to the fault injection logic such that when the fault injection and evaluation state machine is in the "write memory" state, the first preselected test bit pattern is received at the second input of the first MUX and output from the output of the first MUX and input to the ECC syndrome generator logic, and wherein the first ECC syndrome generated by the ECC syndrome generator is stored in the first ECC memory by the fault injection logic when the fault injection and evaluation state machine is in the "write memory" state.

10. The ECC test system of claim 9, wherein the output of the second MUX is electrically coupled to an input of the ECC checker logic, and wherein the second input of the second MUX is electrically coupled to an output of the first ECC memory via the inverter, and wherein when the fault injection and evaluation state machine is in the "read memory" state, the first ECC syndrome stored in the first ECC memory is inverted by the inverter, output from the output of the second MUX, and input to the ECC checker logic via the input of the ECC checker logic.

11. A method for testing error correcting code (ECC) logic of at least a first storage device, the ECC logic for checking bit errors of a memory of the at least first storage device, the method comprising: causing, using fault injection logic, a first preselected test bit pattern to be injected into the ECC logic and passed to an ECC syndrome generator logic of the ECC logic, the ECC syndrome generator logic processing the injected first preselected test bit pattern to generate a first ECC syndrome stored in a first ECC memory of the first storage device; retrieving, using the fault injection logic, the first ECC syndrome from the first ECC memory, modifying the first ECC syndrome in a predetermined manner, and passing the modified first ECC syndrome to the ECC checker logic, the ECC checker logic receiving the modified first ECC syndrome and processing the modified first ECC syndrome to generate a first fault signature recorded by an ECC recorder; and comparing, using fault determination logic, the recorded first fault signature to an expected fault signature to determine whether the recorded first fault signature matches the expected fault signature.

12. The method of claim 11, wherein the fault injection logic comprises a fault injection and evaluation state machine and selection logic, the method further comprising: with the fault injection and evaluation state machine, changing from the "idle" state to a "write memory" state when a fault injection enable signal is asserted, wherein write logic of the fault injection and evaluation state machine injects the first preselected test bit pattern into the ECC logic during the "write memory" state; and with the selection logic, receiving the fault injection enable signal and the first preselected test bit pattern when the fault injection and evaluation state machine is in the "write memory" state, and causing the first preselected test bit pattern to be passed to the ECC syndrome generator logic, and wherein the ECC syndrome generator logic processes the first preselected test bit pattern to generate the first ECC syndrome and causes the first ECC syndrome to be stored in the first ECC memory when the fault injection and evaluation state machine is in the "write memory" state.

13. The method of claim 12, further comprising: with the fault injection and evaluation state machine, changing from the "write memory" state to a "read memory" state after the first ECC syndrome has been stored in the first ECC memory; and with the selection logic, causing the first ECC syndrome to be read from the first ECC memory during the "read memory" state, modified by the fault injection logic in the predetermined manner, and passed to the ECC checker logic for processing by the ECC checker logic to generate the first fault signature.

14. The method of claim 13, wherein the fault injection and evaluation state machine includes the fault decision logic, and wherein the method further comprises: with the fault injection and evaluation state machine, changing from the "read memory" state to a "get log data" state after the first fault signature has been recorded by the ECC recorder; and with the fault decision logic, causing the recorded first fault signature to be received by the fault decision logic during the "get log data" state.

15. The method of claim 14, further comprising: with the fault injection and evaluation state machine, changing from the "get log data" state to a "compare" state after the recorded first fault signature has been received by the fault decision logic; and with the fault decision logic, comparing the recorded first fault signature to the expected fault signature during the "compare" state to determine whether the recorded first fault signature matches the expected fault signature.

16. The method of claim 15, further comprising: with the fault injection and evaluation state machine, changing from the "compare" state to a "capture fault" state if the fault decision logic determines that the recorded first fault signature does not match the expected fault signature during the "compare" state; and with the fault injection and evaluation state machine, changing from the "capture fault" state to an "idle" state after the first fault signature has been captured by the fault decision logic. With the fault determination logic, during the "capture fault" state, generating an interrupt indicating that a fault has been detected in the ECC logic.

17. The method of claim 15, further comprising: With the fault injection and evaluation state machine, during the "compare" state, the fault determination logic determining that the recorded first fault signature does not match the expected fault signature, changing from the "compare" state to a "capture fault" state; and With the fault determination logic, during the "capture fault" state, generating a report indicating that a fault has been detected in the ECC checker logic.

18. The method of claim 15, further comprising: With the fault injection and evaluation state machine, during the "compare" state, the fault determination logic determining that the recorded first fault signature matches the expected fault signature, returning from the "compare" state to the "write memory" state; and With the fault injection logic, when the fault injection and evaluation state machine returns to the "write memory" state, injecting a second preselected test bit pattern into the ECC logic to cause the second preselected test bit pattern to be processed by the ECC syndrome generator logic to generate a second ECC syndrome, the second ECC syndrome being stored in a second ECC memory element of the first memory device.

19. The method of claim 13, wherein the fault injection logic further comprises an inverter, and wherein the selection logic comprises a first multiplexer (MUX) and a second MUX, the first and second MUX each having at least a first input and a second input and an output, the second input of the first MUX being electrically coupled to the fault injection logic such that when the fault injection and evaluation state machine is in the "write memory" state, the first preselected test bit pattern is received at the second input of the first MUX and output from the output of the first MUX and input to the ECC syndrome generator, and wherein the first ECC syndrome generated by the ECC syndrome generator is stored in the first ECC memory by the fault injection logic when the fault injection and evaluation state machine is in the "write memory" state.

20. The method of claim 19, wherein the output of the second MUX is electrically coupled to an input of the ECC checker logic, and the second input of the second MUX is electrically coupled to an output of the first ECC memory via the inverter, and wherein when the fault injection and evaluation state machine is in the "read memory" state, the steps of retrieving the first ECC syndrome from the first ECC memory, modifying the first ECC syndrome in the predetermined manner, and passing the modified first ECC syndrome to the ECC checker logic are performed by the second MUX and the inverter.

21. A computer program for testing error correction code (ECC) logic of at least a first storage device, the ECC logic for checking bit errors of a memory of at least the first storage device, the computer program comprising computer instructions for execution by a processor, the computer program being embodied on a non-transitory computer readable medium, the computer program comprising: a first set of computer instructions for causing fault injection logic to inject a first preselected test bit pattern into the ECC logic; a second set of computer instructions for causing the fault injection logic to pass the first preselected test bit pattern to ECC syndrome generator logic of the ECC logic, the ECC syndrome generator logic processing the first preselected test bit pattern to generate a first ECC syndrome stored in a first ECC memory of the first storage device; a third set of computer instructions for causing the fault injection logic to retrieve the first ECC syndrome from the first ECC memory, modify the first ECC syndrome in a predetermined manner, and pass the modified first ECC syndrome to ECC checker logic of the ECC logic for processing the modified first ECC syndrome to generate a first fault signature recorded by an ECC logger; and a fourth set of computer instructions for causing fault decision logic to compare the recorded first fault signature to an expected fault signature to determine whether the recorded first fault signature matches the expected fault signature.

22. The computer program of claim 21, wherein the fault injection logic comprises a fault injection and evaluation state machine, and wherein the first set of computer instructions and the fourth set of computer instructions are executed by the fault injection and evaluation state machine, wherein when the first set of computer instructions are executed, the fault injection and evaluation state machine changes from an "idle" state to a "write memory" state when a fault injection enable signal is asserted, and wherein during the "write memory" state, the first set of computer instructions causes the first preselected test bit pattern to be injected into the ECC logic by write logic of the fault injection and evaluation state machine, and wherein during the "write memory" state, the second set of computer instructions causes the fault injection logic to pass the injected first preselected test bit pattern to the ECC syndrome generator logic for generating the first ECC syndrome, and causes the first ECC syndrome to be stored in the first ECC memory.

23. The computer program of claim 22, wherein after the first ECC syndrome has been stored in the first ECC memory, the fault injection and evaluation state machine changes from the "write memory" state to a "read memory" state, and wherein during the "read memory" state, the third set of computer instructions cause the fault injection logic to read the first ECC syndrome from the first ECC memory, modify the read first ECC syndrome in the predetermined manner, and transfer the modified first ECC syndrome to the ECC checker logic for processing by the ECC checker logic to generate the first fault signature.

24. The computer program of claim 23, wherein after the first fault signature has been logged by the ECC logger, the fault injection and evaluation state machine changes from the "read memory" state to a "get log data" state, and wherein during the "get log data" state, the fourth set of computer instructions cause the fault decision logic to receive the logged first fault signature.

25. The computer program of claim 24, wherein after the logged first fault signature has been received by the fault decision logic, the fault injection and evaluation state machine changes from the "get log data" state to a "compare" state, and wherein the fourth set of computer instructions cause the fault decision logic to compare the logged first fault signature to the expected fault signature during the "compare" state to determine whether the logged first fault signature matches the expected fault signature.

26. The computer program of claim 25, wherein in the event the fault injection logic determines that the logged first fault signature does not match the expected fault signature during the "compare" state, the fault injection and evaluation state machine changes from the "compare" state to a "capture fault" state, and wherein the fourth set of computer instructions further include computer instructions to cause the fault decision logic to perform at least one of the following during the "capture fault" state: generate an interrupt indicating that a fault has been detected in the ECC logic, and generate a report indicating that a fault has been detected in the ECC checker logic.

27. The computer program of claim 25, wherein in the event the fourth set of computer instructions executed by the fault decision logic during the "compare" state determines that the recorded first fault signature matches the expected fault signature, the fault injection and evaluation state machine returns from the "compare" state to the "write memory" state, and wherein when the fault injection and evaluation state machine returns to the "write memory" state, the first set of computer instructions causes the write logic to inject a second preselected test bit pattern into the ECC logic, and the second set of computer instructions causes the second preselected test bit pattern to be passed to the ECC syndrome generator logic for generating a second ECC syndrome, the second set of computer instructions causing the second ECC syndrome to be stored in a second ECC memory element of the first storage device.

28. The computer program of any one of claim 23, wherein the fault injection logic further comprises an inverter, and wherein the selection logic comprises a first multiplexer (MUX) and a second MUX and an inverter, the first and second MUX each having at least a first input and a second input and an output, the second input of the first MUX electrically coupled to the fault injection logic such that when the fault injection and evaluation state machine is in the "write memory" state, the first set of computer instructions causes the first preselected test bit pattern to be received at the second input of the first MUX, output from the output of the first MUX, and input to the ECC syndrome generator by the fault injection logic, and wherein when the fault injection and evaluation state machine is in the "write memory" state, the second set of computer instructions causes the selection logic to store the first ECC syndrome generated by the ECC syndrome generator in the first ECC memory.

29. The computer program of claim 28, wherein the output of the second MUX is electrically coupled to an input of the ECC checker logic, and the second input of the second MUX is electrically coupled to an output of the first ECC memory via the inverter, and wherein when the fault injection and evaluation state machine is in the "read memory" state, the third set of computer instructions causes the fault injection logic to retrieve the first ECC syndrome from the first ECC memory, apply the retrieved first ECC syndrome to the second input of the second MUX to cause the retrieved first ECC syndrome to be modified via the inverter and passed to the input of the ECC checker logic.

30. An ECC test system for testing error correction code (ECC) logic of at least a first storage device, the ECC logic for checking bit errors of a memory of at least the first storage device, the ECC logic comprising ECC syndrome generator logic and ECC checker logic, the ECC test system comprising: means for injecting a preselected test bit pattern into the ECC logic for processing by the ECC syndrome generator logic to generate an ECC syndrome stored in a first ECC memory of the first storage device; means for retrieving the ECC syndrome from the first ECC memory; means for modifying the retrieved ECC syndrome in a predetermined manner; means for causing the modified ECC syndrome to be passed to the ECC checker logic for processing by the ECC checker logic to generate a failure signature recorded by an ECC recorder; and means for receiving the recorded failure signature from the ECC recorder and for comparing the recorded failure signature to an expected failure signature to determine whether the recorded failure signature matches the expected failure signature.

30. An ECC test system for testing error correction code (ECC) logic of at least a first storage device, the ECC logic for checking bit errors of a memory of at least the first storage device, the ECC logic comprising ECC syndrome generator logic and ECC checker logic, the ECC test system comprising: means for injecting a preselected test bit pattern into the ECC logic for processing by the ECC syndrome generator logic to generate an ECC syndrome stored in a first ECC memory of the first storage device; means for retrieving the ECC syndrome from the first ECC memory; means for modifying the retrieved ECC syndrome in a predetermined manner; means for causing the modified ECC syndrome to be passed to the ECC checker logic for processing by the ECC checker logic to generate a failure signature recorded by an ECC recorder; and means for receiving the recorded failure signature from the ECC recorder and for comparing the recorded failure signature to an expected failure signature to determine whether the recorded failure signature matches the expected failure signature.

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