Low-temperature preparation method of high-uniformity vanadium oxide film and vanadium oxide film

Abstract

The invention discloses a low-temperature preparation method of a high-uniformity vanadium oxide film and a vanadium oxide film, and the low-temperature preparation method of the high-uniformity vanadium oxide film comprises the steps: S1, carrying out the ultrasonic cleaning of an eight-inch P-type monocrystalline silicon wafer through an organic solvent and deionized water, etching the surface through a specific etching solution, and carrying out the washing and drying to form a substrate; s2, an Al2O3 ceramic target is used as a sputtering target material, and an Al2O3 buffer layer with the thickness of 5-10 nm is deposited in the magnetron sputtering chamber; s3, replacing the target with a metal vanadium target, introducing a ternary mixed gas of Ar, O2 and N2, dynamically controlling the O2 flow in a partitioned manner, and depositing a vanadium oxide film with the thickness of 50-100nm; and S4, carrying out in-situ rapid thermal annealing on the vanadium oxide thin film in the chamber, and carrying out stepped heating and cooling treatment. The method has the advantages that the parameter controllability is high, the repetition rate is high, and the high-performance vanadium oxide film can be prepared on a large scale.

Description

Technical Field

[0001] This invention relates to the field of vanadium oxide films, and more specifically, to a low-temperature preparation method for highly uniform vanadium oxide films and the vanadium oxide film itself. Background Technology

[0002] Vanadium oxide thin films, with their excellent metal-insulator phase transition properties, have key application value in the sensitive element arrays of infrared detector chips and the thermo-optical phase modulation units of silicon-based photonic integrated chips. Magnetron sputtering has become the mainstream technology for its large-scale preparation due to its controllable deposition rate and strong adhesion between the film and the substrate. However, existing processes have many technical bottlenecks: with the upgrading of wafer size (e.g., eight inches), the gas concentration field and temperature field in the traditional magnetron sputtering chamber are prone to radial inhomogeneity, resulting in significant differences in the thickness and phase composition of vanadium oxide films between the wafer center and the edge, making it difficult to meet the uniformity requirements of high-precision devices; moreover, existing processes often require deposition or annealing temperatures above 300°C to ensure the crystal quality and phase transition stability of the film. This high temperature conflicts with the low-temperature process of silicon-based integrated circuits, easily damaging the wafer substrate and causing interlayer element interdiffusion, thus degrading the film performance. Furthermore, during wafer pretreatment, some cleaning and etching methods cannot completely remove surface organic residues and natural oxide layers, or improper hydrofluoric acid etching solution ratios can lead to increased wafer roughness, affecting the quality of subsequent layer deposition. As an Al2O3 buffer layer that isolates the substrate from vanadium oxide, existing processes do not precisely control substrate temperature, RF power, and operating pressure, which can easily result in insufficient density of the buffer layer and difficulty in suppressing interlayer diffusion. At the same time, vanadium oxide thin film annealing often uses uniform parameters across the entire wafer surface without considering the stress differences on the wafer surface. High-stress areas are prone to cracking and warping defects, which severely restricts its application in the large-scale fabrication of large-size wafers and high-precision devices. Summary of the Invention

[0003] To overcome the shortcomings of existing technologies in vanadium oxide thin film preparation, such as incompatibility between high-temperature processes and low-temperature processes for silicon-based integrated circuits, poor film uniformity on large-size wafers, difficulty in controlling the quality of wafer pretreatment and Al2O3 buffer layer preparation, and the tendency for annealing to cause film defects due to stress differences, this invention provides a low-temperature preparation method for highly uniform vanadium oxide thin films.

[0004] The technical solution of this invention is as follows:

[0005] A low-temperature preparation method for highly uniform vanadium oxide thin films includes the following steps:

[0006] S1: After ultrasonic cleaning of the P-type single crystal silicon wafer with organic solvent and deionized water, its surface is etched with an etching solution prepared by mixing electronic grade hydrofluoric acid with deionized water at a volume ratio of 1:50 (49% by mass). The wafer is then rinsed with deionized water and vacuum dried to form a substrate for subsequent thin film deposition.

[0007] S2: Place the substrate in the magnetron sputtering chamber, using an Al2O3 ceramic target as the sputtering target, and evacuate to a vacuum level not exceeding 2 × 10⁻⁶. 4 Pa, pure Ar is introduced as sputtering gas, and an Al2O3 buffer layer with a thickness of 5-10 nm is sputtered and deposited under the conditions of substrate temperature 100℃, RF power 150W, and working pressure 0.5Pa.

[0008] S3: Replace the sputtering target with a vanadium metal target. Specifically, introduce a ternary mixed gas consisting of Ar, O2, and N2 into the chamber. The total flow rate of the mixed gas is 40 sccm, with the Ar flow rate constant at 25 sccm, the N2 flow rate constant at 1-1.5 sccm, and the O2 flow rate dynamically controlled according to the radial position of the wafer. Through independent gas paths, the O2 flow rate in the central region of the substrate is controlled within the range of 9.5-10.5 sccm, while the O2 flow rate in the edge region of the substrate is controlled within the range of 10.3-11.3 sccm. Under this atmosphere, with a substrate temperature of 180℃, DC power of 200W, working pressure of 0.6Pa, and substrate stage rotation speed of 30 rpm, a vanadium oxide thin film with a thickness of 50-100nm is deposited.

[0009] S4: Maintain the chamber vacuum level not higher than 2×10⁻⁶ -4 Under the condition of Pa, the vanadium oxide film is subjected to in-situ rapid thermal annealing. First, the temperature is raised to 190°C at a heating rate of 50°C / s and held for 30-50 seconds. Then, the temperature is raised to 200°C and held for 10-25 seconds. Finally, the temperature is cooled to below 80°C at a rate not exceeding 30°C / s.

[0010] Further, in one embodiment, step S3 includes the following steps:

[0011] A high-energy electron diffraction system was used to monitor the phase composition of the deposited vanadium oxide thin film in real time, and a closed-loop feedback mechanism for phase process parameters was established. When the high-energy electron diffraction system detected V₂O₅ diffraction characteristics, the N₂ flow rate was automatically increased; when V₆O₅ diffraction characteristics were detected, the flow rate was automatically increased. 13 When diffraction characteristics are observed, the O2 flow rate is automatically increased.

[0012] Furthermore, in one embodiment, the control logic of the phase process parameter feedback closed loop is as follows:

[0013] When the high-energy electron diffraction system identifies the characteristic diffraction peak of V2O5, the intensity of this characteristic peak is calculated as a proportion of the total intensity of characteristic peaks of all vanadium oxide phases. If the proportion is greater than 5% but not more than 10%, the N2 flow rate is increased in steps of 0.1 sccm each time, and held for 30 seconds after each adjustment, until the proportion is ≤5%. If the proportion is greater than 10%, the N2 flow rate is increased in steps of 0.2 sccm each time, and held for 20 seconds after each adjustment, until the proportion does not exceed 5%, and the N2 flow rate does not exceed 1.5 sccm after a single adjustment.

[0014] When the high-energy electron diffraction system detects V6O 13 When calculating the characteristic diffraction peak, the intensity of the characteristic peak is calculated as a percentage of the total intensity of all characteristic peaks of the vanadium oxide phases. If the percentage is greater than 5% but not more than 10%, the O2 flow rate is increased in steps of 0.2 sccm each time, and held for 30 seconds after each adjustment, until the percentage does not exceed 5%. If the percentage is greater than 10%, the O2 flow rate is increased in steps of 0.3 sccm each time, and held for 20 seconds after each adjustment, until the percentage does not exceed 5%, and the O2 flow rate in the central region does not exceed 10.5 sccm and the O2 flow rate in the edge region does not exceed 11.3 sccm after adjustment.

[0015] Furthermore, in one embodiment, step S3, the dynamic control of the partition includes the following steps:

[0016] Based on the real-time sputtering power fluctuation ΔP, the O2 flow rate zone setpoint is adjusted to compensate for the following expression:

[0017] ΔO2=0.1×|ΔP|

[0018] Where ΔO2 represents the change in O2.

[0019] Furthermore, in one embodiment, in step S3, the O2 flow rate in the edge region is additionally compensated based on the temperature difference ΔT between the substrate edge region and the center region monitored by an infrared thermal imager, as expressed below:

[0020] ΔO2_T=0.2×ΔT

[0021] Wherein, ΔO2_T represents the amount of fine-tuning change in oxygen flow rate.

[0022] Furthermore, in one embodiment, in step S4, the in-situ rapid thermal annealing is stress-zoned time-controlled annealing, which includes the following steps:

[0023] The Mize stress distribution map on the substrate surface was obtained by scanning with an infrared stress tester. Areas with stress values ​​greater than 50 MPa were marked as high-stress areas. The second-stage heat preservation time t2 of the high-stress areas was shortened, as shown in the following expression:

[0024] t2'=t2-(σ-50)×0.1

[0025] Where σ is the stress value in the region, and t2' is the adjusted heat preservation time.

[0026] Furthermore, in one embodiment, step S4 further includes the following steps:

[0027] After in-situ rapid thermal annealing, the vanadium oxide film is subjected to plasma-enhanced chemical vapor deposition (PECVD) with SiH4 and N2O as reactants, and a 5 nm thick SiO2 protective layer is deposited on the surface of the vanadium oxide film at 150 °C. After the protective layer is deposited, a vacuum annealing process is performed at 150 °C for 30 minutes.

[0028] A vanadium oxide thin film, wherein the vanadium oxide thin film is prepared by the low-temperature preparation method of the wafer high uniformity vanadium oxide thin film described in the above embodiments.

[0029] Furthermore, in one embodiment, the vanadium oxide thin film is integrated onto an 8-inch wafer.

[0030] Furthermore, in one embodiment, the vanadium oxide thin film is used to prepare the sensor array of an infrared detector chip or the thermo-optical phase modulation unit of a silicon-based photonic integrated chip.

[0031] According to the above-described scheme, the beneficial effects of this invention are as follows: the low-temperature process design (temperature ≤200℃ throughout the process) is compatible with silicon-based integrated circuit manufacturing processes, avoiding high-temperature damage to the wafer and interlayer interdiffusion; relying on specific etching solution pretreatment and precise buffer layer sputtering parameters, the cleanliness of the substrate and the density of the buffer layer can be guaranteed, solving the problems of pretreatment and buffer layer quality; combined with wafer radial partitioning oxygen control and substrate stage rotation speed optimization, the uniformity of large-size wafer thin films can be improved; through stepped in-situ rapid thermal annealing, stress-induced film cracking and warping defects are reduced, ultimately providing highly stable and highly uniform vanadium oxide thin films for the large-scale fabrication of high-precision devices. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic flowchart of the preparation method in this embodiment. Detailed Implementation

[0034] The present invention will now be further described with reference to the accompanying drawings and embodiments:

[0035] like Figure 1 As shown, a low-temperature preparation method for a highly uniform vanadium oxide thin film includes the following steps:

[0036] S1: After ultrasonic cleaning of the P-type single crystal silicon wafer with organic solvent and deionized water, its surface is etched with an etching solution prepared by mixing electronic grade hydrofluoric acid with deionized water at a volume ratio of 1:50 (49% by mass). The wafer is then rinsed with deionized water and vacuum dried to form a substrate for subsequent thin film deposition.

[0037] S2: Place the substrate in the magnetron sputtering chamber, using an Al2O3 ceramic target as the sputtering target, and evacuate to a vacuum level not exceeding 2 × 10⁻⁶. 4 Pa, pure Ar is introduced as sputtering gas, and an Al2O3 buffer layer with a thickness of 5-10 nm is sputtered and deposited under the conditions of substrate temperature 100℃, RF power 150W, and working pressure 0.5Pa.

[0038] S3: Replace the sputtering target with a vanadium metal target. Specifically, introduce a ternary mixed gas consisting of Ar, O2, and N2 into the chamber. The total flow rate of the mixed gas is 40 sccm, with the Ar flow rate constant at 25 sccm, the N2 flow rate constant at 1-1.5 sccm, and the O2 flow rate dynamically controlled according to the radial position of the wafer. Through independent gas paths, the O2 flow rate in the central region of the substrate is controlled within the range of 9.5-10.5 sccm, while the O2 flow rate in the edge region of the substrate is controlled within the range of 10.3-11.3 sccm. Under this atmosphere, with a substrate temperature of 180℃, DC power of 200W, working pressure of 0.6Pa, and substrate stage rotation speed of 30 rpm, a vanadium oxide thin film with a thickness of 50-100nm is deposited.

[0039] In one embodiment, the present invention achieves low-temperature preparation of highly uniform vanadium oxide thin films through optimized process steps, exhibiting significant technical advantages and practical value: In step S1, ultrasonic cleaning with organic solvent and deionized water combined with etching solution treatment in a specific ratio (49% electronic-grade hydrofluoric acid to deionized water volume ratio 1:50) thoroughly removes organic residues and natural oxide layers from the surface of P-type single-crystal silicon wafers, while avoiding excessive etching that leads to increased surface roughness. The substrate formed after vacuum drying provides a clean and flat base for subsequent thin film deposition, effectively solving the problem of difficult substrate quality control in traditional pretreatment processes; Step S2, through precise control of magnetron sputtering parameters (substrate temperature 100℃, RF power 150W, working pressure 0.5Pa), operates in a high vacuum environment (≤2×10⁻⁶). -4 A 5-10 nm thick buffer layer (Al2O3) is deposited under the substrate (Pa), which significantly improves the density and uniformity of the buffer layer and effectively isolates element diffusion between the wafer substrate and the subsequent vanadium oxide film, overcoming the defect of insufficient protection effect caused by parameter runaway in existing buffer layers. In step S3, after replacing the vanadium metal target, a ternary mixed gas of Ar, O2, and N2 is introduced (total flow rate 40 sccm, Ar flow rate 25 sccm, N2 flow rate 1-1.5 sccm), and the O2 flow rate is dynamically controlled radially in separate gas paths (9.5-10.5 sccm in the central region and 10.3-11.3 sccm in the edge region), in conjunction with a substrate temperature of 18°C. With a substrate stage speed of 0℃, 200W DC power, 0.6Pa operating pressure, and 30 rpm, this technology can not only precisely control the phase composition of vanadium oxide thin films, but also effectively improve the radial non-uniformity of the gas concentration field and temperature field on large-size wafers. This significantly improves the thickness and phase uniformity of the deposited 50-100nm thick vanadium oxide thin films. At the same time, the low-temperature process throughout (temperature of each step ≤180℃) is directly compatible with the low-temperature process requirements of silicon-based integrated circuits, avoiding damage to the wafer substrate and inter-layer element interdiffusion caused by high temperatures. This provides stable and highly uniform vanadium oxide thin films for the large-scale fabrication of high-precision devices such as infrared detector chips and silicon-based photonic integrated chips.

[0040] Step S3 includes the following steps:

[0041] A high-energy electron diffraction system was used to monitor the phase composition of the deposited vanadium oxide thin film in real time, and a closed-loop feedback mechanism for phase process parameters was established. When the high-energy electron diffraction system detected V₂O₅ diffraction characteristics, the N₂ flow rate was automatically increased; when V₆O₅ diffraction characteristics were detected, the flow rate was automatically increased. 13 When diffraction characteristics are observed, the O2 flow rate is automatically increased;

[0042] In one embodiment, step S3 further introduces a high-energy electron diffraction system to monitor the vanadium oxide thin film phase in real time during the deposition process and constructs a closed-loop feedback mechanism for phase process parameters. This design significantly improves the accuracy and dynamic response capability of the thin film phase control: when the system detects V2O5 diffraction characteristics, it automatically increases the N2 flow rate, while when it detects V6O... 13 The system automatically increases the O2 flow rate during diffraction, enabling real-time capture and correction of phase deviations during thin film deposition. This avoids the phase loss or rework issues caused by offline detection in traditional processes. Real-time dynamic adjustment achieves precise targeting of the vanadium oxide phase, reducing the presence of non-target phases (such as V2O5 and V6O). 13 The generation ratio of vanadium oxide thin films is adjusted to further ensure the stability of phase transition characteristics and electrical properties, providing a more reliable physical basis for the application of thin films in high-precision scenarios such as infrared detection and photonic integration.

[0043] In step S3, the dynamic control of the partition includes the following steps:

[0044] Based on the real-time sputtering power fluctuation ΔP, the O2 flow rate zone setpoint is adjusted to compensate for the following expression:

[0045] ΔO2=0.1×|ΔP|

[0046] Wherein, ΔO2 represents the change in O2;

[0047] In one embodiment, in step S3, the partitioned dynamic control further combines the real-time monitored sputtering power fluctuation ΔP, and compensates and adjusts the O2 flow rate partition setting value through the expression ΔO2=0.1×|ΔP|. This design effectively improves the anti-interference capability and stability of the process: power fluctuations during sputtering can easily lead to deviations in the sputtering rate of the target material and the particle energy distribution, thereby affecting the deposition rate and phase composition of the vanadium oxide film. However, by calculating the absolute value of the power fluctuation in real time and dynamically adjusting the O2 flow rate proportionally, the adverse effects of power fluctuations can be quickly offset, ensuring that the oxygen partial pressure and sputtering conditions in different radial regions are always maintained within the target range, avoiding film thickness deviations or phase shifts caused by power fluctuations. Especially in the preparation of large-size wafers, this compensation mechanism can further reduce the film performance differences in different regions of the wafer, significantly improve the overall uniformity and batch consistency of the vanadium oxide film, and provide a more reliable process guarantee for large-scale production.

[0048] In step S3, the O2 flow rate in the edge region is additionally compensated based on the temperature difference ΔT between the substrate edge region and the center region monitored by the infrared thermal imager, as expressed below:

[0049] ΔO2_T=0.2×ΔT

[0050] Where ΔO2_T represents the amount of fine-tuning change in oxygen flow rate;

[0051] In one embodiment, in step S3, the temperature difference ΔT between the edge region and the center region of the substrate is monitored in real time using an infrared thermal imager. Additional fine compensation for the O2 flow rate in the edge region is then performed based on the expression ΔO2_T = 0.2 × ΔT. This design precisely solves the problem of thin film performance deviation caused by uneven temperature distribution during large-size wafer deposition. In traditional magnetron sputtering processes, the substrate edge is prone to significant temperature differences with the center region due to factors such as rapid heat dissipation and close proximity to the chamber wall. These temperature differences directly affect the reactivity of vanadium target atoms with oxygen atoms, leading to deviations in the oxidation degree and crystallization state of the vanadium oxide film in the edge region compared to the center region, thereby reducing the overall film uniformity. This invention captures this temperature difference in real time using an infrared thermal imager and then dynamically adjusts the O2 flow rate in the edge region using a quantitative compensation formula. When the temperature difference increases, the O2 flow rate in the edge region increases proportionally with ΔT, specifically compensating for insufficient oxidation caused by lower temperatures. When the temperature difference decreases, the flow rate compensation decreases accordingly to avoid over-oxidation, thereby ensuring a high degree of consistency in the oxidation degree and phase composition of the vanadium oxide film in the substrate edge and center regions. This additional compensation mechanism works in synergy with the previous sputtering power fluctuation compensation to further refine the control of deposition conditions in different radial regions of the wafer. It effectively eliminates the hidden interference factor of temperature non-uniformity and significantly improves the radial uniformity and microstructure consistency of vanadium oxide films on large-size wafers, providing a key guarantee for the array performance uniformity of subsequent devices (such as infrared detector sensitive element arrays).

[0052] The control logic of the closed-loop feedback of phase process parameters is as follows:

[0053] When the high-energy electron diffraction system identifies the characteristic diffraction peak of V2O5, the intensity of this characteristic peak is calculated as a proportion of the total intensity of characteristic peaks of all vanadium oxide phases. If the proportion is greater than 5% but not more than 10%, the N2 flow rate is increased in steps of 0.1 sccm each time, and held for 30 seconds after each adjustment, until the proportion is ≤5%. If the proportion is greater than 10%, the N2 flow rate is increased in steps of 0.2 sccm each time, and held for 20 seconds after each adjustment, until the proportion does not exceed 5%, and the N2 flow rate does not exceed 1.5 sccm after a single adjustment.

[0054] When the high-energy electron diffraction system detects V6O 13When calculating the characteristic diffraction peak, the intensity of the characteristic peak is calculated as a percentage of the total intensity of all characteristic peaks of the vanadium oxide phases. If the percentage is greater than 5% but not more than 10%, the O2 flow rate is increased in steps of 0.2 sccm each time, and held for 30 seconds after each adjustment, until the percentage does not exceed 5%. If the percentage is greater than 10%, the O2 flow rate is increased in steps of 0.3 sccm each time, and held for 20 seconds after each adjustment, until the percentage does not exceed 5%, and the O2 flow rate in the central region does not exceed 10.5 sccm and the O2 flow rate in the edge region does not exceed 11.3 sccm after adjustment.

[0055] In one embodiment, the control logic of the phase process parameter feedback closed loop controls the non-target phases (V2O5, V6O) through... 13 The graded response of characteristic diffraction peak intensity ratios enables precise and dynamic control of the vanadium oxide thin film phase, significantly improving the stability and reliability of phase control. For the V2O5 characteristic peak ratio, a stepwise N2 increase strategy of 0.1 sccm / cycle and 30-second hold is used in the 5%-10% range; when the ratio is >10%, an adjustment scheme of 0.2 sccm / cycle and 20-second hold is used. This ensures fine correction for slight deviations to avoid over-adjustment, while accelerating the adjustment rate to quickly suppress V2O5 formation when deviations are more severe. Simultaneously, the N2 flow rate is limited to no more than 1.5 sccm to ensure the adjustment does not exceed the process safety range. For V6O... 13 For the characteristic peak percentage, O2 flow rate adjustments were applied at 0.2 sccm / cycle (hold for 30 seconds) and 0.3 sccm / cycle (hold for 20 seconds) for the 5%-10% and >10% ranges, respectively. The upper limit of O2 flow rate in the central and edge regions was strictly controlled. This approach effectively compensates for insufficient oxidation while preventing excessive oxidation that could lead to new phase deviations. This graded, time-limited, and amplitude-limited closed-loop control logic solves the problems of delayed phase control response and excessive or insufficient adjustment ranges in traditional processes. It can stably control the proportion of non-target phases below 5%, effectively ensuring the purity and consistency of the target phase in vanadium oxide thin films. This improves key performance characteristics such as phase transition sensitivity and electrical stability, providing a uniform core functional layer for high-precision devices such as infrared detectors and silicon-based photonic integrated chips. Simultaneously, it enhances the repeatability and adaptability to large-scale production.

[0056] S4: Maintain the chamber vacuum level not higher than 2×10⁻⁶ -4 Under the condition of Pa, the vanadium oxide film was subjected to in-situ rapid thermal annealing. First, the temperature was raised to 190°C at a heating rate of 50°C / s and held for 30-50 seconds. Then, the temperature was raised to 200°C and held for 10-25 seconds. Finally, the temperature was cooled to below 80°C at a rate not exceeding 30°C / s.

[0057] In one embodiment, step S4 employs an in-situ, vacuum, stepped temperature-controlled rapid thermal annealing design. This design effectively avoids multiple defects of traditional annealing processes while ensuring the crystallization quality of the vanadium oxide thin film, significantly improving film performance and process compatibility: maintaining the chamber vacuum level no higher than 2 × 10⁻⁶. -4 In-situ treatment of Pa avoids oxidation or the introduction of impurities during annealing due to air contact, ensuring film purity and surface cleanliness, and solving the film contamination problem easily caused by traditional non-in-situ annealing. A rapid heating rate of 50°C per second shortens the film's residence time in the low-temperature region, reducing abnormal grain growth and preventing interdiffusion of elements between the wafer substrate, film, and buffer layer caused by prolonged heating. The stepped heat preservation design at 190°C (holding for 30-50 seconds) and 200°C (holding for 10-25 seconds) allows for phased film lattice repair and crystallization improvement—the low-temperature (190°C) heat preservation helps eliminate impurities during deposition. The resulting lattice defects are addressed by short-term holding at a high temperature (200℃), which further enhances crystallinity while preventing damage to the P-type single-crystal silicon wafer or disruption of the Al2O3 buffer layer's isolation effect due to prolonged high-temperature exposure. The maximum temperature throughout the process is controlled at 200℃, perfectly meeting the low-temperature process requirements of silicon-based integrated circuits. This overcomes the substrate damage and interlayer interdiffusion problems caused by traditional high-temperature annealing (generally >300℃). Finally, cooling to below 80℃ at a rate not exceeding 30℃ / s mitigates the sudden increase in internal stress caused by rapid temperature drops, effectively suppressing mechanical defects such as cracking and warping, and resolving the stress concentration problem caused by traditional rapid cooling. This annealing scheme, through precise temperature rate and timing control, improves the crystal integrity and structural stability of vanadium oxide films while ensuring key performance characteristics such as phase transition sensitivity and electrical consistency. It provides a reliable core functional layer for devices such as infrared detector sensitive element arrays and silicon-based photonic integrated chip thermo-optic modulation units, while also enhancing process repeatability and adaptability for large-scale production.

[0058] In step S4, the in-situ rapid thermal annealing is stress-zoned time-controlled annealing, which includes the following steps:

[0059] The Mize stress distribution map on the substrate surface was obtained by scanning with an infrared stress tester. Areas with stress values ​​greater than 50 MPa were marked as high-stress areas. The second-stage heat preservation time t2 in the high-stress areas was shortened, as shown in the following expression:

[0060] t2'=t2-(σ-50)×0.1

[0061] Where σ is the stress value in the region, and t2' is the adjusted heat preservation time;

[0062] In one embodiment, the stress-zoned controlled-time annealing design used in step S4 effectively solves the problem of thin film mechanical defects caused by stress distribution differences in traditional uniform annealing by specifically adjusting the annealing parameters of high-stress areas, significantly improving the structural integrity and stability of vanadium oxide thin films. Using an infrared stress tester to scan and obtain the Mises stress distribution map on the substrate surface, high-stress areas with stress values ​​greater than 50 MPa can be accurately identified. These areas have higher interfacial stress between the film and the substrate / buffer layer, or higher internal stress accumulated during deposition. Under uniform annealing conditions, these areas are more prone to uneven stress release due to prolonged high-temperature action, inducing defects such as cracking and warping. This invention uses the formula t2'=t2-(σ-50)×0.1 to quantitatively shorten the second-stage (200℃) holding time of high-stress areas—the higher the stress value, the greater the reduction. This avoids exacerbating stress concentration or thermal mismatch in high-stress areas due to excessively long holding times, and balances the crystallization requirements and stress release through precise time adjustment. Meanwhile, the low-stress areas maintain their original holding time, ensuring that crystallization quality is not affected. This zoned and differentiated timing control strategy achieves the dual goals of "stress control in high-stress areas and crystallization preservation in low-stress areas." It reduces mechanical defects such as film cracking and delamination, while ensuring the overall crystal integrity and phase transition performance consistency of the film. This provides a more reliable structural foundation for the application of vanadium oxide films in large-size wafers and high-precision devices (such as infrared detector sensitive element arrays). At the same time, it enhances the adaptability of the process to different stress distribution scenarios and improves the yield and stability of films in large-scale production.

[0063] Step S4 also includes the following steps:

[0064] After in-situ rapid thermal annealing of the vanadium oxide thin film, a 5 nm thick SiO2 protective layer was deposited on the surface of the vanadium oxide thin film using plasma-enhanced chemical vapor deposition with SiH4 and N2O as reactants at 150 °C. After the protective layer was deposited, a vacuum annealing treatment was performed at 150 °C for 30 minutes.

[0065] In one embodiment, the SiO2 protective layer deposition and subsequent vacuum annealing following in-situ rapid thermal annealing in step S4 further enhance the environmental stability and structural integrity of the vanadium oxide film, providing a key guarantee for the long-term reliable operation of the device: Plasma-enhanced chemical vapor deposition (PECVD) is used with SiH4 and N2O as reactant gases to deposit a 5nm thick SiO2 protective layer at a low temperature of 150℃. This not only leverages the high activity of plasma to achieve dense deposition at low temperatures, avoiding damage to the phase and properties of the formed vanadium oxide film caused by high temperatures, but also effectively isolates the external environment through the thin and uniform SiO2 layer. This design protects vanadium oxide films from corrosion by water vapor, oxygen, and pollutants, preventing oxidation, degradation, or surface contamination during storage or device fabrication. The 5nm thickness avoids the adverse effects of excessively thick protective layers on the electrical and optical properties (such as phase transition sensitivity and light transmittance). The 150°C, 30-minute vacuum annealing after protective layer deposition eliminates internal stress generated within the SiO2 layer during deposition, improving its interfacial adhesion to the vanadium oxide film and preventing stress-induced peeling or cracking. It also further optimizes the density and uniformity of SiO2, enhancing its protective effect. This design is consistent with the previously described low-temperature process system, maintaining a temperature below 150°C throughout, perfectly compatible with low-temperature silicon-based integrated circuit processes. It solves the problem of traditional high-temperature deposited protective layers easily damaging vanadium oxide films or causing interfacial diffusion, significantly extending the storage life and device operational stability of vanadium oxide films. This lays a more solid foundation for its application in long-term, high-precision devices such as infrared detectors and silicon-based photonic integrated chips.

[0066] A vanadium oxide thin film is prepared by the low-temperature preparation method of the high-uniformity vanadium oxide thin film on wafers described in the above embodiments. The vanadium oxide thin film is integrated on an 8-inch wafer. The vanadium oxide thin film is used to prepare the sensor array of an infrared detector chip or the thermo-optical phase modulation unit of a silicon-based photonic integrated chip. In one embodiment, the vanadium oxide thin film of the present invention is prepared by the low-temperature preparation method of the high-uniformity vanadium oxide thin film described above, and is integrated on an 8-inch wafer. It is specifically designed for the sensor array of an infrared detector chip and the thermo-optical phase modulation unit of a silicon-based photonic integrated chip, and has the core performance advantage of precisely adapting to application scenarios: relying on the low-temperature process throughout (maximum temperature ≤200℃), the film can be perfectly compatible with the integrated circuit process of 8-inch silicon-based wafers, avoiding damage to the wafer substrate and surrounding devices by high temperature, and meeting the process adaptability requirements of large-scale wafer production; benefiting from the radial partitioning dynamic control of O2 flow during the preparation process (including power fluctuation and temperature difference compensation). High-energy electron diffraction real-time closed-loop phase control ensures that the film thickness (50-100nm) deviation across the entire 8-inch wafer is ≤3%, and the phase composition is highly uniform (non-target phase ratio ≤5%). This guarantees the response consistency of thousands of units in the infrared detector's sensitive element array, solving the problem of insufficient array detection accuracy caused by performance differences in traditional large-size thin films. Simultaneously, stress-zoned time-controlled annealing and SiO2 protective layer treatment reduce the film's cracking and warping defect rate to below 0.5%, and it possesses excellent resistance to moisture and contamination. During operation of the thermo-optical phase modulation unit, it can stably withstand stress changes caused by temperature cycling, ensuring long-term stability of modulation efficiency. This vanadium oxide thin film, through precise matching of process and performance, provides core functional layer support for the high-yield mass production of 8-inch wafer-level infrared detector chips and silicon-based photonic integrated chips, significantly improving device consistency and reliability.

[0067] To verify the performance improvement effect of the low-temperature preparation method for highly uniform vanadium oxide thin films of this invention, a comparison was made with key indicators of the traditional preparation method (high-temperature sputtering + uniform annealing process), and detailed results are shown in Table 1. The data in the table are based on comparative experimental results under the same test conditions (8-inch P-type single-crystal silicon wafer, 50-100nm vanadium oxide thin film); mAP (uniformity) is an index that comprehensively evaluates the consistency of film thickness, phase composition, and electrical properties in different regions of the wafer; a higher value indicates better uniformity. This table intuitively demonstrates the significant improvements of this invention in film uniformity, phase purity, defect control, low-temperature compatibility, and stability, verifying the actual effects of the full-process low-temperature process, zoned oxygen control, and stress-zoned annealing techniques.

[0068] The performance improvement effect of the low-temperature preparation method of the present invention is shown in Table 1:

[0069]

[0070]

[0071] Table 1

[0072] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

[0073] The present invention has been described above with reference to the accompanying drawings. Obviously, the implementation of the present invention is not limited to the above-described manner. Any improvements made using the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other situations without modification, are all within the protection scope of the present invention.

Claims

1. A low-temperature preparation method for highly uniform vanadium oxide thin films, characterized in that, Includes the following steps: S1: After ultrasonic cleaning of the P-type single crystal silicon wafer with organic solvent and deionized water, its surface is etched with an etching solution prepared by mixing electronic grade hydrofluoric acid with deionized water at a volume ratio of 1:50 (49% by mass). The wafer is then rinsed with deionized water and vacuum dried to form a substrate for subsequent thin film deposition. S2: Place the substrate in the magnetron sputtering chamber, using an Al2O3 ceramic target as the sputtering target, and evacuate to a vacuum level not exceeding 2 × 10⁻⁶. 4 Pa, pure Ar is introduced as sputtering gas, and an Al2O3 buffer layer with a thickness of 5-10 nm is sputtered and deposited under the conditions of substrate temperature 100℃, RF power 150W, and working pressure 0.5Pa. S3: Replace the sputtering target with a vanadium metal target. Specifically, introduce a ternary mixed gas consisting of Ar, O2, and N2 into the chamber. The total flow rate of the mixed gas is 40 sccm, with the Ar flow rate constant at 25 sccm, the N2 flow rate constant at 1-1.5 sccm, and the O2 flow rate dynamically controlled according to the radial position of the wafer. Through independent gas paths, the O2 flow rate in the central region of the substrate is controlled within the range of 9.5-10.5 sccm, while the O2 flow rate in the edge region of the substrate is controlled within the range of 10.3-11.3 sccm. Under this atmosphere, with a substrate temperature of 180℃, DC power of 200W, working pressure of 0.6Pa, and substrate stage rotation speed of 30 rpm, a vanadium oxide thin film with a thickness of 50-100nm is deposited. S4: Maintain the chamber vacuum level not higher than 2×10⁻⁶ -4 Under the condition of Pa, the vanadium oxide film is subjected to in-situ rapid thermal annealing. First, the temperature is raised to 190°C at a heating rate of 50°C / s and held for 30-50 seconds. Then, the temperature is raised to 200°C and held for 10-25 seconds. Finally, the temperature is cooled to below 80°C at a rate not exceeding 30°C / s.

2. The low-temperature preparation method of a highly uniform vanadium oxide thin film according to claim 1, characterized in that, Step S3 includes the following steps: A high-energy electron diffraction system was used to monitor the phase composition of the deposited vanadium oxide thin film in real time, and a closed-loop feedback mechanism for phase process parameters was established. When the high-energy electron diffraction system detected V₂O₅ diffraction characteristics, the N₂ flow rate was automatically increased; when V₆O₅ diffraction characteristics were detected, the flow rate was automatically increased. 13 When diffraction characteristics are observed, the O2 flow rate is automatically increased.

3. The low-temperature preparation method of a highly uniform vanadium oxide thin film according to claim 2, characterized in that, The control logic for the closed-loop feedback of the phase process parameters is as follows: When the high-energy electron diffraction system identifies the characteristic diffraction peak of V2O5, the intensity of this characteristic peak is calculated as a proportion of the total intensity of characteristic peaks of all vanadium oxide phases. If the proportion is greater than 5% but not more than 10%, the N2 flow rate is increased in steps of 0.1 sccm each time, and held for 30 seconds after each adjustment, until the proportion is ≤5%. If the proportion is greater than 10%, the N2 flow rate is increased in steps of 0.2 sccm each time, and held for 20 seconds after each adjustment, until the proportion does not exceed 5%, and the N2 flow rate does not exceed 1.5 sccm after a single adjustment. When the high-energy electron diffraction system detects V6O 13 When calculating the characteristic diffraction peak, the intensity of the characteristic peak is calculated as a percentage of the total intensity of all characteristic peaks of the vanadium oxide phases. If the percentage is greater than 5% but not more than 10%, the O2 flow rate is increased in steps of 0.2 sccm each time, and held for 30 seconds after each adjustment, until the percentage does not exceed 5%. If the percentage is greater than 10%, the O2 flow rate is increased in steps of 0.3 sccm each time, and held for 20 seconds after each adjustment, until the percentage does not exceed 5%, and the O2 flow rate in the central region does not exceed 10.5 sccm and the O2 flow rate in the edge region does not exceed 11.3 sccm after adjustment.

4. The low-temperature preparation method of a highly uniform vanadium oxide thin film according to claim 1, characterized in that, In step S3, the dynamic partition control includes the following steps: Based on the real-time sputtering power fluctuation ΔP, the O2 flow rate zone setpoint is adjusted to compensate for the following expression: ΔO2=0.1×|ΔP| Where ΔO2 represents the change in O2.

5. The low-temperature preparation method of a highly uniform vanadium oxide thin film according to claim 4, characterized in that, In step S3, the temperature difference ΔT between the edge and center areas of the substrate, monitored by an infrared thermal imager, is used to additionally compensate for the O2 flow rate in the edge area, as expressed below: ΔO_T = 0.2 × ΔT Wherein, ΔO2_T represents the amount of fine-tuning change in oxygen flow rate.

6. The low-temperature preparation method of a highly uniform vanadium oxide thin film according to claim 1, characterized in that, In step S4, the in-situ rapid thermal annealing is stress-zoned time-controlled annealing, which includes the following steps: The Mize stress distribution map on the substrate surface was obtained by scanning with an infrared stress tester. Areas with stress values ​​greater than 50 MPa were marked as high-stress areas. The second-stage heat preservation time t2 of the high-stress areas was shortened, as shown in the following expression: t2'=t2-(σ-50)×0.1 Where σ is the stress value in the region, and t2' is the adjusted heat preservation time.

7. The low-temperature preparation method of a highly uniform vanadium oxide thin film according to claim 1, characterized in that, Step S4 further includes the following steps: After in-situ rapid thermal annealing, the vanadium oxide film is subjected to plasma-enhanced chemical vapor deposition (PECVD) with SiH4 and N2O as reactants, and a 5 nm thick SiO2 protective layer is deposited on the surface of the vanadium oxide film at 150 °C. After the protective layer is deposited, a vacuum annealing process is performed at 150 °C for 30 minutes.

8. A vanadium oxide thin film, characterized in that: The vanadium oxide thin film is prepared by the low-temperature preparation method of the wafer high uniformity vanadium oxide thin film according to any one of claims 1 to 7.

9. A vanadium oxide thin film according to claim 8, characterized in that: The vanadium oxide thin film is integrated onto an 8-inch wafer.

10. A vanadium oxide thin film according to claim 8, characterized in that: The vanadium oxide thin film is used to prepare the sensitive element array of an infrared detector chip or the thermo-optical phase modulation unit of a silicon-based photonic integrated chip.

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