Method and device for detecting and repairing PCIE (Peripheral Component Interface Express) link hot plug scene

Abstract

The embodiment of the invention provides a PCIE link hot plug scene detection and repair method and device, and the method comprises the steps: executing an initialization operation which at least comprises the steps: enabling a hot plug management module to receive and forward a reset control signal between a root complex and an end point through configuration, and obtaining the information of connected PCIE equipment; collecting link state data and physical plugging state information from a register of the PCIE controller and a pin related to hot plugging; judging whether the PCIE link is in an abnormal state or not based on link state data and the physical plugging state information; and in response to the abnormal state of the PCIE link, selecting a repair strategy according to the type of the abnormal state, generating a repair control sequence containing a reset control signal, and issuing the repair control sequence through the hot plug management module to trigger link recovery. By adopting the above scheme, rapid detection and automatic repair of the abnormal state of the PCIE link and stable recovery of the link can be realized.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a method and apparatus for detecting and repairing hot-plugging scenarios of PCIe links. Background Technology

[0002] Peripheral Component Interconnect Express (PCIe), as a high-speed serial communication bus, is widely used for high-speed data transmission between the central processing unit (CPU) and peripherals. In practical applications, hot-plugging of PCIe devices is frequent, such as replacing NVMe SSDs, maintaining GPU modules, or dynamically deploying multi-function expansion cards. Currently, hot-plugging of PCIe devices mainly relies on Basic Input / Output System (BIOS) management and driver software polling detection. However, this polling detection method has several drawbacks, which are particularly prominent in data centers, edge computing nodes, and automotive-grade motherboards, seriously affecting system maintainability and stable operation. Therefore, how to achieve rapid detection, automatic repair, and stable recovery of PCIe link abnormal states is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0003] This application provides a method and apparatus for detecting and repairing PCIe link hot-plugging scenarios, which can realize rapid detection, automatic repair and stable recovery of PCIe link abnormal states.

[0004] According to a first aspect of the embodiments of this application, a method for detecting and repairing PCIe link hot-plugging scenarios is provided, comprising: performing an initialization operation, the initialization operation comprising at least: configuring the hot-plugging management module to receive and forward reset control signals between the root complex and the endpoint, and obtaining information on connected PCIe devices; Link status data and physical plug-in / plug-out status information are acquired from the registers and hot-plug-related pins of the PCIe controller; based on the link status data and physical plug-in / plug-out status information, it is determined whether the PCIe link is in an abnormal state; in response to the PCIe link being in an abnormal state, a repair strategy is selected according to the type of abnormal state, a repair control sequence containing the reset control signal is generated, and sent to the target module and / or endpoint via the hot-plug management module to trigger link recovery; wherein, the endpoint is the PCIe device in the device hierarchy where the target module is located; after performing the repair, the link status and the online status of the PCIe device are checked again, and the link is confirmed to have recovered to a normal working state based on the detection results.

[0005] Optionally, the hot-plug management module includes a complex programmable logic device (CPL) chip; the initialization operation includes: storing and alternating the reset signal through a counter and register set inside the CPL chip; clearing the counter; setting the initial value of the register to 0 to indicate that the PCIe device is in an uninserted state; identifying the PCIe device by reading its identification information, treating it as a connected PCIe device, and updating the register; and / or, the hot-plug management module includes: a PCIe switch chip, which has multiple input / output ports for signal forwarding and processing of multiple PCIe devices; the initialization operation includes: setting the reference frequency of the PCIe switch chip to 100MHz; allocating 256KB of cache space to the PCIe switch chip for storing log information during the hot-plugging process of the PCIe device; reading the boundary registers of each PCIe device to obtain at least one or more of the identification information, bus number, device number, and function number of the corresponding PCIe device.

[0006] Optionally, determining whether a PCIe link is in an abnormal state based on the link status data and the physical plug-in / plug-out status information includes: reading the in-situ status register of each PCIe device and status register information related to link training; determining whether each PCIe device has completed online and is in normal working condition; when a PCIe device is detected to have failed to go online or when there is an abnormal flag outside a preset range in the status register, marking the link where the device is located as an abnormal link; when it is confirmed that the PCIe device is online normally and the link status meets predetermined requirements, using the PCIe device as an optimization and adjustment target.

[0007] Optionally, the registers of the PCIe controller include a link status register and a slot status register. The link status data includes an LTSSM status and a DL_Active bit. The physical plug-in / plug-out status information is a device physical plug-in / plug-out event detected by a GPIO hot-plug signal. When it is detected that the PCIe device has failed to come online or that there is an abnormal flag outside the preset range in the status register, the link where the device is located is marked as an abnormal link. This includes: determining that the link status is not in the L0 state based on the LTSSM status and the DL_Active bit, and determining that the link status is abnormal based on the physical plug-in / plug-out status information when the PCIe device is responding to a preset configuration space access.

[0008] Optionally, in response to the PCIe link being in an abnormal state, a repair strategy is selected based on the type of the abnormal state, including one or more of the following: If the link state transitions from a normal state to an abnormal state and recovers within a first preset time, and the PCIe device is able to respond to some access requests, then the abnormal type is determined to be a momentary power failure type, and the repair strategy includes triggering link retraining; if the link state is in the training or recovery phase within a second preset time and cannot recover to a normal state, then the abnormal type is determined to be a link layer deadlock type, and the repair strategy includes performing a reset operation on the subbus; if the PCIe device does not respond to configuration access requests or remains in an unrecoverable state for a long time, then the abnormal type is determined to be a controller failure type, and the repair strategy includes performing a hot reset and re-enumerating the PCIe device.

[0009] Optionally, before determining whether the PCIe link is in an abnormal state based on the link status data and the physical plug-in / plug-out status information, the method further includes: sending a hot-plug-related control signal to the target module through the hot-plug management module and detecting whether the target module returns the expected response; when the target module is detected to respond normally, transmitting the reset control signal issued by the root complex to the endpoint via the hot-plug management module, so that the endpoint completes power-on and link training; when the target module is detected not to respond to the control signal as expected, generating a simulated working signal by the hot-plug management module to replace the output of the target module, and sending the simulated working signal to the endpoint, so that the endpoint follows the predetermined hot-plug timing sequence. The initialization process is executed; the detection and repair method further includes: adjusting the detection time interval based on the historical fault statistics of the PCIE link hot-plug scenario, wherein the adjustment of the detection time interval includes: recording log information for each hot-plug operation, link abnormal event, and repair behavior, including at least timestamps, operation types, PCIE device identification information involved, and processing results; aggregating the log information within a preset statistical time window to obtain the fault occurrence frequency and repair success rate of each link or endpoint; when the fault frequency of a certain link or endpoint exceeds a preset threshold, shortening the status acquisition cycle for that link or device; and gradually extending the status acquisition cycle when no abnormalities are found in multiple rounds of detection and the system operating load is at a low level.

[0010] Optionally, the detection and repair mechanism further includes: receiving an in-situ signal indicating an in-situ state output by the endpoint; responding to the in-situ signal, when the endpoint is detected to be in an in-situ state and hot-plugging is permitted, sending a reset signal to the endpoint via the hot-plug management module to trigger a hot-plug power-on or power-off operation; during the execution of the reset control sequence, forwarding hot-plug control signals from the root complex or the target module via the hot-plug management module to complete the hot-plugging action; and after the hot-plugging operation is completed, updating the configuration data structure in the PCIe device and generating a hot-plugging log record containing the operation results.

[0011] Optionally, when a hot-plugging operation is detected to have been triggered and the PCIe device is in an unavailable state, it is determined that the hot-plugging operation has failed, and a fault diagnosis result is executed for self-repair or error reporting. The self-repair or error reporting based on the fault diagnosis result includes: collecting multi-source state information related to the hot-plugging operation failure and generating a corresponding context snapshot based on the multi-source state information; constructing an ideal execution path for the hot-plugging operation based on the PCIe device type and system configuration, and comparing the ideal execution path with the recorded sequence of actual execution steps to determine at least one deviation node between the ideal execution path and the actual execution step sequence; constructing a fault causal dependency graph for the deviation node, combining the state information recorded in the context snapshot, and identifying the root cause of the hot-plugging operation failure based on the fault causal dependency graph to obtain a fault diagnosis result; matching the current fault mode with historical fault records, and selecting a target self-repair strategy from a preset self-repair strategy set based on the fault diagnosis result and the matching result.

[0012] Optionally, the hot-swap management module can act as a signal intermediary in different hardware topologies in the following ways: when the target module is directly connected to the root complex, the hot-swap management module is placed between the root complex and the endpoint, so that reset signals and presence signals related to hot-swap are forwarded through the hot-swap management module; when the target module is connected to the root complex through a switch, the hot-swap management module is placed between the switch and the endpoint, so that the hot-swap management module can complete the unified access and forwarding of control signals and status signals from the root complex or the switch.

[0013] According to a second aspect of the embodiments of this application, a detection and repair device for PCIe link hot-plugging scenarios is provided, comprising: an initialization unit configured to perform an initialization operation, the initialization operation including at least: configuring a hot-plug management module to receive and forward a reset control signal between a root complex and an endpoint, and acquiring information about connected PCIe devices; an acquisition unit configured to acquire link status data and physical plug-in / plug-out status information from the registers of the PCIe controller and pins related to hot-plugging; a judgment unit configured to determine whether the PCIe link is in an abnormal state based on the link status data and the physical plug-in / plug-out status information; an execution unit configured to, in response to the PCIe link being in an abnormal state, select a repair strategy according to the type of the abnormal state, generate a repair control sequence containing the reset control signal, and send it to a target module and / or endpoint via the hot-plug management module to trigger link recovery; wherein the endpoint is a PCIe device in the device hierarchy where the target module is located; and a detection unit configured to, after performing repair, re-detect the link status and the online status of the PCIe device, and confirm whether the link has recovered to a normal working state based on the detection result.

[0014] The embodiments of this application, by adopting the above technical solutions, have the following technical effects: By configuring the hot-swap management module during the initialization phase to obtain PCIe device information and collecting link status data and physical plug-in / plug-out status information from the PCIe controller register and hot-swap-related pins, the online status of the PCIe link and devices can be monitored in real time at the hardware level. Combined with the logic of automatically judging link anomalies based on the above status data, rapid detection of abnormal PCIe link states is achieved. Furthermore, when an abnormal PCIe link is detected, a repair strategy is automatically selected according to the anomaly type, generating a repair control sequence including a reset control signal, which is then sent to the target module and / or endpoint via the hot-swap management module to automatically trigger link recovery. This completes the automatic repair of abnormal links without manual intervention. In addition, after the repair is performed, the link status and PCIe device online status are checked again, and the link is confirmed to have returned to normal working state based on the detection results. This forms a closed-loop mechanism of anomaly detection, repair execution, and result verification, thereby ensuring that the repaired PCIe link can be in a stable normal working state and achieving stable link recovery. Attached Figure Description

[0015] The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an improper limitation of this application. Wherein: Figure 1 This is a flowchart of a detection and repair method for a PCIe link hot-plugging scenario in an embodiment of this application; Figure 2This is a flowchart illustrating an abnormal state determination method in an embodiment of this application. Figure 3 This is a schematic diagram of the structure of a detection and repair device for a PCIE link hot-plugging scenario in an embodiment of this application. Detailed Implementation

[0016] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0017] As described in the background section, the polling detection method using Basic Input / Output System (BIS) management and driver software has several drawbacks, specifically: Link detection latency, meaning it cannot identify device plugging / unplugging events in real time, resulting in delayed topology information updates; Link anomaly persistence, meaning the controller retains old device configurations even when an anomaly occurs, leading to BAR address conflicts and MMIO access errors; Limited recovery mechanisms, such as only being able to restore links through system reboot or global reset; Inability to distinguish anomaly types, meaning the hardware and software layers cannot accurately identify the specific causes of link power loss, timing loss, or LTSSM lockup; and Lack of self-healing capabilities, for example, the system can only issue an alarm after detecting an anomaly and cannot actively restore the link, causing prolonged device unavailability.

[0018] To address this, this application proposes a closed-loop mechanism for anomaly detection, repair execution, and result verification, thereby ensuring that the repaired PCIe link can maintain a stable normal working state and achieving stable link recovery. Specifically, by configuring a hot-swap management module during the initialization phase to obtain PCIe device information and collecting link status data and physical plug-in status information from the PCIe controller register and hot-swap-related pins, the online status of the PCIe link and device can be monitored in real time at the hardware level. Combined with the logic of automatically judging link anomalies based on the above status data, rapid detection of abnormal PCIe link states is achieved. Furthermore, when an abnormal PCIe link is detected, a repair strategy is automatically selected according to the anomaly type, a repair control sequence containing a reset control signal is generated, and sent to the target module and / or endpoint via the hot-swap management module to automatically trigger link recovery, thereby completing the automatic repair of abnormal links without manual intervention.

[0019] In addition, the link status and PCIe device online status are checked again after the repair is performed, and the link is confirmed to have returned to normal working status based on the test results. This forms a closed-loop mechanism of anomaly detection, repair execution and result verification, thereby ensuring that the repaired PCIe link can be in a stable normal working state and achieving stable link recovery.

[0020] To enable those skilled in the art to better understand and implement this solution, the following detailed description of the specific solution, principles, advantages, and effects of this application is provided with reference to the accompanying drawings and specific embodiments.

[0021] See Figure 1 The flowchart shown in this application represents a detection and repair method for a PCIe link hot-plugging scenario, as illustrated in the following embodiment. Figure 1 As shown, it includes the following steps: S101, Perform initialization operation, the initialization operation includes at least: configuring the hot-swap management module to receive and forward reset control signals between the root complex and the endpoint, and to obtain information on connected PCIe devices.

[0022] In this embodiment, the hot-swap management module is used as a signal relay medium, so that signals (such as reset control signals or in-place signals) can flow between the root complex and the endpoint.

[0023] More specifically, on the host side, the root complex connects the CPU / memory and the PCIe bus, responsible for enumerating, configuring, and managing devices; it is the root of the PCIe topology. On the device side, the endpoint is the specific PCIe peripheral such as a network card / SSD / graphics card; in hot-swapping, it refers to the device being plugged in or removed. By configuring signals in the root complex and endpoints, operations such as detection, execution, and response are achieved. Furthermore, during initialization, a scan of the PCIe devices in the current system is performed, recording the bus number, device number, function number, and associated slot information for each PCIe device, thereby obtaining information on currently connected PCIe devices. Based on this information, it is possible to determine whether a new hot-swapped device is in progress.

[0024] In this embodiment, completely different initialization and read operations are used for different types of hot-swap management modules, so that the functional requirements of the hot-swap management module can be configured based on actual needs.

[0025] Example 1 In Embodiment 1, the hot-plug management module includes a Complex Programmable Logic Device (CPLD) chip. Accordingly, the initialization operation includes: storing and alternating the reset signal using a counter and register internally configured within the CPLD chip; clearing the counter; setting the initial value of the register to 0 to indicate that the PCIe device is not inserted; identifying the PCIe device by reading its identification information, recognizing it as a connected PCIe device, and updating the register.

[0026] Example 2 In Embodiment 2, the hot-swap management module includes a PCIe switch chip. This PCIe switch chip has multiple input / output ports for signal forwarding and processing of multiple PCIe devices. Accordingly, the initialization operation includes: setting the base frequency of the PCIe switch chip to 100MHz; allocating 256KB of cache space to the PCIe switch chip for storing log information during the hot-swap process of PCIe devices; and reading the limit registers of each PCIe device to obtain at least one or more of the following information: the corresponding PCIe device's identification information, bus number, device number, and function number.

[0027] In this embodiment, Embodiment 1 is a lightweight hot-swap control scheme based on CPLD, focusing on basic detection and manual / semi-automatic recovery; while Embodiment 2 is a multi-channel intelligent self-repair system based on PCIe Switch chip, focusing on multi-device parallel detection, automatic repair and log closed-loop management.

[0028] The difference between Embodiment 1 and Embodiment 2 lies in the hardware structure. Embodiment 1 uses a CPLD chip as a signal intermediary and achieves device state switching through counters and registers, which is suitable for embedded or single-card hot-swappable application scenarios.

[0029] Example 2 uses a PCIe switching chip as an intermediary, which has multiple input / output ports, can monitor multiple PCIe devices simultaneously, and can flexibly forward signals between the root complex (RC) and the endpoint (EP).

[0030] The signal detection and response mechanisms differ. In Implementation Example 1, when a PCIe device is inserted, a CPLD counter detects signal changes; if there is no response, the target module signal is simulated. This simulated signal relies on the logic layer to maintain the device state.

[0031] Example 2 directly detects the hardware port response. If the PCIe device does not respond, an analog signal is sent through the physical layer interface of the switching chip, which can accurately identify the device's VEND, Bus, Device, Function, and other information. Regarding the log and storage mechanisms, Example 1 uses timestamps and operation logs, primarily for recording plug-in / plug-out events.

[0032] Example 2 configures a 256KB cache to store detailed logs, supporting the recording of: hot-plug event timestamps; operation type (insert / remove); fault cause diagnosis results; repair result records, and the logs can be used for long-term system maintenance and statistical analysis.

[0033] It should be noted that the differences between the two implementation methods mentioned above stem from the different specific devices used, leading to significant differences in the initial configuration process. For example, PCIe switching chips need to handle protocol-level link management and events, while CPLD chips can handle these tasks through a simple control interface.

[0034] In this embodiment, the hot-swap management module acts as a signal intermediary under different hardware topologies, including: When the target module is directly connected to the root complex, the hot-plug management module is arranged between the root complex and the endpoint, so that the reset signal and the in-place signal related to hot-plugging are forwarded through the hot-plug management module.

[0035] When the target module is connected to the root complex via a switch, the hot-swap management module is placed between the switch and the endpoint. The hot-swap management module is responsible for the unified access and forwarding of control signals and status signals from the root complex or the switch.

[0036] In other words, this application is based on the hardware topology and each is configured with the signal relay function of the hot-swap management module, which enables unified processing of signal transmission under different hardware link topologies to be applicable to different hot-swap scenarios.

[0037] S102 acquires link status data and physical plug-in status information from the registers and hot-plug-related pins of the PCIe controller.

[0038] In this embodiment, after executing step S101, the link status data can be stored in the registers of the PCIe controller. Simultaneously, physical plug-in / plug-out status information can be obtained through the corresponding pins. These two types of data can be used to determine if there is an abnormality in the link. The PCIe controller registers include a Link Status Register and a Slot Status Register. The link status data includes the LTSSM status and the DL_Active bit. That is, the LTSSM status and the DL_Active bit are periodically read using the Link Status Register and the Slot Status Register. The physical plug-in / plug-out status information refers to device physical plug-in / plug-out events detected by GPIO (General Purpose Input / Output) hot-plug signals. That is, GPIO hot-plug signals are used to detect device physical plug-in / plug-out events.

[0039] S103, based on the link status data and the physical plug-in / plug-out status information, determine whether the PCIe link is in an abnormal state.

[0040] In this embodiment, link status data reflects the current state of the link, while physical plug-in / plug-out status information reflects the corresponding hot-plug events. Based on the link status data and physical plug-in / plug-out status information, it can be determined whether the PCIe link is in an abnormal state.

[0041] See Figure 2 , Figure 2 This is a flowchart of an abnormal state determination in an embodiment of this application, such as... Figure 2 As shown, the following steps can be performed: S201, Read the in-situ status registers of each PCIe device and the status register information related to link training.

[0042] In this embodiment, the in-situ status register can store data about the in-situ status of the PCIe device, while the status register information related to link training can reflect the link status. The status registers may include: a link status register, which may contain information about the current operating status of the link; a link capability register, which may contain information about the maximum capability supported by the device; and a slot status register, which may contain information about the slot status of the link.

[0043] S202, determine whether each of the PCIe devices has been online and is in normal working condition.

[0044] In this embodiment, the corresponding presence information can be obtained by reading the presence status register of the PCIe device. Thus, based on the read information, it can be determined whether the PCIe device is in the expected working state.

[0045] S203, when it is detected that the PCIE device has failed to go online or that there is an abnormal flag outside the preset range in the status register, the link where the device is located is marked as an abnormal link.

[0046] In this embodiment, the PCIe device has already completed its online connection and is in normal working order, indicating that the PCIe device is functioning correctly. If the PCIe device fails to go online, the cause is traced back to an abnormal connection. Alternatively, a significant difference between the data recorded in the status register and the expected data can be used to identify an anomaly based on the corresponding anomaly flags, thus initiating the fault location and repair process.

[0047] In one embodiment, step S203 may include: Based on the LTSSM state and the DL_Active bit, the link state is determined to be non-L0 state, and based on the physical plug-in / plug-out state information, when the PCIE device responds to accessing the preset configuration space, the link state is determined to be abnormal.

[0048] S204, when it is confirmed that the PCIE device is online normally and the link status meets the predetermined requirements, the PCIE device is selected as the target for optimization and adjustment.

[0049] Accordingly, if the PCIe device comes online normally and the link status meets the predetermined requirements, it indicates that the link status is not abnormal. At this time, the PCIe device on this link can be optimized and adjusted. Optimization and adjustment can refer to the driver device or hot-swap management module automatically adjusting parameters such as link speed, power management, interrupt policy, and DMA / cache policy based on the PCIe device's capabilities and system resources after the PCIe device comes online, to ensure that the device can achieve maximum performance while operating stably.

[0050] Specifically, this includes: after a PCIe device is hot-swapped and put online, by reading the link status register and the capability information of the PCIe device, automatically performing steps such as link retraining, DMA buffer adjustment, interrupt merging optimization, and NUMA affinity configuration, to achieve dynamic optimization of device communication rate, CPU utilization, and I / O efficiency, thereby improving overall system performance and hot-swappability stability.

[0051] By executing steps S201 to S204, a multi-layered status monitoring mechanism is used to determine link anomalies, thereby improving identification accuracy. In the previous example, the determination of link anomalies was based on the assumption that the PCIe device could connect and operate normally. However, hot-swapping scenarios involve both the link and the PCIe device. Therefore, before executing step S103, the detection and repair method can further include: The hot-swap management module sends hot-swap-related control signals to the target module and detects whether the target module returns the expected response. When the target module is detected to be able to respond normally, the reset control signal issued by the root complex is transmitted to the endpoint via the hot-swap management module, so that the endpoint completes power-on and link training. When the target module is detected to not respond to the control signal as expected, the hot-swap management module generates a simulated working signal to replace the output of the target module and sends the simulated working signal to the endpoint, so that the endpoint executes the initialization process according to the predetermined hot-swap timing.

[0052] Specifically, by performing a detection operation, it can be determined whether the target module (i.e., the PCIe device) can respond normally and whether it can perform hot-swapping operations normally, thereby determining whether the hot-swapping anomaly is due to a link failure or a PCIe device failure. Furthermore, if it is determined that the PCIe device is failing, a simulated working signal is sent to assume that the target module is still online.

[0053] Clearly, this simulated operating signal is not actually emitted by the target module, but rather a simulated status signal generated by the hot-swap management module. This allows the endpoint (upstream control logic or operating system) to perceive that the bus device is still operational, preventing immediate error reporting or system interruption. This allows the system or upper-layer software to continue accessing the PCIe bus, waiting for automatic repair or retry, maintaining link stability and avoiding errors caused by frequent bus disconnections.

[0054] In this embodiment, the solution for detecting that the target module does not respond to the control signal as expected can be: The hot-plug management module sends a hot-plug signal via GPIO signal lines, the hot-plug controller, or the PCIe control register. This signal can be a device insertion (e.g., inserting a new PCIe card) or device removal (e.g., unplugging a PCIe device) signal. For hot-pluggable devices, if a signal event (e.g., device insertion or removal) is detected, this signal triggers corresponding actions in the device hardware, such as reinitializing the device, configuring the device, or generating a state change. After receiving the hot-plug signal, the device's configuration space or status register changes. The hot-plug management module confirms whether the target module has successfully responded to the hot-plug signal by periodically querying these registers or by detecting changes in the device's state.

[0055] Specific inspection methods include: Read the device's configuration space (such as device ID, status register, etc.); check the presence signal (PresenceDetect), that is, check whether the device has notified the system that the device has been connected through the hardware interface (such as device presence signal, device detection pin, etc.); read the relevant flag bits in the Link Status or Slot Status register (such as LinkActive, Slot Presence, etc.), the state changes of these registers indicate whether the device has been recognized and responded successfully.

[0056] More specifically, when a device is inserted, it sends a response signal to the hot-swap management module. This signal may be triggered by a hardware event (such as an interrupt, status change, pin signal trigger, etc.). The hot-swap management module confirms whether the device has been inserted or initialized by reading the device's response status. For example, when a PCIe device is inserted, it notifies the system that the device is physically connected via the PresenceDetect signal. At this time, the hot-swap management module can confirm whether the device is online by reading the SlotStatus or by reading the configuration space.

[0057] When a device is removed, the hot-swap management module detects the disappearance of the device's Presence Detect signal, or that the device's status register indicates that the device is no longer online (e.g., the device's Link Status changes to Down, or SlotStatus changes to Not Present). Simultaneously, the hot-swap management module also triggers system alarms or the device removal process via GPIO signals or interrupt signals. Methods for generating simulated operating signals include: directly driving GPIO levels, such as pulling the signal line high or low to simulate the state of Presence Detect or Attention Button; configuring the PCIeSlot Status register, i.e., simulating the target module's status register value, so that the upstream controller considers the device online when reading it; and simulating configuration space read / write responses. If the system attempts to access the configuration space, the management module can return predefined data, simulating a device response.

[0058] S104, in response to the PCIe link being in an abnormal state, a repair strategy is selected according to the type of the abnormal state, a repair control sequence containing the reset control signal is generated, and sent to the target module and / or endpoint via the hot-plug management module to trigger link recovery; wherein, the endpoint is the PCIe device in the device hierarchy where the target module is located.

[0059] In this embodiment, even if a PCIe link is determined to be in an abnormal state, a repair operation can still be performed. Furthermore, different solutions are provided for different types of abnormalities. For example, in response to the PCIe link being in an abnormal state, a repair strategy is selected based on the type of abnormal state, including one or more of the following: If the link status changes from a normal state to an abnormal state and recovers within a first preset time, and the PCIe device is able to respond to some access requests, then the anomaly type is determined to be a momentary power outage anomaly. The repair strategy includes triggering link retraining. Specifically, if the PCIe device loses power due to some momentary electrical or physical problem (e.g., power fluctuation, loose device, etc.), the link status changes from the normal L0 state to some abnormal state (e.g., Detect or Polling). Then, link retraining is triggered to restore the electrical connection state of the PCIe device. In short, if the link drops from the L0 state but can recover to the normal state in a short time, it can be judged as a momentary power outage anomaly. Typically, the link status register (e.g., LTSSM) reflects the device's power outage / recovery process.

[0060] If the link state remains in the training or recovery phase for a second preset time and cannot recover to a normal state, the anomaly type is determined to be a link-layer deadlock anomaly. The repair strategy includes performing a reset operation on the subbus. Specifically, if the link layer cannot recover for some reason, and the link is in a Polling, Recovery, or Disabled state, the PCIe device is in a "locked-up" state and cannot recover to the normal L0 state, then a Secondary Bus Reset is triggered, i.e., a reset operation is performed on the subbus to reinitialize the link state. In short, when the link enters an unrecoverable state (such as failing to recover successfully for a long time during the Polling or Recovery phase) and cannot recover to the normal L0 state in a short period of time, it can be determined as a link-layer deadlock anomaly. At this time, the link's status register and error counters (such as RX Errors, TX Errors, etc.) will reflect the deadlock state.

[0061] In response to the PCIe device's lack of response to configuration access requests or its prolonged unrecoverable state, the anomaly type is determined to be a controller failure anomaly. The repair strategy includes performing a hot reset and re-enumerating the PCIe device. Specifically, if the device's controller itself (such as the PCIe root complex, endpoint device controller, etc.) fails, the link is in a completely unrecoverable state, and it cannot even respond to configuration space access requests, then a Hot Reset and Re-enumeration are triggered. That is, the device's initial state is restored through a hot reset, and the device tree is re-enumerated. In other words, when the device does not respond at all during link training, configuration space access, etc. (i.e., the device is "silent"), or the device state is in an unstable state for a long time and cannot be restored by any recovery operation, it can be determined as a controller failure anomaly. At this time, the hardware may not be able to issue normal interrupts or respond to configuration space requests, or the operating system may not be able to read the device's configuration registers.

[0062] It is understood that the three abnormal states shown in the above examples are only for illustrative purposes, and other abnormal scenarios may be included in actual application scenarios.

[0063] In some embodiments, the anomaly type can also be determined based on the PCIe device's response. If the PCIe device responds to some requests, but the link state remains in a non-L0 state or frequently switches, it is usually identified as a momentary power-loss anomaly, which can be recovered through link retraining. If the PCIe device is completely unresponsive, especially in operations such as configuration space reading and device address setting, it is usually identified as a controller failure anomaly, requiring a hot reset and re-enumeration. If the PCIe device responds slowly or unstablely, and the link state remains in Polling or Recovery states for an extended period, it may be a link layer deadlock anomaly.

[0064] S105. After performing the repair, the link status and the online status of the PCIe device are checked again, and the link is confirmed to have been restored to normal working status based on the detection results.

[0065] Specifically, by executing steps S101 to S104, a repair operation can be performed when a link anomaly is determined. In this case, further detection can be performed, and subsequent processing operations can be executed when it is determined that the link has returned to normal working condition.

[0066] In this embodiment, the detection time interval is adjusted based on the abnormal data that occurs. Specifically, the detection and repair method further includes: adjusting the detection time interval based on historical fault statistics of the PCIe link hot-plug scenario. This adjustment includes: recording log information for each hot-plug operation, link anomaly event, and repair behavior, including at least a timestamp, operation type, PCIe device identification information involved, and processing result; aggregating the log information within a preset statistical time window to obtain the fault occurrence frequency and repair success rate of each link or endpoint; shortening the status acquisition cycle for that link or device when the fault frequency of a certain link or endpoint exceeds a preset threshold; and gradually extending the status acquisition cycle when no anomalies are found in multiple rounds of detection and the system load is low. In short, the detection cycle is calculated by combining historical fault rates and load status, and the monitoring frequency is dynamically adjusted to avoid bus interference caused by excessive polling.

[0067] It should also be noted that if the recovery fails multiple times (e.g., three times) after the repair is completed, the system management layer (such as BMC or driver log) will be notified for alert and manual intervention.

[0068] In the above example, the repair control sequence generated and issued is often applied to the target endpoint in the form of one or more hot-plug operations in practical applications. That is, the abnormal link is restored through a controlled power-on, power-off and reset process.

[0069] Therefore, in some embodiments, this application specifies the abstract process of hot-plug operation based on the above detection and repair: on the one hand, when the system detects that the endpoint is in place and meets the predetermined safety conditions, the hot-plug management module can actively initiate the hot-plug operation to cooperate with the above repair strategy; on the other hand, even if no obvious abnormality is detected, the hot-plug management module can complete the insertion or removal of the endpoint according to the same control timing.

[0070] More specifically, the approach of this solution is to first detect whether the link is abnormal. If it is abnormal, the repair operation is performed according to the aforementioned process. If it is not abnormal, the PCIe device is then detected. If the PCIe device is not abnormal, hot-plugging can be performed.

[0071] To this end, this application also provides detailed specifications for the triggering conditions, signal forwarding, and result recording of hot-plug operations, so that the detection and repair mechanisms based on the aforementioned examples can be connected and unified with the specific hot-plug processing flow.

[0072] For example, the detection and repair method further includes: receiving an in-situ signal indicating an in-situ state output by the endpoint; in response to the in-situ signal, when it is detected that the endpoint is in an in-situ state and hot-plugging is allowed, sending a reset signal to the endpoint via the hot-plug management module to trigger a hot-plug power-on or power-off operation; during the execution of the reset control sequence, forwarding hot-plug control signals from the root complex or the target module via the hot-plug management module to complete the hot-plugging action; after the hot-plugging operation is completed, updating the configuration data structure in the PCIe device and generating a hot-plugging log record containing the operation result.

[0073] Among them, the hot-plug control signal is a signal related to the hot-plug state.

[0074] Let's take device insertion as an example.

[0075] When the device is inserted into the slot, PRSNT# is pulled low, and the hot-swap management module detects the change in PRSNT#. Once the signal stabilizes, it is determined that the device has been inserted.

[0076] Next, the hot-swap management module pulls PWR_EN high to stabilize the power supply to the slot.

[0077] Then, the hot-swap management module releases the reset signal by pulling PERST# high, causing the device to exit the reset state and begin link training. For example, LTSSM enters Polling→Configuration→L0.

[0078] The PCIe controller detects a new device and completes the configuration by re-enumerating the devices.

[0079] Conversely, when a device is unplugged, if the user or system detects that the device is about to be unplugged, the hot-plug management module notifies the driver to save the context and disable DMA.

[0080] Next, the hot-swap management module pulls PERST# low, thereby cutting off PWR_EN, and PRSNT# goes high. The main control detection device disappears and the topology is updated.

[0081] This entire process is automatically controlled by the hot-swap management module based on the state machine. The hot-swap operation is achieved by transmitting signals through the hot-swap management module.

[0082] In short, the presence signal is used to trigger the hot-plug process, the reset signal ensures that the PCIe device is in its initial state, and the hot-plug control signal means that the PCIe device is in a ready state and can perform the hot-plug process.

[0083] During hot-plugging, the inventors discovered that even if the hot-plugging operation has been triggered, the device may become unusable due to a failure in some part, so diagnostic logic can be executed.

[0084] More specifically, when it is detected that a hot-plug operation has been triggered and the PCIe device is in an unavailable state, it is determined that the hot-plug operation has failed, and the fault diagnosis results are used for self-repair or error reporting.

[0085] In one embodiment, the self-repair or error reporting of the fault diagnosis result includes: collecting multi-source state information related to the hot-plug operation failure, and generating a corresponding context snapshot based on the multi-source state information; constructing an ideal execution path for the hot-plug operation based on the PCIe device type and system configuration, and comparing the ideal execution path with the recorded sequence of actual execution steps to determine at least one deviation node between the ideal execution path and the actual execution step sequence; constructing a fault causal dependency graph for the deviation node, combining the state information recorded in the context snapshot, and identifying the root cause of the hot-plug operation failure based on the fault causal dependency graph to obtain the fault diagnosis result; matching the current fault mode with historical fault records, and selecting a target self-repair strategy from a preset self-repair strategy set based on the fault diagnosis result and the matching result.

[0086] Specifically, multi-source state information includes at least one or more of the following: Slot status information, including power supply status, voltage, current, and / or physical connection detection results.

[0087] Protocol or bus layer status information, including handshake results, error counters, retransmission counts, and / or link training status.

[0088] System-level status information, including driver loading progress, error codes, key kernel log entries, and / or resource allocation results.

[0089] Business layer status information, including the running status, degradation status and / or error alarm information of related businesses.

[0090] Accordingly, the context snapshot is obtained by freezing and archiving multi-source state information when a hot-plug operation is detected to have failed, and is associated with the session identifier of the current hot-plug operation.

[0091] The ideal execution path is generated based on the target device type, slot configuration, and system driver stack information. The ideal execution path consists of multiple step nodes arranged in a preset order. The step nodes include at least the following steps: power-on step, bus or link initialization step, device identification and enumeration step, driver binding step, resource allocation step, and device online confirmation step.

[0092] In this case, the deviation node includes at least one of the following situations: the target step in the ideal execution path is missing in the actual execution step sequence; the target step fails to execute in the actual execution step sequence; the execution order of the target step in the actual execution step sequence is inconsistent with the preset order; the execution time and / or resource consumption of the target step exceeds the preset threshold.

[0093] Constructing a fault causal dependency graph includes: treating events, state changes, and resource changes related to the deviation node as multiple nodes in the causal dependency graph; establishing directed edges between the nodes based on their temporal and resource dependencies; and performing backtracking analysis on the causal dependency graph to identify at least one root cause node located upstream in the causal chain and having a causal impact on the deviation node.

[0094] Historical fault records should include at least one of the following: device type, slot identifier, firmware version, deviation node type, error code combination, environmental parameters, self-healing strategy, and self-healing effect at the time of the fault.

[0095] Matching the current fault mode with historical fault records includes: extracting the fault feature vector corresponding to the current fault; comparing the similarity between the fault feature vector and the feature vector in the historical fault records; when the similarity is greater than a preset threshold, it is determined to be a similar fault mode, and the self-repair strategy corresponding to the similar fault mode is selected first.

[0096] Optionally, the target self-repair strategy is executed, and the self-repair effect is verified; the hot-plug operation failure process, self-repair steps, and self-repair effect are recorded as a repair log, and the historical fault records and the self-repair strategy set are updated based on the repair log.

[0097] Specifically, the selection of a target self-repair strategy includes: determining a set of feasible candidate self-repair strategies based on the fault diagnosis results; comprehensively evaluating the historical success rate, repair time, and impact on business of the candidate self-repair strategies to obtain corresponding strategy scores; and selecting a self-repair strategy whose strategy score meets preset conditions from the candidate self-repair strategies as the target self-repair strategy.

[0098] In another embodiment, the self-repair or error reporting of fault diagnosis results includes: real-time acquisition of the system's hot-plug status information; analysis and processing of the acquired information; and status assessment based on the processing results. This includes recording the timestamps of hot-plug operations; saving the operation type (insertion or removal); and recording the operation results. It also involves analyzing the fault causes based on the operation information; retrieving fault history records; and making fault predictions based on historical data. Finally, it involves determining a repair strategy based on the fault diagnosis results; executing the repair operation; verifying the repair effect; and recording the repair log.

[0099] To better understand and illustrate the solutions in the embodiments of this application, two examples are provided.

[0100] Example 1 Step 1.1: Initialize system configuration.

[0101] Step 1.11: Configure the hot-swap management module as a signal intermediary to transmit reset signals and presence signals.

[0102] Step 1.12: Initialize the register settings of the hot-plug management module. Clear the counter and set the initial value of the register to 0 to indicate that the PCIe device is not inserted.

[0103] Step 1.13: Detect and record information about the PCIe devices connected to the system. Identify and store the devices using their IDs (identity identifiers) and other relevant information.

[0104] Step 1.2: Detect the PCIe link status.

[0105] Step 1.21: Detect whether the target module responds to the hot-plug signal through the hot-plug management module. If a response is detected, proceed to step 1.22; if no response is detected, proceed to step 1.23.

[0106] Step 1.22: If a response is received, a reset signal is transmitted between the target module and the endpoint to implement the hot-plug power-on process. A reset signal is sent via the PCIe bus to complete the communication connection with the target module.

[0107] Step 1.23: If there is no response, send a simulated signal to the endpoint to simulate the working signal emitted by the target module. The simulated signal is sent through the output port of the CPLD chip to simulate the normal working state of the PCIe device.

[0108] Step 1.3: Determine the test result. If the link is normal, return to step 1.1. If the link is abnormal, proceed to step 1.4.

[0109] Step 1.3 may include: Step 1.31: Read the in-situ status register of each PCIe device. Read the status information of the devices through the PCIe bus.

[0110] Step 1.32: Determine if the device is online normally. If the device status is 1 and the counter value is 0, it is determined to be online normally.

[0111] Step 1.33: If the equipment is not online or in an abnormal state, perform fault location and repair. Use the fault diagnosis mechanism to locate the cause of the abnormality and attempt to restore the equipment status.

[0112] Step 1.34: If the device is online normally, perform performance optimization adjustments. Adjust the bandwidth and priority of the PCIe bus according to the device's performance requirements.

[0113] Step 1.4: Perform a hot-plug operation.

[0114] Step 1.41: Receive the presence signal from the endpoint. Receive the signal through the input port of the CPLD chip.

[0115] Step 1.42: Send a reset signal to the endpoint. Send a reset signal via the PCIe bus to prepare for hot-plugging.

[0116] Step 1.43: Transmit signals through the hot-swap management module to realize hot-swap operations. Perform corresponding insertion or removal operations according to the device status.

[0117] Step 1.44: Update system configuration and record hot-plug logs. Record hot-plug timestamps, device identifiers, and operation results.

[0118] Example 2 Step 2.1: Initialize system configuration.

[0119] Step 2.11: Configure the hot-swap management module as a signal intermediary, using a PCIe switch chip to forward and process signals. This chip has multiple input / output ports and can simultaneously support hot-swap operations of multiple PCIe devices.

[0120] Step 2.12: Initialize the register settings of the hot-swap management module. Set the base frequency to 100MHz and allocate 256KB of cache space for storing hot-swap log information.

[0121] Step 2.13: Detect and record the information of the PCIe devices connected in the system. Obtain the device's ID, bus number, device number, and function number by reading the device's VEND (Virtual End) register, and store this information in the database.

[0122] Step 2.2: Detect the PCIe link status.

[0123] Step 2.21: Detect whether the target module responds to the hot-plug signal via the hot-plug management module. If a response is detected, proceed to step 2.22; otherwise, proceed to step 2.23. Step 2.22: If a response is detected, a reset signal is transmitted between the target module and the endpoint to implement the hot-plug power-on process. A reset signal is sent via the PCIe bus, waiting for a response from the target module. Step 2.23: If no response is detected, a simulated signal is sent to the endpoint to simulate the operating signal emitted by the target module. A simulated signal is sent through the output port of the PCIe switch chip to simulate the normal operating state of the PCIe device.

[0124] Step 2.3: Determine the test results. If the link is normal, return to step 2.1. If the link is abnormal, proceed to step 2.4.

[0125] Step 2.31: Read the in-situ status register of each PCIe device. Read the STATUS register of the device's configuration space via the PCIe bus. Step 2.32: Determine if the device is online normally. If the device status is 0x00 and the counter value within the base frequency is less than a preset threshold, it is considered to be online normally. Step 2.33: If the device is not online or its status is abnormal, perform fault location and repair. Analyze the cause of the device abnormality through the fault diagnosis mechanism and attempt to restore the device status. Step 2.34: If the device is online normally, perform performance optimization adjustments. Adjust the transmission frequency and priority of the PCIe bus according to the device's performance requirements.

[0126] Step 2.4: Perform the hot-plug operation.

[0127] Step 2.41: Receive the presence signal from the endpoint. Receive the signal through the input port of the PCIe switch chip. Step 2.42: Send a reset signal to the endpoint. Send a reset signal through the PCIe bus to prepare for hot-plugging. Step 2.43: Transmit signals through the hot-plug management module to implement the hot-plugging operation. Perform the corresponding insertion or removal operation based on the device status. Step 2.44: Update the system configuration and record the hot-plug log. Record the hot-plug timestamp, device identifier, and operation results, and add fault diagnosis results and repair records to the log.

[0128] In some embodiments, the system used to perform the detection and repair method is a multi-coprocessor system, which requires configuring the running process of each coprocessor to execute different code segments when parsing executable and linkable format files.

[0129] Furthermore, in order to enable multiple coprocessors to use a single executable and linkable file format simultaneously, at least the following improvements can be made: Obtain the executable and linkable format files; within these files, each coprocessor in the multi-coprocessor set is assigned an entry function identifier and its corresponding entry address; each coprocessor has its own unique identification information. Parse the header of the executable and linkable format files and load the identified code and data segments into the specified memory addresses.

[0130] For each coprocessor to be loaded and run, based on its identification information, the memory address of the entry function corresponding to the identification information is dynamically resolved by querying the symbol table in the executable and linkable format files, and this address is used as the entry address of the coprocessor. The corresponding entry addresses are then set for each coprocessor in sequence to start each coprocessor. Unlike the executable and linkable format files in existing solutions, this application additionally specifies an entry function identifier and the entry address of the coprocessor code for each coprocessor, enabling each coprocessor to accurately obtain its execution entry point and thus select a segment to execute the processing task.

[0131] To adapt to this change, the steps for generating executable and linkable format files include: The common functions and logic required by the multiple coprocessors are extracted into common functions; for the unique interfaces of each coprocessor, independent entry functions are defined respectively, and the code structure is divided into common function modules, coprocessor independent function modules and entry function modules.

[0132] The compiler and linker assign corresponding entry addresses to the independent entry functions of each coprocessor. The common function module, the coprocessor-independent function module, and the entry function module are compiled by writing a build script to generate corresponding object files. A linker script is also written to define the layout of the code segment and data segment and to specify the entry address of each coprocessor.

[0133] The linker, based on the linking script, links all object files into an executable and linkable file, generating a single executable and linkable file containing the code for all coprocessors. This executable and linkable file includes the code segments, data segments, and symbol tables required by all coprocessors. Common functionalities include at least one of mathematical operations, string processing, data structure operations, and file operations. Common logic includes at least one of state management, error handling, and communication protocols. This part corresponds to the core logic of task scheduling, state switching, and information transfer between coprocessors. Thus, in the obtained executable and linkable format files, each coprocessor has been pre-assigned an entry function identifier, the entry address of its code, and identification information. This allows the identified code and data segments to be loaded into the specified memory addresses during the loading of the executable and linkable format files. Furthermore, based on the entry function identifier and identification information, the entry point of each coprocessor's application can be determined to start each coprocessor. This enables the coprocessor to adaptively read the appropriate code and data segments from memory addresses while it is running, simplifying the interaction between multiple coprocessors and improving the overall system performance.

[0134] Furthermore, by implementing the scheme in the above example, multiple coprocessors can load executable and linkable format files. This can be achieved through data communication. In the traditional approach, CSIRS rate matching is defined at the resource unit (RE) level. Resource units within the same resource block (RB) contain both PDSCH data and CSIRS signals. In this case, without CSIRS rate matching, unused resource units may not be able to store PDSCH data, resulting in wasted resources within a time slot.

[0135] Based on this, this application also provides a resource mapping method for a physical downlink shared channel, wherein the resource mapping method for a physical downlink shared channel includes: A first bitmap is generated, which is a bit mapping table excluding channel state information (CSI) reference signal resources. The bit mapping table records resource particles occupied by CSI reference signals within one or more symbols. The generation of the first bitmap involves: initializing a full-frequency domain bit mapping table, where all bits are set to a first value; for each CSI reference signal resource, performing the following operations: obtaining the resource occupancy pattern of the CSI reference signal resource within a single resource block and generating a corresponding single-resource-block bit mapping; extending the single-resource-block bit mapping to the frequency domain resource length configured for the CSI reference signal resource; performing a logical operation between the extended bit mapping and the current full-frequency domain bit mapping table, and updating the result to the full-frequency domain bit mapping table for the single CSI reference signal resource; traversing all CSI reference signal resources and using the full-frequency domain bit mapping tables of multiple CSI reference signal resources as the first bitmap.

[0136] A second bitmap is generated, which is a user equipment-level resource block allocation bit mapping table. This allocation bit mapping table uses multiple bits to indicate whether a resource block has been allocated to a corresponding user equipment for physical downlink shared channel transmission. The second bitmap is generated as follows: a multi-bit field is used to represent the allocation status of a resource block; when the multi-bit field is set to a third value, it indicates that the corresponding resource block has been allocated to the user equipment for physical downlink shared channel mapping; when the multi-bit field is set to a fourth value, it indicates that the corresponding resource block has not been allocated to the user equipment.

[0137] Based on the first bitmap and the second bitmap, a user equipment-level available resource bitmap is generated. This available resource bitmap is used to identify the resource mapping of the user equipment's physical downlink shared channel data. Specifically, this includes: for any user equipment, expanding the granularity of resource particles in the second bitmap so that the allocation status information of each resource block in the second bitmap is expanded to a bit sequence that can represent all resource particles within that resource block, generating an extended bitmap; performing a logical operation between the extended bitmap and the first bitmap to generate an available resource bitmap for a single user equipment. Each bit in the available resource bitmap indicates whether a resource particle can be used to map the user equipment's physical downlink shared channel data.

[0138] Thus, the first bitmap is a bitmap table excluding Channel State Information Reference Signal (CSIRS) resources. Based on this bitmap table, the resource particles occupied by CSIRS within one or more symbols can be determined. The second bitmap indicates whether a resource block is allocated to a corresponding user equipment (UE) for Physical Downlink Shared Channel (PHS) transmission. By using the first and second bitmaps, a corresponding UE-level available resource bitmap table can be generated. Based on this available resource bitmap table, the resource mapping for UE PHS PHS data can be performed. Compared to existing schemes that perform rate matching through nested loops, this scheme only requires matching. Based on the matched first and second bitmaps, CSIRS rate matching can be achieved, reducing the time required for CSIRS rate matching and enabling faster transmission of executable and linkable format files.

[0139] The detection and repair methods for PCIe link hot-plugging scenarios have been described in detail above through some embodiments. In order to enable those skilled in the art to better understand and implement them, the corresponding products are also described in detail below through some embodiments.

[0140] See Figure 3 The schematic diagram of the PCIe link hot-plugging scenario detection and repair device shown in this application embodiment indicates that the PCIe link hot-plugging scenario detection and repair device 300 may include: an initialization unit 310, configured to perform an initialization operation, the initialization operation including at least: configuring the hot-plug management module to receive and forward reset control signals between the root complex and the endpoint, and acquiring information on connected PCIe devices; an acquisition unit 320, configured to acquire link status data and physical plug-in / plug-out status information from the registers and pins related to hot-plugging of the PCIe controller; and a judgment unit 330, configured to judge based on the link status data and the physical plug-in / plug-out status information. The system processes hot-plug status information to determine if the PCIe link is in an abnormal state. Execution unit 340 is configured to, in response to the PCIe link being in an abnormal state, select a repair strategy based on the type of abnormal state, generate a repair control sequence including the reset control signal, and send it to the target module and / or endpoint via the hot-plug management module to trigger link recovery. The endpoint is a PCIe device in the device hierarchy where the target module resides. Detection unit 350 is configured to, after performing repair, re-detect the link status and the online status of the PCIe device, and confirm whether the link has recovered to a normal working state based on the detection results. Further descriptions of the initialization unit 310, acquisition unit 320, judgment unit 330, execution unit 340, and detection unit 350 can be found in the foregoing examples.

[0141] It is understood that the above division of units is only a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, the above units can be implemented by a processor calling software. For example, the system includes a processor connected to memory, which stores instructions. The processor calls the instructions stored in memory to implement any of the methods in the above embodiments or to implement the functions of each unit. The processor is, for example, a general-purpose processor, such as a central processing unit (CPU), and the memory can be internal or external to the device. Alternatively, the above units can be implemented as hardware circuits. The functions of some or all units can be implemented through the design of the hardware circuit, which can be understood as one or more processors. For example, in one implementation, the hardware circuit is an application-specific integrated circuit (ASIC). By designing the logical relationships between the components within the circuit, the functions of some or all of the above units are implemented. In another implementation, the hardware circuit can be implemented using a programmable logic device (PLD), which can include a large number of logic gates. The logical relationships between the logic gates are configured through a configuration file, thereby implementing the functions of some or all of the above units. All units of the above system can be implemented entirely through processor calling programs, or entirely through hardware circuits, or partially through processor calling programs with the remaining parts implemented through hardware circuits.

[0142] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program including a computer program for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), it performs various functions defined in the system of this application.

[0143] It should be noted that the computer-readable medium shown in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0144] In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying a computer-readable computer program. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0145] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. Each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions. The units described in the embodiments of this application may be implemented in software or hardware, and the described units may also be located in a processor. The names of these units do not, in some cases, constitute a limitation on the unit itself.

[0146] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of this application, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0147] From the above description of the embodiments, those skilled in the art should understand that the embodiments of this application can be provided as methods, systems, or computer program products. This application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. This application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0148] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0149] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0150] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0151] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0152] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for detecting and repairing hot-plugging scenarios in PCIe links, characterized in that, include: Perform initialization operations, which at least include: configuring the hot-plug management module to receive and forward reset control signals between the root complex and the endpoint, and obtaining information about connected PCIe devices; Link status data and physical plug-in status information are acquired from the registers and hot-plug-related pins of the PCIe controller. Based on the link status data and the physical plug-in / plug-out status information, determine whether the PCIe link is in an abnormal state. In response to the PCIe link being in an abnormal state, a repair strategy is selected according to the type of the abnormal state, a repair control sequence containing the reset control signal is generated, and sent to the target module and / or endpoint via the hot-plug management module to trigger link recovery; wherein, the endpoint is the PCIe device in the device hierarchy where the target module is located; After performing the repair, the link status and the online status of the PCIe device are checked again, and the link is confirmed to have returned to normal working status based on the test results.

2. The detection and repair method according to claim 1, characterized in that, The hot-plug management module includes a complex programmable logic device (CPL) chip; the initialization operation includes: storing and alternating the reset signal through a counter and register set inside the CPL chip; clearing the counter; setting the initial value of the register to 0 to indicate that the PCIe device is not inserted; identifying the PCIe device by reading its identification information, treating it as a connected PCIe device, and updating the register. And / or, the hot-swap management module includes: a PCIe switch chip, the PCIe switch chip having multiple input / output ports for signal forwarding and processing of multiple PCIe devices; the initialization operation includes: setting the reference frequency of the PCIe switch chip to 100MHz; allocating 256KB of cache space to the PCIe switch chip for storing log information during the hot-swap process of PCIe devices; reading the limit registers of each PCIe device to obtain at least one or more of the identification information, bus number, device number, and function number of the corresponding PCIe device.

3. The detection and repair method according to claim 1, characterized in that, The step of determining whether a PCIe link is in an abnormal state based on the link status data and the physical plug-in / plug-out status information includes: Read the in-situ status registers and link training-related status register information of each of the PCIe devices; Determine whether each PCIe device has been successfully connected and is in normal working condition; When it is detected that the PCIe device has failed to come online or that there is an abnormal flag outside the preset range in the status register, the link where the device is located is marked as an abnormal link. When it is confirmed that the PCIe device is online normally and the link status meets the predetermined requirements, the PCIe device will be selected for optimization and adjustment.

4. The detection and repair method according to claim 3, characterized in that, The registers of the PCIe controller include: a link status register and a slot status register. The link status data includes: LTSSM status and DL_Active bit. The physical plug-in / plug-out status information is the device physical plug-in / plug-out event detected by the GPIO hot-plug signal. When it is detected that the PCIe device has failed to connect or that there is an abnormal flag outside the preset range in the status register, the link where the device is located is marked as an abnormal link, including: Based on the LTSSM state and the DL_Active bit, the link state is determined to be a non-L0 state, and based on the physical plug-in / plug-out state information, when the PCIE device responds to accessing the preset configuration space, the link state is determined to be an abnormal state.

5. The detection and repair method according to claim 1, characterized in that, In response to the PCIe link being in an abnormal state, a repair strategy is selected based on the type of the abnormal state, including one or more of the following: If the link status changes from normal to abnormal and recovers within a first preset time, and the PCIe device is able to respond to some access requests, then the abnormality type is determined to be a momentary power failure type abnormality, and the repair strategy includes triggering link retraining. If the link state is in the training or recovery phase within a second preset time and cannot be restored to the normal state, then the anomaly type is determined to be a link layer deadlock anomaly, and the repair strategy includes performing a reset operation on the sub-bus. In response to the PCIe device not responding to the configuration access request or being in an unrecoverable state for an extended period, the exception type is determined to be a controller failure exception, and the repair strategy includes performing a hot reset and re-enumerating the PCIe devices.

6. The detection and repair method according to claim 1, characterized in that, Before determining whether the PCIe link is in an abnormal state based on the link status data and the physical plug-in / plug-out status information, the method further includes: The hot-plug management module sends hot-plug related control signals to the target module and detects whether the target module returns the expected response. When the target module responds normally, the reset control signal issued by the root complex is transmitted to the endpoint via the hot-plug management module, enabling the endpoint to complete power-on and link training. When the target module does not respond to the control signal as expected, the hot-plug management module generates a simulated working signal to replace the target module's output and sends the simulated working signal to the endpoint, enabling the endpoint to execute the initialization process according to the predetermined hot-plug timing. The detection and repair method also includes: Based on historical fault statistics of the PCIe link hot-plugging scenario, the detection time interval is adjusted. This adjustment includes: recording log information for each hot-plugging operation, link anomaly event, and repair action, including at least a timestamp, operation type, PCIe device identification information involved, and processing result; aggregating the log information within a preset statistical time window to obtain the fault occurrence frequency and repair success rate of each link or endpoint; shortening the status acquisition cycle for that link or device when the fault frequency of a certain link or endpoint exceeds a preset threshold; and gradually extending the status acquisition cycle when no anomalies are found in multiple rounds of detection and the system load is low.

7. The detection and repair method according to claim 1, characterized in that, Also includes: Receive an in-situ signal indicating the in-situ status output by the endpoint; In response to the presence signal, when the endpoint is detected to be in a present state and hot-plugging is allowed, a reset signal is sent to the endpoint via the hot-plugging management module to trigger a hot-plugging power-on or power-off operation. During the execution of the reset control sequence, the hot-plug control signal from the root complex or the target module is forwarded through the hot-plug management module to complete the hot-plug action; After the hot-plug operation is completed, the configuration data structure in the PCIe device is updated, and a hot-plug log record containing the operation results is generated.

8. The detection and repair method according to claim 7, characterized in that, When it is detected that a hot-plug operation has been triggered and the PCIe device is in an unavailable state, it is determined that the hot-plug operation has failed, and the fault diagnosis results are used for self-repair or error reporting. The self-repair or error reporting of the fault diagnosis results includes: Collect multi-source state information related to the hot-plug operation failure, and generate a corresponding context snapshot based on the multi-source state information; Based on the type of PCIe device and system configuration, an ideal execution path for the hot-plug operation is constructed, and the ideal execution path is compared with the recorded sequence of actual execution steps to determine at least one deviation node between the ideal execution path and the sequence of actual execution steps. For the deviation node, a fault causal dependency graph is constructed by combining the state information recorded in the context snapshot, and the root cause of the hot-plug operation failure is identified based on the fault causal dependency graph to obtain the fault diagnosis result. The current fault mode is matched with historical fault records. Based on the fault diagnosis results and matching results, a target self-repair strategy is selected from a set of preset self-repair strategies.

9. The detection and repair method according to any one of claims 1 to 8, characterized in that, The hot-swap management module serves as a signal intermediary in different hardware topologies, including: When the target module is directly connected to the root complex, the hot-plug management module is arranged between the root complex and the endpoint so that the reset signal and the in-situ signal related to hot-plugging are forwarded through the hot-plug management module. When the target module is connected to the root complex via a switch, the hot-swap management module is placed between the switch and the endpoint. The hot-swap management module is responsible for the unified access and forwarding of control signals and status signals from the root complex or the switch.

10. A detection and repair device for PCIe link hot-plugging scenarios, characterized in that, include: An initialization unit is configured to perform an initialization operation, which includes at least: configuring the hot-plug management module to receive and forward reset control signals between the root complex and the endpoint, and to obtain information about connected PCIe devices; The acquisition unit is configured to acquire link status data and physical plug-in status information from the registers and hot-plug-related pins of the PCIe controller. The judgment unit is configured to determine whether the PCIe link is in an abnormal state based on the link status data and the physical plug-in / plug-out status information. The execution unit is configured to, in response to the PCIe link being in an abnormal state, select a repair strategy according to the type of the abnormal state, generate a repair control sequence containing the reset control signal, and send it to the target module and / or endpoint via the hot-plug management module to trigger link recovery; wherein, the endpoint is a PCIe device in the device hierarchy where the target module is located; The detection unit is configured to re-detect the link status and the online status of the PCIe device after the repair is performed, and to confirm whether the link has been restored to normal working status based on the detection results.

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