Data transmission method and device, electronic equipment and storage medium

Abstract

The invention provides a data transmission method, a data transmission device, electronic equipment, a chip, a storage medium and a computer program product. The data transmission method is applied to a DPU, and comprises the following steps: if an SPDK is abnormally restarted, sending one or more responses sent by the SPDK to a first device through an FPGA, and updating a used ring index udrringgidx; the response represents that the data read-write request corresponding to the response is stored in the second equipment; the method comprises the following steps of: updating a hardware available index hwavalableiidx in the FPGA, wherein the hardware available index hwavalableiidx is equal to uedringiidx; and obtaining a data reading and writing request from the first equipment on the basis of the hwavalabladx.

Description

Technical Field

[0001] This application relates to the field of data processing technology, specifically to a data transmission method, a data transmission device, an electronic device, a chip, a storage medium, and a computer program product. Background Technology

[0002] With the development of cloud computing and data centers, the efficiency and reliability of data transmission have become critical requirements. Data Processing Units (DPUs), as dedicated data-centric processors, offload network, storage, and security functions. Field Programmable Gate Arrays (FPGAs) are widely used in smart network interface cards (NICs) due to their programmability, enabling flexible data processing capabilities. However, FPGAs struggle to support stable operation under high concurrency and high traffic scenarios when resources are limited.

[0003] In related technologies, reliable storage communication is typically ensured through the host-side software layer or the System-on-Chip (SoC)-side high-performance storage development kit (SPDK) mechanism. For example, on the host side, retransmission mechanisms are used to recover read / write (I / O) requests for abnormal events, or on the SoC side, large-page mechanisms are used to save context information for exception recovery. While these methods can achieve lossless communication in some scenarios, they cannot effectively address the problem of I / O loss between the host and the SoC. Summary of the Invention

[0004] This application provides a data transmission method, a data transmission device, an electronic device, a chip, a storage medium, and a computer program product.

[0005] The data transmission method provided in this application embodiment is applied to a DPU and includes: If SPDK restarts abnormally, one or more responses sent by SPDK will be sent to the first device via the FPGA, and the used ring index used_ring_idx will be updated; the response indicates that the data read / write request corresponding to the response has been completed in the second device; Update the hardware availability index hw_available_idx in the FPGA to used_ring_idx; Data read / write requests are obtained from the first device based on the hw_available_idx.

[0006] The data transmission device provided in this application embodiment is applied to a DPU and includes: Control unit: If SPDK restarts abnormally, it sends one or more responses sent by SPDK to the first device via FPGA, and updates the used ring index used_ring_idx; the response indicates that the data read / write request corresponding to the response has been completed in the second device; updates the hardware availability index hw_available_idx=used_ring_idx in the FPGA; and obtains the data read / write request from the first device based on hw_available_idx.

[0007] The electronic device provided in this application includes a processor and a memory. The memory is used to store computer programs, and the processor is used to call and run the computer programs stored in the memory to execute the data transmission method provided in any embodiment of this application.

[0008] The chip provided in this application includes a processor for calling and running a computer program from a memory, causing a device equipped with the chip to execute the data transmission method provided in any embodiment of this application.

[0009] The storage medium provided in the embodiments of this application is used to store a computer program, which causes a computer to execute the data transmission method provided in any embodiment of this application.

[0010] The computer program product provided in the embodiments of this application includes a computer program, which, when executed by a processor, provides a data transmission method in any embodiment of this application.

[0011] The data transmission method, data transmission device, electronic device, chip, storage medium, and computer program product provided in this application firstly, in the event of an abnormal SPDK restart, utilizes the FPGA to directly send the completed SPDK response to the first device, while simultaneously updating the used ring index `used_ring_idx`, thereby avoiding read / write anomalies caused by context loss due to SPDK anomalies. Secondly, by setting `hw_available_idx` to `used_ring_idx`, it ensures that subsequent requests can correctly identify the current processing position. This method effectively avoids the latency and resource consumption problems caused by traditional reliance on Host-side retransmission mechanisms, improves anomaly recovery efficiency, reduces dependence on Host-side software, and enhances the robustness and real-time performance of the system. Attached Figure Description

[0012] Figure 1 Schematic diagram of the implementation flow of the data transmission method provided in the embodiments of this application Figure 1 ; Figure 2 This is a schematic diagram of the data transmission architecture provided in an embodiment of this application; Figure 3 This is a schematic diagram of the SPDK processing logic provided in the embodiments of this application; Figure 4 A flowchart illustrating the data transmission method provided in the embodiments of this application. Figure 2 ; Figure 5 This is a schematic diagram of the structure of the data transmission device provided in the embodiments of this application; Figure 6 A schematic structural diagram of an electronic device provided in the embodiments of this application; Figure 7 This is a schematic structural diagram of the chip provided in an embodiment of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0014] It should be noted that, in the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, in the embodiments of this application, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0015] In the description of the embodiments of this application, the term "correspondence" may indicate that there is a direct or indirect correspondence between two things, or that there is an association between two things, or that there is a relationship of instruction and being instructed, configuration and being configured, etc.

[0016] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant technologies of the embodiments of this application are described below. The following relevant technologies are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and they all fall within the protection scope of the embodiments of this application.

[0017] A Data Processing Unit (DPU) is a dedicated processor built around data. An FPGA, as one of the optional heterogeneous engines for offloading DPU IaaS cloud services, can handle accelerated processing tasks related to networking, storage, and security. An FPGA-based smart network interface card (NIC) can be viewed as a programmable NIC. Compared to ASICs, FPGAs offer unlimited adaptive programmability; however, due to iterative functional requirements, FPGAs suffer from limited embedded memory hardware resources.

[0018] With the rapid growth of cloud service demands, there are scenarios requiring high-concurrency read / write I / O, high-volume processing, and hot upgrades of storage services. If the internal hardware and software cannot meet the robustness required for high-throughput processing, the SoC on the server-side smart network interface card will exhibit macromachine behavior, requiring a power outage and restart to restore operation. However, the context of the abnormal situation cannot be recovered, and the storage event I / O during the anomaly cannot be reconnected. Simultaneously, the update and iteration of storage services also require hot upgrade capabilities without interruption. How major cloud service providers can robustly and completely build lossless storage communication and hot upgrade capabilities for user function iterations has become a pressing technical challenge that needs to be addressed.

[0019] Current mainstream lossless storage communication capabilities typically ensure reliability at the host-side software layer. This involves implementing retransmission mechanisms at the host-side application layer, utilizing reliable communication between the host and the SoC for recovery; or using the SPDK's big-page mechanism on the SoC side to save the I / O context, retrieving and retransmitting the I / O when an I / O exception occurs. This exception handling mechanism relies on the SaaS provider's ability to detect and process storage communication, ensuring lossless storage characteristics in some scenarios. However, it cannot effectively recover from I / O loss during host-SoC communication. Furthermore, for IaaS providers, relying solely on upper-layer software recovery guarantees is insufficient; lossless storage communication on FPGA-based smart network interface cards is a necessary reliability capability. Simultaneously, ensuring lossless storage communication also requires the ability to perform hot upgrades without downtime during functional optimization iterations. Based on the shortcomings of related technical solutions, this solution designs a hardware-software collaborative mechanism, strategy, and device. By leveraging the programmability of FPGAs, a software and hardware co-operation strategy can be designed on the SoC side to meet the requirements of lossless storage communication and hot upgrade capability. At the same time, considering the bottleneck of insufficient hardware resources in the existing FPGA board, this technical solution uses software adaptive I / O loss detection to achieve lossless storage capability with low hardware resource consumption.

[0020] refer to Figure 1 , Figure 1 A schematic diagram of the implementation flow of the data transmission method provided in the embodiments of this application. Figure 1 ,like Figure 1As shown, the data transmission method provided in this application embodiment, applied to a DPU, includes the following steps: Step 101: If SPDK restarts abnormally, send one or more responses sent by SPDK to the first device via FPGA, and update the used ring index used_ring_idx; the response indicates that the data read / write request corresponding to the response has been completed in the second device.

[0021] In this embodiment of the application, the first device is a host device and the second device is a storage device.

[0022] In this embodiment, the communication between the host device and the DPU is based on the virtio communication protocol. The front end and back end of Virtio correspond to the host driver in the DPU scenario and the device implementation in the FPGA, respectively.

[0023] In this embodiment, after the DPU processes each data read / write request, it increments used_ring_idx and notifies the host device to reclaim the corresponding resources. For example, if the host issues two requests, and their order in the Desc Table is Desc[0] and Desc[1] respectively, and Desc[0] is completed first, the DPU returns the response corresponding to Desc[0] to the host device, updates used_ring_idx from 0 to 1, and the host device releases the resources of Desc[0].

[0024] In this embodiment, the processing flow of data read / write requests within the DPU is as follows: the FPGA obtains a certain number of data read / write requests from the host device, stores them locally on the FPGA, and continuously sends the data read / write requests to the SPDK. The SPDK sends the data read / write requests to the storage device. The storage device returns a response to the SPDK after the data read / write request is completed, indicating that the corresponding data read / write request has been completed. The SPDK returns the response to the FPGA, and the FPGA sends the response to the host device to update used_ring_idx.

[0025] SPDK provides a set of user-space storage development tools and libraries designed to achieve high-performance, low-latency storage operations. SPDK fully leverages the performance advantages of modern storage devices through user-space drivers, poll-mode drivers (PMD), and zero-copy mechanisms.

[0026] refer to Figure 2 , Figure 2 This is a schematic diagram of the data transmission architecture provided in the embodiments of this application, such as... Figure 2As shown, Virtio simplifies the implementation and management of virtual devices and improves data transmission efficiency in virtualized environments by defining a standardized set of device interfaces and drivers. Virtio's frontend and backend correspond to the host driver in the DPU scenario and the device implementation in the FPGA, respectively. Data transmission between the host device and storage device is completed through the FPGA in the DPU and the SPDK hosted on the SoC.

[0027] In this embodiment of the application, when the SPDK restarts abnormally, the FPGA may still have responses that have not been sent to the host device. Therefore, the FPGA needs to send all the saved responses to the host device so that the completed but not yet confirmed requests have been processed and the used_ring_idx is updated synchronously.

[0028] In this embodiment, `used_ring_idx` is designed based on the ring buffer structure in the Virtio protocol, where each descriptor represents an I / O request. The value of `used_ring_idx` increments as requests are completed, ensuring that the host can accurately identify which requests have been consumed. In this embodiment, when SPDK restarts abnormally, it sends out the responses corresponding to all completed but unacknowledged requests and updates the used ring index synchronously, enabling the host to release relevant resources in a timely manner.

[0029] Step 102: Update the hardware availability index hw_available_idx=used_ring_idx in the FPGA.

[0030] In this embodiment, the hardware available index is a hardware available index maintained internally by the FPGA, used to indicate the starting position that can be used to obtain new requests. In related technologies, the update of the hardware available index is not affected by the abnormal restart of SPDK, that is, the FPGA will continuously obtain data read and write requests from the host device and update the hardware available index synchronously. This will cause some requests to be lost, causing read and write abnormalities. For example, during the SPDK abnormality process, the FPGA sends Desc[2], but the SPDK does not receive and process Desc[2]. After the SPDK restarts, it will continue to process Desc[3], and Desc[2] will no longer be processed. In this embodiment, after the SPDK restarts abnormally, the hardware available index is set to be equal to the used ring index, so that the FPGA can obtain the unprocessed data read and write requests.

[0031] In this embodiment of the application, updating the hardware availability index hw_available_idx=used_ring_idx in the FPGA includes: Update the hardware availability index hw_available_idx=used_ring_idx in the FPGA using SPDK.

[0032] In this embodiment, the action of updating hw_available_idx=used_ring_idx is controlled by SPDK, which can effectively avoid data loss due to insufficient hardware resources or abnormalities. Specifically, it no longer relies on the complex timer and caching mechanisms inside the FPGA to track timeout descriptors, but instead manages the request status uniformly by the software layer, reducing the occupation of FPGA hardware SRAM and alleviating the pressure on hardware resources. At the same time, the way SPDK updates hw_available_idx is also easier to maintain and upgrade, because software logic modifications are more flexible than hardware design, and functional iteration can be achieved without recompiling and burning the FPGA firmware.

[0033] In this embodiment, the data direction of the DPU is currently that the FPGA obtains data from the Host and then forwards it to the SPDK, which then forwards it to the storage backend to complete the disk write-to-disk process. Alternatively, the data processing capabilities of the SPDK can be hard-coded onto the FPGA. After obtaining the data, the FPGA queries the SPDK for routing information and sends the data to the corresponding storage backend. The entire data transmission process is accelerated by hardware, thereby significantly improving read and write performance.

[0034] Step 103: Obtain a data read / write request from the first device based on the hw_available_idx.

[0035] In this embodiment, the FPGA retrieves new data storage requests from the first device based on the value of the hardware available index. Since the hardware available index is already aligned with the used ring index, this means the FPGA will start retrieving requests from those that have not yet been processed, thus ensuring the continuity and integrity of the requests. This process is completed automatically by the FPGA without host intervention, improving the system's automation and efficiency.

[0036] In this embodiment of the application, the method further includes: if the SPDK restarts abnormally, stopping the acquisition of data read / write requests from the first device; after updating the hardware availability index hw_available_idx=used_ring_idx in the FPGA, acquiring data read / write requests from the first device based on hw_available_idx.

[0037] In this embodiment, when the SPDK restarts abnormally, the FPGA will pause acquiring new data storage requests from the first device. This is because if acquiring new data storage requests is not blocked, hw_available_idx will continue to update, affecting the implementation of the hw_available_idx=used_ring_idx operation.

[0038] In this embodiment of the application, by stopping data acquisition when SPDK restarts abnormally and restarting the acquisition request after recovery by updating hw_available_idx according to used_ring_idx, the problem of data loss or duplicate processing can be effectively prevented, thereby ensuring the lossless nature of I / O and improving the overall system reliability and stability.

[0039] In this embodiment of the application, after obtaining a data read / write request from the first device based on the hw_available_idx, the method further includes: For two duplicate data read / write requests stored locally on the FPGA, the FPGA marks one of the duplicate data read / write requests.

[0040] In this embodiment of the application, during the SPDK exception process, the FPGA may still have requests that have not been sent to the SPDK. For example, the FPGA may have three requests: Desc[0], Desc[1], and Desc[2]. Desc[0] and Desc[1] have been sent to the SPDK. The SPDK restarts abnormally, but Desc[2] has not yet been sent to the SPDK. At this time, used_ring_idx is 2, and hw_available_idx is updated from 3 to 2. The FPGA will start from Desc[2] and obtain requests from the host device. The FPGA will obtain Desc[2] again. The FPGA has two Desc[2] locally. If both Desc[2] are processed, the host device will release resources after the first Desc[2] responds, and the second Desc[2] cannot be processed, resulting in an exception.

[0041] In this embodiment, the FPGA marks one of the two repeated data read / write requests, so that the SPDK can discard one of the two repeated data read / write requests to avoid abnormal situations.

[0042] In this embodiment of the application, the method further includes: The FPGA sends local data read / write requests to the SPDK. The SPDK is used to discard tagged data read / write requests and send untagged data read / write requests to the second device.

[0043] In this embodiment, the second device refers to the device that ultimately receives and processes data read / write requests. After receiving a request from the FPGA, the SPDK identifies requests marked as duplicates and discards them to prevent data conflicts or memory anomalies caused by duplicate requests. Unmarked requests are forwarded normally to the second device for disk write processing.

[0044] In this embodiment, the FPGA sends local data read / write requests to the SPDK. The SPDK discards the marked read / write requests and sends the unmarked data read / write requests to the second device. The SPDK implements deduplication logic, which reduces the dependence on hardware resources, reduces the consumption of FPGA hardware resources, and improves the system's adaptability and iterative upgrade capability.

[0045] In this embodiment of the application, the step of marking one of the two duplicate data read / write requests in the FPGA's local storage by the FPGA includes: For two duplicate data read / write requests stored locally on the FPGA, the earlier data read / write request among the two duplicate data read / write requests is marked by the FPGA.

[0046] In this embodiment of the application, the following situation may occur: if an SPDK exception occurs, Desc[0] has been completed, Desc[1] has been sent to the SPDK but the SPDK fails to process it due to the exception, and Desc[2] is stored inside the FPGA and not sent to the SPDK. Then the FPGA starts to obtain the request from Desc[1] and obtains Desc[2] again. If the newly obtained Desc[2] is marked as discarded, then Desc[2] will be before Desc[1] in the queue order maintained inside the FPGA, which changes the queue order and may cause an exception.

[0047] In this embodiment of the application, the method further includes: using SPDK to return the response corresponding to the data read / write request to the FPGA in the order in which the data read / write requests are obtained by the FPGA.

[0048] In this embodiment, the SPDK must ensure that the order in which it receives requests from the FPGA and replies to the FPGA after completing the requests is consistent. For example, the Host sends two requests, which are in the order of Desc[0] and Desc[1] in the Desc Table. The FPGA first sends Desc[0] to the SPDK, and then sends the request Desc[1] to the SPDK. The SPDK sends these two requests to the storage backend. The storage backend may respond to the request Desc[1] first. The SPDK sends the response to the request Desc[1] to the FPGA. After the Host receives the response, it releases the memory of Desc[1]. At this time, the SPDK crashes abnormally and restarts. The FPGA triggers a retransmission. Since the used ring idx=1, the FPGA will access the non-existent Desc[1] and an error will occur.

[0049] refer to Figure 3 , Figure 3 This is a schematic diagram of the SPDK processing logic provided in the embodiments of this application, such as... Figure 3 As shown, SPDK has two independent queues, queue 1 and queue 2. For queue 1, the order in which SPDK receives requests is blkrequest1, blk request2, and blk request3. Therefore, the order in which the responses are returned to the FPGA should also be the response to blk request1, the response to blk request2, and the response to blk request3. Even if blk request3 completes first, it needs to wait for the responses to blk request1 and blk request2 to return before returning the response to blk request3. The same logic applies to queue 2. Even if blk request3 completes first, it needs to wait for the responses to blk request1 and blk request2 to return before returning the response to blk request3. Furthermore, for queue 2, if SPDK detects a marked blk request1 among the requests sent by the FPGA, it will discard blk request1.

[0050] It should be noted that in this embodiment of the application, the host device includes multiple parallel request queues. For each request queue, there is a corresponding hw_available_idx and used_ring_idx. The DPU performs parallel data transmission on multiple request queues and processes the hw_available_idx and used_ring_idx of each queue separately.

[0051] In this embodiment, a blk_lossless_io module can be added to the FPGA. This module includes one or more of the following functions: reading used_ring_idx; modifying hw_available_idx in the FPGA memory; configuring queue rate limiting, blocking storage queue scheduling, and stopping the FPGA from obtaining request data from the Host; marking duplicate requests that need to be discarded. That is, the functions of SPDK can also be implemented by the FPGA.

[0052] refer to Figure 4 , Figure 4 A flowchart illustrating the data transmission method provided in the embodiments of this application. Figure 2 ,like Figure 4 As shown, it includes the following steps: Step 201: SPDK restarts abnormally.

[0053] SPDK crashed and restarted due to an abnormal situation.

[0054] Step 202: The FPGA stops acquiring requests, ensures there is no data in transit in the FPGA-Host direction, and updates used_ring_idx.

[0055] The FPGA blocks the Virtio queue in the Host-FPGA direction to ensure that all completed request responses are sent to the Host. There is no data in transit in the FPGA-Host direction. The used_ring_idx of all Virtio queues is updated.

[0056] Step 203: Update hw_available_idx.

[0057] Update hw_available_idx=used_ring_idx for all Host-FPGA direction Virtio queues.

[0058] Step 204: Based on hw_available_idx, the FPGA reacquires the request.

[0059] The FPGA enables Virtio queue scheduling in the Host-FPGA direction, and requests are re-transferred from the hw_available_idx position of each Virtio queue.

[0060] Step 205: Mark and discard duplicate requests.

[0061] The FPGA performs data deduplication, marking duplicate requests that are not for the current continuation. The SPDK then discards the marked requests to ensure their uniqueness.

[0062] Step 206: SPDK processes untagged requests normally.

[0063] SPDK sends untagged requests to the storage device, and SPDK startup is complete.

[0064] The data transmission method provided in this application, under FPGA hardware configuration, leverages the characteristics of the Virtio protocol to achieve data retransmission and offloads a portion of the Virtio control plane to the SPDK, reducing FPGA hardware memory resource consumption. A hardware-software collaborative storage anomaly continuation scheme is proposed, with the FPGA hardware incorporating a new I / O resource processing mechanism and the SPDK software incorporating a new resource control and detection mechanism. The FPGA and SPDK, adhering to the Virtio communication protocol, collaboratively ensure lossless storage I / O. This application's scheme places the control logic on the software side and utilizes the new resource control and detection mechanism in the SPDK software, significantly reducing FPGA memory usage and maintenance costs. It can be adopted by various DPU configurations, exhibiting excellent adaptability; and it addresses the shortcomings of inability to intelligently iterate and upgrade functions and the time-consuming compilation, testing, and verification processes.

[0065] The solution proposed in this application can be used to solve the problem of business damage caused by storage anomalies in DPU bare metal server and DPU cloud host scenarios. It can also be applied to other data transmission scenarios, but this application does not limit the scope of the solution.

[0066] This application also provides a data transmission device, see reference. Figure 5 , Figure 5 This is a schematic diagram of the data transmission device provided in an embodiment of this application. The data transmission device in this embodiment is applied to a DPU and includes: Control unit: If SPDK restarts abnormally, it sends one or more responses sent by SPDK to the first device via FPGA, and updates the used ring index used_ring_idx; the response indicates that the data read / write request corresponding to the response has been completed in the second device; updates the hardware availability index hw_available_idx=used_ring_idx in the FPGA; and obtains the data read / write request from the first device based on hw_available_idx.

[0067] In this embodiment of the application, the control unit is configured to: stop obtaining data read / write requests from the first device if the SPDK restarts abnormally; and obtain data read / write requests from the first device based on the hw_available_idx after updating the hardware availability index hw_available_idx=used_ring_idx in the FPGA.

[0068] In this embodiment of the application, the control unit is used to mark one of the two repeated data read / write requests in the FPGA local storage.

[0069] In this embodiment of the application, the control unit is used to send local data read / write requests to the SPDK via the FPGA; The SPDK is used to discard tagged data read / write requests and send untagged data read / write requests to the second device.

[0070] In this embodiment of the application, the control unit is used to mark the earlier data read / write request among two repeated data read / write requests stored locally on the FPGA via the FPGA.

[0071] In this embodiment of the application, the control unit is used to return a response corresponding to a data transmission request to the FPGA in the order in which the FPGA obtains the data transmission requests via SPDK.

[0072] In this embodiment of the application, the control unit is used to update the hardware availability index hw_available_idx=used_ring_idx in the FPGA via SPDK.

[0073] Those skilled in the art should understand that Figure 5 The functions of each unit in the data transmission device shown can be understood by referring to the relevant description of the aforementioned method. Figure 5 The functions of each unit in the data transmission device shown can be implemented by a program running on a processor or by specific logic circuits.

[0074] Figure 6 This is a schematic structural diagram of an electronic device provided in an embodiment of this application. Figure 6 The electronic device shown includes a processor 610, which can call and run computer programs from memory to implement the data transmission method provided in the embodiments of this application.

[0075] Optionally, such as Figure 6As shown, the electronic device may further include a memory 620. The processor 610 can retrieve and run computer programs from the memory 620 to implement the data transmission method provided in the embodiments of this application.

[0076] The memory 620 can be a separate device independent of the processor 610, or it can be integrated into the processor 610.

[0077] Optionally, such as Figure 6 As shown, the electronic device may also include a transceiver 630, which the processor 610 can control to communicate with other devices. Specifically, it can send information or data to other devices or receive information or data sent by other devices.

[0078] The transceiver 630 may include a transmitter and a receiver. The transceiver 630 may further include antennas, and the number of antennas may be one or more.

[0079] Specifically, the electronic device may be a data transmission device in the embodiments of this application, and the electronic device may implement the corresponding processes implemented by the data transmission device in the various methods of the embodiments of this application. For the sake of brevity, it will not be described in detail here.

[0080] For example, embodiments of this application also provide a computer program product, including a computer program that can be executed by a processor 610 of an electronic device to perform the steps described in any of the foregoing methods.

[0081] Figure 7 This is a schematic structural diagram of the chip according to an embodiment of this application. Figure 7 The chip shown includes a processor 710, which can call and run computer programs from memory to implement the methods in the embodiments of this application.

[0082] Optionally, such as Figure 7 As shown, the chip may also include a memory 720. The processor 710 can retrieve and run computer programs from the memory 720 to implement the methods described in this embodiment.

[0083] The memory 720 can be a separate device independent of the processor 710, or it can be integrated into the processor 710.

[0084] Optionally, the chip may also include an input interface 730. The processor 710 can control the input interface 730 to communicate with other devices or chips; specifically, it can acquire information or data sent by other devices or chips.

[0085] Optionally, the chip may also include an output interface 740. The processor 710 can control the output interface 740 to communicate with other devices or chips, specifically, to output information or data to other devices or chips.

[0086] This chip can be applied to the electronic devices in the embodiments of this application, and the chip can implement the corresponding processes implemented by the electronic devices in the various methods of the embodiments of this application. For the sake of brevity, it will not be described in detail here.

[0087] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0088] It should be understood that the processor in the embodiments of this application may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software units in the decoding processor. The software units can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0089] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0090] It should be understood that the above-described memory is exemplary and not a limiting description. For example, the memory in the embodiments of this application may also be static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DR RAM), etc. That is to say, the memory in the embodiments of this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0091] This application also provides a storage medium for storing a computer program. This storage medium can be applied to the electronic device in this application embodiment, and the computer program causes the computer to execute the corresponding processes implemented by the electronic device in the various methods of this application embodiment; for brevity, further details are omitted here.

[0092] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0093] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0094] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0095] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0096] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0097] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0098] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data transmission method, characterized in that, Applied to a DPU, the method includes: If SPDK restarts abnormally, one or more responses sent by SPDK will be sent to the first device via the FPGA, and the used ring index used_ring_idx will be updated; the response indicates that the data read / write request corresponding to the response has been completed in the second device; Update the hardware availability index hw_available_idx in the FPGA to used_ring_idx; Data read / write requests are obtained from the first device based on the hw_available_idx.

2. The method according to claim 1, characterized in that, The method further includes: If the SPDK restarts abnormally, it stops obtaining data read / write requests from the first device; after updating the hardware availability index hw_available_idx=used_ring_idx in the FPGA, it obtains data read / write requests from the first device based on hw_available_idx.

3. The method according to claim 2, characterized in that, After obtaining a data read / write request from the first device based on the hw_available_idx, the method further includes: For two duplicate data read / write requests stored locally on the FPGA, the FPGA marks one of the duplicate data read / write requests.

4. The method according to claim 3, characterized in that, The method further includes: The FPGA sends local data read / write requests to the SPDK. The SPDK is used to discard tagged data read / write requests and send untagged data read / write requests to the second device.

5. The method according to claim 4, characterized in that, For two duplicate data read / write requests in the FPGA's local storage, the method of marking one of the two duplicate data read / write requests by the FPGA includes: For two duplicate data read / write requests stored locally on the FPGA, the earlier data read / write request among the two duplicate data read / write requests is marked by the FPGA.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: SPDK returns the corresponding responses to the data read / write requests to the FPGA in the order in which the data read / write requests are received by the FPGA.

7. The method according to any one of claims 1 to 5, characterized in that, The update of the hardware availability index hw_available_idx=used_ring_idx in the FPGA includes: Update the hardware availability index hw_available_idx=used_ring_idx in the FPGA using SPDK.

8. A data transmission device, characterized in that, Applied to DPU, characterized in that it includes: Control unit: If SPDK restarts abnormally, it sends one or more responses sent by SPDK to the second device via FPGA, and updates the used ring index used_ring_idx; the response indicates that the data read / write request corresponding to the response has been completed in the second device; updates the hardware availability index hw_available_idx=used_ring_idx in the FPGA; and obtains the data read / write request from the first device based on hw_available_idx.

9. An electronic device, characterized in that, include: A processor and a memory, the memory for storing a computer program, the processor for calling and running the computer program stored in the memory to perform the data transmission method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, Used to store a computer program that causes a computer to perform the data transmission method as described in any one of claims 1 to 7.

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