DDR5 module design method, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a DDR5 module design method and device, electronic equipment and a storage medium, and relates to the technical field of high-speed memory module design, and the method comprises the steps that a register clock driver RCD module and a data buffer module are integrated into a single IMB chip; iMB conversion chips are additionally arranged in two channels of a DDR5 module respectively, the IMB conversion chips are symmetrically arranged in the middle of the front face of a PCB, DRAM particle mirror images are arranged on the front face and the back face of the PCB, and data signal MDQ and command address signal QCA transmission path multiplexing is designed; a power management chip PMIC is arranged for multi-phase power supply, a serial detection SPD chip is arranged for centralized control, a Flyby topology is adopted for driving QCA and MDQ signals, and a pre-emphasis technology is combined; a ZQ calibration circuit is arranged in the IMB chip to adjust output impedance, and a pin expansion and signal buffer module is arranged in the IMB chip. According to the method, the problems of complicated layout, high signal transmission risk, difficulty in cooperative control and the like are effectively solved, and the requirements of high-performance calculation on high-density integration and high efficiency of the memory are met.

Description

Technical Field

[0001] This invention relates to the field of high-speed memory module design technology, and in particular to a DDR5 module design method, electronic device and storage medium. Background Technology

[0002] With the rapid development of big data, cloud computing, and artificial intelligence technologies, data processing volume is exploding, placing higher demands on the performance of memory subsystems. DDR5, as the fifth generation of double data rate memory, has become a core component in high-performance computing and artificial intelligence fields due to its higher memory frequency, larger memory capacity, and lower operating voltage.

[0003] However, in traditional DDR5 MRDIMM memory modules, the RCD (register clock driver) and Data Buffer are set up separately, which leads to complex module layout, increased PCB area and increased routing difficulty.

[0004] Meanwhile, discrete chip layout increases signal-driven risks and power consumption, and the complexity of collaborative control also increases, making it difficult to meet the requirements of modern high-performance computing for high-density integration, low power consumption and high efficiency of memory subsystems.

[0005] Therefore, there is an urgent need for a DDR5 module design method that can integrate RCD and Data Buffer functions, optimize signal layout and module structure, improve memory subsystem performance, and reduce power consumption and cost. Summary of the Invention

[0006] This invention provides a DDR5 module design method to address the problems of complex module layout, large PCB area and wiring difficulty, high signal driving risk and power consumption, and complex collaborative control in existing technologies. The technical solution is as follows: According to one aspect of the present invention, a DDR5 module design method includes: integrating a register clock driver (RCD) module and a data buffer (Data Buffer) module into a single IMB chip, and defining an interface; the IMB chip internally integrates a clock synchronization subunit (PLL) module, a DCA decoding circuit module, a QCA driver circuit module, and a Data Buffer module. The system includes a buffer module and a signal calibration unit. IMB conversion chips are added to each of the two channels of the DDR5 module, symmetrically deployed on the center of the front side of the PCB. DRAM chips are mirror-laid on both sides of the PCB. Data signal MDQ and command address signal QCA transmission paths are multiplexed. Equal-length wiring is used to connect the DQ and CA signals to the input pins of the IMB chips. A power management chip (PMIC) is used for power supply, and an SPD chip is used for parameter configuration. Flyby topology drives the QCA and MDQ signals, and pre-emphasis technology is used to optimize the signals. Signal processing is performed through the IMB chips. Differentiated signal multiplexing strategies are used for the DRAM chips on both sides of the DDR5 module. A ZQ calibration circuit is set within the IMB chip to adjust the output impedance, pin expansion, and signal buffer module. The DDR5 gold finger electrical interface specification is adopted.

[0007] In one embodiment, integrating the register clock driver RCD module and the data buffer module into a single IMB chip is achieved through the following steps: using a 14mm×14mm packaged IMB chip, and integrating the RCD module, the data buffer module, and the signal calibration unit; the clock synchronization subunit PLL supports dynamic frequency modulation from 1.0GHz to 4.4GHz; the DCA decoding circuit adopts 2N mode dual-cycle conversion; the QCA driver circuit supports dynamic ODT technology; the output impedance is dynamically adjusted through the ZQ calibration circuit by the signal calibration unit; the data buffer module integrates a DQ latch unit and an MDQ driver circuit; the DQ latch unit is 8-bit parallel processing; the MDQ driver circuit has an adjustable pre-emphasis level; the ZQ calibration circuit is externally connected to a high-precision resistor; the IMB chip supports high-density integration and low-power design.

[0008] In one embodiment, the IMB conversion chips are symmetrically deployed on the center of the front side of the PCB board, and the DRAM chips are mirror-laid on both sides of the PCB board. This is achieved through the following steps: the IMB conversion chips are symmetrically deployed on the center of the front side of the PCB board with the distance from the gold fingers within a set range; each sub-channel includes 32 bits of data and 8 bits of ECC; the front DRAM array is divided into dual channels, and the back DRAM is mirror-laid symmetrically with the front DRAM; the power management chip (PMIC) is placed on the front side of the PCB board; the distance between the serial detection chip (SPD) and the power management chip (PMIC) is set within a set range; and the IMB chips, the power management chip (PMIC), and the host are centrally controlled via an I2C hub bus.

[0009] In one embodiment, the multiplexing of the data signal MDQ and the command address signal QCA transmission path is achieved through the following steps: the MDQ and QCA signals on the front side are multiplexed through vias, the QCK clock signal and the QCS chip selection signal are set to be output independently by the IMB chip to the front and back particles respectively, and the input signal path is designed with equal-length wiring; the length difference of the equal-length wiring is ≤0.1mm.

[0010] In one embodiment, power supply using a power management chip (PMIC) and parameter configuration using an SPD chip are achieved through the following steps: the power management chip (PMIC) is configured using multi-phase power supply technology; the power supply pins of the IMB chip are directly connected via PCB copper foil; and the I2C HUB bus is used to centrally monitor the status of the IMB chip, the power management chip (PMIC), and the host device via the SPD chip.

[0011] In one embodiment, the QCA and MDQ signals are driven using Flyby topology, and pre-emphasis technology is used to achieve the following steps: the QCA and MDQ signals are driven using Flyby topology, each group of signals drives 4 DRAM chips, and pre-emphasis technology is used; the modular design of the IMB chip supports functional upgrades.

[0012] In one embodiment, a ZQ calibration circuit is incorporated within the IMB chip to adjust output impedance, pin expansion, and signal buffering modules. This is achieved using the DDR5 gold finger electrical interface specification through the following steps: the IMB chip adopts the DDR5 gold finger electrical interface specification; the IMB chip supports pin expansion and signal buffering modules, and capacity expansion is achieved by increasing the number of DRAM chips on the transmission lines; the ZQ calibration circuit dynamically adjusts the output impedance using an external resistor; and the IMB chip manages all signal paths within the channel through an internal timing calibration module and a dynamic signal adjustment circuit, optimizing timing synchronization and load balancing in high-frequency scenarios.

[0013] In one embodiment, signal processing via the IMB chip is achieved through the following steps: the DQ signal is input into the Data Buffer module in 5 channels, latched, and then output as 5 groups of MDQ signals; the CA signal in a single channel is expanded into 5 parallel input DCA decoding circuits to generate 5 groups of QCA signals; the DCK signal is phase-calibrated by a PLL to generate QCK differential signals to drive the DRAM chips; 5 groups of parallel outputs are connected to the CA pins of all DRAM chips in a single channel via a Flyby topology; 5 groups of parallel outputs are connected to the DQ pins of all DRAM chips in a single channel via a Flyby topology, using differential pair transmission.

[0014] According to one aspect of the present invention, an electronic device includes at least one processor and at least one memory, wherein computer-readable instructions are stored on the memory; the computer-readable instructions are executed by one or more of the processors to cause the electronic device to implement the DDR5 module design method as described above.

[0015] According to one aspect of the present invention, a storage medium has computer-readable instructions stored thereon, which are executed by one or more processors to implement the DDR5 module design method as described above.

[0016] The beneficial effects of the technical solution provided by this invention are: In the above technical solution, this invention integrates the register clock driver RCD module and the data buffer module into a single IMB chip, and adds IMB conversion chips to each of the two channels of the DDR5 module. The IMB chip integrates multiple functional modules, possessing signal processing and calibration capabilities, which can improve signal quality and stability. In terms of layout, the IMB chip is symmetrically deployed, and the DRAM chips are mirrored, optimizing space utilization and signal transmission. The design employs multiplexing of the data signal MDQ and command address signal QCA transmission paths, combined with equal-length wiring, multi-phase power supply, Flyby topology, and pre-emphasis technology, further optimizing signal transmission. The IMB chip dynamically adjusts the output impedance through the ZQ calibration circuit, supports pin expansion and signal buffering, realizes capacity expansion, and manages all signal paths within the channel, optimizing timing synchronization and load balancing in high-frequency scenarios. Through the above innovative design, this invention not only improves the performance and stability of the DDR5 module, but also enhances its scalability and adaptability, effectively solving problems such as poor signal transmission quality, unreasonable layout, and insufficient scalability in existing technologies. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a DDR5 module design method according to an exemplary embodiment; Figure 2 This is a floorplan diagram of an IMB chip according to an exemplary embodiment; Figure 3 yes Figure 2 A schematic diagram of the overall layout of the DDR5 module in the corresponding embodiment; Figure 4 yes Figure 2 A schematic diagram of the overall layout of the back of the DDR5 module in the corresponding embodiment; Figure 5 yes Figure 2 A schematic diagram of the topology of the MDQ in the DDR5 module in the corresponding embodiment; Figure 6 This is a hardware structure diagram of an electronic device according to an exemplary embodiment; Figure 7 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0019] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0020] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this disclosure means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0021] This invention provides a DDR5 module design method. By integrating RCD and Data Buffer modules into a single IMB chip and optimizing the layout and signal transmission design, it improves the performance and stability of the DDR5 module and expands its capacity. This solves the problems of poor signal transmission quality, unreasonable layout, and limited scalability in existing technologies. This DDR5 module design method is applicable to DDR5 module design devices, which can be electronic devices. The DDR5 module design method in this invention can be applied to various scenarios, such as DDR5 module design.

[0022] Please see Figure 1 This invention provides a DDR5 module design method, which is applicable to electronic devices.

[0023] In the following method embodiments, for ease of description, the execution subject of each step of the method is an electronic device, but this does not constitute a specific limitation.

[0024] like Figure 1 As shown, the method may include the following steps: Step 110: Integrate the register clock driver RCD module and the data buffer module into a single IMB chip and define the interface.

[0025] The IMB chip integrates a clock synchronization subunit PLL module, a DCA decoding circuit module, a QCA drive circuit module, a data buffer module, and a signal calibration unit.

[0026] In one possible implementation, a 14mm×14mm packaged IMB chip is used, and an RCD module is integrated. The output impedance is dynamically adjusted by the ZQ calibration circuit through the signal calibration unit. The clock synchronization subunit PLL supports dynamic frequency modulation from 1.0GHz to 4.4GHz, and the DCA decoding circuit adopts 2N mode dual-cycle conversion. The QCA drive circuit supports dynamic ODT technology.

[0027] The Data Buffer module integrates a DQ latch unit and an MDQ drive circuit; the DQ latch unit is 8-bit parallel processing, and the MDQ drive circuit has an adjustable pre-emphasis level; the ZQ calibration circuit is connected to an external high-precision resistor; the IMB chip supports high-density integration and low-power design.

[0028] Specifically, the IMB chip integrates a clock synchronization subunit (PLL), a DCA decoding circuit, and a QCA driver circuit. The PLL supports dynamic frequency modulation from 1.0GHz to 4.4GHz, dynamically adjusting the output clock phase according to the DRAM operating mode to solve clock synchronization problems in high-frequency scenarios. The DCA decoding circuit uses 2N mode (dual-cycle command transmission) conversion logic to resolve 7 DCA signals into 14 QCA signals, improving command transmission efficiency. The QCA driver circuit: DDR5 chips support dynamic ODT (on-chip termination) technology. By configuring corresponding ODT parameters for the chips through the IMB chip, signal quality is optimized and reflections are reduced under different circuit conditions.

[0029] Specifically, the Data Buffer module integrates a DQ latch unit (8-bit parallel processing) and an MDQ driver circuit (adjustable pre-emphasis level). The DQ latch unit is designed to match DDR5 channels and supports high-speed data latching. The MDQ driver circuit integrates pre-emphasis functionality to compensate for high-frequency attenuation and improve signal integrity. The signal calibration unit, with its ZQ calibration circuit, dynamically adjusts the output impedance and CA bus termination resistor via an external high-precision resistor to ensure impedance matching.

[0030] The IMB chip has 416 pins: 102 input pins (5 channels of 7-bit DCA, 5 channels of 8-bit DQ, 5 pairs of *DQS differential pairs, etc.); 162 output pins (5 groups of 14-bit QCA, 5 groups of 8-bit MDQ, etc.); 143 power supply pins (43 VDD, 100 VSS); and 9 auxiliary signal pins (ZQ pin, DERROR pin, etc.).

[0031] In the above process, this embodiment of the invention integrates the RCD and Data Buffer modules into a single IMB chip through a highly integrated design, reducing PCB routing complexity and improving reliability. Through dynamic frequency modulation, pre-emphasis, and ODT technology, it supports high-frequency DDR5 operation, significantly reducing the number of chips and physical space occupied in the module, thus improving product reliability and design flexibility. Simultaneously, the optimized design of the internal circuitry ensures accurate signal synchronization and transmission quality, laying a solid foundation for subsequent efficient signal transmission.

[0032] Step 120: Add IMB conversion chips to the two channels of the DDR5 module respectively, deploy the IMB conversion chips symmetrically in the center of the front of the PCB board, mirror the DRAM chips on the front and back of the PCB board, and design the multiplexing of the data signal MDQ and the command address signal QCA transmission paths.

[0033] In one possible implementation, the IMB conversion chip is symmetrically deployed in the center of the front side of the PCB with the distance from the gold fingers within a set range; the front DRAM array is divided into dual channels, and the rear DRAM is arranged in a mirror symmetrical layout with the front DRAM; the power management chip PMIC is placed on the front side of the PCB; the distance between the serial detection chip SPD chip and the power management chip PMIC is set within a set range, and the IMB chip, power management chip PMIC and host are centrally controlled through the I2C HUB bus.

[0034] Each sub-channel includes 32 bits of data and 8 bits of ECC.

[0035] In one possible implementation, the MDQ and QCA signals on the front side are multiplexed via vias, and the QCK clock signal and QCS chip select signal are set to be output independently to the front and back chips by the IMB chip, respectively, with equal-length wiring designed for the input signal paths.

[0036] Among them, the length difference of equal-length wiring is ≤0.1mm.

[0037] Specifically, the two IMB chips are symmetrically distributed in the center of the front of the PCB (near the gold fingers), corresponding to two 32-bit data + 8-bit ECC sub-channels of DDR5. DRAM array layout: Front: Divided into A / B dual channels, with 5 groups of chips per channel (4 chips per group). Back: Mirror symmetrical to the front, with MDQ / QCA signals multiplexed through vias.

[0038] Specifically, the signal multiplexing strategy includes: shared signals: QCA, QRST, MDQ, MDQS, and MTDQS are shared by both front and back chips. Independent signals: QCK and QCS are output independently by both front and back chips.

[0039] In the above process, the embodiments of the present invention achieve simplified module structure and improved signal transmission efficiency through symmetrical deployment of IMB chips and differentiated signal multiplexing strategies, while reserving space for future capacity expansion. The mirror-symmetric layout of DRAM chips and the signal multiplexing strategy further reduce the wiring complexity and cost of the PCB board. These designs collectively improve the overall performance and reliability of the module.

[0040] Step 130: Using an equal-length wiring design, connect the DQ signal and CA signal to the input pin of the IMB chip. Use the power management chip PMIC to power the signal and configure the parameters of the SPD chip. Use the Flyby topology to drive the QCA and MDQ signals and combine pre-emphasis technology to optimize the signal.

[0041] In one possible implementation, a multi-phase power supply technology is used to configure the power management chip (PMIC), which is directly connected to the power supply pins of the IMB chip via the PCB copper foil. An I2C hub bus is used to centrally monitor the status of the IMB chip, the PMIC, and the host device via the SPD chip.

[0042] In one possible implementation, a Flyby topology is used to drive the QCA and MDQ signals, with each group of signals driving four DRAM chips, combined with pre-emphasis technology.

[0043] The modular design of the IMB chip supports functional upgrades; the PCB layout can be flexibly adjusted according to parameters such as device size and signal rate, and no restrictions are imposed here.

[0044] Specifically, the DQ / DCA signals of the gold fingers are connected to the IMB chip via microstrip lines on the PCB surface, with a length difference of ≤0.1mm to ensure timing synchronization. DCA→QCA conversion: A 14-bit QCA signal is generated after PLL synchronous decoding. DCK→QCK conversion: The clock signal is phase-calibrated to generate a differential clock pair. DQ→MDQ conversion: The data signal is latched and filtered to generate a pre-emphasized MDQ signal. The QCA / MDQ signals employ a 1-to-4 design, with each signal group driving four DRAM chips, combined with end-matching technology to reduce reflections.

[0045] In the above process, the embodiments of the present invention optimize the signal transmission topology and internal processing logic to improve signal integrity and reduce driving risks. The Flyby topology and pre-emphasis technology reduce signal attenuation and support high-frequency operation. The 1-drive-4 design simplifies wiring and avoids long-distance transmission risks, providing reliable support for DDR5 high-frequency scenarios.

[0046] Step 140: Signal processing is performed through the IMB chip. A differentiated signal multiplexing strategy is adopted for the DRAM chips on the front and back of the DDR5 module. A ZQ calibration circuit is set in the IMB chip to adjust the output impedance, pin expansion and signal buffer module, and the DDR5 gold finger electrical interface specification is adopted.

[0047] In one possible implementation, the IMB chip uses the DDR5 gold finger electrical interface specification. The DQ signal is input into the Data Buffer module in 5 channels, latched, and then output as 5 groups of MDQ signals. The CA signal in a single channel is expanded into 5 parallel input DCA decoding circuits to generate 5 groups of QCA signals. The DCK signal is phase-calibrated by a PLL to generate QCK differential signals to drive the DRAM chips. 5 groups of parallel outputs are connected to the CA pins of all DRAM chips in a single channel via a Flyby topology, and 5 groups of parallel outputs are connected to the DQ pins of all DRAM chips in a single channel via a Flyby topology, using differential pair transmission.

[0048] The IMB chip supports pin expansion and signal buffering modules, as well as capacity expansion by increasing the number of DRAM chips on the transmission line. The IMB chip manages all signal paths in the channel through an internal timing calibration module and dynamic signal adjustment circuit, and optimizes timing synchronization and load balancing in high-frequency scenarios.

[0049] Specifically, PMIC layout: One PMIC is located on the front of the PCB, supporting multi-phase power supply, and connected to the IMB chip power supply pins via copper traces. Low-power design: Integration reduces power loss from discrete chips, and shared power domains reduce interactive power consumption. SPD chip: Centrally monitors the status of the IMB, PMIC, and host via an I2C hub bus. ZQ calibration: Dynamically adjusts output impedance to optimize signal quality.

[0050] In the above process, the embodiments of the present invention reduce energy consumption through multi-phase power supply technology and centralized parameter configuration, integrated and shared power domain design, retain DDR5 gold finger interface, and adapt to existing controllers (such as Intel Xeon Scalable), thereby achieving reduced module power consumption and improved compatibility, and providing an efficient solution for high-performance computing scenarios.

[0051] Through the above process, this invention addresses the problems of complex layout, high power consumption, and high signal transmission risk inherent in traditional DDR5 MRDIMM architectures by integrating IMB chips, optimizing module layout and signal multiplexing, improving signal transmission topology, and refining power management. The solution boasts advantages such as high integration, low power consumption, strong compatibility, and easy scalability, meeting the future demands for memory bandwidth and capacity in high-performance computing and artificial intelligence scenarios.

[0052] like Figure 2 As shown in an exemplary embodiment, the IMB chip uses a 14mm × 14mm package and integrates the following core functional modules: Clock synchronization subunit (PLL): Supports dynamic frequency modulation from 1.0GHz to 4.4GHz, realizes clock synchronization and phase calibration of DCK signal, generates QCK differential clock pair, and ensures timing synchronization in high-frequency scenarios.

[0053] DCA decoding circuit: It adopts 2N mode dual-cycle conversion logic to expand the 7-bit DCA signal in a single channel into 5 parallel inputs, and decodes to generate 5 groups of 14-bit QCA signals. It supports dynamic ODT (on-chip termination) technology and dynamically adjusts the output impedance through the ZQ calibration circuit with external high-precision resistors.

[0054] QCA driver circuit: Supports ODT parameter configuration for DDR5 chips, optimizing signal integrity.

[0055] Data Buffer module: Includes an 8-bit parallel processing DQ latch unit and an MDQ drive circuit with adjustable pre-emphasis level, which latches and filters the DQ signal to generate the MDQ signal.

[0056] Signal calibration unit: Output impedance matching is achieved through ZQ calibration circuit, supporting load balancing in high-frequency scenarios.

[0057] Specifically, the IMB chip has a total of 416 pins, including: The system has 102 input pins (5 x 7-bit DCA signals, 5 x 8-bit DQ signals, 5 x DQS differential pairs, 5 x TDQS differential pairs, 2 x DCK differential pairs, 2 x DCS signals, and 1 x DRST signal); 162 output pins (5 x 14-bit QCA signals, 5 x 8-bit MDQ signals, 5 x MDQS differential pairs, 5 x MTDQS differential pairs, 10 x QCK differential pairs, 10 x QCS signals, 1 x QRST signal, and 1 x ALERT signal); 143 power supply pins (including 43 RCD and Data buffer power supply pins VDD and 100 ground pins VSS); and 9 auxiliary signal pins (1 LSCL pin, 1 LSDA pin, 1 ZQ pin, 1 DERROR pin, and 5 RFU pins). like Figure 3 and Figure 4 As shown, the front and back layout design of the DDR5 module is illustrated. Figure 3As shown, the front is divided into Channel A (left) and Channel B (right). Each channel corresponds to a 32-bit data + 8-bit ECC sub-channel. Each channel contains 5 groups of DRAM chips (e.g., A1-A8 as one group, B1-B8 as another group), with 8 chips in each group, arranged in a 4×2 matrix. Symmetrical deployment of IMB chips: Two IMB chips are located in the center of the front of the PCB, corresponding to the two DDR5 32-bit data + 8-bit ECC sub-channels (Channel A and Channel B). DRAM chip arrangement: Each sub-channel contains 5 groups of DRAM chips (e.g., A1-A8 as one group, B1-B8 as another group), with 8 chips in each group, connected to the QCA and MDQ signals of the IMB chip via a Flyby topology. Power and monitoring module: The PMIC (Power Management Module) is deployed on the front of the PCB, providing stable power to the IMB chip through multi-phase power supply technology; the SPD chip is placed close to the PMIC, centrally monitoring the status of the IMB, PMIC, and host via an I2C HUB bus.

[0058] like Figure 4 As shown, the back-side DRAM chips are completely mirror images of the front-side chips, and the MDQ and QCA signals of the front-side chips are multiplexed through vias (e.g., A_DRAM_A1 and A_DRAM_A5 share the MDQ signal). The back-side chips (A5-A8 / B5-B8) of each channel share the same set of signal paths as the front-side chips (A1-A4 / B1-B4). The QCK clock signal and QCS chip select signal are output independently by the IMB chip to the front and back-side chips, and do not share a transmission path.

[0059] like Figure 5 The diagram illustrates the signal transmission topology and multiplexing strategy, divided into five groups from MDQ_E to MDQ_A. Each group corresponds to a sub-channel (e.g., MDQ_A connects all DRAM chips in channel A). MDQS / MTDQS are differential data strobe signals, transmitted synchronously with MDQ. Input signal path: Equal length routing: The DQ and DCA signals of the gold fingers are connected to the IMB chip via PCB traces, with a trace length difference ≤ 0.1mm to ensure synchronized signal arrival time. Each group of MDQ signals drives 8 DRAM chips (e.g., A_DRAM_A1-A8 share MDQ_A1).

[0060] Specifically, internal signal processing includes: DCA→QCA conversion: The DCA signal is synchronously decoded by the PLL to generate a 14-bit QCA signal, which drives the command address bus of the DRAM chip. DQ→MDQ conversion: The DQ signal is latched and filtered by the Data Buffer module to generate a pre-emphasized adjustable MDQ signal, improving the quality of high-frequency transmission.

[0061] Specifically, the output signal topology is Flyby topology. In this application, signals such as QCA and MDQ use a 1-to-8 design, with each signal group driving eight DRAM chips. Differential pair transmission is used for critical signals such as DQS / TDQS and QCK to suppress common-mode noise.

[0062] Specifically, the signal multiplexing strategy is as follows: Shared signals: QCA, QRST, MDQ, MDQS, and MTDQS are shared by the front and back chips, and the physical path is multiplexed through vias. Independent signals: QCK and QCS are independently output by the IMB chip to the front and back chips to avoid clock and chip select signal conflicts.

[0063] Specifically, power management and parameter configuration include: Multi-phase power supply: The PMIC is directly connected to the VDD pin of the IMB chip via the PCB copper trace, supporting dynamic voltage regulation to reduce power consumption. Centralized monitoring: The SPD chip monitors the status of the IMB chip, PMIC, and host in real time via the I2C HUB bus, achieving overcurrent and overtemperature protection. ZQ calibration: The IMB chip uses an external high-precision resistor connected to the ZQ pin to dynamically adjust the output impedance and optimize signal integrity.

[0064] It's worth noting that the input and output pins of the IMB chip can be expanded by adding internal buffer channels, but its integrated RCD and Data Buffer architecture and module layout principles remain unchanged. Additional signal buffer modules can be added to the IMB chip to support longer module lengths or more DRAM chips, but its core integrated architecture and shared signal logic remain the same. A flyby topology variant can use a T-branch topology instead of the flyby topology, with each group of QCA / MDQ signals split into two paths at the branch point.

[0065] like Figures 2 to 5 As shown, the DQ signals (DQ_A to DQ_E, 8 bits per group) and DCA signals of the gold fingers are connected to the input pins of the IMB chip through PCB traces. An equal-length wiring design (length difference ≤ 0.1mm) is adopted to ensure that the time deviation of the signals reaching the IMB chip is minimized.

[0066] Specifically, after the DCA signal enters the IMB chip, it is synchronized and decoded by the internal PLL (phase-locked loop) to generate the QCA signal (QCA_A to QCA_E, 14 bits per group); after the DCK signal enters the IMB chip, it is clocked and phase-calibrated by the internal PLL to generate the QCK signal (QCK_A to QCK_E, each group corresponding to a pair of CLK differential clocks); after the DCS signal enters the IMB chip, it is synchronized and decoded by the internal PLL to generate the QCS signal (QCS_A to QCS_E, 1 bit per group); after the DRST signal enters the IMB chip, it is synchronized and decoded by the internal PLL to generate the QRST signal; after the DQ signal enters the Data Buffer module, it is latched and filtered to generate the MDQ signal (MDQ_A to MDQ_E, 8 bits per group); and after the DQS signal enters the Data Buffer module... After entering the Buffer module, the signals are latched and filtered to generate MDQS signals (MDQS_A to MDQS_E, each group corresponding to a pair of DQS differential clocks); after entering the DataBuffer module, the TDQS signals are latched and filtered to generate MTDQS signals (MTDQS_A to MTDQS_E, each group corresponding to a pair of TDQS differential clocks). Specifically, QCA, QCK, QCS, QRST, MDQ, MDQS, and MTDQS all use flyby topology (daisy chain) for PCB routing. A_DRAM_A1 to A_DRAM_A4 share the same MDQ signal set; A_DRAM_B1 to A_DRAM_B4 share the same MDQ signal set; A_DRAM_C1 to A_DRAM_C4 share the same MDQ signal set; A_DRAM_D1 to A_DRAM_D4 share the same MDQ signal set; A_DRAM_E1 to A_DRAM_E4 share the same MDQ signal set; B_DRAM_A1 to B_DRAM_A4 share the same MDQ signal set; B_DRAM_B1 to B_DRAM_B4 share the same MDQ signal set; B_DRAM_C1 to B_DRAM_C4 share the same MDQ signal set; B_DRAM_D1 to B_DRAM_D4 share the same MDQ signal set; B_DRAM_E1 to B_DRAM_E4 share the same MDQ signal set. The back-side chips multiplex the MDQ signal with the front-side chips through vias. For example, A_DRAM_A1 and A_DRAM_A5 share the same MDQ signal.

[0067] Specifically, for the DRAM chips on the front and back sides of the DDR5 module, a differentiated signal multiplexing strategy is adopted: QCA (buffered command address signal), QRST (buffered reset signal), MDQ (buffered data signal), MDQS (buffered data strobe signal), and MTDQS (buffered differential data strobe signal) are shared signals for both front and back chips, meaning that the DRAM chips at corresponding positions on the front and back sides share the same physical transmission path for the above signals; QCK (buffered clock signal) and QCS (buffered chip select signal) are independent signals for both front and back chips, which are output independently by the IMB chip to the corresponding DRAM chips on the front and back sides respectively, and do not share a transmission path.

[0068] Through the above process, this invention achieves integrated design: the IMB chip integrates RCD and Data Buffer functions, reducing the number of discrete components and lowering PCB layout complexity. Signal integrity optimization: equal-length routing, Flyby topology, pre-emphasis technology, and dynamic ODT configuration support stable operation of DDR5 at high frequencies (e.g., 8000MT / s). Enhanced scalability: signal multiplexing and Flyby topology design support module capacity expansion (e.g., single-channel 64Gb density). Low power management: multi-phase power supply and centralized monitoring reduce overall power consumption, adapting to the needs of high-performance computing scenarios. This achieves high performance and scalability for DDR5 modules, solving problems such as complex layout, high signal transmission risk, and high power consumption in traditional MRDIMM architectures, providing a highly integrated and highly compatible solution for next-generation memory module design.

[0069] It should be noted that the DDR5 module design provided in the above embodiments is only an example of the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed. That is, the internal structure of the DDR5 module design device will be divided into different functional modules to complete all or part of the functions described above.

[0070] Furthermore, the embodiments of the DDR5 module design apparatus and the DDR5 module design method provided in the above embodiments belong to the same concept, and the specific way in which each module performs operations has been described in detail in the method embodiments, and will not be repeated here.

[0071] Figure 6 A schematic diagram of the structure of an electronic device according to an exemplary embodiment is shown.

[0072] It should be noted that this electronic device is merely an example adapted to the present invention and should not be construed as providing any limitation on the scope of use of the present invention. Furthermore, this electronic device should not be interpreted as requiring or depending on having... Figure 6 One or more components of the exemplary electronic device 2000 shown.

[0073] The hardware structure of electronic devices 2000 can vary significantly due to differences in configuration or performance, such as... Figure 6 As shown, the electronic device 2000 includes: a power supply 210, an interface 230, at least one memory 250, and at least one central processing unit (CPU) 270.

[0074] Specifically, power supply 210 is used to provide operating voltage for various hardware devices on electronic device 2000.

[0075] Interface 230 includes at least one wired or wireless network interface 231 for interacting with external devices. Of course, in other examples adapted to this invention, interface 230 may further include at least one serial-to-parallel conversion interface 233, at least one input / output interface 235, and at least one USB interface 237, etc. Figure 6 As shown, this does not constitute a specific limitation.

[0076] The memory 250 serves as a carrier for resource storage and can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored on it include the operating system 251, application programs 253, and data 255, etc., and the storage method can be temporary storage or permanent storage.

[0077] The operating system 251 is used to manage and control the various hardware devices and application programs 253 on the electronic device 2000, so as to enable the central processing unit 270 to perform calculations and processing on the massive data 255 in the memory 250. It can be Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0078] Application 253 is a computer-readable instruction based on operating system 251 that performs at least one specific task, and may include at least one module ( Figure 6 (Not shown), each module may contain computer-readable instructions for electronic device 2000. For example, a DDR5 module design device can be considered as application program 253 deployed on electronic device 2000.

[0079] Data 255 may be signal information, etc., and is stored in memory 250.

[0080] The central processing unit 270 may include one or more processors and is configured to communicate with the memory 250 via at least one communication bus to read computer-readable instructions stored in the memory 250, thereby performing operations and processing on massive amounts of data 255 stored in the memory 250. For example, a DDR5 module design method can be implemented by the central processing unit 270 reading a series of computer-readable instructions stored in the memory 250.

[0081] Furthermore, the present invention can also be implemented through hardware circuits or a combination of hardware circuits and software. Therefore, the implementation of the present invention is not limited to any specific hardware circuit, software, or combination thereof.

[0082] Please see Figure 7 This invention provides an electronic device 4000, which may include: a desktop computer, a laptop computer, a server, etc., with sensor recognition capabilities.

[0083] exist Figure 7 In this context, the electronic device 4000 includes at least one processor 4001 and at least one memory 4003.

[0084] The data interaction between the processor 4001 and the memory 4003 can be achieved through at least one communication bus 4002. This communication bus 4002 may include a path for transmitting data between the processor 4001 and the memory 4003. The communication bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus 4002 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0085] Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present invention.

[0086] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. Processor 4001 may also be a combination that implements computing functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0087] The memory 4003 may be a ROM (Read Only Memory) or other type of static storage device capable of storing static information and instructions, RAM (Random Access Memory) or other type of dynamic storage device capable of storing information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program instructions or code in the form of instructions or data structures and accessible by the electronic device 4000, but not limited thereto.

[0088] The memory 4003 stores computer-readable instructions, and the processor 4001 can read the computer-readable instructions stored in the memory 4003 through the communication bus 4002.

[0089] The computer-readable instructions are executed by one or more processors 4001 to implement the DDR5 module design method in the above embodiments.

[0090] Furthermore, this embodiment of the invention provides a storage medium storing computer-readable instructions, which are executed by one or more processors to implement the DDR5 module design method described above.

[0091] This invention provides a computer program product, which includes computer-readable instructions stored in a storage medium. One or more processors of an electronic device read the computer-readable instructions from the storage medium, load and execute the computer-readable instructions, thereby enabling the electronic device to implement the DDR5 module design method described above.

[0092] Compared with related technologies, the beneficial effects of the present invention are: 1. This invention simplifies module structure, reduces production costs and design complexity; by integrating the RCD and DataBuffer into a single IMB chip, it reduces the number of discrete chips and independent wiring space, thereby reducing PCB area and wiring difficulty, improving product reliability and simplifying the assembly process. It reduces the number of PCB wiring layers and redundant lines, and by sharing lines and power domains, it reduces production costs and design complexity while improving production efficiency.

[0093] 2. This invention improves signal transmission performance; by managing all DQ signals within the channel through the IMB chip and combining optimized signal topology and module layout, it effectively reduces signal delay, reflection, and interference, thereby improving data transmission rate and stability, and theoretically can support higher DDR5 operating frequencies.

[0094] 3. This invention has the effect of reducing power consumption; by reducing the power supply loss of discrete chips through integrated design, and by sharing circuits and optimizing signal driving logic, the power consumption of signal driving is reduced, which significantly reduces the overall module power consumption and conforms to the design concept of green energy saving.

[0095] 4. This invention can enhance internal collaborative processing capabilities; the RCD and Data Buffer are internally interconnected in the same chip, which significantly enhances their collaborative processing capabilities, effectively solves the problems of signal attenuation, excessive load and timing synchronization in high-speed transmission, and meets the timing requirements of DDR5 8000 and above frequencies.

[0096] 5. This invention has excellent compatibility; by retaining the electrical interface specifications of DDR5 gold fingers, it can be directly adapted to existing DDR5 controllers, such as Intel Xeon Scalable or AMD EPYC processors, without requiring changes to the host hardware design, thus reducing the cost and risk of system upgrades.

[0097] 6. This invention has good scalability; the IMB chip has powerful QCA and MDQ driving capabilities, supporting capacity expansion by increasing the number of chips on the transmission line, meeting the needs of large-capacity memory scenarios such as big data and artificial intelligence, and reserving space for the future development of memory technology.

[0098] 7. This invention integrates RCD and Data Buffer functions into a single IMB chip, enabling direct signal interaction through on-chip interconnect mechanisms, eliminating the need for BCOM interfaces and related pins. This improvement not only simplifies chip pin definitions and PCB routing design, reducing hardware costs, but also enhances signal transmission reliability and module integration by reducing external interfaces, providing a superior solution for timing synchronization in high-frequency scenarios.

[0099] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0100] The above description is only a partial embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A DDR5 module design method, characterized in that, The method includes: The register clock driver RCD module and the data buffer module are integrated into a single IMB chip, and the interface is defined; the IMB chip integrates a clock synchronization subunit PLL module, a DCA decoding circuit module, a QCA driver circuit module, a data buffer module, and a signal calibration unit. IMB conversion chips are added to each of the two channels of the DDR5 module. The IMB conversion chips are symmetrically deployed in the center of the front side of the PCB board. The DRAM chips are mirrored on the front and back sides of the PCB board. The data signal MDQ and the command address signal QCA are multiplexed for transmission paths. The DQ and CA signals are connected to the input pins of the IMB chip using an equal-length wiring design. The power management chip PMIC is used for power supply and the SPD chip is used for parameter configuration. The QCA and MDQ signals are driven by a Flyby topology and the signals are optimized by pre-emphasis technology. Signal processing is performed through the IMB chip, and a differentiated signal multiplexing strategy is adopted for the DRAM chips on both sides of the DDR5 module. A ZQ calibration circuit is set in the IMB chip to adjust the output impedance, pin expansion and signal buffer module, and the DDR5 gold finger electrical interface specification is adopted.

2. The DDR5 module design method as described in claim 1, characterized in that, The integration of the register clock driver RCD module and the data buffer module into a single IMB chip includes: It adopts a 14mm×14mm packaged IMB chip and integrates an RCD module, a data buffer module, and a signal calibration unit; the clock synchronization subunit PLL supports dynamic frequency modulation from 1.0GHz to 4.4GHz; the DCA decoding circuit adopts 2N mode dual-cycle conversion; the QCA drive circuit supports dynamic ODT technology. The output impedance is dynamically adjusted by the ZQ calibration circuit through the signal calibration unit; the data buffer module integrates the DQ latch unit and the MDQ drive circuit; the DQ latch unit is 8-bit parallel processing, and the MDQ drive circuit has an adjustable pre-emphasis level; the ZQ calibration circuit is connected to an external high-precision resistor; the IMB chip supports high-density integration and low-power design.

3. The DDR5 module design method as described in claim 1, characterized in that, The step of symmetrically deploying the IMB conversion chips on the center of the front side of the PCB board and mirror-laying the DRAM chips on both sides of the PCB board includes: The IMB conversion chips are symmetrically deployed in the center of the front of the PCB and the distance from the gold fingers is within a set range; each sub-channel includes 32 bits of data and 8 bits of ECC; The front DRAM array is divided into two channels, the back DRAM is arranged in a mirror symmetrical layout with the front DRAM, and the power management chip (PMIC) is placed on the front of the PCB. The distance between the serial detection chip (SPD) and the power management chip (PMIC) is set within a set range, and the IMB chip, the power management chip (PMIC), and the host are centrally controlled via the I2CHUB bus.

4. The DDR5 module design method as described in claim 1, characterized in that, The design data signal MDQ and command address signal QCA transmission path multiplexing includes: The MDQ and QCA signals on the front side are multiplexed by vias, and the QCK clock signal and QCS chip selection signal are set to be output independently to the front and back particles by the IMB chip respectively. The input signal path is designed with equal-length wiring; the length difference of the equal-length wiring is ≤0.1mm.

5. The DDR5 module design method as described in claim 1, characterized in that, The use of a power management chip (PMIC) for power supply and parameter configuration of an SPD chip includes: The power management chip (PMIC) is configured using multi-phase power supply technology and is directly connected to the power supply pins of the IMB chip via PCB copper foil. The I2C hub bus is used to centrally monitor the status of the IMB chip, the power management chip (PMIC), and the host device via the SPD chip.

6. The DDR5 module design method as described in claim 1, characterized in that, The method employs Flyby topology to drive QCA and MDQ signals, combined with pre-emphasis technology, including: The Flyby topology is used to drive the QCA and MDQ signals, with each group of signals driving four DRAM chips, and pre-emphasis technology is incorporated; the modular design of the IMB chip supports functional upgrades.

7. The DDR5 module design method as described in claim 1, characterized in that, The ZQ calibration circuit within the IMB chip is used to adjust the output impedance, and the pin expansion and signal buffering module adopts the DDR5 gold finger electrical interface specification, including: The IMB chip adopts the DDR5 gold finger electrical interface specification; the IMB chip supports pin expansion and signal buffer modules, and capacity expansion is achieved by increasing the number of DRAM chips on the transmission line; The ZQ calibration circuit dynamically adjusts the output impedance through an external resistor; the IMB chip manages all signal paths within the channel through an internal timing calibration module and a dynamic signal adjustment circuit, and optimizes timing synchronization and load balancing in high-frequency scenarios.

8. The DDR5 module design method as described in claim 1, characterized in that, The signal processing via the IMB chip includes: The DQ signal is input into the Data Buffer module in 5 channels and latched, and then output as 5 groups of MDQ signals. The CA signal in a single channel is expanded into 5 parallel input DCA decoding circuits to generate 5 groups of QCA signals. The DCK signal is phase-calibrated by PLL to generate QCK differential signals to drive DRAM chips. Five sets of parallel outputs are used, connected to the CA pins of all DRAM chips in a single channel via Flyby topology, and five sets of parallel outputs are used, connected to the DQ pins of all DRAM chips in a single channel via Flyby topology, using differential pair transmission.

9. An electronic device, characterized in that, include: At least one processor and at least one memory, wherein, The memory stores computer-readable instructions; The computer-readable instructions are executed by one or more of the processors, causing the electronic device to implement the DDR5 module design method as described in any one of claims 1 to 7.

10. A storage medium having computer-readable instructions stored thereon, characterized in that, The computer-readable instructions are executed by one or more processors to implement the DDR5 module design method as described in any one of claims 1 to 7.

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