Charging and discharging compensation circuit, charging and discharging compensation method, display screen and electronic equipment

Abstract

The invention discloses a charging and discharging compensation circuit, a charging and discharging compensation method, a display screen and electronic equipment, and belongs to the technical field of display. The charging and discharging compensation circuit comprises a load capacitor, a preprocessing circuit, a current mirror circuit, a switching circuit, a sampling detection circuit and a capacitance compensation circuit. The preprocessing circuit adjusts the voltage of the load capacitor to a preset value; the current mirror image circuit outputs mirror image current for charging or discharging the load capacitor; the switching circuit is used for controlling the charging or discharging time of the load capacitor; the sampling detection circuit generates a mirror current calibration signal or a load capacitor calibration signal based on the magnitude between the capacitor voltage on the load capacitor and the target voltage; the capacitance compensation circuit compensates the load capacitance based on the load capacitance calibration signal. According to the invention, the load capacitance of all the pixel columns can be compensated through the capacitance compensation circuit, the pixel voltage difference caused by the charging and discharging current difference between different pixel columns can be compensated, and the image display quality is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a charge-discharge compensation circuit, a charge-discharge compensation method based on the charge-discharge compensation circuit, a display screen having the charge-discharge compensation circuit, and an electronic device having the display screen. Background Technology

[0002] Currently, displays, as human-computer interaction interfaces, are increasingly widely used, including but not limited to smartphones, tablets, laptops, televisions, desktop monitors, AR / VR / MR / XR devices, and HUDs. In a display, each pixel unit corresponds to a pixel circuit. The pixel circuit is positioned where scan lines, arranged in a row direction, supply control signals, and data lines, arranged in a column direction, supply data signals, intersect to drive the corresponding pixel unit to display an image. During image display, the capacitors in the pixel circuit need to be charged so that they can control the light-emitting element to emit light during the light-emitting phase.

[0003] As monitor sizes increase and the number of pixels grows, the differences between pixel columns due to manufacturing processes become increasingly significant, severely impacting image quality. Traditional pixel column compensation methods involve adjusting the charging and discharging current of the pixel column. However, because the charging and discharging current of a pixel column is relatively small, the compensation range becomes even smaller, making precise current control increasingly difficult. This affects the accuracy of pixel data voltage, resulting in unsatisfactory image compensation effects.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a charge-discharge compensation circuit that can compensate for the load capacitance of all columns, eliminate pixel voltage differences caused by differences in the charge-discharge current of pixel columns, and improve image display quality.

[0006] The present invention also aims to provide a charge-discharge compensation method that can compensate for the load capacitance of all columns, eliminate pixel voltage differences caused by differences in the charge-discharge current of pixel columns, and improve image display quality.

[0007] The present invention also aims to provide a display screen and an electronic device that can compensate for the load capacitance of all columns, eliminate pixel voltage differences caused by differences in pixel column charging and discharging currents, and improve image display quality.

[0008] To achieve the above objectives, a specific embodiment of the present invention provides a charge / discharge compensation circuit, including...

[0009] At least one load capacitor;

[0010] At least one preprocessing circuit, each of the preprocessing circuits corresponding to one of the load capacitors, the preprocessing circuits being connected to the corresponding load capacitors to form a connection point, the preprocessing circuits being used to adjust the voltage of the corresponding load capacitors to a preset value;

[0011] A current mirror circuit is used to mirror a reference current and output a mirror current for charging or discharging a load capacitor through at least one output branch, with each output branch corresponding to one connection point.

[0012] At least one switching circuit, each of the switching circuits corresponds to one of the output branches, and each of the output branches is connected to the corresponding connection point through the corresponding switching circuit. The switching circuit is used to control the preprocessing circuit to adjust the voltage of the corresponding load capacitor to a preset value and the charging or discharging time of the load capacitor.

[0013] A sampling and detection circuit is used to generate a mirror current calibration signal for adjusting the reference current based on the magnitude between the capacitor voltage on the load capacitor and the target voltage in a first mode, and to generate a load capacitance calibration signal based on the magnitude between the capacitor voltage on the load capacitor and the target voltage in a second mode.

[0014] At least one capacitor compensation circuit is provided, each capacitor compensation circuit corresponds to one load capacitor, the capacitor compensation circuit is connected to a connection point, and the capacitor compensation circuit compensates the load capacitor based on the load capacitor calibration signal so as to obtain the corresponding capacitor voltage based on the mirror current through the compensated load capacitor.

[0015] In one or more embodiments of the present invention, each of the preprocessing circuits is controlled by the same control signal to adjust the voltage of the corresponding load capacitor to a preset value.

[0016] In one or more embodiments of the present invention, the preprocessing circuit includes:

[0017] The first MOSFET has its source terminal connected to a reference voltage source or ground, its drain terminal connected to the load capacitor to form the connection point, and its gate terminal connected to a control signal.

[0018] In one or more embodiments of the present invention, the current mirror circuit includes:

[0019] The second MOSFET has its drain terminal connected to the reference current source, its source terminal connected to the voltage source or ground, and its gate terminal connected to the drain terminal.

[0020] At least one third MOS transistor is provided, with the drain terminal of each third MOS transistor serving as the output branch, the source terminals being connected to a voltage source or ground, and the gate terminals being connected to the gate terminals of the second MOS transistor.

[0021] In one or more embodiments of the present invention, the switching circuit includes:

[0022] The fourth MOSFET has its source terminal connected to the output branch, its drain terminal connected to the connection point, and its gate terminal connected to the control signal.

[0023] In one or more embodiments of the present invention, the sampling detection circuit includes:

[0024] Detecting resistance;

[0025] Several calibration circuits, each corresponding to a pixel column, and each calibration circuit is connected to a voltage source or ground through a detection resistor to form a detection point. Each calibration circuit is used to receive the capacitor voltage on the load capacitor and the target voltage, and selects to convert the capacitor voltage on the corresponding load capacitor into a sampling current or the target voltage into a comparison current and input it into the detection resistor.

[0026] At least one detection circuit is configured to generate a mirror current calibration signal in a first mode based on the magnitude of the sampling voltage generated by the sampling current in the detection resistor and the comparison voltage generated by the comparison current in the detection resistor, and to generate a load capacitance calibration signal in a second mode based on the magnitude of the sampling voltage generated by the sampling current in the detection resistor and the comparison voltage generated by the comparison current in the detection resistor.

[0027] In one or more embodiments of the present invention, all pixel columns share a single detection circuit.

[0028] In one or more embodiments of the present invention, the calibration circuit includes:

[0029] The fifth MOSFET is connected in series with the detection resistor between the voltage source and ground;

[0030] The first switch has one end connected to the reference voltage and the other end connected to the gate of the fifth MOSFET.

[0031] The second switch has one end connected to the capacitor voltage on the load capacitor and the other end connected to the gate terminal of the fifth MOSFET.

[0032] The third switch has one end connected to a voltage source and the other end connected to the gate of the fifth MOSFET.

[0033] A switch control circuit, connected to the first switch, the second switch, and the third switch, is used to control the closing or opening of the first switch, the second switch, and the third switch.

[0034] In one or more embodiments of the present invention, the switch control circuit is a logic circuit composed of gate-level circuits, with inputs of calibration_mode0, calibration_mode1 and data[M], and outputs of Q1, Q2 and Q3. Q1, Q2 and Q3 control the closing or opening of the first switch, the second switch and the third switch, respectively. Among them, calibration_mode0 and calibration_mode1 are configurable 2-bit registers, and data[M] is the highest bit value of the grayscale value corresponding to the pixel column.

[0035] In one or more embodiments of the present invention, the switching circuit for controlling the charging or discharging time of the load capacitor includes:

[0036] During charging or discharging, the M-bit counter counts from 0 to 2. M -1 is used to count the charging or discharging time, and the switching circuit corresponding to the column of pixels is turned off when the counter counts from zero to the gray value corresponding to the column of pixels. M is the color depth of the display, and M is an integer greater than 0.

[0037] In one or more embodiments of the present invention, the capacitor compensation circuit includes a compensation control circuit, a switching unit, and a compensation capacitor array. The compensation capacitor array is connected to a connection point through the switching unit. The compensation control circuit generates a load capacitance compensation control signal based on a load capacitance calibration signal to control the switching unit to turn on and off, thereby controlling the number of compensation capacitors in the compensation capacitor array connected to the connection point.

[0038] In one or more embodiments of the present invention, the compensation capacitor array includes a plurality of compensation capacitors, the switching unit includes a plurality of switches, each of the switches being turned on and off based on the control of a corresponding load capacitor compensation control signal, and each of the compensation capacitors being connected to a connection point through a corresponding switch.

[0039] In one or more embodiments of the present invention, the switching unit further includes a main switch that is turned on and off under the control of a load capacitance compensation control signal, and each of the switches is connected to a connection point through the main switch.

[0040] In one or more embodiments of the present invention, a charge-discharge compensation method based on the aforementioned charge-discharge compensation circuit includes:

[0041] The voltage of the corresponding load capacitor is adjusted to a preset value through each preprocessing circuit;

[0042] The reference current is mirrored by a current mirror circuit and the mirrored current is output through at least one output branch to charge or discharge the load capacitor.

[0043] The preprocessing circuit is controlled by a switching circuit to adjust the voltage of the corresponding load capacitor to a preset value and to control the charging or discharging time of the load capacitor.

[0044] In the first mode, the sampling and detection circuit generates a mirror current calibration signal for adjusting the reference current based on the magnitude between the capacitor voltage on the load capacitor and the target voltage. In the second mode, the sampling and detection circuit generates a load capacitance calibration signal based on the magnitude between the capacitor voltage on the load capacitor and the target voltage.

[0045] The load capacitance is compensated by a capacitor compensation circuit based on the load capacitance calibration signal, and the corresponding capacitor voltage is obtained based on the mirror current through the compensated load capacitance.

[0046] In one or more embodiments of the present invention

[0047] The step of generating a mirror current calibration signal for adjusting the reference current based on the magnitude between the capacitor voltage on the load capacitor and the target voltage in the first mode via a sampling detection circuit, and generating a load capacitance calibration signal based on the magnitude between the capacitor voltage on the load capacitor and the target voltage in the second mode via a sampling detection circuit, includes:

[0048] In the first mode, a target voltage is selected, and the target voltage is sampled to obtain the comparison voltage;

[0049] Set the discharge or charge time, sample the capacitor voltage on the load capacitor of the selected pixel column after discharge or charge to obtain the sample voltage, generate a mirror current calibration signal for adjusting the reference current based on the magnitude between the sample voltage and the comparison voltage, and calibrate the mirror current by adjusting the reference current.

[0050] In the second mode, the corresponding sampling voltage is obtained by sampling the capacitor voltage generated on the load capacitor of each of the remaining pixel columns based on the calibrated mirror current.

[0051] The load capacitance calibration signal for each of the remaining pixel columns is determined based on the magnitude of the sampling voltage and the comparison voltage.

[0052] In one or more embodiments of the present invention, selecting a target voltage includes:

[0053] Divide the ramp voltage evenly into 2 M M represents the display's color depth;

[0054] When discharging, select the voltage closest to the minimum value of the ramp voltage as the target voltage; when charging, select the voltage closest to the maximum value of the ramp voltage as the target voltage.

[0055] In one or more embodiments of the present invention, the step of setting the discharge or charging time in the first mode, sampling the capacitor voltage on the load capacitor of the selected pixel column after discharge or charging to obtain a sample voltage, and calibrating the mirror current based on the magnitude between the sample voltage and the comparison voltage includes:

[0056] In the first mode, a discharge time is set and each pixel column is discharged starting from the maximum value of the ramp voltage, or a charging time is set and each pixel column is charged starting from the minimum value of the ramp voltage, and the pixel column that is discharged or charged the slowest is determined.

[0057] The capacitor voltage on the load capacitor after discharge or charging is sampled for the pixel column that discharges or charges the slowest. The mirror current is calibrated based on the magnitude between the sampled voltage and the comparison voltage.

[0058] In one or more embodiments of the present invention, setting the discharge or charge time includes: using an M-bit counter from 0 to 2 M -1 is used to count the charging or discharging time, and the discharging or charging ends when the counter counts from zero to the gray value corresponding to a column of pixels. M is the color depth of the display, and M is an integer greater than 0.

[0059] An embodiment of the present invention provides a display screen including the charge / discharge compensation circuit described above.

[0060] An embodiment of the present invention provides an electronic device including the display screen described above.

[0061] Compared with existing technologies, this invention can quickly charge or discharge the capacitors of all pixel circuits in each column, ensuring that the capacitor voltage values ​​meet actual usage requirements. Furthermore, each column of pixel circuit capacitors employs independent constant current control during charging or discharging, avoiding interference between columns. Simultaneously, by compensating the load capacitance of all pixel columns through a capacitor compensation circuit, it can compensate for differences in pixel voltage caused by variations in charging and discharging currents between different pixel columns, thereby improving image display quality. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 This is a schematic diagram of the charge-discharge compensation circuit according to an embodiment of the present invention.

[0064] Figure 2 This is a partial circuit diagram of a charge-discharge compensation circuit according to an embodiment of the present invention.

[0065] Figure 3 This is a partial circuit diagram of a charge-discharge compensation circuit according to another embodiment of the present invention.

[0066] Figure 4 This is a circuit diagram of charge / discharge time control according to an embodiment of the present invention;

[0067] Figure 5 This is a schematic diagram of the sampling and detection circuit according to an embodiment of the present invention;

[0068] Figure 6 This is a circuit diagram of a sampling and detection circuit according to an embodiment of the present invention;

[0069] Figure 7 This is a circuit diagram of a sampling and detection circuit according to another embodiment of the present invention;

[0070] Figure 8 This is a circuit diagram of a capacitor compensation circuit according to an embodiment of the present invention;

[0071] Figure 9 This is a schematic diagram of a ramp voltage according to an embodiment of the present invention;

[0072] Figure 10 This is a schematic diagram of a ramp voltage according to another embodiment of the present invention. Detailed Implementation

[0073] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0074] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0075] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0076] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0077] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0078] Various components and devices may be referred to or shown in the singular (e.g., “MOS transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0079] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0080] like Figures 1 to 4As shown, a charge / discharge compensation circuit according to a preferred embodiment of the present invention can quickly charge or discharge the capacitors of all pixel circuits in each column, so that the voltage of the capacitors meets the actual use requirements, and the capacitors of each column of pixel circuits are independent of each other and do not interfere with each other when charging or discharging.

[0081] Specifically, in combination Figures 1 to 8 As shown, the charge / discharge compensation circuit includes at least one load capacitor, at least one preprocessing circuit 10, a current mirror circuit 20, a sampling detection circuit, at least one switching circuit 30, and at least one capacitor compensation circuit 40. The load capacitor is used to store charge; here, the load capacitor is the equivalent load capacitor of all pixel circuits in each column. Therefore, the number of load capacitors can be determined based on the number of columns.

[0082] Each preprocessing circuit 10 corresponds to a load capacitor, meaning each preprocessing circuit 10 corresponds to one load capacitor. The preprocessing circuit 10 is connected to the corresponding load capacitor to form connection point A. The preprocessing circuit 10 can adjust the voltage value of the load capacitor to a preset value, such as by charging the load capacitor or by discharging the load capacitor. The choice can be made according to actual needs.

[0083] The current mirror circuit 20 is used to convert the reference current I REF The image is mirrored and output through at least one output branch to provide a reference current I. REF A proportional mirror current I is used to charge or discharge the load capacitor. Here, the output branch corresponds one-to-one with connection point A, or in other words, the output branch corresponds one-to-one with the load capacitor. Furthermore, the proportionality here includes, but is not limited to, 1:1, and can be adjusted according to actual needs.

[0084] Each output branch corresponds to a specific switching circuit 30. Each output branch is connected to its corresponding connection point A via the corresponding switching circuit 30. In other words, the switching circuit 30 connects to connection point A and the output branch. This switching circuit 30 controls the charging or discharging time of the load capacitor by controlling the preprocessing circuit 10, ensuring that the voltage across the load capacitor reaches the desired voltage value (preset value). Here, the charging or discharging time refers to the time it takes for the load capacitor to reach the desired voltage value from its current voltage value.

[0085] The sampling and detection circuit generates a mirror current calibration signal for adjusting the reference current based on the difference between the capacitor voltage on the load capacitor and the target voltage in a first mode, and generates a load capacitance calibration signal based on the difference between the capacitor voltage on the load capacitor and the target voltage in a second mode. In one embodiment, the first mode is calibration_mode0 mode and the second mode is calibration_mode1 mode. The mirror current calibration signal is used to control external devices or modules to adjust the reference current.

[0086] The capacitor compensation circuit 40 corresponds one-to-one with the load capacitor and is connected to the connection point A. The capacitor compensation circuit 40 compensates the load capacitor based on the load capacitor calibration signal so that the corresponding capacitor voltage can be obtained based on the mirror current I through the compensated load capacitor, thereby compensating for the differences between different pixel columns and improving the display effect.

[0087] In specific implementation, the preprocessing circuit 10 first charges or discharges the corresponding load capacitor to make its voltage value reach the preset value, and the switching circuit 30 is in the off state during the charging or discharging process of the load capacitor by the preprocessing circuit 10.

[0088] When the voltage value of the load capacitor reaches the preset value, the preprocessing circuit 10 is disconnected, and the current mirror circuit 20 starts to work, which will reference the current I. REF Mirror the image and output it through the output branch to the reference current I. REF A proportional mirror current I is generated. Simultaneously, the switching circuit 30 is closed. At this time, due to the presence of the mirror current I in the output branch, the voltage value of the load capacitor continuously decreases or increases from a preset value, i.e., the load capacitor is discharged or charged.

[0089] When the charging or discharging time of the load capacitor is reached, the switching circuit 30 is disconnected. At this time, there is no current in the circuit, and therefore the capacitor voltage of the load capacitor no longer decreases or increases. The voltage value of the capacitor at this time is the required voltage value.

[0090] Combination Figure 2 and Figure 3 As shown, the preprocessing circuit 10 includes a first MOSFET. The gate of the first MOSFET is connected to a control signal, and its source is connected to a reference voltage source V. H Alternatively, the drain terminal is connected to the corresponding load capacitor to form connection point A. In specific implementation, the control signal controls the first MOSFET to conduct, and the reference voltage source is electrically connected to the load capacitor. Then, the voltage value of the load capacitor can be adjusted to the same voltage value as the reference voltage source by charging or discharging.

[0091] In this embodiment, all preprocessing circuits 10 are controlled by the same control signal, so that the preprocessing circuit 10 adjusts the voltage value of the corresponding load capacitor to a preset value, such as... Figure 2 As shown, the gate terminals of all the first MOSFETs are controlled by the control signal S0. Of course, in other embodiments, each first MOSFET can also be controlled individually by different control signals, which can be selected according to actual needs.

[0092] Combination Figure 2 and Figure 3 As shown, the current mirror circuit 20 includes a second MOSFET and at least one third MOSFET. The drain terminal of the second MOSFET is connected to the reference current I. REF The source terminal of each third MOSFET is connected to either the voltage source VDD or ground, and the gate terminal is connected to the drain terminal. The drain terminal of each third MOSFET serves as the output branch for the output mirror current I, while the source terminals are all connected to either the voltage source VDD or ground, and the gate terminals are all connected to the gate terminal of the second MOSFET. The second MOSFET and a third MOSFET can form a base current mirror to reflect the reference current I. REF Mirror to the corresponding output branch.

[0093] In this embodiment, the second MOS transistor and the third MOS transistor are selected from either PMOS transistors or NMOS transistors, depending on the actual needs.

[0094] Combination Figure 2 and Figure 3 As shown, the switching circuit 30 includes a fourth MOSFET, which can be either a PMOS or an NMOS transistor. The source terminal of the fourth MOSFET is connected to the corresponding output branch, the drain terminal is connected to the corresponding connection point A, and the gate terminal is connected to the control signal. In a specific implementation, the control signal turns on the fourth MOSFET, thereby forming a loop between the output branch and the corresponding load capacitor. This generates a current in the loop, and as time passes, the voltage across the load capacitor changes.

[0095] In this embodiment, each fourth MOSFET is controlled by a different control signal; that is, each fourth MOSFET is controlled by a corresponding control signal. Figure 2 and Figure 3 As shown, each fourth MOSFET is controlled by a different control signal. By controlling each fourth MOSFET with a different control signal, the charging or discharging time of each load capacitor can be controlled independently.

[0096] In this embodiment, each switching circuit 30 further includes a counter and a comparator circuit. The first input terminal of the comparator circuit is used to receive the grayscale value, the second input terminal of the comparator circuit is connected to the output terminal of the counter, and the output terminal of the comparator circuit is connected to the gate terminal of the fourth MOS transistor. The M-bit counter is used to count from 0 to 2. M -1 is used to count charging or discharging time, where M is an integer greater than 0. For example... Figure 4 As shown, when the counter counts from 0 to the grayscale value corresponding to a certain column of pixels, the fourth MOS transistor in the switching circuit 30 corresponding to that column of pixels is turned off by the control signal output by the corresponding comparator circuit. At this time, the circuit is broken, no current flows, and the discharge of the load capacitor stops, and the voltage of the load capacitor is fixed. Here, the grayscale value is pixel data. For example, for a display with a color depth of 10, the pixel data is 10'h200, etc.

[0097] Combining 5~ Figure 7 As shown, the sampling and detection circuit includes a detection resistor R, several calibration circuits, and at least one detection circuit. Each calibration circuit is connected to a voltage source or ground (GND) through the detection resistor R, forming a detection point P. Each calibration circuit receives the capacitor voltage on the load capacitor and the target voltage, and selects to convert the capacitor voltage on the corresponding load capacitor into a sampling current or the target voltage into a comparison current input to the detection resistor. The detection circuit generates a mirror current calibration signal based on the magnitudes of the sampling voltage generated by the sampling current on the detection resistor R and the comparison voltage generated by the comparison current on the detection resistor R in calibration_mode0 mode, and generates a load capacitance calibration signal based on the magnitudes of the sampling voltage generated by the sampling current on the detection resistor R and the comparison voltage generated by the comparison current on the detection resistor R in calibration_mode1 mode.

[0098] In practical implementation, under calibration_mode0 mode, firstly, a whole row of pixel data is sent. The pixel data in the first pixel column is 10'h200, and the pixel data in other columns is 10'h000, to determine the discharge or charging time of the load capacitor. The most significant bit of the pixel data in the first pixel column is configured as 1, and all bits of the pixel data in other columns are configured as 0. The detection circuit obtains the sampling voltage Cal_Vdata generated by the calibration circuit corresponding to the first pixel column through the detection resistor R. Then, another whole row of pixel data is sent. The pixel data in the second pixel column is 10'h200, and the pixel data in other columns is 10'h000. The most significant bit of the pixel data in the second pixel column is configured as 1, and all bits of the pixel data in other columns are configured as 0. The detection circuit obtains the sampling voltage Cal_Vdata generated by the calibration circuit in the second pixel column through the detection resistor R. Repeating this process yields the sampling voltage Cal_Vdata for all pixel columns, confirming the differences between each pixel column.

[0099] Using the pixel column with the smallest or largest sampling voltage Cal_Vdata as a reference, pixel data 10'h300 is selected to determine the charging or discharging time of the load capacitor for subsequent calibration. Selecting a larger value like pixel data 10'h300 can reduce calibration error. The sampling voltage Cal_Vdata of the pixel column with the slowest discharging or charging is obtained. It is then checked whether the sampling voltage Cal_Vdata is equal to the comparison voltage Vdata_p corresponding to pixel data 10'h300. If they are equal, the current configuration for this charging or discharging is saved; otherwise, a mirror current calibration signal is generated through the detection circuit to continue adjusting the reference current I. REF It continuously sends pixel data 10'h300 for detection until the obtained sampling voltage Cal_Vdata equals the comparison voltage Vdata_p, and saves the charging or discharging current configuration at this time. The charging or discharging current configuration obtained here is used as the charging or discharging current for the display screen.

[0100] In calibration_mode1 mode, using the adjusted charging or discharging current, a whole row of pixel data is sent. The pixel data for the first column is 10'h300, and the pixel data for all other columns is 10'h000. The detection circuit acquires the sampling voltage Cal_Vdata corresponding to the first pixel column and compares it with the comparison voltage Vdata_p. If Cal_Vdata is too small or too large, a load capacitance calibration signal is generated, incrementing the compensation capacitor configuration value of the load capacitance for the first pixel column by 1. This process is repeated until the sampling voltage Cal_Vdata is the same as the comparison voltage Vdata_p. At this point, the compensation capacitor configuration value of the load capacitance for the first column is the final compensation capacitor configuration value for that pixel column. Repeating the above steps yields the final compensation capacitor configuration value for each pixel column.

[0101] In this embodiment, all pixel columns share a single detection circuit. Of course, in other embodiments, a separate detection circuit can be set for each pixel column, depending on actual needs.

[0102] Combination Figure 6 and Figure 7 As shown, the calibration circuit includes a fifth MOSFET T, a first switch K1, a second switch K2, and a third switch K3. The fifth MOSFET T is connected in series with the sensing resistor R to the reference voltage source V. H Between the ground (GND), one end of the first switch K1 is connected to the calibration voltage Vcal, and the opposite end is connected to the gate of the fifth MOSFET T. One end of the second switch K2 is connected to the capacitor voltage Vdata of the load capacitor, and the opposite end is connected to the gate of the fifth MOSFET T. One end of the third switch K3 is connected to the reference voltage source V. H The gate terminal of the fifth MOSFET T at the opposite end.

[0103] In practice, during the initial detection, the first switch K1 is closed, the second switch K2 circuit and the third switch K3 are open, so that the calibration voltage Vcal can be input into the calibration circuit; during subsequent detection, the first switch K1 and the third switch K3 are open, and the second switch K2 is closed, so that the capacitor voltage Vdata of the pixel circuit can be input into the calibration circuit.

[0104] In this embodiment, the first switch K1, the second switch K2, and the third switch K3 can be controlled to be turned on or off by the switch control circuit shown in the figure. This switch control circuit is a simple logic circuit composed of gate-level circuits. Its inputs are calibration_mode0, calibration_mode1, and data[M], and its output control signals are Q1, Q2, and Q3. Q1, Q2, and Q3 can control the closing or opening of the first switch K1, the second switch K2, and the third switch K3, respectively. Here, calibration_mode0 and calibration_mode1 are configurable 2-bit registers, and data[M] is the highest bit of the grayscale value of the pixel in that column (M is the color depth of the grayscale).

[0105] The relationship between calibration_mode0, calibration_mode1, data[M] and the first switch K1, the second switch K2, and the third switch K3 is shown in the table below.

[0106]

[0107] Furthermore, taking a color depth of 10 and compensation for the first pixel column as an example, the following will explain in detail how the sampling detection circuit performs detection.

[0108] First, configure calibration_mode0 and calibration_mode1 to 1 and 0 respectively. Then, receive a whole row of pixel data, where the pixel data in the first column is 10'h200 (the most significant bit must be 1), and the pixel data in the other columns is 10'h000. Under the control of the switch control circuit, the first switch K1 corresponding to the first pixel column is closed, the second switch K2 and the third switch K3 are open, and the calibration voltage Vcal is connected to the gate of the fifth MOSFET T. At this time, the calibration voltage Vcal will generate a first current I1 from the source terminal S to the drain terminal D of the fifth MOSFET T, and the first current I1 will flow through the resistor R. Since the data[M] corresponding to other pixel columns is 0, the third switch K3 is closed, the first switch K1 and the second switch K2 are open, and the fifth MOSFET T does not generate current. Therefore, only the first current I1 flows through the detection resistor R. At this time, the detection circuit detects that the voltage at the detection point P represents the calibration voltage Vcal, and the converted data is the comparison voltage Vdata_p corresponding to the first pixel column.

[0109] Next, configure calibration_mode0 and calibration_mode1 to 0 and 1 respectively. Then, receive a whole row of pixel data, where the first column of pixel data is 10'h300 and the other columns are 10'h000. Under the control of the switch control circuit, the second switch K2 is closed, and the first switch K1 and the third switch K3 are open. The gate of the fifth MOSFET T is connected to the capacitor voltage Vdata of the load capacitor. The voltage Vdata depends on the input pixel data corresponding to the first pixel column. At this time, the capacitor voltage Vdata of the load capacitor will generate a second current I1' from the source terminal S to the drain terminal D of the fifth MOSFET T. The second current I1' will flow through the detection resistor R. Since the data[M] corresponding to other pixel columns is 0, the third switch K3 is closed, the first switch K1 and the second switch K2 are open, the fifth MOSFET T does not generate current, so the detection resistor R only flows through the second current I1'. At this time, the detection circuit detects that the voltage at the detection point P represents the capacitor voltage Vdata of the first pixel column, and the converted data is the sampling voltage Cal_Vdata corresponding to the first pixel column.

[0110] Finally, it is determined whether the sampling voltage Cal_Vdata is the same as the comparison voltage Vdata_p, and the load capacitance is adjusted according to the determination result. Specifically, for circuits that use a discharge method to bring the load capacitance to the target voltage, if the sampling voltage Cal_Vdata is less than the comparison voltage Vdata_p, the load compensation capacitor configuration value for the first pixel column is incremented by 1. Conversely, for circuits that use a charging method to bring the load capacitance to the target voltage, if the sampling voltage Cal_Vdata is greater than the comparison voltage Vdata_p, the load compensation capacitor configuration value for the first pixel column is incremented by 1.

[0111] Repeat the above process until the sampling voltage Cal_Vdata is the same as the comparison voltage Vdata_p. At this point, the actual load capacitance of the first pixel column is equal to the original load capacitance plus the compensation capacitance. The load compensation capacitance configuration values ​​for the remaining pixel columns are obtained in the same way and saved to memory. When the chip powers on, the charging and discharging current configuration and the load compensation capacitance configuration values ​​are loaded.

[0112] like Figure 1 Each capacitor compensation circuit 40 corresponds to a load capacitor. The capacitor compensation circuit is connected to connection point A. The capacitor compensation circuit compensates the load capacitor based on the load capacitor calibration signal so that the corresponding capacitor voltage can be obtained based on the mirror current I through the compensated load capacitor.

[0113] like Figure 8The capacitor compensation circuit includes a compensation control circuit, a switching unit, and a compensation capacitor array. The compensation capacitor array is connected to connection point A through the switching unit. The compensation control circuit generates a load capacitance compensation control signal based on the load capacitance calibration signal to control the switching unit to turn on and off, thereby controlling the compensation capacitors in the compensation capacitor array that are connected to connection point A.

[0114] The compensation capacitor array includes multiple compensation capacitors C11, C12, C13 to C1n, and the switching unit includes multiple switches K11, K12, K13 to K1n. Each switch is turned on and off based on the control of a corresponding load capacitance compensation control signal. Each compensation capacitor is connected to connection point A through a corresponding switch. The switching unit also includes a master switch K10, which is turned on and off under the control of the load capacitance compensation control signal. Each switch is connected to connection point A through the master switch. In other embodiments, the master switch K10 may not be provided.

[0115] The values ​​of compensation capacitors C11, C12, C13 to C1n can be the same or different. The number of times switches K11, K12, K13 to K1n are closed can result in different sizes of compensation capacitors. When a load capacitance calibration signal is generated due to the sampling voltage Cal_Vdata not being equal to the comparison voltage Vdata_p, indicating that compensation is needed, the compensation control circuit generates a corresponding load capacitance compensation control signal. The main switch K10 closes under the load capacitance compensation control signal. When switch K11 closes under the corresponding load capacitance compensation control signal, the load capacitance is compensated through compensation capacitor C11. That is, the compensated load capacitance can be considered as the sum of compensation capacitor C11 and the original load capacitance in the circuit. When switch K12 is closed, the load capacitance is compensated through compensation capacitor C12.

[0116] It can be seen that the load capacitor compensation control signal of the control switches K11, K12, K13 to K1n can be a string of digital values ​​such as 1 and 0, which controls the opening and closing of the switches K11, K12, K13 to K1n. This string of digital values ​​is the load compensation capacitor configuration value. If you want to use compensation capacitors C11 and C12 for compensation, the signal of control switches K11 and K12 is 1, and the signal of the other control switches is 0. If you want to add compensation capacitor C13 for compensation, the signal of control switch K13 becomes 1, that is, the load compensation capacitor configuration is increased by 1.

[0117] The following two embodiments will be used as examples to describe in detail the charging and discharging part of the charging and discharging compensation circuit of the present invention.

[0118] Example 1

[0119] like Figure 2As shown, the charge / discharge compensation circuit includes n preprocessing circuits 10, n switching circuits 30, and a current mirror circuit 20 with n output branches. The first MOS transistor in the preprocessing circuit 10 is a PMOS transistor, the second and third MOS transistors in the current mirror circuit 20 are both NMOS transistors, and the fourth MOS transistor in the switching circuit 30 is an NMOS transistor. The source terminal of each first MOS transistor (denoted as T11 to Tn1) is connected to a reference voltage source V. H The drain terminal of the first MOSFET is connected to the corresponding load capacitor (denoted as C1 to Cn) to form connection point A, and the gate terminal is connected to the control signal S0; the drain terminal of the second MOSFET (denoted as T0) is connected to the reference current source I. bias The source terminal is grounded, and the gate terminal is connected to the drain terminal; the drain terminal of each third MOSFET (denoted as T13~Tn3) serves as the output branch, the source terminal is grounded, and the gate terminal is connected to the gate terminal of the second MOSFET; the source terminal of each fourth MOSFET (denoted as T12~Tn2) is connected to the drain terminal of the corresponding third MOSFET, the drain terminal is connected to connection point A, and the gate terminal is connected to the corresponding control signal (denoted as S1~Sn).

[0120] In practical implementation, after the start of a line's timing, control signal S0 turns on all the first MOSFETs (T11 to Tn1), while simultaneously, control signals (S1 to Sn) turn off the corresponding fourth MOSFETs (T12 to Tn2), such as control signal S1 turning off the fourth MOSFET T12. At this time, the voltage values ​​of all load capacitors (C1 to Cn) are increased to a high-voltage reference voltage V. H .

[0121] Furthermore, control signal S0 turns off all the first MOSFETs, while control signals (S1~Sn) turn on the corresponding fourth MOSFETs (T12~Tn2), and the charge / discharge compensation circuit begins to discharge. At this time, the current mirror circuit 20 can mirror a current I in each output branch, and this mirror current I is related to the reference current I. REF Proportional. In practical implementation, the mirror current I and the reference current I can be controlled by adjusting the width-to-length ratio of the second and third MOSFETs. REF Based on the proportional relationship, an appropriate current can be selected according to actual needs.

[0122] Furthermore, the discharge time of the load capacitor can be controlled by counting, such as using an M-bit counter from 0 to 2. M -1 is used for discharge time counting, and M is an integer greater than 0. For example... Figure 4As shown, when the counter counts from 0 to the grayscale value corresponding to a certain pixel column, the fourth MOSFET in the switching circuit corresponding to that pixel column is turned off by the corresponding control signal. At this time, the loop is broken, no current flows, and the discharge of the load capacitor stops, so the capacitor voltage is fixed. This capacitor voltage is the capacitor voltage corresponding to the grayscale value of that pixel column, and this voltage is stored by the load capacitor. After all the load capacitors in all columns have discharged, they are written together into the pixel driving circuit of a certain row. Here, the grayscale value is the pixel data.

[0123] Example 2

[0124] like Figure 3 As shown, unlike Embodiment 1, the first MOS transistor in the preprocessing circuit 10 is an NMOS transistor, the second and third MOS transistors in the current mirror circuit 20 are both PMOS transistors, and the fourth MOS transistor in the switching circuit 30 is a PMOS transistor. The source terminal of each first MOS transistor is connected to a reference voltage source V. L The drain of the first MOSFET is connected to the load capacitor, forming connection point A, and the gate is connected to the control signal S0; the drain of the second MOSFET is connected to the reference current I. REF The source terminal of each third MOSFET is connected to the voltage VDD, and the gate terminal is connected to the drain terminal. The drain terminal of each third MOSFET serves as the output branch, the source terminal is connected to the voltage VDD, and the gate terminal is connected to the gate terminal of the second MOSFET. The source terminal of each fourth MOSFET T12 to Tn2 is connected to the drain terminal of the third MOSFET, the drain terminal is connected to the connection point A, and the gate terminal is connected to the corresponding control signals S1 to Sn.

[0125] In practical implementation, after the start of a line's timing, control signal S0 turns on all the first MOSFETs T11 to Tn1, while simultaneously, control signals S1 to Sn turn off the corresponding fourth MOSFETs T12 to Tn2. At this time, the voltage values ​​of all load capacitors are adjusted to a low-voltage reference voltage V. L .

[0126] Furthermore, control signal S0 turns off all the first MOSFETs, while control signals S1 to Sn turn on the corresponding fourth MOSFETs T12 to Tn2, and the charge / discharge compensation circuit begins charging. At this time, the current mirror circuit 20 can mirror a current I in each output branch, and this mirror current I is compared with the reference current I. REF Proportional.

[0127] Furthermore, the charging time of the load capacitor can be controlled by counting, such as using an M-bit counter from 0 to 2. M -1 is used to count charging time, and M is an integer greater than 0. For example Figure 4As shown, when the counter counts from 0 to the grayscale value corresponding to a pixel in a certain column (where the grayscale value is pixel data), the fourth MOSFET in the corresponding switching circuit is turned off by the corresponding control signal. At this point, the circuit is broken, no current flows, and charging of the load capacitor stops, keeping the load capacitor voltage fixed. This voltage is the voltage corresponding to the grayscale value of the pixel in that column, and it is stored by the load capacitor. Once all the load capacitors in all columns are fully charged, the data is written together into the pixel driving circuit of a certain row.

[0128] In this embodiment, the charging and discharging of the capacitor load can be achieved through the specific circuit described above. Of course, in other embodiments, the charging and discharging of the capacitor load can also be achieved through other means.

[0129] Based on the above circuit, the present invention also discloses a charge / discharge compensation method for a charge / discharge compensation circuit, comprising:

[0130] Each preprocessing circuit 10 adjusts the voltage of the corresponding load capacitor to a preset value.

[0131] The reference current I is reflected by the current mirror circuit 20. REF The image is mirrored and the mirror current I is output through at least one output branch to charge or discharge the load capacitor.

[0132] The preprocessing circuit controls the switching circuit 30 to adjust the voltage of the corresponding load capacitor to a preset value and to control the charging or discharging time of the load capacitor.

[0133] In the first mode, the sampling and detection circuit 40 generates a mirror current calibration signal for adjusting the reference current based on the magnitude between the capacitor voltage on the load capacitor and the target voltage. In the second mode, the sampling and detection circuit 40 generates a load capacitor calibration signal based on the magnitude between the capacitor voltage on the load capacitor and the target voltage. Specifically, firstly, in the first mode, a target voltage is selected from the ramp voltage, and the target voltage is sampled to obtain a comparison voltage. In one embodiment, the ramp voltage can be evenly divided into 2... M M represents the color depth of the display; during discharge, the voltage closest to the minimum value of the ramp voltage is selected as the target voltage, and during charging, the voltage closest to the maximum value of the ramp voltage is selected as the target voltage.

[0134] Secondly, a discharge or charge time is set, and the capacitor voltage on the load capacitor of the selected pixel column after discharge or charge is sampled to obtain a sampled voltage. Based on the magnitude between the sampled voltage and the comparison voltage, a mirror current calibration signal is generated to adjust the reference current. The mirror current is calibrated by adjusting the reference current. In one embodiment, a discharge time is set and each pixel column is discharged starting from the maximum value of the ramp voltage, or a charge time is set and each pixel column is charged starting from the minimum value of the ramp voltage, and the pixel column with the slowest discharge or charge is determined. In one embodiment, an M-bit counter can be used to count from 0 to 2. M -1 is used to count the charging or discharging time, and the discharging or charging ends when the counter counts from zero to the gray value corresponding to a column of pixels, thereby setting the charging or discharging time. M is the color depth of the display, and M is an integer greater than 0.

[0135] In the second mode, the capacitor voltage generated on the load capacitor of each pixel column based on the calibrated mirror current is sampled to obtain the corresponding sampling voltage; the load capacitor calibration signal corresponding to the remaining pixel columns is determined based on the magnitude of the sampling voltage and the comparison voltage.

[0136] The load capacitance is compensated by a capacitor compensation circuit based on a load capacitance calibration signal, and the corresponding capacitor voltage is obtained based on the mirror current of the compensated load capacitance. In one embodiment, if the sampling voltage is less than the comparison voltage, the output load capacitance calibration signal controls the capacitor compensation circuit to compensate the load capacitance, thereby adding a compensation capacitor to the original load capacitance.

[0137] The following sections will explain in detail how to perform compensation during the discharge and charging processes.

[0138] (1) Discharge process

[0139] like Figure 9 The diagram shown is a schematic of a ramp voltage, which can be represented by the following formula:

[0140] V data =V H -(I L / C L )*t, i.e., C L =I L *t / (V H -V data );

[0141] Where t is T*P W T represents the number of clock cycles, ranging from 0 to 2. M -1, P W C represents the periodic time length. L For load capacitance; V dataIt is the voltage across the load capacitor; I L It is the pixel column discharge current; V H As a reference voltage value, C can be obtained when all parameters are fixed. L .

[0142] Discharge current I of different pixel columns L They are not equal, therefore the load capacitance C cannot be directly calculated. L However, the load capacitance C after pixel column compensation L The discharge time can be determined by inputting the grayscale value of the test pixel, and then determined by detecting the voltage of the compensated capacitor. L +△C max This corresponds to the load capacitance after compensation for the pixel column with the fastest discharge, C. L +△C k It is the load capacitance after compensation for any pixel column.

[0143] In practical implementation, the preprocessing circuit 10 will first adjust each load capacitor to a preset value, that is, adjust it to the reference voltage value V. H To compensate for the discharge process, this invention first uses a reference voltage value V H and V L Choose a target voltage Vcal. The target voltage Vcal can be selected as follows: [The text abruptly ends here, likely due to an incomplete sentence or a formatting error.] L To V H The voltage between them is divided into 2 equal parts. M Parts, corresponding to pixel grayscale value 2 M -1 to 0, where V H The corresponding minimum grayscale value of the pixel is 0, V L The corresponding pixel maximum grayscale value is 2. M -1.

[0144] For any pixel in any pixel column, the corresponding grayscale value formula is G. k =(2 M -1)*(I L / C L )*tk0 / (V H -V L G k It is the grayscale value of a pixel in any pixel column, t k0 I is the discharge time corresponding to a pixel in any pixel column. L It is the actual discharge current of any pixel array, C L It is the actual load capacitance of any pixel column.

[0145] In this embodiment, to achieve better calibration accuracy, reuse the latch circuit, and ensure coverage of the maximum difference across all pixel columns, the target voltage Vcal is preferably selected to be close to the voltage V. L point.

[0146] Furthermore, after selecting the target voltage Vcal, all pixel columns are discharged sequentially, with a discharge time of (2... M -1)*(V H -Vcal) / (V H -V L The process involves 10 clock cycles. After the discharge time ends, the slowest discharging pixel column is identified. In practice, this can be determined using a detection circuit, such as checking if the pixel column has discharged to the target voltage Vcal to determine if it is the slowest discharging pixel column.

[0147] Once the pixel column with the slowest discharge is determined, the reference current I of the current mirror circuit 20 is further adjusted. REF By changing the reference current I REF To change the mirrored current output of the current mirror circuit 20 in the pixel column, and at the same time, to discharge the pixel column for a discharge time of (2 M -1)*(V H -Vcal) / (V H -V L ( ) clock cycles. Simultaneously, determine the capacitor voltage V of that pixel column. data Is it the same as the target voltage Vcal? If the capacitor voltage V of this pixel column is... data If the voltage is the same as the target voltage Vcal, then the calibration is complete, and the current reference current I... REF This is the calibrated reference current, and at this time, the current reference current I... REF The configuration parameters are stored for later use of the reference current I. REF Calibrate other pixel columns. If the capacitor voltage V of that pixel column... data If the current is not the same as the target voltage Vcal, then continue to adjust the reference current I of the current mirror circuit 20. REF until it discharges (2 M -1)*(V H -Vcal) / (V H -V L The capacitor voltage V during ) clock cycles data Same as the target voltage Vcal.

[0148] Furthermore, after calibrating the pixel column with the slowest discharge time, the compensation capacitors for the remaining pixel columns are determined based on the discharge current of that slowest-discharging pixel column. In specific implementation, the compensation capacitors for the remaining pixel columns can be obtained as follows:

[0149] From the above and in combination Figure 9 As shown, the column of pixels with the slowest discharge starts from voltage V. H The time taken to discharge to Vcal is (2 M -1)*(V H -Vcal) / (V H -V L The load capacitance of the corresponding pixel column is C for 10 clock cycles. L =(2 M -1)*P w *I L / (V H -V L The first pixel column of the remaining pixel columns starts from V. H Discharge to Vcal, where the discharge time is (2 M -1)*(V H -Vcal) / (V H -V L The discharge current I is fixed. L Also, fix and adjust the compensation capacitor value ΔC of the capacitor compensation circuit so that the capacitor voltage V of the pixel column is... data Corresponding to the target voltage Vcal. If the capacitor voltage V of this pixel column... data Corresponding to the target voltage Vcal, detection stops, and the current load compensation capacitor configuration value of the capacitor compensation circuit is saved; otherwise, the detection continues by changing the load compensation capacitor configuration value of the capacitor compensation circuit until the capacitor voltage Vcal of that pixel column is reached. data Corresponding to the target voltage Vcal, detection stops, and the load compensation capacitor configuration value of the capacitor compensation circuit at this time is saved. The final actual load capacitance of the corresponding pixel column at this point is the load capacitance C of that pixel column. L Add the compensation capacitor ΔC of the capacitor compensation circuit corresponding to that pixel column. Similarly, the load compensation capacitor configuration values ​​for the capacitor compensation circuits corresponding to the remaining pixel columns are obtained using the same method.

[0150] As shown above, the capacitor compensation circuit consists of N parallel-connected compensation capacitors, each controlled by an individual switch. The capacitance values ​​of the compensation capacitors can be the same or unequal. The compensation capacitors and the load capacitor are connected in parallel to the charge / discharge compensation circuit. When the pixel column does not require capacitor compensation, the main switch is open; when the pixel column requires capacitor compensation, the main switch is closed. The control switch within the capacitor compensation circuit is opened or closed based on the configuration value of the load compensation capacitor. The configuration value of the load compensation capacitor is stored in memory and loaded after the monitor is powered on to improve the display effect.

[0151] (2) Charging process

[0152] like Figure 10 The diagram shown is a schematic of a ramp voltage, which can be represented by the following formula:

[0153] V data =V L +(I L / C L )*t, i.e., C L =I L *t / (V data -V L );

[0154] Where t is T*P W T represents the number of clock cycles, ranging from 0 to 2. M -1, P W C represents the periodic time length. L It is the load capacitance; V data It is the voltage across the load capacitor; I L It is the pixel column charging current; V L As a reference voltage value, C can be obtained when all parameters are fixed. L .

[0155] Charging current I for different pixel columns L They are not equal, therefore the load capacitance C cannot be directly calculated. L However, the load capacitance C after pixel column compensation L The charging time can be determined by inputting the grayscale value of the test pixel, and then determined by detecting the compensated capacitor voltage. L +△C max This corresponds to the load capacitance after compensation for the fastest charging pixel column, C. L +△C k It is the load capacitance after compensation for any pixel column.

[0156] In practical implementation, the preprocessing circuit 10 will first adjust each load capacitor to a preset value, that is, adjust it to the voltage V. LIn order to compensate for the charging process, the present invention first addresses the voltage V. H and V L Choose a target voltage Vcal. The target voltage Vcal can be selected as follows: [The text abruptly ends here, likely due to an incomplete sentence or a formatting error.] L To V H The voltage between them is divided into 2 equal parts. M Parts, corresponding to pixel grayscale value 2 M -1 to 0, where V L The corresponding minimum grayscale value of the pixel is 0, V H The corresponding pixel maximum grayscale value is 2. M -1.

[0157] In this embodiment, to achieve better calibration accuracy, reuse the latch circuit, and ensure coverage of the maximum difference across all pixel columns, the target voltage Vcal is preferably selected to be close to the voltage V. H point.

[0158] Furthermore, after selecting the target voltage Vcal, all pixel columns are charged sequentially, with a charging time of (2... M -1)*(Vcal-V L ) / (V H -V L The charging process takes 10 clock cycles. After the charging time is complete, the slowest charging pixel column is identified. In practice, this can be determined using a detection circuit, such as checking if the pixel column has reached the target voltage Vcal to determine if it is the slowest charging pixel column.

[0159] Furthermore, after determining the pixel column with the slowest charging, the reference current I of the current mirror circuit 20 is further adjusted. REF By changing the reference current I REF This changes the mirrored current output of the current mirror circuit 20 in the pixel column, and simultaneously charges the pixel column for a charging time of (2... M -1)*(Vcal-V L ) / (V H -V L ( ) clock cycles. Simultaneously, determine the capacitor voltage V of that pixel column. data Is it the same as the target voltage Vcal? If the capacitor voltage V of this pixel column is... data If the current reference current I is the same as the target voltage Vcal, then... REF This is the calibrated reference current, and at this time, the current reference current I... REF The configuration parameters are stored for later use of the reference current I. REF Calibrate other pixel columns. If the capacitor voltage V of that pixel column...data If the current is not the same as the target voltage Vcal, then continue to adjust the reference current I of the current mirror circuit 20. REF Until it is charging (2 M -1)*(Vcal-V L ) / (V H -V L The capacitor voltage V during ) clock cycles data Same as the target voltage Vcal.

[0160] Furthermore, after calibrating the pixel column with the slowest charging time, the compensation capacitors for the remaining pixel columns are determined based on the charging current of that slowest-charging pixel column. In specific implementation, the compensation capacitors for the remaining pixel columns can be obtained as follows:

[0161] From the above and in combination Figure 10 As shown, the column of pixels that charge the slowest starts from voltage V. L The time required to charge to Vcal is (2 M -1)*(Vcal-V L ) / (V H -V L The load capacitance of the corresponding pixel column is C for 10 clock cycles. L =(2 M -1)*P w *I L / (V H -V L The first pixel column of the remaining pixel columns starts from V. L Charging to Vcal, where the charging time is (2 M -1)*(Vcal-V L ) / (V H -V L The charging current I is fixed. L Also, fix and adjust the compensation capacitor value ΔC of the capacitor compensation circuit so that the capacitor voltage V of the pixel column is... data Corresponding to the target voltage Vcal. If the capacitor voltage V of this pixel column... data Corresponding to the target voltage Vcal, detection stops, and the current load compensation capacitor configuration value of the capacitor compensation circuit is saved; otherwise, the detection continues by changing the load compensation capacitor configuration value of the capacitor compensation circuit until the capacitor voltage Vcal of that pixel column is reached. data Corresponding to the target voltage Vcal, detection stops, and the load compensation capacitor configuration value of the capacitor compensation circuit at this time is saved. The final actual load capacitance of the corresponding pixel column at this point is the load capacitance C of that pixel column. LAdd the compensation capacitor ΔC of the capacitor compensation circuit corresponding to that pixel column. Similarly, the load compensation capacitor configuration values ​​for the capacitor compensation circuits corresponding to the remaining pixel columns are obtained using the same method.

[0162] As shown above, the capacitor compensation circuit consists of N parallel-connected compensation capacitors, each controlled by an individual switch. The capacitance values ​​of the compensation capacitors can be the same or unequal. The compensation capacitors and the load capacitor are connected in parallel to the charge / discharge compensation circuit. When the pixel column does not require capacitor compensation, the main switch is open; when the pixel column requires capacitor compensation, the main switch is closed. The control switch within the capacitor compensation circuit is opened or closed based on the configuration value of the load compensation capacitor. The configuration value of the load compensation capacitor is stored in memory and loaded after the monitor is powered on to improve the display effect.

[0163] This invention also discloses a display screen having the aforementioned charge / discharge compensation circuit, capable of charging or discharging the load capacitors in all columns of pixel circuits in the same row, ensuring that the voltage values ​​of the load capacitors meet actual usage requirements, and that the charging or discharging of the load capacitors in each column of pixel circuits is independent and does not interfere with each other. The display screen referred to here includes, but is not limited to, OLED / LED / LCD / LCOS / MICRO-LED / MICRO-OLED displays.

[0164] Meanwhile, this invention also discloses an electronic device having the aforementioned display screen, capable of charging or discharging the load capacitors in all columns of pixel circuits in the same row within a short period of time, ensuring that the voltage values ​​of the load capacitors meet actual usage requirements, and that the charging or discharging of the load capacitors in each column of pixel circuits is independent and does not interfere with each other. This electronic device includes, but is not limited to, smartphones, tablets, laptops, televisions, desktop monitors, VR / AR / MR / XR, and HUD devices.

[0165] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0166] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A charge / discharge compensation circuit, characterized in that, include At least one load capacitor; At least one preprocessing circuit, each of the preprocessing circuits corresponding to one of the load capacitors, the preprocessing circuits being connected to the corresponding load capacitors to form a connection point, the preprocessing circuits being used to adjust the voltage of the corresponding load capacitors to a preset value; A current mirror circuit is used to mirror a reference current and output a mirror current for charging or discharging a load capacitor through at least one output branch, with each output branch corresponding to one connection point. At least one switching circuit, each of the switching circuits corresponds to one of the output branches, and each of the output branches is connected to the corresponding connection point through the corresponding switching circuit. The switching circuit is used to control the preprocessing circuit to adjust the voltage of the corresponding load capacitor to a preset value and the charging or discharging time of the load capacitor. A sampling and detection circuit is used to generate a mirror current calibration signal for adjusting the reference current based on the magnitude between the capacitor voltage on the load capacitor and the target voltage in a first mode, and to generate a load capacitance calibration signal based on the magnitude between the capacitor voltage on the load capacitor and the target voltage in a second mode. At least one capacitor compensation circuit is provided, each capacitor compensation circuit corresponds to one load capacitor, the capacitor compensation circuit is connected to a connection point, and the capacitor compensation circuit compensates the load capacitor based on the load capacitor calibration signal so as to obtain the corresponding capacitor voltage based on the mirror current through the compensated load capacitor.

2. The charge / discharge compensation circuit as described in claim 1, characterized in that, Each of the preprocessing circuits is controlled by the same control signal to adjust the voltage of the corresponding load capacitor to a preset value.

3. The charge / discharge compensation circuit as described in claim 1, characterized in that, The preprocessing circuit includes: The first MOSFET has its source terminal connected to a reference voltage source or ground, its drain terminal connected to the load capacitor to form the connection point, and its gate terminal connected to a control signal.

4. The charge / discharge compensation circuit as described in claim 1, characterized in that, The current mirror circuit includes: The second MOSFET has its drain terminal connected to the reference current source, its source terminal connected to the voltage source or ground, and its gate terminal connected to the drain terminal. At least one third MOS transistor is provided, with the drain terminal of each third MOS transistor serving as the output branch, the source terminals being connected to a voltage source or ground, and the gate terminals being connected to the gate terminals of the second MOS transistor.

5. The charge / discharge compensation circuit as described in claim 1, characterized in that, The switching circuit includes: The fourth MOSFET has its source terminal connected to the output branch, its drain terminal connected to the connection point, and its gate terminal connected to the control signal.

6. The charge / discharge compensation circuit as described in claim 1, characterized in that, The sampling and detection circuit includes: Detecting resistance; Several calibration circuits, each corresponding to a pixel column, and each calibration circuit is connected to a voltage source or ground through a detection resistor to form a detection point. Each calibration circuit is used to receive the capacitor voltage on the load capacitor and the target voltage, and selects to convert the capacitor voltage on the corresponding load capacitor into a sampling current or the target voltage into a comparison current and input it into the detection resistor. At least one detection circuit is configured to generate a mirror current calibration signal in a first mode based on the magnitude of the sampling voltage generated by the sampling current in the detection resistor and the comparison voltage generated by the comparison current in the detection resistor, and to generate a load capacitance calibration signal in a second mode based on the magnitude of the sampling voltage generated by the sampling current in the detection resistor and the comparison voltage generated by the comparison current in the detection resistor.

7. The charge / discharge compensation circuit as described in claim 6, characterized in that, All pixel columns share a single detection circuit.

8. The charge / discharge compensation circuit as described in claim 6, characterized in that, The calibration circuit includes: The fifth MOSFET is connected in series with the detection resistor between the voltage source and ground; The first switch has one end connected to the reference voltage and the other end connected to the gate of the fifth MOSFET. The second switch has one end connected to the capacitor voltage on the load capacitor and the other end connected to the gate terminal of the fifth MOSFET. The third switch has one end connected to a voltage source and the other end connected to the gate of the fifth MOSFET. A switch control circuit, connected to the first switch, the second switch, and the third switch, is used to control the closing or opening of the first switch, the second switch, and the third switch.

9. The charge / discharge compensation circuit as described in claim 8, characterized in that, The switch control circuit is a logic circuit composed of gate-level circuits. The inputs are calibration_mode0, calibration_mode1 and data[M], and the outputs are Q1, Q2 and Q3. Q1, Q2 and Q3 control the closing or opening of the first switch, the second switch and the third switch, respectively. Among them, calibration_mode0 and calibration_mode1 are configurable 2-bit registers, and data[M] is the highest bit value of the grayscale value corresponding to the pixel column.

10. The charge / discharge compensation circuit as described in claim 1, characterized in that, The switching circuit is used to control the charging or discharging time of the load capacitor, including: During charging or discharging, the M-bit counter counts from 0 to 2. M -1 is used to count the charging or discharging time, and the switching circuit corresponding to the column of pixels is turned off when the counter counts from zero to the gray value corresponding to the column of pixels. M is the color depth of the display, and M is an integer greater than 0.

11. The charge / discharge compensation circuit as described in claim 1, characterized in that, The capacitor compensation circuit includes a compensation control circuit, a switching unit, and a compensation capacitor array. The compensation capacitor array is connected to the connection point through the switching unit. The compensation control circuit generates a load capacitance compensation control signal based on the load capacitance calibration signal to control the switching unit to turn on and off, thereby controlling the number of compensation capacitors in the compensation capacitor array connected to the connection point.

12. The charge / discharge compensation circuit as described in claim 11, characterized in that, The compensation capacitor array includes multiple compensation capacitors, and the switching unit includes multiple switches. Each switch is turned on and off based on the control of a corresponding load capacitor compensation control signal. Each compensation capacitor is connected to a connection point through a corresponding switch.

13. The charge / discharge compensation circuit as described in claim 12, characterized in that, The switching unit also includes a main switch that is turned on and off under the control of a load capacitance compensation control signal, and each of the switches is connected to a connection point through the main switch.

14. A charge / discharge compensation method based on the charge / discharge compensation circuit of claim 1, characterized in that, include The voltage of the corresponding load capacitor is adjusted to a preset value through each preprocessing circuit; The reference current is mirrored by a current mirror circuit and the mirrored current is output through at least one output branch to charge or discharge the load capacitor. The preprocessing circuit is controlled by a switching circuit to adjust the voltage of the corresponding load capacitor to a preset value and to control the charging or discharging time of the load capacitor. In the first mode, the sampling and detection circuit generates a mirror current calibration signal for adjusting the reference current based on the magnitude between the capacitor voltage on the load capacitor and the target voltage. In the second mode, the sampling and detection circuit generates a load capacitance calibration signal based on the magnitude between the capacitor voltage on the load capacitor and the target voltage. The load capacitance is compensated by a capacitor compensation circuit based on the load capacitance calibration signal, and the corresponding capacitor voltage is obtained based on the mirror current through the compensated load capacitance.

15. The charge / discharge compensation method for the charge / discharge compensation circuit as described in claim 14, characterized in that, The step of generating a mirror current calibration signal for adjusting the reference current based on the magnitude between the capacitor voltage on the load capacitor and the target voltage in the first mode via a sampling detection circuit, and generating a load capacitance calibration signal based on the magnitude between the capacitor voltage on the load capacitor and the target voltage in the second mode via a sampling detection circuit, includes: In the first mode, a target voltage is selected, and the target voltage is sampled to obtain the comparison voltage; Set the discharge or charge time, sample the capacitor voltage on the load capacitor of the selected pixel column after discharge or charge to obtain the sample voltage, generate a mirror current calibration signal for adjusting the reference current based on the magnitude between the sample voltage and the comparison voltage, and calibrate the mirror current by adjusting the reference current. In the second mode, the corresponding sampling voltage is obtained by sampling the capacitor voltage generated on the load capacitor of each of the remaining pixel columns based on the calibrated mirror current. The load capacitance calibration signal for each of the remaining pixel columns is determined based on the magnitude of the sampling voltage and the comparison voltage.

16. The charge / discharge compensation method as described in claim 15, characterized in that, Selecting a target voltage includes: Divide the ramp voltage evenly into 2 M M represents the display's color depth; When discharging, select the voltage closest to the minimum value of the ramp voltage as the target voltage; when charging, select the voltage closest to the maximum value of the ramp voltage as the target voltage.

17. The charge / discharge compensation method as described in claim 15, characterized in that, The step of setting the discharge or charge time in the first mode, sampling the capacitor voltage on the load capacitor of the selected pixel column after discharge or charge to obtain a sample voltage, and calibrating the mirror current based on the magnitude between the sample voltage and the comparison voltage includes: In the first mode, a discharge time is set and each pixel column is discharged starting from the maximum value of the ramp voltage, or a charging time is set and each pixel column is charged starting from the minimum value of the ramp voltage, and the pixel column that is discharged or charged the slowest is determined. The capacitor voltage on the load capacitor after discharge or charging is sampled for the pixel column that discharges or charges the slowest. The mirror current is calibrated based on the magnitude between the sampled voltage and the comparison voltage.

18. The charge / discharge compensation method as described in claim 15, characterized in that, The set discharge or charge time includes: from 0 to 2 using an M-bit counter. M -1 is used to count the charging or discharging time, and the discharging or charging ends when the counter counts from zero to the gray value corresponding to a column of pixels. M is the color depth of the display, and M is an integer greater than 0.

19. A display screen, characterized in that, Includes the charge / discharge compensation circuit as described in any one of claims 1 to 13.

20. An electronic device, characterized in that, Includes the display screen as described in claim 19.

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