Driving circuit and electronic device having the same

Abstract

A driving circuit and an electronic device having the same are provided. The electronic device includes: a display panel; a processor outputting a transmission signal; and a driving controller receiving the transmission signal and outputting an image data signal based on the transmission signal in such a manner that an image is displayed on the display panel. The drive controller includes a memory storing an image data signal. In the still image mode, when a current image corresponding to a portion of the display panel is different from a previous image corresponding to the portion of the display panel, the processor outputs a transmission signal. In the still image mode, when a display time of a still image corresponding to the portion of the display panel reaches a predetermined time, the driving controller allows the display panel to be refreshed by the image data signal read from the memory.

Description

[0001] This application claims priority to and all benefits arising therefrom of Korean Patent Application No. 10-2024-0125923, filed on September 13, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments of this disclosure described herein relate to drive circuits and electronic devices including such drive circuits. Background Technology

[0003] Electronic devices may include pixels connected to data lines and scan lines. Each pixel includes a light-emitting element and pixel circuitry for controlling the light-emitting element. The pixel circuitry may supply a current to the light-emitting element corresponding to a data signal. In this case, light with a predetermined brightness may be generated in response to the current flowing through the light-emitting element.

[0004] In an electronic device that includes pixels for displaying images, the display quality of the images displayed on it can be improved by increasing the operating frequency of the electronic device, while its power consumption can be reduced by decreasing the operating frequency of the electronic device. Summary of the Invention

[0005] Embodiments of this disclosure provide an electronic device capable of operating at various driving frequencies.

[0006] According to an embodiment, an electronic device includes: a display panel; a processor that outputs a transmission signal; and a drive controller that receives the transmission signal and outputs an image data signal based on the transmission signal in a manner that causes an image to be displayed on the display panel. In such an embodiment, the drive controller includes a memory storing the image data signal. In such an embodiment, in still image mode, the processor outputs the transmission signal when a current image corresponding to a portion of the display panel differs from a previous image corresponding to that portion of the display panel. In such an embodiment, in still image mode, when the display time of the still image corresponding to that portion of the display panel reaches a predetermined time, the drive controller allows the display panel to be refreshed by the image data signal read from the memory.

[0007] In one embodiment, when the current image corresponding to that portion of the display panel is different from the previous image corresponding to that portion of the display panel, the processor can output a transmission signal corresponding to that portion of the display panel. In such an embodiment, the drive controller can store the image data signal corresponding to that portion of the display panel in a memory.

[0008] In an embodiment, during a refresh frame in still image mode, the drive controller can read image data signals corresponding to the full image of the display panel from the memory and can output image data signals corresponding to the full image of the display panel.

[0009] In an embodiment, in still image mode, after receiving the transmission signal corresponding to the new image, the drive controller can set the next frame as the refresh frame.

[0010] In one embodiment, when the still image mode is initiated, the processor can output a transmission signal to the drive controller corresponding to the full image of the display panel.

[0011] In an embodiment, in still image mode, when the full image of the current frame is the same as the full image of the previous frame, the processor may not output a transmission signal to the drive controller.

[0012] In one embodiment, the transmission signal may include a still image mode signal indicating a still image mode. In such an embodiment, the drive controller may recover the still image mode signal included in the transmission signal.

[0013] In one embodiment, the drive controller may further include: a receiver, which recovers the image signal, the multi-frequency mode signal, and the still image mode signal based on the transmitted signal, wherein the image signal, the multi-frequency mode signal, and the still image mode signal are included in the transmitted signal; and a controller, which converts the image signal into an image data signal. In such an embodiment, when the display time of the still image reaches a predetermined time and the still image mode signal is at an active level, the controller may output the image data signal read from the memory.

[0014] In this embodiment, when the multi-frequency mode signal is at the active level, the controller can output an image data signal corresponding to the transmitted signal.

[0015] In an embodiment, the memory can remain in a closed state when the multi-frequency mode signal is at an active level and the still image mode signal is at an inactive level.

[0016] In an embodiment, in multi-frequency mode, when the display time of the still image corresponding to that part of the display panel reaches a predetermined time, the processor can output a transmission signal corresponding to the full image of the display panel to the drive controller, and the controller can allow the display panel to be refreshed.

[0017] In one embodiment, during the first frame of the still image mode, the processor may output a transmission signal corresponding to the full image of the display panel to the drive controller. In such an embodiment, during the first frame of the still image mode, the drive controller may store the image data signal corresponding to the transmission signal in memory.

[0018] According to an embodiment, an electronic device includes: a display panel; a processor for outputting a transmission signal; and a drive controller for receiving the transmission signal and outputting an image data signal based on the transmission signal in a manner that causes an image to be displayed on the display panel. In such an embodiment, the drive controller includes a memory storing the image data signal. In such an embodiment, the processor divides the display panel into a first display area and a second display area in a still image mode, and outputs the transmission signal when a current image corresponding to the second display area is different from a previous image corresponding to the second display area. In such an embodiment, in a still image mode, when the display time of a still image corresponding to the first display area reaches a predetermined time, the drive controller allows the display panel to be refreshed by the image data signal read from the memory.

[0019] In one embodiment, when the current image corresponding to the second display area of ​​the display panel is different from the previous image corresponding to the second display area of ​​the display panel, the processor can output a transmission signal corresponding to the second display area of ​​the display panel. In such an embodiment, the drive controller can store the image data signal corresponding to the second display area of ​​the display panel in a memory.

[0020] In one embodiment, during a refresh frame in still image mode, the drive controller can read from memory an image data signal corresponding to the full image of the display panel.

[0021] In an embodiment, in still image mode, when the full image of the current frame is the same as the full image of the previous frame, the processor may not output a transmission signal.

[0022] According to an embodiment, a driving circuit includes: a driving controller that receives a transmission signal from an external source and outputs an image data signal based on the transmission signal; and a data driving circuit that converts the image data signal into a data signal. In such an embodiment, the driving controller includes a memory storing the image data signal. In such an embodiment, in still image mode, when the display time of the still image reaches a predetermined time, the driving controller outputs the image data signal read from the memory to the data driving circuit.

[0023] In an embodiment, during the refresh frame of the still image mode, the drive controller can read the image data signal corresponding to the full image of the display panel from the memory, and can output the image data signal corresponding to the full image of the display panel to the data drive circuit.

[0024] In one embodiment, the drive controller may further include: a receiver, capable of recovering an image signal, a multi-frequency mode signal, and a still image mode signal based on the transmitted signal, wherein the image signal, the multi-frequency mode signal, and the still image mode signal are included in the transmitted signal; and a controller, capable of converting the image signal into an image data signal. In such an embodiment, when the display time of the still image reaches a predetermined time and the still image mode signal is at an active level, the controller may output the image data signal read from the memory.

[0025] In an embodiment, the memory can remain in a closed state when the multi-frequency mode signal is at an active level and the still image mode signal is at an inactive level. Attached Figure Description

[0026] The above and other features of the embodiments of this disclosure will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

[0027] Figure 1 An electronic device according to an embodiment of the present disclosure is shown.

[0028] Figure 2 An image displayed on an electronic device according to an embodiment of the present disclosure is shown.

[0029] Figure 3A and Figure 3B This is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0030] Figure 4A It is a diagram used to describe the operation of an electronic device in normal mode.

[0031] Figure 4B It is a diagram used to describe the operation of an electronic device in still image mode.

[0032] Figure 4C It is a diagram used to describe the operation of electronic devices in multiple frequency modes.

[0033] Figure 5 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0034] Figure 6 This is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0035] Figure 7 This is a block diagram showing the configuration of the processor and drive controller of an electronic device.

[0036] Figure 8A This is a diagram showing the image displayed on the display panel in normal mode.

[0037] Figure 8B This is a diagram showing the image displayed on the display panel in multi-frequency mode.

[0038] Figure 9 and Figure 10 It is a diagram used to describe the operation of the processor and drive controller in normal mode and multi-frequency mode.

[0039] Figure 11A , Figure 11B , Figure 11C , Figure 11D and Figure 11E This is a diagram showing an image displayed on the display panel in still image mode.

[0040] Figure 12 and Figure 13 It is a diagram used to describe the operation of the processor and drive controller in still image mode. Detailed Implementation

[0041] The invention will now be described more fully with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0042] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element, or there can be intermediary elements between them. In contrast, when an element is referred to as being "directly on" another element, no intermediary element exists.

[0043] In the specification, the expression "connected" or "coupled" between the first component (or area, layer, part, etc.) and the second component means that the first component is directly connected or directly coupled to the second component, or that the third component is located between them.

[0044] The same reference numerals denote the same elements. Furthermore, in the drawings, the thickness, scale, and dimensions of parts are enlarged for effective depiction of the technical content.

[0045] It will be understood that although the terms “first,” “second,” “third,” etc., may be used in this document to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part without departing from the teachings of this document.

[0046] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the relative terms are intended to cover different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “down” of other elements will be oriented “up” of other elements. Thus, depending on the specific orientation of the drawing, the term “down” can cover both “down” and “up” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” other elements will be oriented “above” of other elements. Thus, the term “below” or “under” can cover both “up” and “down” orientations.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. Thus, “a” element is referred to in the claims, followed by “the” element, to include one element and multiple elements. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limited to “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items. It will be further understood that, when used in this specification, the terms “comprising” and / or variations thereof or “including” and / or variations thereof indicate the presence of the recited features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0048] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the relevant technical context and shall not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0049] Embodiments are described herein with reference to illustrative drawings of idealized embodiments. Thus, variations in the shapes illustrated are expected due to factors such as manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the areas illustrated herein, but rather include deviations in shape, for example, due to manufacturing processes. For instance, areas illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, illustrated sharp corners may be rounded. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate precise shapes of the areas, nor are they intended to limit the scope of the claims.

[0050] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 An electronic device ED according to an embodiment of the present disclosure is shown.

[0052] refer to Figure 1 In embodiments, for example, the electronic device ED can be a portable terminal. Portable terminals can include tablet computers, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), game consoles, and watch-type electronic devices, etc. However, this disclosure is not limited thereto. In addition to large electronic devices such as televisions or outdoor billboards, embodiments of this disclosure can be small to medium-sized electronic devices such as personal computers (e.g., laptop computers), self-service terminals, car navigation units, and cameras. The above examples are provided by way of example only, and it will be apparent that this disclosure can be applied to any other electronic device without departing from the concept of this disclosure.

[0053] In an embodiment, such as Figure 1As shown, the display surface of the electronic device ED, on which a first image IM1 and a second image IM2 are displayed, is parallel to a plane defined by a first direction DR1 and a second direction DR2. The electronic device ED includes a plurality of regions separated or divided on the display surface. The display surface includes a display area DA in which the first image IM1 and the second image IM2 are displayed, and a non-display area NDA adjacent to the display area DA. The non-display area NDA may be referred to as a border area. In an embodiment, for example, the display area DA may have a rectangular shape in a plan view. The non-display area NDA surrounds the display area DA. Furthermore, although not illustrated, for example, the electronic device ED may include a partially curved shape.

[0054] The display area DA of the electronic device ED includes a first display area DA1 and a second display area DA2. In a specific application, a first image IM1 may be displayed in the first display area DA1, and a second image IM2 may be displayed in the second display area DA2. In an embodiment, for example, the first image IM1 may be an image with a fast change cycle (e.g., video), and the second image IM2 may be an image with a long change cycle (e.g., a still image such as a photograph or text information).

[0055] The operating modes of the electronic device ED can include a single-frequency mode and a multi-frequency mode. In single-frequency mode, the electronic device ED can drive both the first display area DA1 and the second display area DA2 at a default frequency. In multi-frequency mode, according to an embodiment, the electronic device ED can drive the first display area DA1, in which a first image IM1 is displayed, at a first operating frequency, and can drive the second display area DA2, in which a second image IM2 is displayed, at a second operating frequency. In an embodiment, the first operating frequency can be higher than or equal to the default frequency. In an embodiment, the second operating frequency can be lower than the first operating frequency. The electronic device ED can reduce power consumption by lowering the operating frequency of the second display area DA2.

[0056] The size of each of the first display area DA1 and the second display area DA2 can be a preset size and can be changed by the application.

[0057] In an embodiment, when a still image is displayed in the first display area DA1 and a video is displayed in the second display area DA2, the first display area DA1 can be driven at a frequency lower than the default frequency, and the second display area DA2 can be driven at a frequency higher than or equal to the default frequency.

[0058] In this embodiment, the display area DA can be divided into three or more display areas. The operating frequency of each display area can be determined based on the type of image (still image or video) displayed in each display area.

[0059] In an embodiment, the single-frequency mode may include a normal mode and a still image mode. In normal mode, the electronic device ED may drive both the first display area DA1 and the second display area DA2 at a default frequency. In still image mode, the electronic device ED may drive both the first display area DA1 and the second display area DA2 at a still image frequency lower than the default frequency.

[0060] Figure 2 An image is shown displayed on an electronic device ED according to an embodiment of the present disclosure.

[0061] refer to Figure 2 In an embodiment, the display area DA of the electronic device ED includes a first display area DA1, a second display area DA2, and a third display area DA3.

[0062] In single-frequency mode, the electronic device ED can drive all first display areas DA1, second display area DA2 and third display area DA3 at the default frequency.

[0063] In a specific application, a first image IM1 can be displayed in a first display area DA1, a second image IM2 can be displayed in a second display area DA2, and a third image IM3 can be displayed in a third display area DA3. In an embodiment, the first image IM1 and the third image IM3 can be images with a fast change period (e.g., video), and the second image IM2 can be an image with a long change period (e.g., a still image such as a photograph or text information). In this case, embodiments of the electronic device ED can operate in a multi-frequency mode.

[0064] In multi-frequency mode, according to an embodiment, the electronic device ED can drive a first display area DA1 displaying a first image IM1 and a third display area DA3 displaying a third image IM3 at a first operating frequency, and can drive a second display area DA2 displaying a second image IM2 at a second operating frequency. In an embodiment, the first operating frequency may be higher than or equal to a default frequency. In an embodiment, the second operating frequency may be lower than the first operating frequency. The electronic device ED can reduce power consumption by lowering the operating frequency of the second display area DA2.

[0065] The size of each of the first display area DA1, the second display area DA2, and the third display area DA3 can be a preset size and can be changed by the application.

[0066] Figure 3A and Figure 3B This is a perspective view of the electronic device ED2 according to an embodiment of the present disclosure. Figure 3A The illustration shows the electronic device ED2 in its unfolded state. Figure 3B The illustration shows the electronic device ED2 in a folded state.

[0067] like Figure 3A and Figure 3B As shown, an embodiment of the electronic device ED2 includes a display area DA and a non-display area NDA. The electronic device ED2 can display images through the display area DA. In the unfolded state of the electronic device ED2, the display area DA may include a plane defined by a first direction DR1 and a second direction DR2. The thickness direction of the electronic device ED2 may be parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. Accordingly, the front (or upper) surface and rear (or lower) surface of the components constituting the electronic device ED2 may be defined based on the third direction DR3. The non-display area NDA may be referred to as a border area. In an embodiment, for example, the display area DA may have a rectangular shape when viewed in a plan view or on the third direction DR3. The non-display area NDA surrounds the display area DA.

[0068] The display area DA may include a first non-folded area NFA1, a folded area FA, and a second non-folded area NFA2. The folded area FA may be bent around a folding axis FX extending in the first direction DR1.

[0069] When the electronic device ED2 is folded, the first non-folded area NFA1 and the second non-folded area NFA2 can face each other. Accordingly, when fully folded, the display area DA may not be exposed to the outside, which can be referred to as "inward folding". However, the embodiment is not limited to this, and the operation of the electronic device ED2 is not limited to this.

[0070] In an embodiment of the invention, when the electronic device ED2 is folded, the first non-folded region NFA1 and the second non-folded region NFA2 can be opposite each other. Accordingly, when folded, the first non-folded region NFA1 can be exposed to the outside, which can be referred to as "outward folding".

[0071] Electronic device ED2 may perform only one operation selected from inward folding and outward folding. Alternatively, electronic device ED2 may perform both inward folding and outward folding. In this case, the same area of ​​electronic device ED2, such as the folding area FA, may fold inward and outward. Alternatively, some areas of electronic device ED2 may fold inward and other areas may fold outward.

[0072] Figure 3Aand Figure 3B The diagram illustrates one folded region and two non-folded regions, but the number of folded regions and non-folded regions is not limited thereto. In an embodiment, for example, electronic device ED2 may include multiple non-folded regions (more than two) and multiple folded regions, each of the folded regions being situated between adjacent non-folded regions.

[0073] Figure 3A and Figure 3B The illustration shows an embodiment in which the folding axis FX is parallel to the short axis of the electronic device ED2. However, this disclosure is not limited thereto. In another embodiment, for example, the folding axis FX may extend in a direction parallel to the long axis of the electronic device ED2 (e.g., a second direction DR2).

[0074] Figure 3A and Figure 3B The illustration shows an embodiment in which the first non-folded region NFA1, the folded region FA, and the second non-folded region NFA2 are arranged sequentially in the second direction DR2. However, this disclosure is not limited thereto. In another embodiment, for example, the first non-folded region NFA1, the folded region FA, and the second non-folded region NFA2 may be arranged sequentially in the first direction DR1.

[0075] Multiple display areas DA1 and DA2 can be defined within the display area DA of the electronic device ED2. As an example, Figure 3A The illustration shows an embodiment where only two display areas, DA1 and DA2, are defined within the display area DA. However, the number of display areas DA1 and DA2 is not limited to this.

[0076] Multiple display areas DA1 and DA2 may include a first display area DA1 and a second display area DA2. In an embodiment, for example, the first display area DA1 may be an area in which a first image IM1 is displayed, and the second display area DA2 may be an area in which a second image IM2 is displayed. In an embodiment, for example, the first image IM1 may be a video, and the second image IM2 may be a still image.

[0077] The electronic device ED2 according to the embodiment can operate differently depending on the operating mode. The operating modes of the electronic device ED2 may include a single-frequency mode and a multi-frequency mode. The single-frequency mode of the electronic device ED2 may include a normal mode and a still image mode.

[0078] In normal mode, electronic device ED2 can drive both the first display area DA1 and the second display area DA2 at a default frequency. In still image mode, electronic device ED2 can drive both the first display area DA1 and the second display area DA2 at a still image frequency lower than the default frequency. In multi-frequency mode, according to an embodiment, electronic device ED2 can drive the first display area DA1, in which a first image IM1 is displayed, at a first operating frequency, and can drive the second display area DA2, in which a second image IM2 is displayed, at a second operating frequency. In an embodiment, the first operating frequency can be higher than or equal to the default frequency. The second operating frequency can be lower than the first operating frequency.

[0079] The size of each of the first display area DA1 and the second display area DA2 can be a preset size and can be changed by the application. In an embodiment, the first display area DA1 can correspond to the first non-folding area NFA1, and the second display area DA2 can correspond to the second non-folding area NFA2. Furthermore, a first portion of the folding area FA can correspond to the first display area DA1, and a second portion of the folding area FA can correspond to the second display area DA2.

[0080] In an embodiment, the entire folded area FA may correspond to only one of the first display area DA1 and the second display area DA2.

[0081] In this embodiment, the first display area DA1 may correspond to a first portion of the first non-foldable area NFA1, and the second display area DA2 may correspond to a second portion of the first non-foldable area NFA1, the foldable area FA, and the second non-foldable area NFA2. That is, the size of the second display area DA2 may be larger than the size of the first display area DA1.

[0082] In this embodiment, the first display area DA1 may correspond to a first portion of the first non-foldable area NFA1, the foldable area FA, and the second non-foldable area NFA2, and the second display area DA2 may correspond to a second portion of the second non-foldable area NFA2. That is, the size of the first display area DA1 may be larger than the size of the second display area DA2.

[0083] like Figure 3B As illustrated in the figure, when the folded area FA is folded, the first display area DA1 can correspond to the first non-folded area NFA1, and the second display area DA2 can correspond to the folded area FA and the second non-folded area NFA2.

[0084] As an example of an electronic device Figure 3A and Figure 3BThe illustration shows an embodiment where electronic device ED2 includes only one folded region. However, this disclosure is not limited thereto. In another embodiment, for example, this disclosure can also be applied to electronic devices having two or more folded regions, rollable electronic devices, or slidable electronic devices.

[0085] Figure 4A This is a diagram used to describe the operation of an electronic device (ED) in normal mode.

[0086] Figure 4B This is a diagram used to describe the operation of an electronic device (ED) in still image mode.

[0087] Figure 4C This is a diagram used to describe the operation of an electronic device (ED) in multiple frequency modes.

[0088] refer to Figure 4A The first image IM1 displayed in the first display area DA1 can be a video. The second image IM2 displayed in the second display area DA2 can be a still image or an image with a long change period (e.g., a keyboard image used to manipulate a game). Figure 4A The image shows a first image IM1 displayed in a first display area DA1 and a second image IM2 displayed in a second display area DA2 as examples, and various images can be displayed on an electronic device ED.

[0089] In normal mode NM, the operating frequency of the first display area DA1 and the second display area DA2 of the electronic device ED is the default frequency. In an embodiment, for example, the default frequency may be 120 Hz. In normal mode NM, the images of the first to 120th frames F1 to F120 can be sequentially displayed for one second in the first display area DA1 and the second display area DA2 of the electronic device ED.

[0090] refer to Figure 4B In the still image mode STM, the first image IM1 displayed in the first display area DA1 and the second image IM2 displayed in the second display area DA2 can be still images.

[0091] In Still Image Mode (STM), the operating frequency of the first display area DA1 and the second display area DA2 of the electronic device ED can be a still image frequency lower than the default frequency. In an embodiment, for example, when the default frequency is 120Hz, the still image frequency can be 1Hz. In this case, data signals corresponding to the first image IM1 and the second image IM2 can be provided to the first display area DA1 and the second display area DA2 only during the first frame F1. That is, since no new data signals are provided to the first display area DA1 and the second display area DA2 during the second to 120th frames F2 to F120, the same first image IM1 and second image IM2 as those during the first frame F1 can be displayed on the electronic device ED during the second to 120th frames F2 to F120.

[0092] refer to Figure 4C In Multi-Frequency Mode (MFM), the electronic device ED can set the operating frequency of a first display area DA1, in which a first image IM1 (i.e., video) is displayed, to a first operating frequency, and can set the operating frequency of a second display area DA2, in which a second image IM2 (i.e., still image) is displayed, to a second operating frequency lower than the first operating frequency. The first operating frequency can be 120 Hz, and the second operating frequency can be 1 Hz. The first and second operating frequencies can be changed in various ways.

[0093] In Multi-Frequency Mode (MFM), when the first operating frequency is 120Hz and the second operating frequency is 1Hz, a data signal corresponding to the first image IM1 can be provided for one second in the first display area DA1 of the electronic device ED during the first to 120th frames F1 to F120. A data signal corresponding to the second image IM2 can be provided to the second display area DA2 only during the first frame F1. That is, since no new data signal is provided to the second display area DA2 during the second to 120th frames F2 to F120, the same second image IM2 as the second image IM2 during the first frame F1 can be displayed on the electronic device ED during the second to 120th frames F2 to F120.

[0094] Figure 4C The illustrated electronic device ED operates in multi-frequency mode (MFM), where the first operating frequency is 120 Hz and the second operating frequency is 1 Hz, but this disclosure is not limited thereto. The second operating frequency can be changed in various ways to a frequency lower than the first operating frequency, for example, 60 Hz, 30 Hz, or 10 Hz, etc.

[0095] Figure 5 This is a block diagram of an electronic device ED according to an embodiment of the present disclosure.

[0096] refer to Figure 5 An embodiment of the electronic device ED includes a processor AP, a drive circuit DDI, a display panel DP, and a voltage generator 300.

[0097] The processor AP can be one of an application processor, a graphics processor, a main processor, and a central processing unit (CPU). The drive circuit DDI includes a drive controller 100 and a data drive circuit 200. In embodiments, the drive controller 100 and the data drive circuit 200 may be implemented in a single chip (or on the same single chip), but this disclosure is not limited thereto.

[0098] The processor AP provides a transmission signal TS to the drive controller 100.

[0099] The drive controller 100 operates in response to a transmission signal TS from the processor AP. The drive controller 100 converts the image signal included in the transmission signal TS into an image data signal DS and outputs the image data signal DS. The drive controller 100 outputs a scan control signal SCS, a data control signal DCS, and a transmit control signal ECS in response to control signals included in the transmission signal TS.

[0100] In one embodiment, the drive controller 100 includes a memory 110. The drive controller 100 can store the image data signal DS in the memory 110.

[0101] The data drive circuit 200 receives the data control signal DCS and the image data signal DS from the drive controller 100. The data drive circuit 200 converts the image data signal DS into a data signal and then outputs the data signal to the multiple data lines DL1 to DLm, which will be described later.

[0102] Voltage generator 300 generates voltages for operating the display panel DP. In an embodiment, voltage generator 300 generates a first drive voltage ELVDD, a second drive voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2.

[0103] The display panel DP includes scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, emission control lines EML1 to EMLn, data lines DL1 to DLm and pixels PX. The display panel DP may further include a scan drive circuit SDC and an emission drive circuit EDC. In an embodiment, the scan drive circuit SDC is arranged on a first side of the display panel DP. The scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1 extend from the scan drive circuit SDC in a first direction DR1.

[0104] The transmit drive circuit EDC is arranged on the second side of the display panel DP. The transmit control lines EML1 to EMLn extend from the transmit drive circuit EDC in the opposite direction to the first direction DR1.

[0105] Scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1, as well as transmit control lines EML1 to EMLn, are arranged spaced apart from each other in the second direction DR2. Data lines DL1 to DLm extend from the data drive circuit 200 in the opposite direction to the second direction DR2 and are arranged spaced apart from each other in the first direction DR1. Here, n and m are natural numbers greater than 1.

[0106] In an embodiment, such as Figure 5 As shown, the scan drive circuit SDC and the emitter drive circuit EDC are arranged facing each other, with the pixel PX between them, but this disclosure is not limited thereto. In another embodiment, for example, the scan drive circuit SDC and the emitter drive circuit EDC may be arranged adjacent to each other in the non-display area NDA of the display panel DP. In embodiments, the scan drive circuit SDC and the emitter drive circuit EDC may be implemented using a single circuit or a single circuit.

[0107] Multiple pixels PX are electrically connected to scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1, emission control lines EML1 to EMLn, and data lines DL1 to DLm. Each of the multiple pixels PX can be electrically connected to four scan lines and one emission control line. In an embodiment, for example, as... Figure 5 As shown, the pixels in the first row can be connected to scan lines GIL1, GCL1, GWL1, and GWL2, as well as the emission control line EML1. The pixels in the i-th row can be connected to scan lines GILi, GCLi, GWLi, and GWLi+1, as well as the emission control line EML1. The pixels in the n-th row can be connected to scan lines GILn, GCLn, GWLn, and GWLn+1, as well as the emission control line EMLn.

[0108] Each of the multiple pixels PX includes a light-emitting element ED (see Figure 6 ) and the pixel circuit PXC used to control the emission of the light-emitting element ED (see Figure 6 The pixel circuit (PXC) may include one or more transistors and one or more capacitors. The scan drive circuit (SDC) and the emitter drive circuit (EDC) may include transistors formed using the same process as the pixel circuit (PXC).

[0109] Each of the multiple pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2 from the voltage generator 300.

[0110] The scan drive circuit SDC receives the scan control signal SCS from the drive controller 100. In response to the scan control signal SCS, the scan drive circuit SDC can output scan signals to scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1.

[0111] According to an embodiment, the drive controller 100 can determine the operating mode based on information included in the transmitted signal TS. In an embodiment, the drive controller 100 can determine the operating mode as one of a normal mode, a still image mode, and a multi-frequency mode based on the information included in the transmitted signal TS.

[0112] When the determined operating mode is still image mode, the drive controller 100 can perform self-refresh on the image displayed on the display panel DP by using the image data signal DS stored in the memory 110.

[0113] When the determined operating mode is multi-frequency mode, the drive controller 100 can divide the display panel DP into multiple display areas and drive the multiple display areas at different operating frequencies.

[0114] The detailed operation of the drive controller 100 will be described in detail later.

[0115] Figure 6 This is a circuit diagram of a pixel PX according to an embodiment of the present disclosure.

[0116] Figure 6 The diagram connects to Figure 5 The diagram illustrates the equivalent circuit diagram of pixel PX for the j-th data line DLj among data lines DL1 to DLm, the i-th scan lines GILi, GCLi, and GWLi among scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1, the (i+1)-th scan line GWLi+1, and the i-th emission control line EML1 to EMLn. Here, i is a natural number less than or equal to n, and j is a natural number less than or equal to m.

[0117] Figure 5 Each of the plurality of pixels PX shown can have the same as Figure 6 The pixel PX shown has the same circuit configuration.

[0118] refer to Figure 6According to an embodiment, a pixel PX includes a pixel circuit PXC and at least one light-emitting element ED. In an embodiment, the light-emitting element ED may be a light-emitting diode. In an embodiment, a pixel PX is described as including one light-emitting element ED. The pixel circuit PXC includes first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, and a capacitor Cst.

[0119] In an embodiment, using an oxide semiconductor as the semiconductor layer, the third transistor T3 and the fourth transistor T4 among the first to seventh transistors T1 to T7 are N-type transistors. Each of the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 is a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, this disclosure is not limited thereto. In an embodiment, for example, the first to seventh transistors T1 to T7 may all be P-type transistors or N-type transistors. In an embodiment, at least one of the first to seventh transistors T1 to T7 may be an N-type transistor, and the other transistors among the first to seventh transistors T1 to T7 may be P-type transistors. Furthermore, the circuit configuration of the pixel according to embodiments of this disclosure is not limited to... Figure 6 Examples of implementations. Figure 6 The configuration of the pixel circuit PXC shown in the figure can be modified and implemented.

[0120] Scan lines GILi, GCLi, GWLi, and GWLi+1 can transmit scan signals GIi, GCI, GWi, and GWi+1, respectively. Transmit control line EMLi can transmit transmit control signal EMi. Data line DLj can transmit data signal Dj. Data signal Dj can have input to electronic device ED (see...). Figure 5 ) image signal RGB (see Figure 7 The corresponding voltage levels. The first to fourth drive voltage lines VL1, VL2, VL3 and VL4 can respectively transmit the first drive voltage ELVDD, the second drive voltage ELVSS, the first initialization voltage VINT1 and the second initialization voltage VINT2.

[0121] The first transistor T1 includes a first electrode connected to the first drive voltage line VL1 via a fifth transistor T5, a second electrode electrically connected to the anode of the light-emitting element ED via a sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 can receive the data signal Dj transmitted via the data line DLj based on the switching operation of the second transistor T2, and can then supply a drive current Id to the light-emitting element ED.

[0122] The second transistor T2 includes a first electrode connected to the data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the scan line GWLi. The second transistor T2 can be turned on in response to the scan signal GWi transmitted through the scan line GWLi, and can transmit the data signal Dj transmitted through the data line DLj to the first electrode of the first transistor T1.

[0123] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the scan line GCLi. The third transistor T3 can be turned on in response to the scan signal GCI transmitted through the scan line GCLi, and therefore, the gate electrode and the second electrode of the first transistor T1 can be connected, that is, the first transistor T1 can be a diode.

[0124] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to a third drive voltage line VL3 through which the first initialization voltage VINT1 is transmitted, and a gate electrode connected to the scan line GILi. The fourth transistor T4 can be turned on in response to the scan signal GIi transmitted via the scan line GILi, causing the first initialization voltage VINT1 to be transmitted to the gate electrode of the first transistor T1. Accordingly, an initialization operation to initialize the voltage of the gate electrode of the first transistor T1 can be performed.

[0125] The fifth transistor T5 includes a first electrode connected to the first drive voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the emitter control line EMLi.

[0126] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting element ED, and a gate electrode connected to the emission control line EMLi.

[0127] The fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on in response to the transmit control signal EMi transmitted via the transmit control line EMi. In this way, the first drive voltage ELVDD can be compensated by the diode-connected first transistor T1 so that it can be supplied to the light-emitting element ED.

[0128] The seventh transistor T7 includes a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the fourth drive voltage line VL4, and a gate electrode connected to the scan line GWLi+1. The seventh transistor T7 is turned on in response to the scan signal GWi+1 transmitted through the scan line GWLi+1, and bypasses the current of the anode of the light-emitting element ED to the fourth drive voltage line VL4.

[0129] In the embodiment, as described above, one end of capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end of capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light-emitting element ED can be connected to the second driving voltage line VL2 to which the second driving voltage ELVSS is applied. The structure of the pixel PX according to the embodiment is not limited to... Figure 6 The structure is illustrated in the figure. In embodiments, for example, the number of transistors included in a pixel PX, the number of capacitors included in the pixel PX, and the connection relationship between the transistors and capacitors can be modified in various ways.

[0130] Figure 7 This is a block diagram showing the configuration of the processor AP and drive controller 100 of the electronic device ED.

[0131] refer to Figure 7 In this embodiment, the processor AP includes an image processor 10 and a transmitter 20. The image processor 10 determines the electronic device ED (see...). Figure 5 The transmitter 20 determines the operating mode and generates an image control signal IS corresponding to the operating mode. The transmitter 20 converts the image control signal IS into a transmission signal TS and outputs the transmission signal TS.

[0132] In this embodiment, the processor AP can output a transmission signal TS of a type suitable for the interface between the processor AP and the drive controller 100. In this embodiment, the interface between the processor AP and the drive controller 100 can be a Mobile Industrial Processor Interface (MIPI).

[0133] Receiver 120 receives the transmission signal TS provided by processor AP. Receiver 120 recovers the image signal RGB, control signal CTRL, multi-frequency mode signal MFD, and still image mode signal ST_M included in the transmission signal TS.

[0134] The controller 130 outputs image data signal DS, data control signal DCS, scan control signal SCS and transmit control signal ECS based on image signal RGB, control signal CTRL, multi-frequency mode signal MFD and still image mode signal ST_M.

[0135] When the still image mode signal ST_M is at the first level, the controller 130 can write the image data signal DS into the memory 110, or read the image data signal DS stored in the memory 110.

[0136] Figure 8A This is a diagram showing the image displayed on the display panel DP in normal mode.

[0137] Figure 8BThis is a diagram showing an image displayed on the display panel DP in multi-frequency mode.

[0138] Figure 9 and Figure 10 This is a diagram used to describe the operation of the processor AP and the drive controller 100 in normal mode and multi-frequency mode.

[0139] refer to Figure 7 , Figure 8A and Figure 9 The first planning signal TS_AP and the second planning signal DS_AP are signals used to predict the transmission signal TS and the image data signal DS when the image processor 10 in the processor AP determines the operating mode. The first planning signal TS_AP and the second planning signal DS_AP may be different from the actual transmission signal TS and the actual image data signal DS.

[0140] During the first frame F1, both the multi-frequency mode signal MFD and the still image mode signal ST_M are at a low level (i.e., inactive level), and the electronic device ED operates in normal mode. Figure 8A As illustrated, in normal mode, the full image F_IMG is displayed in the display area DA of the display panel DP. In normal mode, the transmission signal TS corresponds to the full image F_IMG. The image data signal DS output from the controller 130 corresponds to the full image F_IMG in the same manner as the transmission signal TS.

[0141] The control signal CTRL included in the transmission signal TS comprises a blank period BLK and an active period ACT. During the active period ACT, the controller 130 can control... Figure 5 The data driving circuit 200, the scan driving circuit SDC, and the transmit driving circuit EDC shown in the figure enable the image corresponding to the image data signal DS to be displayed on the display panel DP.

[0142] refer to Figure 7 , Figure 8B and Figure 9 During frames F2, F3, F4, F5, F6 and F7 from the second to the seventh, the multi-frequency mode signal MFD is at a high level (i.e., the active level) and the still image mode signal ST_M is at a low level, and the electronic device ED operates in multi-frequency mode.

[0143] When the still image mode signal ST_M is low (i.e., inactive), the memory 110 remains in the off state and does not operate in this state.

[0144] In multi-frequency mode, the full-image F_IMG is displayed in the display area DA of the display panel DP. For example... Figure 8BAs illustrated, in multi-frequency mode, the display area DA of the display panel DP can be divided into a first display area DA1, a second display area DA2, and a third display area DA3. Images ST1 and ST3 displayed in the first display area DA1 and the third display area DA3, respectively, are still images, while images 'A', 'B', 'C', 'D', 'E', and 'F' displayed in the second display area DA2 are video. During frames F2, F3, F4, F5, F6, and F7 from the second to the seventh frame, images 'A', 'B', 'C', 'D', 'E', and 'F' can be displayed sequentially in the second display area DA2. In this embodiment, it will be understood that images ST1 and ST3 displayed in the first display area DA1 and the third display area DA3, respectively, are related to... Figure 8A The portion of the full image F_IMG shown in the first frame F1 is the same as that illustrated in the figure.

[0145] Since the images ST1 and ST3, which correspond to the first display area DA1 and the third display area DA3 respectively, do not change in the multi-frequency mode, the processor AP can predict the first planning signal TS_AP and the second planning signal DS_AP to provide the drive controller 100 with signals corresponding to the images 'A', 'B', 'C', 'D', 'E' and 'F' that will be displayed in the second display area DA2 during the second to seventh frames F2, F3, F4, F5, F6 and F7.

[0146] During each of the second, third, and fourth frames F2, F3, and F4, the transmission signal TS and the image data signal DS can be the same as the first planning signal TS_AP and the second planning signal DS_AP, respectively.

[0147] The processor AP can include information about the starting position of each of the first display area DA1, the second display area DA2, and the third display area DA3 in the transmission signal TS, and can transmit that information.

[0148] Controller 130 can control the display of images 'A', 'B', and 'C' in the second display area DA2 during the second, third, and fourth frames F2, F3, and F4, respectively. Figure 5 The diagram shows the data driving circuit 200, the scan driving circuit SDC, and the transmit driving circuit EDC.

[0149] The pixel PX of the first display area DA1 and the third display area DA3 (see...) Figure 6 It can display an image corresponding to the data signal Dj stored in the capacitor Cst (i.e., the data signal Dj stored in the first frame F1).

[0150] When the operating frequency of the first display area DA1 or the third display area DA3 is 30Hz, the image data signal DS output from the first display area DA1 and the third display area DA3 can be refreshed every 1 / 30 second (i.e., 0.033 seconds). When the operating frequency of the second display area DA2 is 120Hz, the processor AP provides the drive controller 100 with a transmission signal TS corresponding to the full image F_IMGd of the display area DA in the fifth frame F5.

[0151] Images ST1 and ST3, displayed in the first display area DA1 and the third display area DA3 respectively, are still images, and therefore, images ST1 and ST3 in the full image F_IMGd during the fifth frame F5 are the same as those during the previous frames F1, F2, F3, and F4. Because image 'D' corresponding to the second display area DA2 is a new image, the full image F_IMGd includes images ST1, 'D', and ST3.

[0152] The processor AP can provide the drive controller 100 with signals corresponding to the images 'E' and 'F' that will be displayed in the second display area DA2, respectively, in the sixth frame F6 and the seventh frame F7 of the multi-frequency mode.

[0153] Controller 130 can control the display of images 'E' and 'F' in the second display area DA2 during the sixth frame F6 and the seventh frame F7, respectively. Figure 5 The diagram shows the data driving circuit 200, the scan driving circuit SDC, and the transmit driving circuit EDC.

[0154] Figure 10 The operation of the electronic device ED in frames F1, F2, and F3 of the first, second, and third frames shown in the figure is related to... Figure 9 The operations illustrated herein are the same, and therefore any repeated detailed descriptions will be omitted.

[0155] refer to Figure 7 , Figure 8B and Figure 10 When the operating frequency of the first display area DA1 or the third display area DA3 is 1Hz, the image data signal DS output from the first display area DA1 and the third display area DA3 can be refreshed every 1 second. When the operating frequency of the second display area DA2 is 120Hz, the processor AP provides the drive controller 100 with a transmission signal TS corresponding to the full image F_IMGd of the display area DA in frame 121 F121.

[0156] Images ST1 and ST3 displayed in the first display area DA1 and the third display area DA3, respectively, are still images, and therefore, images ST1 and ST3 in the full image F_IMGd during frame 121 F121 are the same as the images during the previous frames F1, F2, and F3. Because image 'D' corresponding to the second display area DA2 is a new image, the full image F_IMGd includes images ST1, 'D', and ST3.

[0157] When the operating frequency of each of the first display area DA1 and the third display area DA3 is low, due to leakage current, etc., the data stored in pixel PX (see...) Figure 6 The amount of charge in capacitor Cst in the display panel (DP) decreases, which may reduce the display quality of the image displayed on the display panel (DP).

[0158] In multi-frequency mode, when the operating frequency of each of the first display area DA1 and the third display area DA3 is lower than the reference frequency (e.g., 10Hz), when updating the images of the first display area DA1 and the third display area DA3, the processor AP can repeatedly and additionally update the images corresponding to 1 or 2 frames.

[0159] In other words, in order to update the images of the first display area DA1 and the third display area DA3 in the 122nd frame F122, which is consecutive to the 121st frame F121, the processor AP outputs a transmission signal TS corresponding to the full image F_IMGe. The full image F_IMGe includes images ST1, 'E', and ST3.

[0160] The processor AP can provide the drive controller 100 with a signal corresponding to the image 'F' that will be displayed in the second display area DA2 in frame 123 F123.

[0161] Controller 130 can control the image 'F' in frame 123 (F123) to be displayed in the second display area DA2. Figure 5 The diagram shows the data driving circuit 200, the scan driving circuit SDC, and the transmit driving circuit EDC.

[0162] Figure 11A , Figure 11B , Figure 11C , Figure 11D and Figure 11E This is a diagram showing an image displayed on the display panel DP in still image mode.

[0163] Figure 12 and Figure 13 This is a diagram used to describe the operation of the processor AP and the drive controller 100 in still image mode.

[0164] refer to Figure 12 During frame 0 (F0), both the multi-frequency mode signal MFD and the still image mode signal ST_M are at a low level, and the electronic device ED operates in normal mode. In normal mode, the processor AP provides the drive controller 100 with the transmission signal TS corresponding to the full image IMG1. During the activation period ACT of the control signal CTRL, the drive controller 100 can provide the data drive circuit 200 with the image data signal DS corresponding to the full image IMG1.

[0165] exist Figure 12 and Figure 13 In the memory, the memory status signal M_STATE indicates the operating state of memory 110. During frame 0, F0 (which is in normal mode), memory 110 remains in the OFF state, where it is not in operation.

[0166] refer to Figure 7 and Figure 12 When the multi-frequency mode signal MFD is at a low level and the still image mode signal ST_M is at a high level (i.e., the active level), the electronic device ED operates in still image mode starting from the first frame F1.

[0167] like Figure 11A As illustrated, in still image mode, the display area DA of the display panel DP can be divided into first, second, and third display areas DA1, DA2, and DA3. The full-image IMG2 displayed in display area DA includes images 'Q', 'R', and 'S'. Image 'S' includes images 'T' and 'U'. In this embodiment, images 'Q', 'R', and 'S' are displayed in the first, second, and third display areas DA1, DA2, and DA3, respectively. The full-image IMG2 displayed on the display panel DP in still image mode can include still images such as photographs or text information.

[0168] During the first frame F1, which serves as the start or initial frame of the still image mode, the processor AP provides the drive controller 100 with a transmission signal TS corresponding to the full image IMG2. The drive controller 100 may provide the data drive circuit 200 with an image data signal DS corresponding to the full image IMG2.

[0169] In the first frame F1, the controller 130 in the drive controller 100 writes the image data signal DS corresponding to the full image IMG2 in the first frame F1 (which is the start of the still image mode) into the memory 110. In this case, the memory status signal M_STATE indicates that the memory 110 is in the Write state.

[0170] During frames 2 to 600, from F2 to F600, it is maintained during its duration. Figure 11A As shown in the full-image IMG2, the processor AP does not send the transmission signal TS. In other words, when the full-image IMG2 of the previous frame is the same as the full-image IMG2 of the current frame, the processor AP does not send the transmission signal TS.

[0171] Because no transmission signal TS corresponding to a new image is received during frames F2 to F600 (from the second to the 600th frame), the drive controller 100 can remain in the blank period BLK during which neither the image data signal DS nor the control signal CTRL is output. The memory status signal M_STATE indicates that the memory 110 is in standby mode, where the memory 110 does not perform write or read operations. During frames F2 to F600 (from the second to the 600th frame), the transmission signal TS can remain at a high or low level.

[0172] like Figure 11B As illustrated, the processor AP provides a transmission signal TS corresponding to the new image 'V' to the drive controller 100, causing the new image 'V' to be displayed in the second display area DA2 in frame 601 F601. That is, in still image mode, when the current image corresponding to the second display area DA2 is different from the previous image corresponding to the second display area DA2, the processor AP outputs the transmission signal TS. The drive controller 100 can provide an image data signal DS corresponding to the image 'V' to the data drive circuit 200.

[0173] In frame 601 (F601), controller 130 in drive controller 100 writes the image data signal DS corresponding to image 'V' to memory 110. In this case, memory status signal M_STATE indicates that memory 110 is in write state. In this way, even in still image mode, only the image corresponding to a portion of the display panel DP can be updated to a new image. Furthermore, some updated images can be stored in memory 110.

[0174] The memory 110 can store the images 'Q' and 'S' of the full image IMG2 stored in the first frame F1, as well as the image data signal DS corresponding to the new image 'V'. That is, the image data signal DS corresponding to the full image IMG3 can be stored in the memory 110.

[0175] In an embodiment, such as Figure 11B and Figure 12As shown, the still images (i.e., images 'Q' and 'S') displayed in the first display area DA1 and the third display area DA3 remain unchanged during frames F2 to F600 from the second to the 600th frame. When the display time of the still image in still image mode reaches a predetermined time, the controller 130 may refresh the image displayed on the display panel DP. In an embodiment, for example, the controller 130 may refresh the image displayed on the display panel DP every 600 frames.

[0176] In one embodiment, the controller 130 can refresh the image data signal DS during the next frame after receiving a new image. For example... Figure 12 As shown, when the transmission signal TS corresponding to the new image 'V' is received in frame 601 F601, the full image IMG3 stored in memory 110 can be read in frame 602 F602, and then the image data signal DS can be refreshed. Frame 602 F602 can be a refresh frame. That is, in still image mode, after receiving the transmission signal TS corresponding to the new image 'V', the drive controller 100 sets the next frame as a refresh frame.

[0177] The timing or refresh period at which the controller 130 reads the full image IMG3 stored in the memory 110 and refreshes the image data signal DS can be changed in various ways.

[0178] like Figure 11C As illustrated, the processor AP provides the drive controller 100 with a transmission signal TS corresponding to the new image 'W', so that the new image 'W' is displayed in the second display area DA2 in frame 1201 F1201. The drive controller 100 can provide the data drive circuit 200 with an image data signal DS corresponding to the new image 'W'.

[0179] In frame 1201 (F1201), controller 130 in drive controller 100 writes the image data signal DS corresponding to the new image 'W' into memory 110. In this case, memory status signal M_STATE indicates that memory 110 is in write state.

[0180] The image data signal DS corresponding to the new image 'W' can be stored in the memory 110. That is, the image data signal DS corresponding to the full image IMG4 can be stored in the memory 110.

[0181] Figure 13 The 1201st frame F1201 shown in the figure is... Figure 12 The same as frame F1201 shown in the figure, and therefore any repeated detailed descriptions of it will be omitted.

[0182] During frames 1202 to 1800 (F1202 to F1800), it is maintained during that period. Figure 11C The full image IMG4 shown in the diagram does not send the transmission signal TS to the processor AP.

[0183] refer to Figure 7 , Figure 11D and Figure 13 In frame 1801 (F1801), the processor AP divides the display panel DP into first, second, third, fourth, and fifth display areas DA1, DA2, DA3, DA4, and DA5. The processor AP provides the drive controller 100 with transmission signals TS corresponding to the new images 'X' and 'Y', so that images 'X' and 'Y' are displayed in the second display area DA2 and the fourth display area DA4, respectively. The drive controller 100 can provide the data drive circuit 200 with image data signals DS corresponding to the new images 'X' and 'Y'.

[0184] In frame 1801 (F1801), controller 130 in drive controller 100 writes the image data signal DS corresponding to the new images 'X' and 'Y' into memory 110. In this case, the memory status signal M_STATE indicates that memory 110 is in write state. In this way, even in still image mode, only the image corresponding to a portion of the display panel DP can be updated to a new image. Furthermore, some updated images can be stored in memory 110.

[0185] The image data signal DS corresponding to the images 'Q', 'X', 'Y', and 'U' can be stored in the memory 110. That is, the image data signal DS corresponding to the full image IMG5 can be stored in the memory 110.

[0186] When it is determined that the still image mode lasts for a long time, the controller 130 can refresh the image displayed on the display panel DP.

[0187] In one embodiment, the controller 130 may refresh the image data signal DS during the next frame after receiving a new image. In another embodiment, for example, such as... Figure 13 As shown, when the transmission signal TS corresponding to the new images 'X' and 'Y' is received in frame 1801 F1801, the full image IMG5 stored in memory 110 can be read in frame 1802 F1802, and then the image data signal DS can be refreshed.

[0188] The timing or refresh cycle of the controller 130 reading the full image IMG5 stored in the memory 110 and refreshing the image data signal DS can be changed in various ways.

[0189] During frames 1803 to 2400, from F1803 to F2400, it was maintained during that period. Figure 11D The full image IMG5 shown in the diagram does not send the transmission signal TS to the processor AP.

[0190] refer to Figure 7 , Figure 11E and Figure 13 In frame 2401 (F2401), when the display time of the still image in still image mode reaches a predetermined time, the controller 130 reads the image data signal DS corresponding to the full image from the memory 110. In this case, the memory status signal M_STATE indicates that the memory 110 is in the Read state. When the processor AP sends the transmission signal TS corresponding to the new images 'Z' and 'P' while reading the image data signal DS corresponding to the full image from the memory 110, the controller 130 can stop reading the image data signal DS from the memory 110 and can provide the image data signal DS corresponding to the new images 'Z' and 'P' to the data drive circuit 200.

[0191] When the display time of the still image in still image mode reaches a predetermined time, the controller 130 in the drive controller 100 writes the image data signal DS corresponding to the new image 'Z' and 'P' into the memory 110. In this case, the memory status signal M_STATE indicates that the memory 110 is in the write state. In this way, even in still image mode, only the image corresponding to a portion of the display panel DP can be updated to a new image. Furthermore, some updated images can be stored in the memory 110.

[0192] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0193] The processor of an electronic device with this configuration can send transmission signals, including information (e.g., multi-frequency mode and still image mode) and image signals, to the drive circuit. The drive circuit of the electronic device can operate in multi-frequency mode and still image mode based on the information provided from the processor.

[0194] Electronic devices can minimize power consumption by reducing some or all of the operating frequencies of the display panel in multi-frequency mode and still image mode.

[0195] In still image mode, the driving circuit of the electronic device can store image data signals in the device's memory. The driving circuit can read the image data signals stored in memory when it determines that self-refresh is required in still image mode, and can output the image data signals to the data driving circuit.

[0196] In still image mode, the operating frequency of electronic devices can be reduced. By providing image data signals stored in memory to the display panel as needed, degradation of display quality can be effectively prevented.

[0197] While the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made herein without departing from the spirit or scope of the invention as defined in the claims.

Claims

1. An electronic device comprising: Display panel; Processor, output transmission signals; as well as The drive controller receives the transmission signal and outputs an image data signal based on the transmission signal in a manner that causes an image to be displayed on the display panel. The drive controller includes a memory for storing the image data signals. In still image mode, when the current image corresponding to a portion of the display panel differs from the previous image corresponding to that portion of the display panel, the processor outputs the transmission signal, and In the still image mode, when the display time of the still image corresponding to the portion of the display panel reaches a predetermined time, the drive controller allows the display panel to be refreshed by the image data signal read from the memory.

2. The electronic device according to claim 1, wherein, When the current image corresponding to the portion of the display panel is different from the previous image corresponding to the portion of the display panel, the processor outputs the transmission signal corresponding to the portion of the display panel, and The drive controller stores the image data signal corresponding to the portion of the display panel in the memory.

3. The electronic device according to claim 1, wherein, During the refresh frame of the still image mode, the drive controller reads the image data signal corresponding to the full image of the display panel from the memory and outputs the image data signal corresponding to the full image of the display panel.

4. The electronic device according to claim 3, wherein, In the still image mode, after receiving the transmission signal corresponding to the new image, the drive controller sets the next frame as the refresh frame.

5. The electronic device according to claim 1, wherein, When the still image mode is initiated, the processor outputs a transmission signal to the drive controller that corresponds to the full image of the display panel.

6. The electronic device according to claim 5, wherein, In the still image mode, when the full image of the current frame is the same as the full image of the previous frame, the processor does not output the transmission signal.

7. The electronic device according to claim 1, wherein, The transmission signal includes a still image mode signal indicating the still image mode, and The drive controller recovers the still image mode signal included in the transmitted signal.

8. The electronic device according to claim 7, wherein, The drive controller further includes: A receiver recovers an image signal, a multi-frequency mode signal, and a still image mode signal based on the transmitted signal, wherein the image signal, the multi-frequency mode signal, and the still image mode signal are included in the transmitted signal; and The controller converts the image signal into the image data signal, and Specifically, when the display time of the still image reaches the predetermined time and the still image mode signal is at the active level, the controller outputs the image data signal read from the memory.

9. The electronic device according to claim 8, wherein, When the multi-frequency mode signal is at the activation level, the controller outputs the image data signal corresponding to the transmission signal.

10. The electronic device according to claim 8, wherein, The memory remains in the off state when the multi-frequency mode signal is at the active level and the still image mode signal is at the inactive level.

11. The electronic device according to claim 1, wherein, In multi-frequency mode, when the display time of the still image corresponding to the portion of the display panel reaches the predetermined time, the processor outputs the transmission signal corresponding to the full image of the display panel to the drive controller, and the drive controller allows the display panel to be refreshed.

12. The electronic device according to claim 1, wherein, During the first frame of the still image mode, the processor outputs the transmission signal corresponding to the full image of the display panel to the drive controller, and In the first frame at the start of the still image mode, the drive controller stores the image data signal corresponding to the transmission signal in the memory.

13. An electronic device comprising: Display panel; Processor, output transmission signals; as well as The drive controller receives the transmission signal and outputs an image data signal based on the transmission signal in a manner that causes an image to be displayed on the display panel. The drive controller includes a memory for storing the image data signals. In still image mode, the processor divides the display panel into a first display area and a second display area, and outputs the transmission signal when the current image corresponding to the second display area is different from the previous image corresponding to the second display area. In the still image mode, when the display time of the still image corresponding to the first display area reaches a predetermined time, the drive controller allows the display panel to be refreshed by the image data signal read from the memory.

14. The electronic device according to claim 13, wherein, When the current image corresponding to the second display area of ​​the display panel is different from the previous image corresponding to the second display area of ​​the display panel, the processor outputs the transmission signal corresponding to the second display area of ​​the display panel, and The drive controller stores the image data signal corresponding to the second display area of ​​the display panel in the memory.

15. The electronic device according to claim 13, wherein, During the refresh frame of the still image mode, the drive controller reads the image data signal corresponding to the full image of the display panel from the memory.

16. The electronic device according to claim 15, wherein, In the still image mode, when the full image of the current frame is the same as the full image of the previous frame, the processor does not output the transmission signal.

17. A driving circuit, comprising: The drive controller receives transmission signals from the outside and outputs image data signals based on the transmission signals; as well as The data driving circuit converts the image data signal into a data signal. The drive controller includes a memory for storing the image data signals. In still image mode, when the display time of the still image reaches a predetermined time, the drive controller outputs the image data signal read from the memory to the data drive circuit.

18. The driving circuit according to claim 17, wherein, During the refresh frame of the still image mode, the drive controller reads the image data signal corresponding to the full image of the display panel from the memory and outputs the image data signal corresponding to the full image of the display panel to the data drive circuit.

19. The driving circuit according to claim 17, wherein, The drive controller further includes: A receiver recovers an image signal, a multi-frequency mode signal, and a still image mode signal based on the transmitted signal, wherein the image signal, the multi-frequency mode signal, and the still image mode signal are included in the transmitted signal; and The controller converts the image signal into the image data signal, and Specifically, when the display time of the still image reaches the predetermined time and the still image mode signal is at the active level, the controller outputs the image data signal read from the memory.

20. The driving circuit according to claim 19, wherein, The memory remains in the off state when the multi-frequency mode signal is at the active level and the still image mode signal is at the inactive level.

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