Display device

Abstract

The invention provides a display device which can restrain long-term reliability reduction. The display device includes: a transistor connected to a third node; a transistor having a gate electrode connected to the second node and connected between the third node and the fourth node; a transistor connected between the second node and the fourth node; a transistor connected between the initialization voltage line and the third node; the transistor is connected between the fourth node and the fifth node; a transistor connected between a reference voltage power line and the first node; a transistor connected between the reference voltage line and the third node; a transistor connected between the power line and the fifth node; a capacitor element connected between the first node and the second node; a capacitor element connected between the first node and the third node; and a light emitting element connected to the fifth node.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device. Background Technology

[0002] In recent years, display devices, including light-emitting elements, have become widespread in televisions, smartphones, and other devices. For example, a display device includes multiple pixels and control circuitry for driving these pixels. Each pixel includes multiple transistors, capacitors, and light-emitting elements. Light-emitting elements are self-emissive components, such as light-emitting diodes (LEDs), miniature LEDs, or organic electroluminescent (EL) elements. The control circuitry in the display device supplies voltage to each pixel, causing a current corresponding to the supplied voltage to flow in the light-emitting elements contained within each pixel. Each light-emitting element emits light with a brightness corresponding to the current flowing within it, and the pixels, including the light-emitting elements, can display images at a grayscale level corresponding to that brightness.

[0003] For example, Non-Patent Document 1 discloses an active matrix type organic light-emitting diode display device (AMOLED). The pixel in the display device described in Non-Patent Document 1 includes seven transistors (T1 to T7), two capacitor elements (CVdt, CVth) connected in series, and a light-emitting element (Pix.OLED). Furthermore, the driving method of the display device described in Non-Patent Document 1 includes supplying a driving voltage Vdd to the junction (N2) of the two capacitor elements through transistor T5 or T6, and independently performing a programming phase for image data acquisition (Vdt refresh) and threshold voltage detection (Vth detection).

[0004] Existing technical documents

[0005] Non-patent literature

[0006] Non-patent literature 1: Lujiang H, etal. , "Improvement OF the Low Temperature Poly-Silicon AMOLED Pixel Circuit with Independnt Threshould Voltage Detection", Society for Information Display Digest of Technical Papers, (USA), 2024, p. 41-44 Summary of the Invention

[0008] The technical problem that the invention aims to solve

[0009] For example, when a large voltage, such as a driving voltage, is applied to a capacitor, the load on the capacitor increases, which may compromise its long-term reliability. Furthermore, in recent years, display devices, including light-emitting elements, have been required to drive at higher speeds to handle high resolutions, large screens, or high frequencies. Consequently, increased power consumption is anticipated when display devices, including light-emitting elements, are required to handle high resolutions, large screens, or high frequencies, thus necessitating measures to suppress this increase.

[0010] In view of these issues, one objective of one embodiment of the present invention is to provide a display device capable of suppressing long-term reliability degradation. Another objective of one embodiment of the present invention is to provide a display device capable of achieving high-speed driving. Furthermore, one objective of one embodiment of the present invention is to provide a display device capable of suppressing increased power consumption.

[0011] Solutions for solving technical problems

[0012] In a display device according to one embodiment of the present invention, a plurality of pixels are arranged in a matrix in a first direction and a second direction intersecting the first direction. The display device includes: an image data signal line supplied with a data voltage, a second terminal of a second capacitor element, and a second terminal of a fourth transistor; an initialization voltage power supply line supplied with an initialization voltage; a reference voltage power supply line supplied with a reference voltage and a first terminal of the second capacitor element; a reference voltage line supplied with a reference voltage; and a power supply line supplied with a constant voltage, a first terminal of a first capacitor element, a first terminal of a fifth transistor, and a first terminal of a light-emitting element. Each of the plurality of pixels includes: a first transistor controlled by a first control signal and electrically connected between the image data signal line and the second terminal of the second capacitor element; a second transistor having a gate electrode electrically connected to the first terminal of the first capacitor element and electrically connected between the second terminal of the fourth transistor and the first terminal of the fifth transistor, which are electrically connected to the second terminal of the second capacitor element; and a third transistor controlled by a second control signal. The following components are connected in series: a first transistor, electrically connected between the first terminal of the first capacitor element and the first terminal of the fifth transistor; a fourth transistor, controlled by a third control signal, electrically connected between the initialization voltage power supply line and the first terminal of the second transistor; a fifth transistor, controlled by a fourth control signal, electrically connected between the second terminal of the second transistor and the first terminal of the light-emitting element; a sixth transistor, controlled by a fifth control signal, electrically connected between the reference voltage power supply line and the first terminal of the second capacitor element; a seventh transistor, controlled by a sixth control signal, electrically connected between the reference voltage line and the second terminal of the fourth transistor; an eighth transistor, controlled by the fifth control signal, electrically connected between the power supply line and the first terminal of the light-emitting element; a first capacitor element, electrically connected between the first terminal of the second capacitor element and the gate electrode; a second capacitor element, electrically connected between the second terminal of the first capacitor element and the second terminal of the first transistor; and a light-emitting element, electrically connected between the power supply line and the second terminal of the fifth transistor.

[0013] In a display device according to one embodiment of the present invention, a plurality of pixels are arranged in a matrix in a first direction and a second direction intersecting the first direction. The display device includes: an image data signal line supplied with a data voltage, a first terminal of a first capacitor element, and a second terminal of a fourth transistor; an initialization voltage power supply line supplied with an initialization voltage; a reference voltage power supply line supplied with a reference voltage and a second terminal of the first capacitor element; a reference voltage line supplied with a reference voltage; a power supply line supplied with a constant voltage, a second terminal of a second capacitor element, a first terminal of a fifth transistor, and a first terminal of a light-emitting element; and a reset voltage power supply line supplied with a reset voltage. Each of the plurality of pixels includes: a first transistor controlled by a first control signal and electrically connected between the image data signal line and the second terminal of the second capacitor element; a second transistor having a gate electrode electrically connected to the second terminal of the second capacitor element and electrically connected between the second terminal of the fourth transistor and the first terminal of the fifth transistor; and a third transistor controlled by a second control signal and electrically connected between the gate electrode and the fifth transistor. The following transistors are connected: a first terminal of the body transistor; a fourth transistor, controlled by a third control signal, electrically connected between the initialization voltage power supply line and the first terminal of the second transistor; a fifth transistor, controlled by a fourth control signal, electrically connected between the second terminal of the second transistor and the first terminal of the light-emitting element; a sixth transistor, controlled by a fifth control signal, electrically connected between the reference voltage power supply line and the second terminal of the first capacitor element; a seventh transistor, controlled by the fourth control signal, electrically connected between the reference voltage line and the second terminal of the fourth transistor; an eighth transistor, controlled by the fifth control signal, electrically connected between the power supply line and the first terminal of the light-emitting element; a ninth transistor, controlled by the second control signal, electrically connected between the reset voltage power supply line and the first terminal of the fifth transistor; a second capacitor element, electrically connected between the second terminal of the first capacitor element and the gate electrode; a first capacitor element, electrically connected between the first terminal of the second capacitor element and the second terminal of the fourth transistor; and a light-emitting element, electrically connected between the power supply line and the second terminal of the fifth transistor. Attached Figure Description

[0014] Figure 1 This is a schematic diagram illustrating the structure of a display device according to the first embodiment of the present invention.

[0015] Figure 2 This is a schematic diagram showing the input signal of the pixel circuit according to the first embodiment of the present invention.

[0016] Figure 3 This is a circuit diagram illustrating the structure of the pixel circuit according to the first embodiment of the present invention.

[0017] Figure 4 This is a timing diagram of a display device according to the first embodiment of the present invention.

[0018] Figure 5 This is a timing diagram of a display device according to the first embodiment of the present invention.

[0019] Figure 6 This is a timing diagram of a display device according to the first embodiment of the present invention.

[0020] Figure 7 This is a timing diagram of a display device according to the first embodiment of the present invention.

[0021] Figure 8 This is a timing diagram of a display device according to the first embodiment of the present invention.

[0022] Figure 9 This is a layout diagram of pixels according to the first embodiment of the present invention.

[0023] Figure 10 It shows along Figure 9 End view of the cut-off end face of A1-A2 in the layout shown.

[0024] Figure 11 It shows along Figure 9 End view of the cut-off end face of B1-B2 in the layout shown.

[0025] Figure 12 It shows along Figure 9 End face view of the C1-C2 cut-off end face in the layout shown.

[0026] Figure 13 This is a timing diagram illustrating a method for manufacturing a display device according to the first embodiment of the present invention.

[0027] Figure 14 This is a layout diagram of pixels according to the first embodiment of the present invention.

[0028] Figure 15 This is a layout diagram of pixels according to the first embodiment of the present invention.

[0029] Figure 16 This is a layout diagram of pixels according to the first embodiment of the present invention.

[0030] Figure 17 This is a graph showing the relationship between potential difference and capacitance value according to the first embodiment of the present invention.

[0031] Figure 18 This is a schematic diagram illustrating the structure of a display device according to a second embodiment of the present invention.

[0032] Figure 19 This is a block diagram illustrating the structure of the control circuit according to the second embodiment of the present invention.

[0033] Figure 20 This is a circuit diagram illustrating the circuit structure of the scan driver according to the second embodiment of the present invention.

[0034] Figure 21 This is a schematic diagram showing the input signal of the pixel circuit according to the second embodiment of the present invention.

[0035] Figure 22 This is a circuit diagram illustrating the structure of the pixel circuit according to the second embodiment of the present invention.

[0036] Figure 23 This is a timing diagram of a display device according to the second embodiment of the present invention.

[0037] Figure 24 This is a timing diagram of a display device according to the second embodiment of the present invention.

[0038] Figure 25 This is a timing diagram of the control circuit according to the second embodiment of the present invention.

[0039] Figure 26 This is a timing diagram of the control circuit according to the second embodiment of the present invention.

[0040] Figure 27 This is a timing diagram of the control circuit according to the second embodiment of the present invention.

[0041] Figure 28 This is a timing diagram of the pixel circuit according to the second embodiment of the present invention.

[0042] Figure 29 This is a schematic diagram illustrating the structure of a display device according to a third embodiment of the present invention.

[0043] Figure 30 This is a schematic diagram showing the input signal of the pixel circuit according to the third embodiment of the present invention.

[0044] Figure 31 This is a circuit diagram illustrating the structure of the pixel circuit according to the third embodiment of the present invention.

[0045] Figure 32 This is a timing diagram of the pixel circuit according to the third embodiment of the present invention.

[0046] Figure 33 This is a timing diagram of the pixel circuit according to the third embodiment of the present invention.

[0047] Figure 34 This is a timing diagram of the pixel circuit according to the third embodiment of the present invention.

[0048] Figure 35 This is a timing diagram of the pixel circuit according to the third embodiment of the present invention.

[0049] Figure 36 This is a schematic diagram showing the input signal of the pixel circuit according to the fourth embodiment of the present invention.

[0050] Figure 37 This is a circuit diagram illustrating the structure of the pixel circuit according to the fourth embodiment of the present invention.

[0051] Figure 38 This is a timing diagram of a display device according to the fourth embodiment of the present invention.

[0052] Figure 39 This is a timing diagram of the pixel circuit according to the fourth embodiment of the present invention.

[0053] Figure 40 This is a timing diagram of the pixel circuit according to the fourth embodiment of the present invention.

[0054] Figure 41 This is a timing diagram of the pixel circuit according to the fourth embodiment of the present invention. Detailed Implementation

[0055] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in the examples below. Furthermore, in order to make the explanation clearer, the drawings sometimes schematically represent the width, thickness, shape, structure, etc. of each part compared to the actual form; however, this is only an example and does not limit the interpretation of the present invention. In addition, the words "first" and "second" used to label each element are convenient identifiers used to distinguish each element and do not have further meaning unless specifically explained.

[0056] Furthermore, in this specification, unless otherwise expressly stated, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," or "α includes one selected from the group consisting of A, B, and C" do not preclude the possibility that α includes multiple combinations of A to C. Moreover, these expressions do not preclude the possibility that α includes other elements.

[0057] In the description of this invention, when expressions such as identical (equivalent) and consistent are used, identical and consistent may also include errors within the design scope.

[0058] For example, one embodiment of the present invention relates to a display device that uses an EL element as a self-emissive light-emitting element. For example, a display device using an EL element is sometimes referred to as a self-emissive display device, an EL display device, etc.

[0059] [1. First Implementation Method]

[0060] [1-1. Overview of display device 10]

[0061] Reference Figure 1 This section provides an overview of the display device 10 according to the first embodiment. Figure 1 This is a schematic diagram showing the structure of the display device 10. Figure 1 The structure of the display device 10 shown is an example, and the structure of the display device 10 is not limited to... Figure 1 The structure shown.

[0062] The display device 10 includes an array substrate 100, a flexible printed circuit board 200 (FPC 200), and an IC chip 110. In addition, the display device 10 includes a display area 22 disposed on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0063] In display area 22, a plurality of pixels 180 are arranged in a matrix along a first direction D1 (column direction) and a second direction D2 (row direction) intersecting the first direction D1. Pixel 180 is the smallest unit constituting a part of the image displayed in display area 22. The plurality of pixels 180 may, for example, correspond to sub-pixels R, G, and B respectively. Alternatively, three sub-pixels may form one pixel. The arrangement of the pixels 180 is not limited; for example, the arrangement of the plurality of pixels 180 may be a stripe arrangement. The arrangement in display device 10 may be a triangular arrangement, a PenTile arrangement, etc.

[0064] Subpixels R, G, and B are configured to display images of different colors. For example, subpixels R, G, and B each have a light-emitting element that includes a light-emitting layer emitting red, green, and blue light, respectively. The display device 10 can display an image by supplying arbitrary voltage or current to each of the three subpixels.

[0065] An IC chip 110 and two control circuits 120 are disposed in the peripheral area 24. The two control circuits 120 are located on the left and right sides of the display area 22. The IC chip 110 is connected to the terminal portion 150 via connecting wires 341. The two control circuits 120 are each connected to the IC chip 110 via connecting wires 342. The peripheral area 24 is sometimes referred to as the border area. Connecting wires 341 are sometimes referred to as connecting wires 341 individually, and bundles of multiple connecting wires 341 are sometimes referred to as connecting wires 341. Similarly, connecting wires 342 are sometimes referred to as connecting wires 342 individually, and bundles of multiple connecting wires 342 are sometimes referred to as connecting wires 342.

[0066] Terminal area 26 is provided with terminal portion 150 and FPC 200 electrically connected to terminal portion 150. Terminal area 26 is the area opposite to the area where display area 22 is provided in the first direction D1 relative to peripheral area 24.

[0067] The FPC 200 is connected to an external device (not shown) on the outside of the display device 10. The display device 10 is connected to the external device via the FPC 200 and the terminal portion 150 connected to the FPC. Control signals and voltages are sent from the external device to the display device 10 via the FPC 200 and the terminal portion 150 connected to the FPC. The display device 10 uses the received control signals and voltages from the external device to drive each pixel 180 disposed on the display device 10. As a result, the display device 10 is able to display an image in the display area 22.

[0068] IC chip 110 supplies signals and voltages that drive each pixel 180 to the two control circuits 120 and each pixel 180 (pixel circuit 181) via FPC 200, terminal 150 and connecting wiring 341.

[0069] The IC chip 110 and the two control circuits 120 can each be referred to as a control circuit individually, or a circuit group including part or all of the IC chip 110 and the two control circuits 120 can be referred to as a control circuit.

[0070] [1-2. Structure of IC chip 110]

[0071] Reference Figure 1 This section describes the overview of IC chip 110. IC chip 110 is located adjacent to display area 22 along the first direction D1. Image data signal lines 321, 322, and 323 extend from IC chip 110 along the first direction D1 and are connected to a plurality of pixels 180 arranged along the first direction D1.

[0072] For example, IC chip 110 includes multiple selection circuits (not shown). These selection circuits are switches controlled by on and off signals supplied to a selection signal. The selection circuits are selected according to the on signal supplied to the selection signal, supplying an image data signal SL(m) including a data signal VDATA to the image data signal line 321 and the pixel 180 electrically connected to the image data signal line 321. The selection signal and the image data signal SL(m) are transmitted from an external device to IC chip 110 via FPC 200 and terminal portion 150 connected to the FPC. For example, the data signal VDATA (image data signal SL(m)) includes a voltage VSIGL (see reference). Figure 5 ) and above and voltage VSIGH (refer to) Figure 5 The following are the voltage values. Voltage VSIGH is greater than voltage VSIGL. Voltage VSIGL is sometimes referred to as the first voltage, and voltage VSIGH is sometimes referred to as the second voltage.

[0073] For example, the on signal is a signal containing the voltage of the selection circuit (switch) that is turned on, and the off signal is a signal containing the voltage of the selection circuit (switch) that is turned off. In this invention, the on signal can be a high-level voltage (potential) (High, High, HI), and the off signal can be a low-level voltage (potential) (Low, Low, LO). The on signal can also be a low-level voltage (potential) (Low, Low, LO), and the off signal can also be a high-level voltage (potential) (High, High, HI). A high-level voltage is greater than a low-level voltage. Furthermore, in a display device according to one embodiment of this specification, as an example, the on signal is a high-level voltage, and the off signal is a low-level voltage.

[0074] [1-3. Structure of Control Circuit 120]

[0075] Reference Figure 1 This section describes the general outline of the control circuit 120. Two control circuits 120 are positioned adjacent to both sides of the display area 22 along the second direction D2. Scan signal lines 330, 331, 332, 333, and 334 extend from the control circuits 120 along the second direction D2 and connect to a plurality of pixels 180 arranged along the second direction D2. As an example, Figure 1The scan signal lines of the display device 10 shown are connected to both of the two control circuits 120. Each scan signal line can also be connected to one of the two control circuits 120. That is, the nth scan signal line can be electrically connected along the second direction D2 to the control circuit 120 on the right side of the display area 22, and the (n+1)th scan signal line can be electrically connected along the second direction D2 to the control circuit 120 on the left side of the display area 22. The value n is a positive integer.

[0076] The control circuit 120 includes a shift register circuit 130 and a scan driver circuit 160. For example, the control circuit 120 is a gate driver, and is input to control signals including a clock signal, a start pulse, multiple enable signals, etc., and a drive voltage VDDEL (see reference). Figure 2 ) and reference voltage VSSEL (refer to Figure 2 The control circuit 120 can select the scan lines sequentially by means of control signals and power inputs.

[0077] Shift register circuit 130 is electrically connected to scan driver circuit 160. Shift register circuit 130 includes multiple shift registers (not shown). Additionally, the aforementioned multiple control signals are supplied to shift register circuit 130 via multiple connection lines 342, via drive power line PVDD (see reference). Figure 2 The shift register circuit 130 is supplied with a drive voltage VDDEL via the reference voltage line PVSS (refer to...). Figure 2 The reference voltage VSSEL is supplied to the shift register circuit 130. The shift register circuit 130 has the following function: based on the above-mentioned multiple control signals, it generates multiple output signals (not shown) with different timing shifts, and outputs them to the scan driver circuit 160 in sequence.

[0078] The scan driver circuit 160 includes multiple scan drivers. For example, multiple output signals are supplied to the multiple scan drivers from the shift register circuit 130, and multiple enable signals are supplied to the multiple scan drivers from the IC chip 110 via multiple connection lines 342. A drive voltage VDDEL is supplied to the multiple scan drivers via the drive power line PVDD, and a reference voltage VSSEL is supplied to the multiple scan drivers via the reference voltage line PVSS. The multiple scan drivers have the following function: based on the multiple output signals and multiple enable signals, they sequentially supply scan signals with different timings (e.g., first scan signal SC1(n), second scan signal SC2(n), third scan signal SC3(n), fourth scan signal SC4(n), and fifth scan signal SC5(n)) to each scan signal line, and drive the pixels 180 (pixel circuit 181) electrically connected to each scan signal line. For example, the fourth scan signal SC4(n) and the scan signal line 333 to which the fourth scan signal SC4(n) is supplied are called scan signals and scan signal lines.

[0079] [1-4. Pixel 180 structure]

[0080] Reference Figures 1-3 This section provides an overview of pixel 180 and pixel circuit 181. Figure 2 This is a schematic diagram showing the input signal to the pixel circuit 181 included in pixel 180. Figure 3 This is a circuit diagram showing the structure of pixel circuit 181. As an example, Figure 2 as well as Figure 3 It shows Figure 1 The structure of pixel circuit 181 of pixel 180 is shown. The structure of pixel 180 and pixel circuit 181 is not limited to... Figures 1-3 The structure shown. Adjustments can be made as needed. Figure 1 Explain the same or similar structures.

[0081] Pixel circuit 181 is used to drive pixel 180. The pixel circuits for sub-pixels R, G, and B included in pixel 180 are the same as those for pixel circuit 181, but the light-emitting elements (OLEDs) emit different colors. In the following description, as an example, an OLED that emits red light will be described.

[0082] like Figure 2As shown, the pixel circuit 181 is supplied with image data signal SL(m), first scan signal SC1(n), second scan signal SC2(n), third scan signal SC3(n), fourth scan signal SC4(n), fifth scan signal SC5(n), reference voltage VREF, and initialization voltage VINI. Additionally, as power supplies for driving the pixel 180, the pixel circuit 181 is supplied with driving voltage VDDEL and reference voltage VSSEL. For example, the reference voltage VREF, initialization voltage VINI, driving voltage VDDEL, and reference voltage VSSEL can be constant voltages or variable voltages that vary according to the timing of each signal.

[0083] The first scan signal SC1(n) is supplied to scan signal line 330, the second scan signal SC2(n) is supplied to scan signal line 331, the third scan signal SC3(n) is supplied to scan signal line 332, the fourth scan signal SC4(n) is supplied to scan signal line 333, and the fifth scan signal SC5(n) is supplied to scan signal line 334. Furthermore, the first scan signal SC1(n) also functions as the seventh scan signal SC7(n) described later. The first scan signal SC1(n) is sometimes referred to as the second control signal, the second scan signal SC2(n) is sometimes referred to as the fourth control signal, the third scan signal SC3(n) is sometimes referred to as the fifth control signal, the fourth scan signal SC4(n) is sometimes referred to as the first control signal, and the fifth scan signal SC5(n) is sometimes referred to as the sixth control signal.

[0084] Additionally, the reference voltage VREF is supplied to the reference voltage power line SVR, the initialization voltage VINI is supplied to the initialization voltage power line SVI, the drive voltage VDDEL is supplied to the drive power line PVDD, and the reference voltage VSSEL is supplied to the reference voltage line PVSS. For example, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the reference voltage line PVSS are each electrically connected to different connection lines 342. Alternatively, for example, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the reference voltage line PVSS can also be different connection lines 342.

[0085] For example, the reference voltage VREF, initialization voltage VINI, drive voltage VDDEL, and reference voltage VSSEL are supplied from an external device to the IC chip 110 via FPC 200, terminal section 150, and connection wiring 341. Additionally, for example, the reference voltage VREF, initialization voltage VINI, drive voltage VDDEL, and reference voltage VSSEL are supplied from the IC chip 110 to a plurality of pixels 180 (pixel circuit 181) via connection wiring 342, precharge voltage power line SVP, reference voltage power line SVR, initialization voltage power line SVI, drive power line PVDD, and reference voltage line PVSS. Furthermore, although the illustration is omitted, the reference voltage VREF, initialization voltage VINI, drive voltage VDDEL, and reference voltage VSSEL can be connected from an external device via FPC200, terminal section 150, and connection wiring 341 without passing through IC chip 110 and connection wiring 342 to the reference voltage power line SVR, initialization voltage power line SVI, drive power line PVDD, and reference voltage line PVSS, and can also be supplied to multiple pixels 180 (pixel circuit 181). For example, the reference voltage VREF, initialization voltage VINI, and reference voltage VSSEL are less than the drive voltage VDDEL.

[0086] like Figure 3 As shown, the device includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a capacitor element CV, a capacitor element CD, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (source electrode and drain electrode) formed by a first electrode and a second electrode. Each of the capacitor elements CV, CD, and OLED has a pair of electrodes formed by a first electrode and a second electrode. Furthermore, the capacitor element CV is sometimes referred to as the first capacitor element, and the capacitor element CD is sometimes referred to as the second capacitor element.

[0087] For example, the first transistor T1 is a selection transistor. The first transistor T1 has the function of supplying the image data signal SL(m) to the sixth node N6. In addition, since the sixth node N6 of the pixel circuit 181 is connected to the third node N3, the first transistor T1 also has the function of supplying the image data signal SL(m) to the third node N3.

[0088] For example, the second transistor T2 is a driving transistor. Between the gate electrode 622 and the first electrode (source) 624 of the second transistor T2, a threshold voltage VTH is acquired based on the initialization voltage VINI. This acquired threshold voltage VTH is applied to the capacitor element CV, thereby performing the acquisition and storage of the threshold voltage VTH. Furthermore, the second transistor T2 controls the amount of current flowing from the driving power line PVDD to the light-emitting element OLED based on the gate voltage (the voltage between the gate electrode 622 and the first electrode (source) 624) after correcting for deviations in the threshold voltage VTH, and the input image data signal SL(m). That is, the second transistor T2 has the function of causing a current corresponding to the displayed grayscale (brightness) to flow to the light-emitting element OLED from the driving voltage VDDEL, thereby causing the OLED to emit light.

[0089] The third transistor T3 functions as follows: it turns on the second node N2 and the fourth node N4, making the potential difference between the gate electrode 622 and the second electrode 626 of the second transistor T2 0V. When the threshold voltage VTH is obtained, it transfers the decrease in drain potential (potential of node N4) caused by discharge to the gate (node ​​N2). When Vgs (the difference between the gate potential and the source potential) reaches the threshold voltage Vth, the discharge stops.

[0090] The fourth transistor T4 has the following function: it turns on the third node N3 and the initialization voltage power supply line SVI to supply the initialization voltage VINI to the third node N3 (sixth node N6), thereby initializing the third node N3 (sixth node N6).

[0091] The fifth transistor T5 has the following function: to turn on the fourth node N4 (the second electrode 626 of the second transistor T2) and the fifth node N5 (the first electrode 32 of the light-emitting element OLED).

[0092] The sixth transistor T6 has the following functions: turning on the first node N1 and the reference voltage power line SVR to supply the reference voltage power line SVR to the first node N1; fixing the potential of the first node N1 when acquiring the threshold voltage VTH and writing the image data signal SL(m).

[0093] The seventh transistor T7 has the following function: to turn on the third node N3 (sixth node N6) and the reference voltage line PVSS to supply the reference voltage VSSEL to the third node N3.

[0094] The eighth transistor T8 has the following functions: turning on the first electrode 32 and the second electrode 34 of the light-emitting element OLED so that the potential difference between the electrodes of the light-emitting element OLED is zero; suppressing the light emission of the light-emitting element OLED during periods other than the light emission period; and supplying the driving voltage VDDEL to the source and drain electrodes (i.e., node N4) of the second transistor T2 via the fifth transistor T5 during the initialization period before the acquisition of the threshold voltage VTH.

[0095] The capacitor element CV has the function of maintaining (storing) a charge equivalent to the threshold voltage VTH of the second transistor T2, as detailed below.

[0096] The capacitor element CD has the capacity to hold (store) the data voltage (VSIGL, reference) contained in the image data signal SL(m) supplied to the third node N3 (sixth node N6). Figure 39 ) and above and voltage VSIGH (refer to) Figure 39 The function of the charge at voltages below a certain level.

[0097] The OLED (Optical Display Cell) exhibits diode characteristics, emitting light based on the current flowing within it. The current flowing within the OLED is the drain current (Ion) of the second transistor T2. The first electrode 32 of the OLED is the cathode electrode, and the second electrode 34 is the anode electrode.

[0098] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scan signal line 333. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the third node N3 (sixth node N6), the first electrode 624 of the second transistor T2, the second electrode 646 of the fourth transistor T4, and the second electrode 54 of the capacitor element CD. A fourth scan signal SC4(n) is supplied to the scan signal line 333. The fourth scan signal SC4(n) is used to control the switching of the first transistor T1. In other words, the first transistor T1 is controlled by the fourth scan signal SC4(n) to be in a conducting state (on state) or a non-conducting state (off state). When the signal supplied to the fourth scan signal SC4(n) is LO, the first transistor T1 is in a non-conducting state. When the signal supplied to the fourth scan signal SC4(n) is HI, the first transistor T1 is in a conducting state.

[0099] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the second node N2, the first electrode 42 of the capacitor element CV, and the first electrode 634 of the third transistor T3. The second electrode 626 is electrically connected to the fourth node N4, the second electrode 636 of the third transistor T3, and the first electrode 654 of the fifth transistor T5. The threshold voltage of the second transistor T2 is a threshold voltage VTH. The second transistor T2 controls the amount of current flowing in the light-emitting element OLED based on the potential difference Vgs between the voltage supplied to the gate electrode 622 (second node N2) and the voltage supplied to the first electrode 624 (third node N3), and the potential difference Vds between the second electrode 626 (fourth node N4) and the first electrode 624. For example, when the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 is less than the threshold voltage VTH, the second transistor T2 becomes non-conducting, and no current flows in the light-emitting element OLED, therefore pixel 180 displays black. For example, when the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 is above the threshold voltage VTH, and the potential difference Vds between the voltage supplied to the fourth node N4 and the voltage supplied to the third node N3 is greater than 0V, the second transistor T2 becomes in the conducting state. Based on the grayscale value displayed according to the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3, the current flowing in the light-emitting element OLED is controlled, and the light-emitting element OLED emits light with a brightness based on the displayed grayscale value.

[0100] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The gate electrode 632 is electrically connected to the scan signal line 330. A first scan signal SC1(n) is supplied to the scan signal line 330. The first scan signal SC1(n) is used to control the switching of the third transistor T3. In other words, the third transistor T3 is controlled by the first scan signal SC1(n) to be in a conducting state (on state) or a non-conducting state (off state). When the signal supplied to the first scan signal SC1(n) is LO, the third transistor T3 becomes non-conducting; when the signal supplied to the first scan signal SC1(n) is HI, the third transistor T3 becomes conducting.

[0101] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the scan signal line 330. The first electrode 644 is electrically connected to the initialization voltage power supply line SVI. The switching of the fourth transistor T4 is controlled by the first scan signal SC1(n). In other words, the fourth transistor T4 is controlled by the first scan signal SC1(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the first scan signal SC1(n) is LO, the fourth transistor T4 is in a non-conducting state; when the signal supplied to the scan signal line 330 is HI, the fourth transistor T4 is in a conducting state.

[0102] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the scan signal line 331. The second electrode 656 is electrically connected to the first electrode 32 of the light-emitting element OLED and the first electrode 684 of the eighth transistor T8. A second scan signal SC2(n) is supplied to the scan signal line 331. The second scan signal SC2(n) is used to control the switching of the fifth transistor T5. In other words, the fifth transistor T5 is controlled by the second scan signal SC2(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the second scan signal SC2(n) is LO, the fifth transistor T5 is in a non-conducting state; when the signal supplied to the second scan signal SC2(n) is HI, the fifth transistor T5 is in a conducting state.

[0103] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the scan signal line 332. The first electrode 664 is electrically connected to the reference voltage power supply line SVR. The second electrode 666 is electrically connected to the first node N1, the second electrode 44 of the capacitor element CV, and the first electrode 52 of the capacitor element CD. A third scan signal SC3(n) is supplied to the scan signal line 332. The third scan signal SC3(n) is used to control the switching of the sixth transistor T6. In other words, the sixth transistor T6 is controlled by the third scan signal SC3(n) to be in a conducting state (on state) or a non-conducting state (off state). When the signal supplied to the third scan signal SC3(n) is LO, the sixth transistor T6 is in a non-conducting state; when the signal supplied to the third scan signal SC3(n) is HI, the sixth transistor T6 is in a conducting state.

[0104] The seventh transistor T7 includes a gate electrode 672, a first electrode 674, and a second electrode 676. The gate electrode 672 is electrically connected to the scan signal line 334. The first electrode 674 is electrically connected to the reference voltage line PVSS. The scan signal line 334 supplies the fifth scan signal SC5(n). The seventh transistor T7 uses the fifth scan signal SC5(n) to control its switching. In other words, the seventh transistor T7 is controlled by the fifth scan signal SC5(n) to be in an on state (conducting state) or a non-conducting state (off state). When the signal supplied to the fifth scan signal SC5(n) is LO, the seventh transistor T7 is in a non-conducting state; when the signal supplied to the fifth scan signal SC5(n) is HI, the seventh transistor T7 is in a conducting state.

[0105] The eighth transistor T8 includes a gate electrode 682, a first electrode 684, and a second electrode 686. The gate electrode 682 is electrically connected to the scan signal line 332 and the gate electrode 662 of the sixth transistor T6. The second electrode 686 is electrically connected to the second electrode 34 of the light-emitting element OLED and the driving power line PVDD. As described above, a third scan signal SC3(n) is supplied to the scan signal line 332. The eighth transistor T8 uses the third scan signal SC3(n) to control its switching. In other words, the eighth transistor T8 is controlled by the third scan signal SC3(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the third scan signal SC3(n) is LO, the eighth transistor T8 is in a non-conducting state; when the signal supplied to the third scan signal SC3(n) is HI, the eighth transistor T8 is in a conducting state.

[0106] The capacitor element CV has the function of maintaining (storing) a charge equivalent to the threshold voltage VTH of the second transistor T2, as detailed below.

[0107] The capacitor element CD holds (stores) the data voltage (VSIGL, reference) contained in the image data signal SL(m) supplied to the first node N1. Figure 5 ) and above and voltage VSIGH (refer to) Figure 5 The function of the charge at voltages below a certain level.

[0108] The first electrode 32 of the OLED light-emitting element is a cathode electrode, and the second electrode 34 of the OLED light-emitting element is an anode electrode.

[0109] For example, the ON state of a transistor in display device 10 refers to the state where the source and drain electrodes of the transistor are connected and the transistor is ON, while the OFF state of a transistor in display device 10 refers to the state where the source and drain electrodes of the transistor are not connected and the transistor is OFF. Furthermore, in each transistor, the source and drain electrodes may sometimes switch positions depending on the voltage or potential supplied to each electrode. Additionally, even when the transistor is in the OFF state, those skilled in the art can easily understand the possibility of a slight current flowing through it, such as leakage current.

[0110] Figure 3 The transistors shown are n-channel field-effect transistors, with the channel region containing group 14 elements such as silicon and germanium, or oxides exhibiting semiconductor properties. For example, crystalline silicon can be used as the channel region containing group 14 elements. The crystalline silicon can be low-temperature polycrystalline silicon (LTPS) or monocrystalline silicon. Furthermore, metal oxides exhibiting semiconductor properties can be used, for example, as oxides exhibiting semiconductor properties. As an example, an oxide semiconductor containing two or more metals including indium (In) can be used as the metal oxide exhibiting semiconductor properties. Besides indium, other metal oxides exhibiting semiconductor properties can include gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium oxide (Zr), and lanthanides. Furthermore, the metal oxide exhibiting semiconductor properties can be amorphous, crystalline, or a mixture of amorphous and crystalline phases.

[0111] For example, each transistor in the display device 10 is formed using a thin-film transistor (TFT). The channel region of each transistor can also be formed using single-crystal silicon, such as a silicon wafer or an SOI substrate. Furthermore, if the display device 10 includes both transistors with group 14 elements in their channel regions and transistors with oxides exhibiting semiconductor properties in their channel regions, the manufacturing method of the display device 10 includes: forming a semiconductor layer containing group 14 elements; and forming a semiconductor layer containing oxides exhibiting semiconductor properties (e.g., an oxide semiconductor layer). The display device 10 can be appropriately matched to the transistor structure, capacitor connections, power supply voltage, etc., according to its application and specifications.

[0112] For example, transistors with metal oxides possessing semiconductor properties have extremely low leakage current. Therefore, by using transistors with metal oxides possessing semiconductor properties, the charge equivalent to the voltage (potential) written to the capacitor element is difficult to dislodge from the capacitor element. As a result, by using transistors with metal oxides possessing semiconductor properties, the charge written to the capacitor element can be maintained for a long time. Furthermore, under the same gate-source voltage (the potential difference (Vgs) between the gate electrode and the source electrode) and source-drain voltage (e.g., the potential difference (Vds) between the source electrode and the drain electrode), the drain current of transistors with metal oxides possessing semiconductor properties is sometimes larger than that of transistors with crystalline silicon (e.g., low-temperature polycrystalline silicon (LTPS)). As a result, under the same drain current conditions, the gate-source voltage and the source-drain voltage of transistors with metal oxides possessing semiconductor properties can be smaller than those of transistors with crystalline silicon. Therefore, by using transistors with metal oxides possessing semiconductor properties, the power consumption of the display device 10 can be suppressed.

[0113] [1-5. Driving method of display device 10]

[0114] Reference Figures 4-8 This describes the driving method of the display device 10. Figures 4-8 This is a schematic diagram showing the timing of the display device 10. Adjustments can be made as needed. Figures 1-3 Explain the same or similar structures.

[0115] Furthermore, the horizontal axis of the timing diagram in each embodiment is time. Additionally, in the image data signal SL(m) containing the data signal VDATA in each embodiment, as an example, the data signal VDATA supplied to the selected pixel (pixel circuit) is represented by a diagonal line as a data voltage above VSIGL and below VSIGH, while the data signal VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit) is omitted and represented by a solid line. In fact, in the image data signal SL(m) containing the data signal VDATA in each embodiment, the voltage of the data signal VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit) is also supplied continuously or intermittently.

[0116] For example, the frequency driving the display device 10 is 60Hz, and one frame (1 FRAME) is driven at 60Hz. For example, in Figure 4 The image shows a portion of the current frame (KthFRAME), the previous frame (K-1stFRAME), and the next frame (K+1stFRAME). Additionally, Figures 5-8This shows the emission period PEM of the previous frame (K-1stFRAME), the period PIN, period PVH, period PWR, and period PEM of the current frame (KthFRAME), and the period PIN, period PVH, period PWR, and period PEM of the next frame. Additionally, Figures 5-8 A horizontal period (horizontal period HRP) is shown for a single pixel 180 (pixel circuit 181).

[0117] First, refer to Figure 4 This provides an overview of the driving method for the display device 10. (For example...) Figure 4 As shown, the driving method of the display device 10 includes at least an initialization period PIN (period PIN), a threshold voltage acquisition and holding period PVH (period PVH), and a write period PWR (period PWR) in one frame. In the pixels 180 (pixel circuits 181) included in the display device 10, the period PWR is executed after the period PVH. In addition, after the emission period PEM of the previous frame, the period PIN, period PVH, and period PWR of the current frame are executed, and after the emission period PEM of the current frame, the period PIN, period PVH, and period PWR of the next frame are executed.

[0118] The PIN period is the period for initializing the second node, the third node N3 (sixth node N6), and the fourth node N4. The PVH period is the period for acquiring the threshold voltage of the second transistor T2 by performing an operation that makes the potential difference Vgs of the second transistor T2 the same as the threshold voltage, and for maintaining a charge equivalent to the threshold voltage at the second node N2 (the first electrode 42 of the capacitor element CV). The PWR period is the period for writing the data signal VDATA to the pixel 180 (pixel circuit 181). That is, the PWR period is the period for supplying the data voltage to the sixth node N6 (the second electrode 54 of the capacitor element CD) and maintaining a charge equivalent to the data voltage. Furthermore, the PEM period is the period during which the pixel 180 emits light based on the written data voltage and the acquired threshold voltage (threshold voltage correction) of the second transistor T2.

[0119] Next, refer to Figures 4-8 This describes the specific driving method of the pixel 180 (pixel circuit 181) of the display device 10.

[0120] Pixel 180 (pixel circuit 181) is input with a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a fifth scan signal SC5(n), an image data signal SL(m) including a data signal VDATA, an initialization voltage VINI, and a reference voltage VREF. For example, pixel 180 (pixel circuit 181) is selected based on the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n). The image data signal SL(m), the initialization voltage VINI, and the reference voltage VREF are input to the selected pixel 180 (pixel circuit 181) according to the timing of each signal. The same operation is performed on all pixels 180 (pixel circuit 181), and an image corresponding to the current frame of 1 FRAME is displayed in the display area 22 of the display device 10 based on the image data signal SL(m) input to all pixels 180 (pixel circuit 181).

[0121] For example, Figures 4-8 The signals in each period of each frame of the timing diagram shown, as well as the voltages (potentials) supplied to each node, are shown in Table 1.

[0122]

[0123] For example, as shown in Table 1, when the voltage VSIGH is 4V, pixel 180 supplied with voltage VSIGH does not emit light and becomes black. Conversely, when the voltage VSIGL is 0V, pixel 180 supplied with voltage VSIGL emits light and displays white. For example, the threshold voltage VTH of the second transistor T2 is 1V, voltage VH (HI) is 8V, voltage VL (LO) is -5V, initialization voltage VINI is 3V, reference voltage VREF is 2V, drive voltage VDDEL is 6V, reference voltage VSSEL is -2V, voltage VM is 5V, and voltage VN is -5V. That is, the reference voltage VREF is different from the initialization voltage VINI; both the reference voltage VREF and the initialization voltage VINI are greater than the reference voltage VSSEL and less than the drive voltage VDDEL.

[0124] [1-5-1. First Example of a Driving Method for Display Device 10]

[0125] Reference Figure 5Table 1 illustrates a first example of a driving method for the display device 10. The driving method shown in the first example includes the following steps: pixel 180 (pixel circuit 181) displays a white image in the previous frame (K-1st FRAME) based on the voltage VSIGH of the data signal VDATA, and then pixel 180 (pixel circuit 181) displays a black image in Kth FRAME based on the voltage VSIGL of the data signal VDATA. In other words, the driving method shown in the first example includes the step of displaying images of different colors in consecutive frames.

[0126] Depending on the period, an image data signal SL(m) containing a data signal VDATA is input to each pixel 180 (pixel circuit 181). The data signal VDATA is analog data (analog voltage) containing a voltage above VSIGL and below VSIGH. For example, in period PWR, a voltage above VSIGL and below VSIGH is selected using a selection signal (not shown) and supplied to the image data signal SL(m). For example, in periods other than PWR, the data signal VDATA is supplied with voltages other than those supplied to the selected pixel 180 (pixel circuit 181).

[0127] The emission period PEM of K-1stFRAME is the period during which pixel 180 (pixel circuit 181) emits light according to the potential difference Vgs of the second transistor T2 ((voltage supplied to the second node N2 (voltage V(N2))) - (voltage supplied to the third node N3 (voltage V(N3)))). For example, pixel 180 (pixel circuit 181) emits red light, and white light is emitted by using three pixels: pixel 180 emitting red light, pixel 180 emitting blue light, and pixel 180 emitting green light.

[0128] For example, during the PEM of the K-1stFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181). The first scan signal SC1(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are supplied with LO, and the second scan signal SC2(n) and the fifth scan signal SC5(n) are supplied with HI. The first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are in the off state, and the fifth transistor T5 and the seventh transistor T7 are in the on state. In addition, for example, the voltage held by the third node N3 (sixth node N6) is voltage Vnd (-2), the voltage held by the second node N2 is voltage Vnq (2V), and the potential difference Vgs is 4V. Therefore, the second transistor T2 is in the on state, enabling the current Ion, based on the potential difference Vgs and Vds corresponding to the voltage VSIGH input to HRP during the K-1stFRAME level, to flow from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. As a result, the light-emitting element OLED emits light. Furthermore, the voltage held by the first node N1 becomes 0V through capacitive coupling based on the capacitor element CV and the capacitor element CD. For example, pixel 180 (pixel circuit 181) emits red light, and white light is emitted by using three pixels: pixel 180 emitting red light, pixel 180 emitting blue light, and pixel 180 emitting green light.

[0129] During the period following the emission period PEM of K-1stFRAME, between the emission period PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with a voltage equal to the voltage of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181). First, the fifth scan signal SC5(n) changes from being supplied with HI to being supplied with LO. When the fifth scan signal SC5(n) is supplied with LO, the third scan signal SC3(n) changes from being supplied with LO to being supplied with HI. When the third scan signal SC3(n) is supplied with HI, the first scan signal SC1(n) changes from being supplied with LO to being supplied with HI. The second scan signal SC2(n) is supplied with HI, and the fourth scan signal SC4(n) is supplied with LO.

[0130] As a result, during the period between the PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the seventh transistor T7 changes from the on state to the off state, and the current Ion no longer flows from the driving power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. The sixth transistor T6 and the eighth transistor T8 change from the off state to the on state, the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes 0V, the light-emitting element OLED stops emitting light, and the voltage supplied to the first node N1 rises from 0V to voltage Vnq (reference voltage VREF, 2V) to become voltage Vnq. The third transistor T3 changes from the off state to the on state, the fifth transistor T5 remains on state, the first transistor T1 remains off state, the second node N2 and the fourth node N4 are turned on, and voltage Vnr (driving voltage VDDEL, 6V) is supplied to the second node N2 (gate electrode 622 of the second transistor T2) and the fourth node N4 (second electrode 626 of the second transistor T2). Additionally, the fourth transistor T4 changes from the off state to the on state, supplying voltage Vnp (initialization voltage VINI, 3V) to the third node N3 (the first electrode 624 of the second transistor T2) and the sixth node N6 (the second electrode 616 of the first transistor T1). The potential difference Vgs is 3V (6V-3V), and the second transistor T2 is in the on state.

[0131] As described above, during the period PIN, the second node N2 and the fourth node N4 are initialized by the driving voltage VDDEL, the first node N1 is initialized by the reference voltage VREF, and the third node N3 (sixth node N6) is initialized by the initialization voltage VINI.

[0132] In the period PVH following the period PIN, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181). The state of supplying HI to the second scan signal SC2(n) changes to the state of supplying LO. Other scan signals are in the same state as the period PIN. The fifth transistor T5 changes from the on state to the off state, while the other transistors are in the same state as the period PIN.

[0133] As a result, during the PVH period, the first node N1 maintains voltage Vnq, and the third node N3 (sixth node N6) maintains voltage Vnp. The second transistor T2 is in the on state, with current Ion flowing through it. Meanwhile, the voltage supplied to the second node N2 and the fourth node N4 is gradually released (discharged) by the off state of the fifth transistor T5. When the potential difference Vgs between the voltage supplied to the second node N2 and the fourth node N4 and the voltage supplied to the third node N3 (sixth node N6) becomes the threshold voltage VTH, the second transistor T2 becomes off. At this time, the voltage supplied to the second node N2 and the fourth node N4 is voltage Vnl, for example, 4V. In reality, the threshold voltage VTH may deviate during manufacturing, such as 3.8V or 4.1V. The threshold voltage VTH is obtained through the operation during the PVH period and then corrected using the obtained threshold voltage VTH.

[0134] As described above, during the PVH period, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0135] During the period between period PVH and period PWR, or within period PWR, the image data signal SL(m) (data signal VDATA) is supplied with voltage VSIGH (4V). First, the first scan signal SC1(n) changes from being supplied with HI to being supplied with LO. When the first scan signal SC1(n) is supplied with LO, the fourth scan signal SC4(n) changes from being supplied with LO to being supplied with HI. The third scan signal SC3(n) is supplied with HI, and the second scan signal SC2(n) and the fifth scan signal SC5(n) are supplied with LO. The first transistor T1 changes from the off state to the on state, and the third transistor T3 and the fourth transistor T4 change from the on state to the off state. The other transistors are in the same state as during period PVH. The voltage supplied to the second node N2 is maintained by voltage Vnl (e.g., 4V), and the voltage supplied to the first node N1 is maintained by voltage Vnq (reference voltage VREF, 2V). The voltage supplied to the third node N3 (sixth node N6) gradually increases from voltage Vnp to voltage Vnl (voltage VSIGH, for example, 4V). At this time, the capacitor element CD maintains the potential difference (based on the sixth node N6, -2V) by maintaining a charge equivalent to the potential difference between Vnq supplied to the first node N1 (reference voltage VREF, 2V) and the voltage Vnl supplied to the third node N3 (sixth node N6) (voltage VSIGH, for example, 4V). That is, the potential difference Vgs is 0V.

[0136] As described above, during the PWR period, a data signal VDATA is written to pixel 180 (pixel circuit 181). Additionally, the capacitor element CD maintains the voltage contained in the data signal VDATA.

[0137] During the period following PWR, the fourth scan signal SC4(n) changes from being supplied with HI to being supplied with LO. When the fourth scan signal SC4(n) is supplied with LO, the third scan signal SC3(n) changes from being supplied with HI to being supplied with LO. When the third scan signal SC3(n) is supplied with LO, the fifth scan signal SC5(n) changes from being supplied with LO to being supplied with HI. The first transistor T1, the sixth transistor T6, and the eighth transistor T8 change from the on state to the off state, and the seventh transistor T7 changes from the off state to the on state. Other scan signals and other transistors are in the same state as during PWR. The voltage supplied to the second node N2 and the voltage supplied to the third node N3 (sixth node N6) decreases from voltage Vnl to voltage Vnd (-2V). That is, the potential difference Vgs remains at 0V. At this time, the voltage supplied to the first node N1, which is coupled through capacitor elements CV and CD, decreases from voltage Vnq to voltage Vnt (-4V).

[0138] During the light-emitting period PEM of KthFRAME following the period PWR of KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181). Additionally, the second scan signal SC2(n) changes from being supplied with LO to being supplied with HI. Consequently, the fifth transistor T5 changes from the off state to the on state. Other scan signals and other transistors are in the same state as during the period following the period PWR of KthFRAME. With the fifth transistor T5 on, the first electrode 32 of the light-emitting element OLED and the second electrode 626 (fourth node N4) of the second transistor T2 are connected. The potential difference Vgs is the sum of the potential difference held by capacitor CD and the potential difference held by capacitor CV, which is (initial voltage VINI (3V) - voltage of data signal VDATA (voltage VSIGH, 4V) + threshold voltage VTH (1V) = 0V). The data signal VDATA contains a voltage VSIGH. The potential difference Vgs of pixel 180 (pixel circuit 181) is 0V, the second transistor T2 is in the off state, and therefore the drain current Ion does not flow. Consequently, the OLED light-emitting element does not emit light. As a result, pixel 180 (pixel circuit 181) emitting red light becomes black. Similarly, pixels 180 emitting blue light and green light also do not emit light, thus a black color is achieved by using three pixels: red-emitting, blue-emitting, and green-emitting.

[0139] The display device 10 can independently control each node. Furthermore, the display device 10 includes a structure where the first node N1, second node N2, third node N3 (sixth node N6), capacitor element CV, and capacitor element CD are not directly connected to the light-emitting element OLED. Additionally, the voltage supplied to the first node N1, second node N2, third node N3 (sixth node N6), capacitor element CV, and capacitor element CD is a constant voltage such as a driving voltage VDDEL, an initialization voltage VINI, a reference voltage VREF, or a data signal VDATA. Therefore, for example, no charge redistribution occurs between the first node N1, second node N2, and third node N3 (sixth node N6), capacitor element CD, capacitor element CV, and the parasitic capacitance attached to the light-emitting element OLED. As a result, the display device 10 can suppress voltage fluctuations in the first node N1, second node N2, and third node N3 (sixth node N6) caused by charge redistribution. Furthermore, the acquisition of the threshold voltage VTH in the PVH is performed using the initialization voltage VINI supplied to the third node N3 as a reference voltage. As a result, the display device 10 can acquire the threshold voltage VTH with minimal impact from potential fluctuations caused by the driving voltage VDDEL. Therefore, the display device 10 can suppress the decrease in holding potential caused by charge redistribution, enabling high-speed and high-precision acquisition of the threshold voltage. Consequently, the display device 10 can accurately store and retain the data signal VDATA voltage (potential difference) after the threshold voltage has been corrected and supply it as the potential difference Vgs of the second transistor T2, achieving high brightness and high-quality display.

[0140] Furthermore, in the display device 10, the reference voltage VREF is different from the initialization voltage VINI. The reference voltage VREF is the voltage between voltage VSIGH and voltage VSIGL (intermediate voltage, intermediate potential). As a result, the potential difference between the voltage supplied to the first electrode 52 of the capacitor element CD and the voltage supplied to the second electrode 54 is the same as the potential difference between the voltage supplied to the first electrode 42 of the capacitor element CV and the voltage supplied to the second electrode 44. Therefore, it is possible to suppress the situation where the potential difference of the capacitor element CD of the display device 10 deviates significantly from the potential difference of the capacitor element CV. In other words, the display device 10 disperses the voltage applied to the capacitor element CD and the capacitor element CV, which can reduce the load applied to the capacitor element CD and the capacitor element CV and suppress the decrease in the withstand voltage of the capacitor element CD and the capacitor element CV. In addition, since the display device 10 can suppress the decrease in the withstand voltage of the capacitor element CD and the capacitor element CV, the insulating film used to form the capacitor element CD and the capacitor element CV can be made thinner. Therefore, in the display device 10, the area required for capacitor element CD and capacitor element CV can be reduced, so that the capacitance value can be adequately ensured even when the area of ​​the pixel is small.

[0141] [1-5-2. A second example of a driving method for the display device 10]

[0142] Reference Figure 6 This section describes a second example of a driving method for pixel circuit 181. The driving method shown in the second example includes the following steps: pixel 180 (pixel circuit 181) displays a white image in the previous frame (K-1st FRAME) based on the voltage VSIGH contained in the data signal VDATA, and subsequently, pixel 180 (pixel circuit 181) also displays a white image in Kth FRAME based on the voltage VSIGH contained in the data signal VDATA. In other words, the driving method shown in the second example includes the step of displaying images of the same color (white) in consecutive frames. Further details can be added as needed. Figures 1-5 Explain the same or similar structures.

[0143] The voltages (potentials) of each node during the light-emitting period PEM of K-1thFRAME to the period PVH of K-1thFRAME, and during the period between the period PVH of K-1thFRAME and the period PWR of K-1thFRAME, are the same as the structure described in "1-5-1. First Example of Driving Method of Display Device 10". Furthermore, the structure of each scan signal and the operation of each transistor during each period are the same as the structure described in "First Example of Driving Method of Display Device 10". Therefore, the same structure as described in "First Example of Driving Method of Display Device 10" will be described as needed. In addition, the image data signal SL(m) is supplied with a data signal VDATA containing VSIGL (0V) corresponding to white during the period PWR of K-1thFRAME, and is supplied with the same data signal VDATA as the structure described in "1-5-1. First Example of Driving Method of Display Device 10" during periods other than the period PWR of K-1thFRAME.

[0144] During the light emission period PEM of K-1stFRAME, similar to the structure described in "1-5-1. First Example of Driving Method of Display Device 10", pixel 180 (pixel circuit 181) emits red light, and white light is emitted by using three pixels: pixel 180 that emits red light, pixel 180 that emits blue light, and pixel 180 that emits green light.

[0145] In the period PIN of KthFRAME, similar to the structure described in "1-5-1. First example of driving method of display device 10", the second node N2 and the fourth node N4 are initialized by driving voltage VDDEL, the first node N1 is initialized by reference voltage VREF, and the third node N3 (sixth node N6) is initialized by initialization voltage VINI.

[0146] In the period PVH following the period PIN, similar to the structure described in "1-5-1. First Example of Driving Method of Display Device 10", the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0147] During the period between period PVH and period PWR, or within period PWR, the image data signal SL(m) (data signal VDATA) is supplied with a voltage VSIGL (0V). The voltage supplied to the second node N2 is maintained by a voltage Vnl (e.g., 4V), and the voltage supplied to the first node N1 is maintained by a voltage Vnq (reference voltage VREF, 2V). The voltage supplied to the third node N3 (sixth node N6) gradually decreases from voltage Vnp (initial voltage VINI, 3V) to 0V (voltage VSIGL). At this time, the capacitor element CD maintains the potential difference (reference voltage N6, 2V) by maintaining a charge equivalent to the potential difference between the voltage Vnq supplied to the first node N1 (reference voltage VREF, 2V) and the 0V (voltage VSIGL) supplied to the third node N3 (sixth node N6). Furthermore, capacitor CV maintains the potential difference (referenced to first node N1, 2V) by holding a charge equivalent to the potential difference between the voltage Vnl (e.g., 4V) supplied to the second node N2 and the voltage Vnq (reference voltage VREF, 2V) supplied to the first node N1. That is, the potential difference Vgs is 4V obtained by combining the potential difference maintained by capacitor CD and capacitor CV. For example, if the threshold voltage VTH deviates and the voltage Vnl supplied to the second node N2 becomes 3.9V, the potential difference Vgs becomes 3.9V (Vgs = (Vnl (3.9V) - VREF (2V)) + (VREF (2V) - VSIL (0V))).

[0148] As described above, during the PWR period, a data signal VDATA is written to pixel 180 (pixel circuit 181). Additionally, the capacitor element CD maintains the voltage contained in the data signal VDATA.

[0149] During the period following PWR, by supplying HI to the fifth scan signal SC5(n), the seventh transistor T7 changes from the off state to the on state. Since the third node N3 (sixth node N6) is connected to the reference voltage VSSEL, the voltage supplied to the third node N3 (sixth node N6) drops from 0V to Vnd (-2V). Simultaneously, the voltage of the second node N2, which is capacitively coupled through capacitors CV and CD, drops from Vnl to Vnq (2V). That is, the potential difference Vgs remains at 4V. At this time, the voltage supplied to the first node N1, which is capacitively coupled through capacitors CV and CD, drops from Vnq to 0V.

[0150] During the light emission period PEM of KthFRAME following the period PWR of KthFRAME, the potential difference Vgs becomes the sum of the potential difference held by capacitor element CD and the potential difference held by capacitor element CV (reference voltage VREF (2V) - voltage contained in data signal VDATA (voltage VSIGL, 0V) + (initialization voltage VINI (3V) + threshold voltage VTH (1V) - reference voltage VREF (2V) = 4V). That is, based on data signal VDATA and the corrected threshold voltage, pixel 180 (pixel circuit 181) It can display images. When the data signal VDATA includes the voltage VSIGL, the potential difference Vgs is 4V, the second transistor T2 is in the on state, so the current Ion flows from the driving power line PVDD to the light-emitting element OLED and the reference voltage line PVSS, and the light-emitting element OLED emits light. For example, pixels 180 that emit red light, pixels 180 that emit blue light, and pixels 180 that emit green light emit light respectively, and white is formed by using the three pixels that emit red light, blue light, and green light.

[0151] The second example of the driving method for the display device 10 has the same effect as that described in "1-5-1. The first example of the driving method for the display device 10".

[0152] [1-5-3. A third example of a driving method for display device 10]

[0153] Reference Figure 7This describes a third example of the driving method for the display device 10. The driving method shown in the third example includes the following steps: pixel 180 (pixel circuit 181) displays a black image in the previous frame (K-1st FRAME) based on the voltage VSIGL contained in the data signal VDATA, and then pixel 180 (pixel circuit 181) also displays a black image in Kth FRAME based on the voltage VSIGH contained in the data signal VDATA. In other words, the driving method shown in the third example includes the step of displaying images of the same color (black) in consecutive frames. The method can be modified as needed. Figures 1-6 Explain the same or similar structures.

[0154] The voltages (potentials) of each node in the PEM during the light-emitting periods of KthFRAME (PVH) to KthFRAM (PEM) are the same as those described in "1-5-1. First Example of the Driving Method of Display Device 10". Furthermore, the structures of each scan signal in each period and the operation of each transistor are the same as those described in "1-5-1. First Example of the Driving Method of Display Device 10". Therefore, the same structures as those described in "1-5-1. First Example of the Driving Method of Display Device 10" will be described as needed.

[0155] During the light emission period of the K-1stFRAME in the PEM, for example, the voltage maintained by the first node N1 is Vnt (-4V). Additionally, the voltage supplied to the second node N2 and the voltage maintained by the third node N3 are Vnd (-2V), and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, the drain current Ion does not flow, and the OLED does not emit light.

[0156] As a result, pixel 180 (pixel circuit 181) that emits red light becomes black. In addition, similar to pixel 180 that emits red light, pixel 180 that emits blue light and pixel 180 that emits green light also do not emit light. Therefore, black is formed by using three pixels: pixel 180 that emits red light, pixel 180 that emits blue light, and pixel 180 that emits green light.

[0157] During the period following the light-emitting period PEM of K-1stFRAME, between the light-emitting period PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the sixth transistor T6 and the eighth transistor T8 change from the off state to the on state. The potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes 0V, and the light-emitting element OLED stops emitting light. The voltage supplied to the first node N1 rises from voltage Vnt (-4V) to voltage Vnq (reference voltage VREF, 2V) to become voltage Vnq. The third transistor T3 changes from the off state to the on state, the fifth transistor T5 remains on state, the first transistor T1 remains off state, the second node N2 and the fourth node N4 are turned on, and voltage Vnr (driving voltage VDDEL, 6V) is supplied to the second node N2 (gate electrode 622 of the second transistor T2) and the fourth node N4 (second electrode 626 of the second transistor T2). Additionally, the fourth transistor T4 changes from the off state to the on state, supplying voltage Vnp (initialization voltage VINI, 3V) to the third node N3 (the first electrode 624 of the second transistor T2) and the sixth node N6 (the second electrode 616 of the first transistor T1). The potential difference Vgs is 3V (6V-3V), and the second transistor T2 is in the on state.

[0158] As described above, similar to the structure explained in "1-5-1. First Example of Driving Method of Display Device 10", in the period PIN, the second node N2 and the fourth node N4 are initialized by the driving voltage VDDEL, the first node N1 is initialized by the reference voltage VREF, and the third node N3 (sixth node N6) is initialized by the initialization voltage VINI.

[0159] In the period PVH following the period PIN, similar to the structure described in "1-5-1. First Example of Driving Method of Display Device 10", the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0160] During the period PWR following the period PVH, a data signal VDATA is written to the pixel 180 (pixel circuit 181) in the same manner as described in "1-5-1. First Example of Driving Method for Display Device 10". Additionally, the capacitor element CD maintains the voltage contained in the data signal VDATA.

[0161] During the light-emitting period PEM of the KthFRAME following the PWR period and the period after the PWR period, the pixel circuit 181 operates in the same manner as the structure described in "1-5-1. First Example of Driving Method of Display Device 10". The potential difference Vgs is 0V, the second transistor T2 is in the off state, so the drain current Ion does not flow, and the light-emitting element OLED does not emit light. As a result, black is formed by using three pixels: a pixel 180 that emits red light, a pixel 180 that emits blue light, and a pixel 180 that emits green light.

[0162] The third example of the driving method of the display device 10 has the same effect as that described in "1-5-1. The first example of the driving method of the display device 10".

[0163] [1-5-4. Fourth example of a driving method for display device 10]

[0164] Reference Figure 8 This describes a fourth example of a driving method for the display device 10. The driving method shown in the fourth example includes the following steps: pixel 180 (pixel circuit 181) displays a black image in the previous frame (K-1st FRAME) based on the voltage VSIGL of the data signal VDATA, and then pixel 180 (pixel circuit 181) displays a white image in Kth FRAME based on the voltage VSIGH of the data signal VDATA. In other words, the driving method shown in the fourth example includes the step of displaying images of different colors in consecutive frames. The method can be modified as needed. Figures 1-7 Explain the same or similar structures.

[0165] The voltages (potentials) of each node in the light-emitting period PEM of K-1stFRAME to the light-emitting period PVH of KthFRAME, the structure of each scan signal, and the operation of each transistor are the same as those described in "1-5-3. Third Example of the Driving Method of Display Device 10". Furthermore, the voltages (potentials) of each node in the light-emitting period PEM of KthFRAME (later than the KthFRAME's PVH), the structure of each scan signal, and the operation of each transistor are the same as those described in "1-5-2. Second Example of the Driving Method of Display Device 10". Therefore, their description is omitted here.

[0166] The fourth example of the driving method for the display device 10 has the same effect as that described in "1-5-1. The first example of the driving method for the display device 10".

[0167] [1-6. End face structure of pixel 180]

[0168] Reference Figures 9-12 This describes the end face structure of pixel 180. Figure 9 It is a layout diagram with a resolution of 180 pixels. Figure 10 It shows along Figure 9 End view of the cut-off end face of A1-A2 in the layout shown. Figure 11 It shows along Figure 9 End view of the cut-off end face of B1-B2 in the layout shown. Figure 12 It shows along Figure 9 End face view of the C1-C2 cut-off end face in the layout shown. Figure 9 The layout of the 180 pixels shown and Figures 10-12 The end face of pixel 180 shown is an example; the planar layout and end face of pixel 180 are not limited to... Figures 9-12 The example shown. Adjustments can be made as needed. Figures 1-8 Explain the same or similar structures.

[0169] also, Figure 11 as well as Figure 12 The end face of the pixel 180 shown omits the structure of the layer above the insulating layer 141 (the side opposite to the substrate 101) along the D3 direction.

[0170] Additionally, as an example of the end face with pixel 180, Figure 10 The end face of pixel 180 shown is along the functional layer 148, the second wiring 140C, the contact hole opening 147 for the cathode electrode, the second contact hole opening 138H, the first wiring 132K, the first contact hole opening 135J, and the semiconductor layer 122D. As an example of the end face of pixel 180, Figure 11 The end face of pixel 180 shown is the end face along the first wiring 132G, the first contact hole opening 135H, the semiconductor layer 122A, the second wiring 140A, the organic insulating film opening 138A for the capacitor element CS, the gate wiring 127A, and the first wiring 132E. As an example of the end face of pixel 180, Figure 12 The end face of the pixel 180 shown is the end face along the first wiring 132E, the first contact hole opening 135C, the gate wiring 127A, the first contact hole opening 135B, the semiconductor layer 122C, the gate wiring 127B, the second wiring 140B, the first wiring 132F, and the first contact hole opening 135A.

[0171] The substrate 101 includes a first surface 101A and a second surface 101B opposite to the first surface 101A. A semiconductor layer 122 is disposed on the first surface 101A of the substrate 101, separated by a base layer 121. The semiconductor layer 122 includes a semiconductor layer 122A, which includes a channel region 123 (see reference). Figure 14) and impurity region 124A (refer to Figure 14 Additionally, semiconductor layer 122 includes semiconductor layer 122D and semiconductor layer 122C. For example, the impurity region is referred to as the source region or drain region. Furthermore, for example, the second transistor T2 includes semiconductor layer 122A, and the first electrode 624 and the second electrode 626 include impurity region 124A. In other words, semiconductor layer 122A includes the channel region of the channel region of the second transistor T2.

[0172] Similar to semiconductor layer 122A, the third transistor T3 includes semiconductor layer 122C, and the first electrode 634 and the second electrode 636 include impurity regions. In other words, semiconductor layer 122C includes the channel region of the third transistor T3. Furthermore, the fifth transistor T5 includes semiconductor layer 122D, and the first electrode 654 and the second electrode 656 include impurity regions. The eighth transistor T8 includes semiconductor layer 122D, and the first electrode 684 and the second electrode 686 include impurity regions. In other words, semiconductor layer 122D includes the channel region of both the fifth transistor T5 and the eighth transistor T8. That is, semiconductor layer 122D serves as the channel region for both the fifth transistor T5 and the eighth transistor T8.

[0173] A gate insulating layer 125, a conductive layer 126, an insulating layer 128, and a conductive layer 132 are sequentially disposed on the semiconductor layer 122. The conductive layer 126 includes gate wiring 127A (gate electrode 622) and gate wiring 127B (gate electrode 632). The conductive layer 132 includes first wiring 132K, first wiring 132G, first wiring 132E (first electrode 42), and first wiring 132F. Furthermore, the region where the conductive layer 126 overlaps with the semiconductor layer 122 is a channel region. In other words, the region where the gate electrode of each transistor overlaps with the semiconductor layer is a channel region.

[0174] Each transistor of pixel 180 is formed using a semiconductor layer 122 (channel region 123 and impurity region 124A), a gate insulating layer 125, and a conductive layer 126 (e.g., gate wiring 127A).

[0175] First contact hole openings 135J, 135H, 135B, and 135A reaching semiconductor layer 122 penetrate gate insulating layer 125 and insulating layer 128, and are disposed on gate insulating layer 125 and insulating layer 128. For example, first contact hole opening 135J exposes semiconductor layer 122D (e.g., second electrode 626 and first electrode 684), and first wiring 132K is electrically connected to semiconductor layer 122D through first contact hole opening 135J. Additionally, first contact hole opening 135H exposes semiconductor layer 122A (e.g., second electrode 626), and first wiring 132G is electrically connected to semiconductor layer 122A through first contact hole opening 135H. First contact hole opening 135C exposes conductive layer 126 (gate wiring 127A), and first contact hole opening 135B exposes semiconductor layer 122 (semiconductor layer 122C). The first wiring 132E is electrically connected to the gate wiring 127A through the first contact hole opening 135C, and the first wiring 132E is electrically connected to the semiconductor layer 122D through the first contact hole opening 135B. That is, an opening reaching the conductive layer 126 or the semiconductor layer 122 can also be provided in the insulating layer 128. In addition, the first contact hole opening 135A exposes the semiconductor layer 122C (e.g., the second electrode 636), and the first wiring 132F is electrically connected to the semiconductor layer 122C through the first contact hole opening 135A.

[0176] Insulating layer 131 is provided in such a way that it covers conductive layer 132 and insulating layer 131 not exposed by conductive layer 132. Insulating layer 136 is provided in such a way that it covers insulating layer 131.

[0177] The second contact hole opening is disposed on insulating layer 131 and insulating layer 136. For example, the second contact hole opening includes second contact hole opening 138H. Additionally, an organic insulating film opening 138A for capacitor element CS is disposed on insulating layer 136. Conductive layer 139 is disposed on insulating layer 136, organic insulating film opening 138A for capacitor element CS, and second contact hole opening 138H. Conductive layer 139 includes second wiring 140C (first electrode 32), second wiring 140A (first electrode 52 and second electrode 44), and second wiring 140B. Second contact hole opening 138H exposes first wiring 132K. Second contact hole opening 138H electrically connects second wiring 140C (first electrode 32) to first wiring 132K. Organic insulating film opening 138A for capacitor element exposes insulating layer 131. For example, capacitor element CV is formed using insulating layer 131 as dielectric, and employs first wiring 132E (first electrode 42) and second wiring 140A (first electrode 52 and second electrode 44). Capacitor element CD is formed using insulating layer 131 as dielectric, and employs first wiring 132H (second electrode 54) and second wiring 140A (first electrode 52 and second electrode 44). For example, second wiring 140A also serves as a pixel electrode. Furthermore, although not shown in the figures, for example, the second contact hole opening 138 exposes a portion of the plurality of terminals (not shown) included in terminal portion 150. A portion of the exposed terminals is electrically connected to FPC 200 using a conductive film such as an anisotropic conductive film (not shown). Furthermore, the pixel electrodes are independently provided for each pixel.

[0178] The insulating layer 141 is provided in such a way that it covers the conductive layer 139.

[0179] The substrate layer 121, semiconductor layer 122, gate insulating layer 125, conductive layer 126, insulating layer 128, conductive layer 132, insulating layer 131, insulating layer 136, conductive layer 139, and insulating layer 141 are collectively referred to as array section 170.

[0180] Next, the layer above the insulating layer 141 will be described. A contact hole opening 147 for the cathode electrode is provided in the insulating layer 141. The contact hole opening 147 for the cathode electrode exposes the conductive layer 139 (e.g., the second wiring 140C).

[0181] The cathode electrode 143 is provided to cover the exposed conductive layer 139, the contact hole opening 147 for the cathode electrode, and the insulating layer 141. A functional layer 148 is provided on top of the cathode electrode 143. A common electrode 149 is provided on top of the functional layer 148, covering it. The common electrode 149 is electrically connected to the cathode electrode (the first electrode 32 of the OLED). Here, the OLED is composed of the cathode electrode 143, the functional layer 148, and the common electrode 149 (anode electrode).

[0182] The structure of functional layer 148 can be appropriately selected. For example, functional layer 148 can be constructed by combining carrier injection layer, carrier transport layer, light emission layer, carrier blocking layer, exciton blocking layer, etc. For example, Figure 9 The functional layer 148 shown includes a first layer 144, a second layer 145, and a third layer 146. For example, the first layer 144 is a carrier (electron) injection and transport layer, the second layer 145 is a light-emitting layer, and the third layer 146 is a carrier (hole) injection and transport layer. For example, similar to the pixel electrode, the functional layer 148 is independently configured for each pixel.

[0183] A sealing film 165 is disposed on the common electrode 149. For example, the sealing film 165 includes a first inorganic insulating layer 152, an organic insulating layer 154, and a second inorganic insulating layer 156. Furthermore, the first inorganic insulating layer 152 and the second inorganic insulating layer 156 are formed in such a way that they at least cover the display area 22. A cover film 158 is disposed on the second inorganic insulating layer 156.

[0184] For example, the first layer 144, the second layer 145 (light-emitting layer), and the third layer 146, as well as the common electrode 149, included in the functional layer 148 are not disposed on the IC chip 110 and the control circuit 120. A sealing film 165 and a cover film 158 are disposed on the IC chip 110 and the control circuit 120. The sealing film 165 and the cover film 158 prevent impurities (water, oxygen, etc.) from entering the light-emitting element OLED and various transistors from the outside of the display device 10.

[0185] The conductive layers 126, 132, 139, and common electrode 149 are made of common metallic materials. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and their alloys or compounds are used as common metallic materials.

[0186] For example, semiconductor layer 122 may contain crystalline silicon or metal oxide.

[0187] The materials used to form the substrate layer 121, the gate insulating layer 125, the insulating layer 131, the first inorganic insulating layer 152, and the second inorganic insulating layer 156 can be general insulating materials. For example, inorganic insulating layers such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), and silicon oxynitride (SiNxOy) can be used as these insulating layers.

[0188] The materials used to form insulating layers 128, 136, 141, and 154 can be, for example, organic compound materials with excellent surface flatness. Insulating layers 128, 136, and 141 are sometimes referred to as organic insulating layers.

[0189] [1-7. Method for manufacturing display device 10]

[0190] Reference Figure 9 , Figures 13-16 This describes the manufacturing method of the display device 10 (pixel 180). Figure 13 This is a sequence diagram illustrating the manufacturing method of the display device 10. Adjustments can be made as needed. Figures 1-12 Explain using the same or similar structures. As an example, Figure 13 The manufacturing method shown includes a method in which the semiconductor layer is an oxide semiconductor layer formed using an oxide semiconductor.

[0191] like Figures 10-12 As shown, when the manufacturing of the display device 10 (pixel 180) begins, a substrate layer 121 is formed on the first surface 101A of the substrate 101.

[0192] like Figure 9 , Figure 13 or Figure 14 As shown, a semiconductor layer 122 is formed on the substrate layer 121. Figure 13Step 10 (S10)). Semiconductor layer 122 includes semiconductor layers 122A, 122B, 122C, 122D, 122E, and 122F. Semiconductor layer 122A also serves as the semiconductor layer for the second transistor T2 and the fourth transistor T4. Semiconductor layer 122B is the semiconductor layer for the first transistor T1. Semiconductor layer 122C is the semiconductor layer for the third transistor T3. Semiconductor layer 122D also serves as the semiconductor layer for the fifth transistor T5 and the eighth transistor T8. Semiconductor layer 122E is the semiconductor layer for the sixth transistor T6. Semiconductor layer 122F is the semiconductor layer for the seventh transistor T7. In other words, semiconductor layer 122A includes the channel region of the second transistor T2 and the channel region of the fourth transistor T4, semiconductor layer 122B includes the channel region of the first transistor T1, semiconductor layer 122C includes the channel region of the third transistor T3, semiconductor layer 122D includes the channel region of the fifth transistor T5 and the channel region of the eighth transistor T8, semiconductor layer 122E includes the channel region of the sixth transistor T6, and semiconductor layer 122F includes the channel region of the seventh transistor T7.

[0193] Gate insulating layer 125 ( Figures 10-12 ) is formed on the semiconductor layer 122 and on the substrate layer 121 on which the semiconductor layer 122 is not formed. Figure 13 Step 12 (S12)).

[0194] A conductive layer 126 is formed on the gate insulating layer 125. Figures 10-12 () Figure 13 Step 13 (S13)). For example... Figure 9 , Figure 13 ,or Figure 14 As shown, the conductive layer 126 includes gate wiring 127A (gate electrode 622), gate wiring 127B (scan signal line 330), gate wiring 127C (scan signal line 331), gate wiring 127D (scan signal line 332), gate wiring 127E (scan signal line 333), gate wiring 127F (scan signal line 334), and gate wiring 127G (refer to voltage power supply line SVR). Gate wiring 127B (scan signal line 330) includes gate electrodes 632 and 642, gate wiring 127C (scan signal line 331) includes gate electrode 652, gate wiring 127D (scan signal line 332) includes gate electrodes 662 and 682, gate wiring 127E (scan signal line 333) includes gate electrode 612, and gate wiring 127F (scan signal line 334) includes gate electrode 672.

[0195] The region where the gate electrode 622 of the second transistor T2 overlaps with the semiconductor layer 122A is the channel region 123, which corresponds to the channel length of the second transistor T2. Similarly, the region where the gate electrode 612 of the first transistor T1 overlaps with the semiconductor layer 122B is the channel region of the first transistor T1, and also corresponds to its channel length. For the second transistor T2 and all other transistors except the first transistor T1, the region where the gate electrode overlaps with the semiconductor layer is the channel region of the transistor, and also corresponds to its channel length.

[0196] like Figure 14 As shown, in a top-down view, the channel region 123 of the second transistor T2 is larger (longer) than the channel regions of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. That is, the channel length of the second transistor T2 is greater than the channel lengths of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. Since the second transistor T2 operates in the saturation region, it is necessary to suppress the bending effect. Therefore, the second transistor T2 needs to have higher tolerance to hot carriers than the other transistors in pixel 180. To suppress the bending effect and ensure reliability (hot carrier tolerance), the channel length of the second transistor T2 is longer than the channel lengths of the other transistors in pixel 180.

[0197] Insulation layer 128 ( Figures 10-12 ) is formed on the conductive layer 126 and on the gate insulating layer 125 where the conductive layer 126 is not formed. Figure 13 Step 14 (S14)).

[0198] like Figure 9 , Figure 13 or Figure 14 As shown, holes are made in the first contact hole opening portions 135A~135O. Figure 13 Step 15 (S15)). Each opening is formed in the gate insulating layer 125 and the insulating layer 128, exposing the wiring, semiconductor layer, or electrode corresponding to each opening. For example, the first contact hole opening 135A exposes the semiconductor layer 122C, and the first contact hole opening 135C exposes the gate wiring 127A. The other openings also expose their respective wiring, semiconductor layer, or electrode.

[0199] A conductive layer 132 is formed on top of the insulating layer 128. Figures 10-12 () Figure 13Step 16 (S16)). For example... Figure 9 , Figure 13 or Figure 15 As shown, the conductive layer 132 includes first wiring 132A (drive power line PVDD), first wiring 132B (initialization voltage power line SVI), first wiring 132C (image data signal line 321), first wiring 132D (reference voltage line PVSS), first wiring 132E (first electrode 42), first wiring 132F, first wiring 132G, first wiring 132H (second electrode 54), first wiring 132I, first wiring 132J, first wiring 132K and first wiring 132L.

[0200] like Figure 15 As shown, in top view, for example, the first wiring 132B is electrically connected to the second transistor T4 via the first contact hole opening 135E, and the first wiring 132C is electrically connected to the first transistor T1 via the first contact hole opening 135F. The first wiring 132D is electrically connected to the seventh transistor T7 via the first contact hole opening 135M. The first wiring 132E is electrically connected to the gate wiring 127A via the first contact hole opening 135C, and to the third transistor T3 via the first contact hole opening 135B. Other first wirings are also electrically connected to the gate wiring or transistors (semiconductor layer 122) via their respective corresponding openings.

[0201] In addition, such as Figure 15 As shown, the first wiring 132E (first electrode 42), the gate wiring 127A (gate electrode 622), and the semiconductor layer 122A (channel region 123) overlap. That is, the channel region and gate electrode 622 of the second transistor T2 overlap with the first electrode 42 of the capacitor element CV. In addition, the first electrode 42 and the first wiring 132H (second electrode 54) are arranged adjacent to each other on the gate electrode 622.

[0202] Insulation layer 131 ( Figures 10-12 ) is formed on the conductive layer 132 and on the insulating layer 128 where the conductive layer 132 is not formed. Figure 13 Step 17 (S17)).

[0203] like Figure 9 , Figure 13 or Figure 15 As shown, holes are made in the second contact hole opening portions 138C~138H. Figure 13 Step 18 (S18)). Each opening is made in the insulating layer 131, exposing the wiring, semiconductor layer or electrode corresponding to each opening.

[0204] Insulation layer 136 (organic insulation layer) Figures 10-12) is formed on the insulating layer 131 ( Figure 13 Step 19 (S19)).

[0205] like Figure 9 , Figure 13 or Figure 15 As shown, insulating layer 136 (organic insulating layer) has openings ( Figure 13 Step 20 (S20)). In the openings of S20, organic insulating film openings 138A and 138B for capacitor elements are formed. Additionally, in the openings of S20, similar to the openings of S18, second contact hole openings 138C to 138H are formed. That is, the second contact hole openings 138C to 138H are formed twice. Each opening is formed in the insulating layer 136, exposing the corresponding insulating layer, wiring, or electrode. For example, in the organic insulating film opening 138A for capacitor elements, only the insulating layer 136 on the first wiring 132E (first electrode 42) is removed, exposing the insulating layer 131. On the other hand, in the organic insulating film opening 138B for capacitor elements, only the insulating layer 136 on the first wiring 132H (second electrode 54) is removed, exposing the first wiring 132H. The other openings also expose their respective corresponding insulating layers, wiring, or electrodes.

[0206] Conductive layer 139 ( Figures 10-12 ) is formed on the insulating layer 136, on the insulating layer 131 exposed at the opening 138A of the organic insulating film for the capacitor element, and on the insulating layer 131 exposed at the opening 138B of the organic insulating film for the capacitor element. Figure 13 Step 21 (S21)). For example... Figure 9 or Figure 16 As shown, the conductive layer 139 includes a second wiring 140A (first electrode 52 and second electrode 44), a second wiring 140B, a second wiring 140C (first electrode 32), a second wiring 140D, and a second wiring 140E (refer to voltage power line SVR).

[0207] like Figure 16As shown, in top view, the second wiring 140A (first electrode 52 and second electrode 44) is electrically connected to the sixth transistor T6 via the second contact hole opening 138I, the first wiring 132I, and the first contact hole opening 135N. The second wiring 140C is electrically connected to the first wiring 132K, the fifth transistor T5, and the eighth transistor T8 via the second contact hole opening 138H and the first contact hole opening 135J. The second wiring 140E is electrically connected to the first wiring 132J, the sixth transistor T6, and the gate wiring 127G via the second contact hole opening 138G and the first contact hole opening 135P. Other second wirings are also electrically connected to the first wiring, the gate wiring, or the transistor (semiconductor layer 122) via corresponding openings.

[0208] In addition, such as Figure 16 As shown, the second wiring 140A (first electrode 52 and second electrode 44), the first wiring 132E (first electrode 42), the gate electrode 622, and the semiconductor layer 122A (channel region 123) overlap. That is, the second transistor T2 overlaps with the capacitor element CV. Furthermore, the first electrode 42 and the first wiring 132H (second electrode 54) are arranged adjacent to each other above the gate electrode 622. That is, the capacitor element CV is arranged adjacent to the capacitor element CD.

[0209] Insulation layer 141 (organic insulation layer) Figures 10-12 ) is formed on the conductive layer 139 and on the insulating layer 136 where the conductive layer 139 is not formed. Figure 13 Step 22 (S22)).

[0210] like Figure 9 as well as Figure 10 As shown, insulating layer 141 (organic insulating layer) has openings ( Figure 13 Step 23 (S23)). In the opening of S23, a contact hole opening 147A for the cathode electrode is formed. The contact hole opening 147A for the cathode electrode removes the insulating layer 141 above the second wiring 140C, exposing the second wiring 140C. The contact hole opening 147A for the cathode electrode is sometimes referred to as an organic insulating layer opening. Furthermore, as Figure 9 as well as Figure 10 As shown, the contact hole opening 147A for the cathode electrode overlaps with the second wiring 140C when viewed from above.

[0211] The cathode electrode 143 is disposed on the exposed second wiring 140C, on the contact hole opening 147A for the cathode electrode, and on the insulating layer 141. Additionally, the functional layer 148 is disposed on the cathode electrode 143. Figure 10 The common electrode 149 is disposed on the functional layer 148. Figure 13Step 24 (S24). In addition, for example, the cathode electrode 143 and the functional layer 148 are provided on a pixel-by-pixel basis, and the common electrode 149 is provided in a manner that overlaps with the display area 22.

[0212] Following S24, a sealing film 165 and a covering film 158 are sequentially disposed on the common electrode 149. Figure 10 ).

[0213] As described above, the manufacturing of the display device 10 (pixel 180) is now complete.

[0214] [1-8. Relationship between potential difference and capacitance]

[0215] Reference Figure 17 The relationship between the absolute value of the potential difference (potential difference Vcv) between the voltage supplied to the first electrode 42 of the capacitor element CV and the voltage supplied to the second electrode 44 and the capacitance value Ccvv of the capacitor element CV, and the relationship between the potential difference Vcv and the capacitance value Ccdv of the capacitor element CD are explained.

[0216] Ideally, the absolute value of the potential difference between the electrodes of capacitor element CV is the same as the absolute value of the potential difference between the electrodes of capacitor element CD. The capacitance values ​​Ccvv and Ccdv are estimated in such a way that the withstand voltages of capacitor elements CV and CD are the same or approximately the same. At this time, the second electrode 44 and the first electrode 52 are electrically connected to the first node N1 and are supplied with a reference voltage VREF (2V).

[0217] For example, the ratio of leakage charge (leakage current) of capacitor element CV and capacitor element CD is set to 2:3, the charge Qcv that capacitor element CV can hold is 440fC, and the charge Qcd that capacitor element CD can hold is 660fC. Additionally, for example, the second electrode 54 is supplied with a maximum voltage VSIGL (4V), and the potential difference between the electrodes of capacitor element CD (the potential difference between the voltage supplied to the first electrode 52 and the voltage supplied to the second electrode 54) is the potential difference Vcd (4V - potential difference Vcv).

[0218] like Figure 17 As shown, for example, when the potential difference Vcv is 2.2V, the required capacitance value Ccvv is 200fF. At this time, the potential difference Vcd is 1.8V (4V-2.2V), and the capacitance value Ccdv is 370fF. For example, in order to obtain the threshold voltage VTH at high speed, it is preferable to estimate the capacitance value Ccvv to be less than the capacitance value Ccdv.

[0219] As described above, the relationship between potential difference Vcv and capacitance value Ccvv, and the relationship between potential difference Vcd and capacitance value Ccdv, can be predicted, and the predicted capacitance values ​​Ccvv and Ccdv can be used for design.

[0220] Furthermore, by using the estimated capacitance values ​​Ccvv and Ccdv, it is possible to achieve a balance between the required withstand voltages of capacitor elements CV and CD, and to obtain the threshold voltage VTH at high speed.

[0221] [2. Second Implementation]

[0222] Reference Figures 18-28 This describes the display device 20 according to the second embodiment. Figure 18 This is a schematic diagram showing the structure of the display device 20. Figure 19 This is a schematic diagram showing the structure of the control circuit 120A according to the second embodiment. Figure 20 This is a circuit diagram showing the structure of the scan driver 160A(n) according to the second embodiment. Figure 21 This is a schematic diagram showing the input signal to pixel 180A (pixel circuit 181A) according to the second embodiment. Figure 22 This is a circuit diagram showing the structure of pixel circuit 181A. Figure 23 , Figures 25-28 This is a timing diagram of display device 20. Figure 24 This is the timing diagram for the 120A control circuit. Adjustments should be made as needed. Figures 1-17 Explanation of the same or similar structure, sometimes omitting the similarity. Figures 1-17 Descriptions of the same or similar structures.

[0223] The display device 20 includes a control circuit 120A, a pixel 180A, and a pixel circuit 181A. Specifically, the display device 20 includes the structures shown in (1) to (6) below. The main difference is that the structures shown in (1) to (6) are different from the structure of the display device 10 according to the first embodiment.

[0224] (1) It has the structure and function obtained by replacing the control circuit 120 of the display device 10 according to the first embodiment with the control circuit 120A, and the structure and function associated with the control circuit 120A are different from the structure and function associated with the control circuit 120.

[0225] (2) The electrical connection between control circuit 120A and pixel 180A (pixel circuit 181A) is different from the electrical connection between control circuit 120 and pixel 180 (pixel circuit 181).

[0226] (3) The first scan signal SC1(n) also serves as the scan signal SC3(n). That is, the display device 20 does not include the scan signal line 332 on which the scan signal SC3(n) and the scan signal SC3(n) are supplied.

[0227] (4) Pixel 180A (pixel circuit 181A) includes a ninth transistor T9. The ninth transistor T9 is electrically connected between the sixth node N6 and the third node N3, and the gate electrode 692 of the ninth transistor T9 is electrically connected to the scan signal line 334.

[0228] (5) The driving method of the display device 20 includes the steps of performing the period PWR and period PVH in parallel.

[0229] (6) The driving method of the display device 20 includes the steps of performing the period PIN and the period PWR in parallel.

[0230] The structures in display device 20 other than those shown in (1) to (6) and the structures in display device 20 other than those associated with the structures shown in (1) to (6) are the same structures as those in display device 10 according to the first embodiment. When describing the structure and function of display device 20, the same structures and functions as those in display device 10 will be described as needed.

[0231] [2-18. Structure of the 120A Control Circuit]

[0232] Reference Figures 18-20 This section provides an overview of the control circuit 120A.

[0233] like Figure 18 As shown, two control circuits 120A are positioned adjacent to both sides of the display area 22 along the second direction D2. Scan signal lines 330, 331, 333, and 334 extend from the control circuits 120A along the second direction D2 and are connected to a plurality of pixels 180 arranged along the second direction D2.

[0234] like Figure 19 As shown, the control circuit 120A includes a shift register circuit 130A and multiple scan drivers 160A(n). For example, the control circuit 120A is a gate driver. The value n is a positive integer. For example, the control circuit 120A is input with control signals such as clock signal CLK, start pulse STV, enable signals EN1~EN6, and voltages such as drive voltage VDDEL and reference voltage VSSEL. The control circuit 120A can sequentially select scan lines through the input of control signals and power supply.

[0235] The shift register circuit 130A is electrically connected to multiple scan drivers 160A(n). The shift register circuit 130A includes multiple shift registers (e.g., shift registers 111 and 112). In addition, clock signals CLK, start pulse STV, etc. are supplied to the shift register circuit 130A via multiple connection lines 342, drive voltage VDDEL is supplied to the shift register circuit 130A via drive power line PVDD, and reference voltage VSSEL is supplied to the shift register circuit 130A via reference voltage line PVSS. The shift register circuit 130A has the following function: based on control signals such as clock signal CLK and start pulse STV, it generates multiple output signals (output signal SR1, output signal SR2, ...) with different timing shifts, and outputs them sequentially to multiple scan drivers (e.g., scan driver 160A(1), scan driver 160A(2), ...).

[0236] For example, shift register 111 is electrically connected to shift register 112. Shift register 111 is electrically connected to scan driver 160A (1) and supplies output signal SR1 to input terminal IN1 of scan driver 160A (1). Shift register 112 is electrically connected to scan driver 160A (2) and supplies output signal SR2 to input terminal IN1 of scan driver 160A (2).

[0237] The scan driver 160A(n) has 7 input terminals (input terminals IN1~IN7) and 9 output terminals (output terminals OUT1~OUT9). Enable signals EN1~EN6 are supplied from the IC chip 110 to the multiple scan drivers 160A(n) via multiple connection lines 342, a drive voltage VDDEL is supplied to the multiple scan drivers 160A(n) via the drive power line PVDD, and a reference voltage VSSEL is supplied to the multiple scan drivers 160A(n) via the reference voltage line PVSS. The scan driver 160A(n) performs the following function: based on the aforementioned multiple output signals and enable signals EN1~EN6, it sequentially supplies scan signals with different timings (e.g., first scan signal SC1(n), second scan signal SC2(n), fourth scan signal SC4(n), and fifth scan signal SC5(n)) to each scan signal line, and drives the pixels 180A (pixel circuit 181A) electrically connected to each scan signal line.

[0238] For example Figure 20As shown, the scan driver 160A(n) includes inverter circuits INV1~INV5 and six transmission gates TMG. Each of the six transmission gates TMG includes a switch SW and a transistor TR1. The switch SW has a structure formed by electrically connecting an n-channel field-effect transistor and a p-channel field-effect transistor. Transistor TR1 is electrically connected to inverter circuit INV3, reference voltage line PVSS, p-channel field-effect transistor, and the corresponding output terminal (transmission gate TMG). Inverter circuit INV1 is electrically connected to input terminal IN1 and inverter circuit INV2. Inverter circuit INV2 is electrically connected to output terminal OUT1, inverter circuit INV3, and the switch SW (n-channel field-effect transistor) in the six transmission gates TMG. Inverter circuit INV3 is electrically connected to inverter circuit INV4, the switch SW (p-channel field-effect transistor) in the six transmission gates TMG, and output terminal OUT3. Inverter circuit INV4 is electrically connected to inverter circuit INV5, and inverter circuit INV5 is electrically connected to output terminal OUT2. Six transmission gates TMG are electrically connected one-to-one with input terminals IN2~IN7 and one-to-one with output terminals OUT4~IN9. Specifically, the transmission gate TMG connected to input terminal IN2 is electrically connected to output terminal OUT4; the transmission gate TMG connected to input terminal IN3 is electrically connected to output terminal OUT5; the transmission gate TMG connected to input terminal IN4 is electrically connected to output terminal OUT6; the transmission gate TMG connected to input terminal IN5 is electrically connected to output terminal OUT7; the transmission gate TMG connected to input terminal IN6 is electrically connected to output terminal OUT8; and the transmission gate TMG connected to input terminal IN7 is electrically connected to output terminal OUT9.

[0239] For example Figure 18 as well as Figure 19 As shown, scan signals SC1(n), SC2(n), and SC5(n) are input for each of the k rows. Scan signal lines 330 from row n to row k are electrically connected along the second direction D2. Similarly, scan signal lines 331 and 334 from row n to row k are electrically connected. That is, multiple pixels 180A (pixel circuits 181A) electrically connected to scan signal lines 330, 331, and 334 from row n to row k are input with scan signal SC1(n) supplied to the common scan signal line 330 at the same timing, scan signal SC2(n) supplied to the common scan signal line 331 at the same timing, and scan signal SC5(n) supplied to the common scan signal line 334 at the same timing.

[0240] For example Figure 18 as well as Figure 19As shown, a scan signal SC4(n) is input for each row. That is, multiple pixels 180A (pixel circuits 181A) electrically connected to the scan signal line 333 of the nth row are input with the scan signal SC4(n) supplied to the scan signal line 333 of the nth row. Similarly, multiple pixels 180A (pixel circuits 181A) electrically connected to the scan signal line 333 of the (n+1)th row are input with the scan signal SC4(n+1) supplied to the scan signal line 333 of the (n+2)th row, and multiple pixels 180A (pixel circuits 181A) electrically connected to the respective scan signal lines 333 of the (n+2)th to (k)th rows are input with the scan signals SC4(n+2) to SC4(k) supplied to the respective scan signal lines 333 of the (n+2)th to (k)th rows.

[0241] Figure 19 The control circuit 120A shown is an example, where n is 1 and k is 6. That is, multiple pixels 180A (pixel circuit 181A) electrically connected to the scan signal lines 330, 331 and 334 of the first to sixth rows are input with scan signal SC1 (1) supplied to the common scan signal line 330 at the same timing, scan signal SC2 (1) supplied to the common scan signal line 331 at the same timing, and scan signal SC5 (1) supplied to the common scan signal line 334 at the same timing. In addition, multiple pixels 180A (pixel circuits 181A) electrically connected to the scan signal line 333 of the first row are input with scan signal SC4 (1) supplied to the scan signal line 333 of the first row. Similarly, multiple pixels 180A (pixel circuits 181A) electrically connected to the scan signal line 333 of the second to sixth rows are input with scan signal SC4 (n) (scan signals SC4 (2) to SC4 (6)) supplied to the scan signal line 333 of the corresponding row.

[0242] The multiple pixels 180A (pixel circuit 181A) in the seventh to twelfth rows of the six rows following the initial six rows, and the multiple pixels 180A (pixel circuit 181A) up to the sixth row, are similarly input with scan signal SC1 (2) at the same timing, scan signal SC2 (2) at the same timing, and scan signal SC5 (2) at the same timing, and are respectively input with scan signals SC4 (7) to SC4 (12) supplied to the scan signal line 333 of the corresponding row.

[0243] In addition, Figure 19In the control circuit 120A shown, the scan signals SC1(n), SC2(n), and SC5(n) supplied to the scan signal lines 330, 331, and 334 of the first to sixth rows are referred to as scan signals SC1[1-6], SC2[1-6], and SC5[1-6], respectively. The scan signals SC1(n), SC2(n), and SC5(n) supplied to the scan signal lines 330, 331, and 334 of the seventh to twelfth rows are referred to as scan signals SC1[7-12], SC2[7-12], and SC5[7-12].

[0244] [2-2. Structure of pixel 180A]

[0245] Reference Figure 21 as well as Figure 22 This section provides an overview of pixel 180A and pixel circuit 181A.

[0246] As explained in (3) above, pixel 180A (pixel circuit 181A) does not include the scan signal line 332 on which the scan signal SC3(n) is supplied, and the first scan signal SC1(n) also serves as the scan signal SC3(n) contained in pixel 180 (pixel circuit 181).

[0247] The gate electrode 662 of the sixth transistor T6 and the gate electrode 682 of the eighth transistor T8 are electrically connected to the scan signal line 330, which is supplied with the first scan signal SC1(n). The sixth transistor T6 and the eighth transistor T8 use the first scan signal SC1(n) to control the switch. In other words, the sixth transistor T6 and the eighth transistor T8 are controlled by the first scan signal SC1(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the first scan signal SC1(n) is LO, the sixth transistor T6 and the eighth transistor T8 are in a non-conducting state; when the signal supplied to the first scan signal SC1(n) is HI, the sixth transistor T6 and the eighth transistor T8 are in a conducting state.

[0248] Additionally, as explained in (4) above, pixel 180A (pixel circuit 181A) includes a ninth transistor T9.

[0249] The ninth transistor T9 functions to turn on the sixth node N6 and the third node N3. The ninth transistor T9 includes a gate electrode 692, a first electrode 694, and a second electrode 696. The gate electrode 692 is electrically connected to the scan signal line 334. The first electrode 694 is electrically connected to the second electrode 616 of the first transistor T1, the second electrode 54 of the capacitor element CD, and the sixth node N6. The second electrode 696 is electrically connected to the third node N3, the first electrode 624 of the second transistor T2, the second electrode 646 of the fourth transistor T4, and the second electrode 676 of the seventh transistor T7. The ninth transistor T9 uses the fifth scan signal SC5(n) to control its switching. In other words, the ninth transistor T9 is controlled by the fifth scan signal SC5(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the fifth scan signal SC5(n) is LO, the ninth transistor T9 is in a non-conducting state; when the signal supplied to the fifth scan signal SC5(n) is HI, the ninth transistor T9 is in a conducting state.

[0250] The first transistor T1 to the ninth transistor T9 in the display device 20 are n-channel field-effect transistors, and the channel region of each transistor T1 to the ninth transistor T9 is formed using an oxide semiconductor layer with semiconductor properties.

[0251] The structure and function of pixel circuit 181A, other than those described in “2-2. Structure of pixel 180A”, are the same as those of pixel circuit 181.

[0252] [2-3. Driving method for display device 20]

[0253] Reference Figures 23-28 This describes the driving method of the display device 20. The horizontal axis of the timing diagram represents time.

[0254] For example, based on Figure 23 The driving method of the timing diagram display device 20 shown is based on Figure 4 Compared to the driving method of the timing diagram display device 10, this method includes the steps of performing threshold voltage acquisition and holding period PVH (period PVH) after performing initialization period PIN (period PIN), and performing writing period PWR (period PWR) in parallel with period PVH. In other words, period PWR is performed concurrently with period PVH and is executed within period PVH. Alternatively, period PWR can also be performed within period PIN.

[0255] For example, Figure 19 , Figure 20 as well as Figure 24The diagram illustrates the case where the period between the emission period PEM in the K-1stFRAME period and the emission period PEM in the KthFRAME period includes the period PIN and the period PVH, and the period between the emission period PEM in the K-1stFRAME period and the emission period PEM in the KthFRAME period is a horizontal period HRP of 6 cycles (6 horizontal periods (6HRP)).

[0256] As described in "2-1. Control Circuit 120A", the output signals SR1 and SR2 (refer to...) Figure 24 It is based on the clock signal CLK (refer to...) Figure 19 ), Start pulse STV (refer to) Figure 19 The output signals SR1 and SR2 are generated by control signals such as SR1 and SR2. Specifically, output signal SR2 is obtained by shifting output signal SR1. Furthermore, the pulse widths of output signals SR1 and SR2 are equal.

[0257] As described in “2-1. Control Circuit 120A”, the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n) and the fifth scan signal SC5(n) are generated based on the output signal SR1, the output signal SR2 and the enable signals EN1~EN6.

[0258] For example, refer to Figure 19 , Figure 20 as well as Figure 24 The first scan signal SC1 (1), the second scan signal SC2 (1) and the fifth scan signal SC5 (1) are generated based on the rise and fall of the output signal SR1. The fourth scan signal SC4 (1) is generated based on the output signal SR1 and the enable signal EN1. The fourth scan signal SC4 (2) is generated based on the output signal SR1 and the enable signal EN2. The fourth scan signal SC4 (3) is generated based on the output signal SR1 and the enable signal EN3. The fourth scan signal SC4 (4) is generated based on the output signal SR1 and the enable signal EN4. The fourth scan signal SC4 (5) is generated based on the output signal SR1 and the enable signal EN5. The fourth scan signal SC4 (6) is generated based on the output signal SR1 and the enable signal EN6.

[0259] The fourth scan signal SC4(1) is generated during the period PIN, and the pixel 180A (pixel circuit 181A) electrically connected to the fourth scan signal SC4(1) is input with the image data signal SL(m) before the period PVH and during the period HRP (period PWR) overlapping with the period PIN.

[0260] Additionally, refer to Figure 19 , Figure 20 as well as Figure 24 The first scan signal SC1 (2), the second scan signal SC2 (2) and the fifth scan signal SC5 (2) are generated based on the rise and fall of the output signal SR2. The fourth scan signal SC4 (7) is generated based on the output signal SR2 and the enable signal EN1. The fourth scan signal SC4 (8) is generated based on the output signal SR2 and the enable signal EN2. The fourth scan signal SC4 (9) is generated based on the output signal SR2 and the enable signal EN3. The fourth scan signal SC4 (10) is generated based on the output signal SR2 and the enable signal EN4. The fourth scan signal SC4 (11) is generated based on the output signal SR2 and the enable signal EN5. The fourth scan signal SC4 (12) is generated based on the output signal SR2 and the enable signal EN6.

[0261] For easy observation Figure 24 Although the illustration is omitted, similar to the fourth scan signal SC4 (1), the fourth scan signal SC4 (7) is generated during the period PIN, and the pixel 180A (pixel circuit 181A) electrically connected to the fourth scan signal SC4 (7) is input with the image data signal SL (m) during the period HRP (period PWR) overlapping with the period PIN.

[0262] The driving method of the display device 20 includes driving k rows of pixels 180A (pixel circuit 181A) by shifting the first scan signal SC1(n), the second scan signal SC2(n), the fifth scan signal SC5(n), and the fourth scan signals SC4(n) to SC4(n+k) by k rows each time using output signals SR1 and SR2. Thus, the control circuit 120A can drive k rows of pixels 180A (pixel circuit 181A) at a timing using a common control signal. As a result, the display device 20 includes a simplified control circuit structure compared to the case where pixels are driven for each row. Furthermore, the display device 20 includes a structure that achieves low power consumption through the simplification of the control circuit, including a simplified control circuit structure compared to the case where pixels are driven for each row.

[0263] Next, refer to Figures 25-28 This describes a horizontal period (horizontal period HRP) of the driving method for the pixels 180 (pixel circuit 181) of the display device 20. Furthermore, taking the fourth scan signal SC4(n+3) among the fourth scan signals SC4(n) to SC4(n+k) as an example, it is referenced to... Figures 25-28 The driving method of the pixel 180 (pixel circuit 181) of the display device 20 will be described.

[0264] The horizontal period HRP in the driving method of the display device 20 includes a period PWR and a period PVH. In the horizontal period HRP, a pixel 180A (pixel circuit 181A) is input with a first scan signal SC1(n), a second scan signal SC2(n), a fourth scan signal SC4(n+3), and an image data signal SL(m). For example, a pixel 180A (pixel circuit 181A) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n). The image data signal SL(m) is input to the selected pixel 180A (pixel circuit 181A) according to the timing of each signal. The same operation is performed on all pixels 180A (pixel circuit 181A), and based on the image data signal SL(m) input to all pixels 180A (pixel circuit 181A), an image equivalent to the current frame of 1 FRAME is displayed in the display area 22 of the display device 20.

[0265] For example, to Figures 23-28 The signals and voltages (potentials) supplied by each node in each period of each frame in the timing diagram shown are the same as those in Table 1.

[0266] [2-3-1. First Example of a Driving Method for Display Device 20]

[0267] Reference Figure 25 This describes a first example of a driving method for the display device 20. Similar to the first example of a driving method for the display device 10 according to the first embodiment, the first example of a driving method for the display device 20 includes the step of displaying images of different colors in consecutive frames.

[0268] Similar to the first example of the driving method for the display device 10 according to the first embodiment, an image data signal SL(m) including a data signal VDATA is input to each pixel 180 (pixel circuit 181) according to each period. The data signal VDATA is analog data containing a voltage of VSIGL or higher and a voltage of VSIGH or lower. For example, in period PWR, a voltage of VSIGL or higher and a voltage of VSIGH or lower is selected using a selection signal (not shown) and supplied to the image data signal SL(m). For example, in periods other than period PWR, the data signal VDATA is supplied with voltages other than those supplied to the selected pixel 180 (pixel circuit 181).

[0269] During the PEM (Power Emitting Mode) of the K-1stFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to the selected pixel 180A (pixel circuit 181A). The first scan signal SC1(n) and the fourth scan signal SC4(n+3) are supplied with LO (Local Off), and the second scan signal SC2(n) and the fifth scan signal SC5(n) are supplied with HI (High On). The first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are in the off state, while the fifth transistor T5, the seventh transistor T7, and the ninth transistor T9 are in the on state. Additionally, for example, the voltage supplied to the third node N3 and the sixth node N6 is voltage Vnd (-2V), the voltage supplied to the second node N2 is voltage Vnq (2V), and the potential difference Vgs is 4V. Therefore, the second transistor T2 is in the on state, enabling the current Ion, based on the potential difference Vgs and Vds corresponding to the voltage VSIGH input to HRP during the K-1stFRAME level, to flow from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. As a result, the light-emitting element OLED emits light. Furthermore, the voltage supplied to the first node N1 becomes 0V through capacitive coupling based on the capacitor element CV and the capacitor element CD. For example, pixel 180 (pixel circuit 181) emits red light, and white light is emitted by using three pixels: pixel 180 emitting red light, pixel 180 emitting blue light, and pixel 180 emitting green light.

[0270] During the period following the emission period PEM of K-1stFRAME, between the emission period PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with a voltage equal to the voltage of the data signal VDATA supplied to the selected pixel 180A (pixel circuit 181A). First, the fifth scan signal SC5(n) changes from being supplied with HI to being supplied with LO. When the fifth scan signal SC5(n) is supplied with LO, the first scan signal SC1(n) changes from being supplied with LO to being supplied with HI. The second scan signal SC2(n) is supplied with HI, and the fourth scan signal SC4(n+3) is supplied with LO.

[0271] As a result, during the period between the PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the seventh transistor T7 and the ninth transistor T9 change from the on state to the off state, and the current Ion no longer flows from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. In addition, the sixth node N6 and the third node N3 become non-conductive. The third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 change from the off state to the on state, the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes 0V, the light-emitting element OLED stops emitting light, and the voltage supplied to the first node N1 rises from 0V to voltage Vnq (reference voltage VREF, 2V) to become voltage Vnq. The sixth node N6 (the second electrode 616 of the first transistor T1) is in a floating state. To maintain the voltage rise (2V-0V) supplied to the first node N1 through the capacitive coupling between the first node N1 and the sixth node N6 via the capacitor element CD, the voltage supplied to the sixth node N6 changes from voltage Vnd (-2V) to 0V. The third transistor T3, the eighth transistor T8, and the fifth transistor T5 are in the conducting state. The first transistor T1 remains in the off state. The second node N2 and the fourth node N4 are conducting, supplying voltage Vnr (driving voltage VDDEL, 6V) to the second node N2 (the gate electrode 622 of the second transistor T2) and the fourth node N4 (the second electrode 626 of the second transistor T2). In addition, the fourth transistor T4 changes from the off state to the conducting state, supplying voltage Vnp (initialization voltage VINI, 3V) to the third node N3 (the first electrode 624 of the second transistor T2). The potential difference Vgs is 3V (6V-3V), and the second transistor T2 is in the conducting state.

[0272] As described above, during the period PIN, the second node N2 and the fourth node N4 are initialized by the drive voltage VDDEL, the first node N1 is initialized by the reference voltage VREF, and the third node N3 is initialized by the initialization voltage VINI.

[0273] In the period PVH following the period PIN, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181). The state of supplying HI to the second scan signal SC2(n) changes to the state of supplying LO. The other scan signals are in the same state as the period PIN. The fifth transistor T5 changes from the on state to the off state, and the other transistors are in the same state as the period PIN.

[0274] As a result, during the PVH period, the first node N1 maintains voltage Vnq, and the third node N3 maintains voltage Vnp. The second transistor T2 is in the on state, with current Ion flowing through it. The first node N1 maintains voltage Vnq, the third node N3 maintains voltage Vnp, and the sixth node N6 maintains 0V. Furthermore, through the off state of the fifth transistor T5, the voltage supplied to the second node N2 and the fourth node N4 is released and gradually decreases from voltage Vnr (discharge). When the potential difference Vgs between the voltage supplied to the second node N2 and the fourth node N4 and the voltage supplied to the third node N3 becomes the threshold voltage VTH, the second transistor T2 becomes off. At this time, the voltage supplied to the second node N2 and the fourth node N4 is voltage Vnl (e.g., 4V).

[0275] As described above, during the PVH period, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0276] During the period PWR, which operates in parallel with the period PVH, the image data signal SL(m) (data signal VDATA) is supplied with voltage VSIGH (4V). The fourth scan signal SC4(n+3) changes from being supplied with LO to being supplied with HI. The first scan signal SC1(n) is supplied with HI, and the second scan signal SC2(n) and the fifth scan signal SC5(n) are supplied with LO. The first transistor T1 changes from the off state to the on state. The other transistors become the same as during the period PVH. The voltage supplied to the first node N1 is maintained at voltage Vnq (reference voltage VREF, 2V), the voltage supplied to the second node N2 is maintained at voltage Vnl (e.g., 4V), the voltage supplied to the third node N3 is maintained at voltage Vnp, and the voltage supplied to the sixth node N6 gradually increases from 0V to become voltage Vnl (voltage VSIGH, e.g., 4V). At this point, the capacitor element CD maintains the potential difference (based on the sixth node N6, -2V) by maintaining a charge equivalent to the potential difference between the voltage Vnq supplied to the first node N1 (reference voltage VREF, 2V) and the voltage Vnl supplied to the sixth node N6 (voltage VSIGH, for example, 4V). The potential difference Vgs is 1V, the same as the threshold voltage VTH.

[0277] As described above, during the PWR period, a data signal VDATA is written to pixel 180A (pixel circuit 181A). Additionally, the capacitor element CD maintains the voltage contained in the data signal VDATA.

[0278] During the period PVH following the period PWR, the image data signal SL(m) (data signal VDATA) is supplied with a voltage equal to the voltage supplied to the selected pixel 180 (pixel circuit 181) other than the data signal VDATA. The fourth scan signal SC4(n+3) changes from being supplied with HI to being supplied with LO. The first scan signal SC1(n) is supplied with HI, and the second scan signal SC2(n) and the fifth scan signal SC5(n) are supplied with LO. The first transistor T1 changes from being on to being off. The other transistors are in the same state as during the period PWR. The voltage sustaining voltage Vnq (reference voltage VREF, 2V) supplied to the first node N1, the voltage sustaining voltage Vnl (e.g., 4V) supplied to the second node N2 and the sixth node N6, and the voltage sustaining voltage Vnp supplied to the third node N3 are maintained. At this point, the capacitor element CD maintains the potential difference (based on the sixth node N6, -2V) by maintaining a charge equivalent to the potential difference between the voltage Vnq supplied to the first node N1 (reference voltage VREF, 2V) and the voltage Vnl supplied to the sixth node N6 (voltage VSIGH, for example, 4V). The potential difference Vgs is 1V, the same as the threshold voltage VTH.

[0279] As described above, during the PVH period, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0280] During the period between PVH and PEM, the first scan signal SC1(n) changes from being supplied with HI to being supplied with LO. When the first scan signal SC1(n) is supplied with LO, the fifth scan signal SC5(n) changes from being supplied with LO to being supplied with HI. When the fifth scan signal SC5(n) is supplied with LO, the second scan signal SC2(n) changes from being supplied with LO to being supplied with HI. The third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 change from being on to being off, and the fifth transistor T5, the seventh transistor T7, and the ninth transistor T9 change from being off to being on. Other scan signals and other transistors are in the same state as during PVH. The voltage supplied to the third node N3 decreases from voltage Vnp to voltage Vnd (-2V), thereby, through capacitive coupling of capacitors CD and CV, the voltage supplied to the second node N2 and the voltage supplied to the sixth node N6 decreases from voltage Vnl to voltage Vnd (-2V). That is, when the potential difference Vgs is 0V, the second transistor T2 is in the off state. At this time, the voltage supplied to the first node N1, which is coupled through the capacitor elements CV and CD, drops from the voltage Vnq to the voltage Vnt (-4V).

[0281] During the light-emitting period (PEM), the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to the selected pixel 180A (pixel circuit 181A). The scan signal and other transistors are in the same state as during the period PVH and the light-emitting period (PEM). Since the potential difference Vgs is 0V, the second transistor T2 is in the off state, so the current Ion does not flow. As a result, the light-emitting element OLED does not emit light. Consequently, the pixel 180A (pixel circuit 181A) that emits red light becomes black. In addition, similarly to the pixel 180A that emits red light, the pixels 180A that emit blue light and the pixels 180A that emit green light also do not emit light, thus forming a black image by using the three pixels 180A that emit red light, the pixel 180A that emits blue light, and the pixel 180A that emits green light.

[0282] Display device 20 functions similarly to display device 10. Furthermore, it can independently control each node. The driving method of display device 20 includes a step of performing period PWR in parallel with period PIN, and a step of performing period PWR in parallel with period PVH. That is, the driving method of display device 20 can write data voltage to the pixel circuit at arbitrary timings. As a result, compared to a dedicated period driving method without performing period PWR, the driving method of display device 20 can extend the light emission period (PEM). Therefore, display device 20 can maintain the light emission period for a longer time and suppress brightness within a unit period, thus achieving higher reliability.

[0283] [2-3-2. A second example of a driving method for the display device 20]

[0284] Reference Figure 26 This section describes a second example of the driving method for the display device 20. The driving method shown in this second example of the display device 20, like the second example of the driving method for the display device 10 according to the first embodiment, includes the step of displaying an image of the same color (white) in consecutive frames.

[0285] The voltages (potentials) of each node in the period preceding the period PWR, which is executed in parallel with the light emission period PEM of K-1FRAME to the period PVH of K-1FRAME, are the same as the structure described in "2-3-1. First Example of Driving Method for Display Device 20". Furthermore, the structure of each scan signal in each period and the operation of each transistor are the same as the structure described in "2-3-1. First Example of Driving Method for Display Device 20". Therefore, the same structure as described in "2-3-1. First Example of Driving Method for Display Device 20" will be described as needed. In addition, the image data signal SL(m) is supplied with a data signal VDATA containing VSIGL (0V) corresponding to white during the period PWR of K-1FRAME, and the same data signal VDATA as the structure described in "2-3-1. First Example of Driving Method for Display Device 20" is supplied during periods other than the period PWR of K-1FRAME.

[0286] During the light emission period PEM of K-1stFRAME, similar to the structure described in "2-3-1. First Example of Driving Method of Display Device 20", pixel 180A (pixel circuit 181A) emits red light, and white light is emitted by using three pixels: pixel 180A that emits red light, pixel 180A that emits blue light, and pixel 180A that emits green light.

[0287] In the period PIN of KthFRAME, similar to the structure described in "2-3-1. First example of driving method of display device 20", the second node N2 and the fourth node N4 are initialized by driving voltage VDDEL, the first node N1 is initialized by reference voltage VREF, and the third node N3 is initialized by initialization voltage VINI.

[0288] During the period PVH of KthFRAME, similar to the structure described in "2-3-1. First example of driving method of display device 20", the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0289] During the period PWR of KthFRAME, which is executed in parallel with the period PVH of KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with a voltage VSIGL (0V). The voltage supplied to the first node N1 is maintained at a voltage Vnq (reference voltage VREF, 2V), the voltage supplied to the second node N2 is maintained at a voltage Vnl (e.g., 4V), the voltage supplied to the third node N3 is maintained at a voltage Vnp, and the voltage supplied to the sixth node N6 is VSIGL (0V), maintained at 0V. The capacitor element CD maintains this potential difference (2V) by holding a charge equivalent to the potential difference between Vnq (reference voltage VREF, 2V) supplied to the first node N1 and 0V supplied to the sixth node N6. Additionally, the potential difference Vgs is 1V, the same as the threshold voltage VTH.

[0290] As described above, during the PWR period of KthFRAME, a data signal VDATA is written to pixel 180A (pixel circuit 181A). Additionally, the capacitor element CD maintains the voltage contained in the data signal VDATA.

[0291] During the period PVH of KthFRAME following the period PWR of KthFRAME, similarly to the period PWR of KthFRAME, the voltage supplied to the first node N1 is maintained at voltage Vnq (reference voltage VREF, 2V), the voltage supplied to the second node N2 is maintained at voltage Vnl (e.g., 4V), the voltage supplied to the third node N3 is maintained at voltage Vnp, and the voltage supplied to the sixth node N6 is maintained at 0V. The capacitor element CD maintains the potential difference (2V referenced to the sixth node N6) by maintaining a charge equivalent to the potential difference between Vnq supplied to the first node N1 and 0V supplied to the sixth node N6. The potential difference Vgs is 1V, the same as the threshold voltage VTH.

[0292] As described above, during the period PVH of KthFRAME, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0293] During the period between the PVH period of KthFRAME and the PEM period of KthFRAME, the voltage supplied to the third node N3 drops from Vnp (3V) to Vnd (-2V). This causes the voltage supplied to the second node N2 to drop from Vnl (e.g., 4V) to Vnq (2V) through capacitive coupling via capacitors CD and CV. That is, the potential difference Vgs is 4V, and the second transistor T2 is in the on state. At this time, the voltage supplied to the first node N1, capacitively coupled via capacitors CV and CD, drops from Vnq (2V) to 0V.

[0294] During the light emission period, the potential difference Vgs in the PEM is 4V, and the second transistor T2 is in the on state, so a current Ion flows. Thus, the OLED emits light. For example, pixels 180A emitting red light, 180A emitting blue light, and 180A emitting green light emit light respectively, and a white color is formed by using these three pixels.

[0295] The second example of the driving method for the display device 20 has the same effect as that described in "2-3-1. The first example of the driving method for the display device 20".

[0296] [2-3-3. A third example of a driving method for display device 20]

[0297] Reference Figure 27 This describes a third example of the driving method for the display device 20. The third example of the driving method for the pixel circuit 181A, like the third example of the driving method for the display device 10 according to the first embodiment, includes the step of displaying images of the same color (black) in consecutive frames.

[0298] The voltages (potentials) of each node in the light-emitting periods PWR to KthFRAM, which are executed in parallel with the period PVH of KthFRAME, are the same as the structure described in "2-3-2. Second Example of the Driving Method of Display Device 20". Furthermore, the structure of each scan signal in each period and the operation of each transistor are the same as the structure described in "2-3-1. First Example of the Driving Method of Display Device 20". Therefore, the same structure as described in "2-3-1. First Example of the Driving Method of Display Device 20" and "2-3-2. Second Example of the Driving Method of Display Device 20" will be described as needed.

[0299] During the light emission period of the K-1stFRAME in the PEM, for example, the voltage supplied to the first node N1 is voltage Vnt (-4V). Additionally, the voltages supplied to the second node N2, the third node N3, and the sixth node N6 are voltage Vnd (-2V), and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, the current Ion does not flow, and the OLED does not emit light.

[0300] As a result, pixel 180A (pixel circuit 181A) that emits red light becomes black. In addition, similar to pixel 180A that emits red light, pixel 180A that emits blue light and pixel 180A that emits green light also do not emit light. Therefore, black is formed by using three pixels: pixel 180A that emits red light, pixel 180A that emits blue light, and pixel 180A that emits green light.

[0301] During the period following the light emission period PEM of K-1stFRAME, between the light emission period PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the voltage supplied to the first node N1 rises from voltage Vnt (-4V) to voltage Vnq (reference voltage VREF, 2V) to become voltage Vnq. The second node N2 and the fourth node N4 are turned on, supplying voltage Vnr (drive voltage VDDEL, 6V) to the second node N2 (gate electrode 622 of the second transistor T2) and the fourth node N4 (second electrode 626 of the second transistor T2). Voltage Vnp (initialization voltage VINI, 3V) is supplied to the third node N3 (first electrode 624 of the second transistor T2). The sixth node N6 (the second electrode 616 of the first transistor T1) is in a floating state. In order to maintain the voltage rise (2V - (-4V)) supplied to the first node N1 through the capacitive coupling between the first node N1 and the sixth node N6 via the capacitor element CD, the voltage supplied to the sixth node N6 changes from voltage Vnd (-2V) to voltage Vnl (e.g., 4V). The potential difference Vgs is 3V (6V - 3V), and the second transistor T2 is in a conducting state.

[0302] As described above, in the period PIN of KthFRAME, the second node N2 and the fourth node N4 are initialized by the driving voltage VDDEL, the first node N1 is initialized by the reference voltage VREF, and the third node N3 is initialized by the initialization voltage VINI.

[0303] In the period PVH of KthFRAME following period PIN of KthFRAME, the first node N1 maintains voltage Vnq, the third node N3 maintains voltage Vnp, and the sixth node N6 maintains voltage Vnl. The second transistor T2 is in the on state, with current Ion flowing through it. Through the off state of the fifth transistor T5, the voltage supplied to the second node N2 and the fourth node N4 is released and gradually decreases from voltage Vnr (discharge). When the potential difference Vgs between the voltage supplied to the second node N2 and the fourth node N4 and the voltage supplied to the third node N3 becomes the threshold voltage VTH, the second transistor T2 becomes off. At this time, the voltage supplied to the second node N2 and the fourth node N4 is voltage Vnl (e.g., 4V).

[0304] As described above, during the period PVH of KthFRAME, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0305] During the period PWR of KthFRAME, which is executed in parallel with the period PVH of KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with a voltage VSIGH (4V). A voltage maintenance voltage Vnq is supplied to the first node N1, a voltage maintenance voltage Vnl (e.g., 4V) is supplied to the second node N2, a voltage maintenance voltage Vnp is supplied to the third node N3, and a voltage VSIGH (4V) is supplied to the sixth node N6, maintaining the voltage Vnl (voltage VSIGH, e.g., 4V). Meanwhile, the capacitor element CD maintains the potential difference (based on the sixth node N6, -2V) by maintaining a charge equivalent to the potential difference between Vnq supplied to the first node N1 (reference voltage VREF, 2V) and the voltage Vnl supplied to the sixth node N6 (voltage VSIGH, e.g., 4V). The potential difference Vgs is 1V, the same as the threshold voltage VTH.

[0306] As described above, during the PWR period, a data signal VDATA is written to pixel 180A (pixel circuit 181A). Additionally, the capacitor element CD maintains the voltage contained in the data signal VDATA.

[0307] During the period PVH of KthFRAME after the period PWR of KthFRAME, similar to "2-3-1. First example of the driving method of display device 20", the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0308] During the period between the PVH period of KthFRAME and the PEM period of KthFRAME, similar to "2-3-1. First Example of Driving Method of Display Device 20", the voltage supplied to the third node N3 drops from voltage Vnp to voltage Vnd (-2V), thereby, through capacitive coupling of capacitor element CD and capacitor element CV, the voltage supplied to the second node N2 and the voltage supplied to the sixth node N6 drop from voltage Vnl to voltage Vnd (-2V). The potential difference Vgs is 0V, the second transistor T2 is in the off state, and the voltage supplied to the first node N1, which is capacitively coupled through capacitor element CV and capacitor element CD, drops from voltage Vnq to voltage Vnt (-4V).

[0309] During the light-emitting period PEM of the KthFRAME, similar to "2-3-1. First Example of Driving Method for Display Device 20", the potential difference Vgs is 0V, the second transistor T2 is in the off state, and therefore the current Ion does not flow. Thus, the light-emitting element OLED does not emit light. As a result, the pixel 180A (pixel circuit 181A) emitting red light becomes black. Furthermore, similarly to the pixel 180A emitting red light, the pixels 180A emitting blue light and the pixels 180A emitting green light also do not emit light; therefore, a black color is formed by using three pixels: the pixel 180A emitting red light, the pixel 180A emitting blue light, and the pixel 180A emitting green light.

[0310] The third example of the driving method for the display device 20 has the same effect as that described in "2-3-1. The first example of the driving method for the display device 20".

[0311] [2-3-4. Fourth example of a driving method for display device 20]

[0312] Reference Figure 28 A fourth example of the driving method for the display device 20 will be described. The driving method shown in the fourth example of the driving method for the pixel circuit 181A is similar to the fourth example of the driving method for the display device 10 according to the first embodiment, and includes the step of displaying images of different colors in consecutive frames.

[0313] The voltages (potentials) of each node, the structure of each scan signal, and the operation of each transistor during the period preceding the period PWR, which is executed in parallel with the light emission period PEM of K-1stFRAME to the period PVH of KthFRAME, are the same as those described in "2-3-3. Third Example of Driving Method for Display Device 20". Furthermore, the structure of each scan signal and the operation of each transistor are the same as those described in "2-3-1. First Example of Driving Method for Display Device 20". Therefore, the same structure as described in "2-3-1. First Example of Driving Method for Display Device 20" and "2-3-3. Third Example of Driving Method for Display Device 20" will be described as needed.

[0314] During the light-emitting period PEM of K-1stFRAME, similar to "2-3-3. Third Example of Driving Method for Display Device 20", the voltage supplied to the first node N1 is voltage Vnt (-4V), the voltage supplied to the second node N2, the voltage supplied to the third node N3, and the voltage supplied to the sixth node N6 are voltage Vnd (-2V), and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, the current Ion does not flow, and the light-emitting element OLED does not emit light.

[0315] During the period following the light-emitting period PEM of K-1stFRAME, between the light-emitting period PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, similar to "2-3-3. Third Example of the Driving Method of Display Device 20", the voltage supplied to the first node N1 becomes voltage Vnq, and voltage Vnr is supplied to the second node N2 (gate electrode 622 of the second transistor T2) and the fourth node N4 (second electrode 626 of the second transistor T2). The voltage Vnp (initialization voltage VINI, 3V) is supplied to the third node N3 (the first electrode 624 of the second transistor T2) under a floating voltage VDDEL (6V). The sixth node N6 (the second electrode 616 of the first transistor T1) is in a floating state. In order to maintain the voltage rise (2V - (-4V)) supplied to the first node N1 through the capacitive coupling between the first node N1 and the sixth node N6 via the capacitor element CD, the voltage supplied to the sixth node N6 changes from voltage Vnd (-2V) to voltage Vnl (e.g., 4V). In addition, the potential difference Vgs is 3V (6V - 3V), and the second transistor T2 is in a conducting state.

[0316] As described above, in the period PIN of KthFRAME, the second node N2 and the fourth node N4 are initialized by the driving voltage VDDEL, the first node N1 is initialized by the reference voltage VREF, and the third node N3 is initialized by the initialization voltage VINI.

[0317] In the period PVH of KthFRAME following the period PIN of KthFRAME, similar to "2-3-3. Third example of the driving method of display device 20", the first node N1 maintains voltage Vnq, the third node N3 maintains voltage Vnp, the sixth node N6 maintains voltage Vnl, and the voltage supplied to the second node N2 and the fourth node N4 becomes voltage Vnl (e.g., 4V).

[0318] As described above, during the period PVH of KthFRAME, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0319] During the period PWR of KthFRAME, which is executed in parallel with the period PVH of KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with a voltage VSIGL (0V). The voltage supplied to the first node N1 is maintained by a voltage Vnq, the voltage supplied to the second node N2 is maintained by a voltage Vnl (e.g., 4V), the voltage supplied to the third node N3 is maintained by a voltage Vnp, and the voltage supplied to the sixth node N6 drops from voltage Vnl to 0V (voltage VSIGL) to become 0V. At this time, the capacitor element CD maintains the potential difference (2V with reference to the sixth node N6) by maintaining a charge equivalent to the potential difference between Vnq supplied to the first node N1 (reference voltage VREF, 2V) and 0V supplied to the sixth node N6. The potential difference Vgs is 1V, the same as the threshold voltage VTH.

[0320] As described above, during the PWR period, a data signal VDATA is written to pixel 180A (pixel circuit 181A). Additionally, the capacitor element CD maintains the voltage contained in the data signal VDATA.

[0321] During the period PVH of KthFRAME following the period PWR of KthFRAME, the voltage supplied to the first node N1 is maintained at Vnq (reference voltage VREF, 2V), the voltage supplied to the second node N2 is maintained at Vnl (e.g., 4V), the voltage supplied to the third node N3 is maintained at Vnp, and the voltage supplied to the second node N2 is maintained at 0V. At this time, the capacitor element CD maintains the potential difference (referenced to the sixth node N6, 2V) by maintaining a charge equivalent to the potential difference between Vnq (reference voltage VREF, 2V) supplied to the first node N1 and 0V supplied to the sixth node N6. The potential difference Vgs is 1V, the same as the threshold voltage VTH.

[0322] As described above, during the period PVH of KthFRAME after the period PWR of KthFRAME, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0323] During the period between the PVH phase of KthFRAME and the PEM phase of KthFRAME, the voltage supplied to the third node N3 decreases from Vnp (3V) to Vnd (-2V), thereby causing the voltage supplied to the second node N2 to decrease from Vnl to Vnq (2V) through capacitive coupling of capacitors CD and CV. That is, the potential difference Vgs is 4V, and the second transistor T2 is in the on state. At this time, the voltage supplied to the first node N1, which is capacitively coupled through capacitors CV and CD, decreases from Vnq (2V) to 0V. The sixth node N6 (the second electrode 616 of the first transistor T1) is connected to the third node N3 because the ninth transistor T9 is in the on state, and the voltage supplied to the sixth node N6 changes from 0V to Vnd (-2V).

[0324] During the light emission period of KthFRAME, the potential difference Vgs in the PEM is 4V, the second transistor T2 is in the on state, and therefore a current Ion flows. As a result, pixel 180A (pixel circuit 181A) emits red light. Similarly, pixels 180A emitting blue light and 180A emitting green light also emit light, thus emitting white light by using these three pixels.

[0325] The fourth example of the driving method for the display device 20 has the same effect as that described in "2-3-1. The first example of the driving method for the display device 20".

[0326] [3. Third Implementation Method]

[0327] Reference Figure 4 , Figures 29-35 This section provides an overview of the display device 30 according to the third embodiment. Figure 29 This is a schematic diagram showing the structure of the display device 30. Figure 30 This is a schematic diagram showing the input signal to pixel 180B (pixel circuit 181B) according to the third embodiment. Figure 31 This is a circuit diagram showing the structure of pixel circuit 181B. Figures 32-35 This is a timing diagram of display device 30.

[0328] The display device 30 includes a control circuit 120B, a pixel 180B, and a pixel circuit 181B. The structures of the control circuit 120B, the pixel 180B, and the pixel circuit 181B are different from the structures of the control circuit 120, the pixel 180, and the pixel circuit 181 of the display device 10 according to the first embodiment. Specifically, the display device 30 includes the structures shown in (7) to (15) below. The main difference is that the structures shown in (7) to (15) are different from the structures of the display device 10 according to the first embodiment.

[0329] (7) It has the structure and function obtained by replacing the control circuit 120 of the display device 10 according to the first embodiment with the control circuit 120B, and the structure and function associated with the control circuit 120B are different from the structure and function associated with the control circuit 120.

[0330] (8) It has the structure and function obtained by replacing the pixel 180 (pixel circuit 181) of the display device 10 according to the first embodiment with the pixel 180B (pixel circuit 181B), and the structure and function associated with the pixel 180B (pixel circuit 181B) are different from the structure and function associated with the pixel 180 (pixel circuit 181).

[0331] (9) The electrical connection between control circuit 120B and pixel 180B (pixel circuit 181B) is different from the electrical connection between control circuit 120 and pixel 180 (pixel circuit 181).

[0332] (10) The second scan signal SC2(n) also serves as the scan signal SC5(n) according to the first embodiment. That is, the display device 30 does not include the scan signal SC5(n) and the scan signal line 334 on which the scan signal SC5(n) is supplied. The timing of the fall and rise of the second scan signal SC2(n) is different from the timing of the fall and rise of the second scan signal SC2(n) according to the first embodiment.

[0333] (11) Add a scan signal line 335 and a sixth scan signal SC6(n) supplied to the scan signal line 335.

[0334] (12) Add a scan signal line 336 and a seventh scan signal SC7(n) supplied to the scan signal line 336.

[0335] (13) Add a constant voltage VSH and a constant voltage power supply line SVS supplied with a constant voltage VSH.

[0336] (14) Pixel 180A (pixel circuit 181A) includes a ninth transistor T9. The ninth transistor T9 is electrically connected between the fourth node N4 and the constant voltage power supply line SVS, and the gate electrode 692 of the ninth transistor T9 is electrically connected to the scan signal line 335.

[0337] (15) The gate electrode 642 of the fourth transistor T4 is electrically connected to the scan signal line 336 instead of the scan signal line 330.

[0338] The structures other than those shown in (7) to (15) of the display device 30, and the structures other than those associated with the structures shown in (7) to (15) of the display device 30, are the same structures as those of the display device according to the first embodiment. When describing the structure and function of the display device 30, the same structures and functions as those of the display device 10 will be described as needed.

[0339] [3-1. Structure of Control Circuit 120B]

[0340] Reference Figure 29 This section describes the general outline of the control circuit 120B. Similar to the two control circuits 120, the two control circuits 120B are positioned adjacent to both sides of the display area 22 along the second direction D2. Scan signal lines 330, 331, 332, 333, 335, and 336 extend from the control circuit 120 along the second direction D2 and connect to the plurality of pixels 180 arranged along the second direction D2. As an example, Figure 29 Each scan signal line of the display device 30 shown is connected to both sides of the two control circuits 120B. Each scan signal line can also be connected to one of the two control circuits 120B. That is, the nth scan signal line can be electrically connected along the second direction D2 to the control circuit 120 on the right side of the display area 22, and the (n+1)th scan signal line can be electrically connected along the second direction D2 to the control circuit 120 on the left side of the display area 22. The value n is a positive integer.

[0341] The control circuit 120B includes a shift register circuit 130B and a scan driver circuit 160B. The scan driver circuit 160B includes multiple scan drivers. For example, multiple output signals are supplied from the shift register circuit 130B to the multiple scan drivers, and multiple enable signals as described in the first embodiment are supplied from the IC chip 110 to the multiple scan drivers via multiple connection lines 342, a drive voltage VDDEL is supplied to the multiple scan drivers via the drive power line PVDD, and a reference voltage VSSEL is supplied to the multiple scan drivers via the reference voltage line PVSS. The multiple scan drivers have the following function: based on the multiple output signals and the multiple enable signals, they sequentially supply scan signals with different timings (e.g., first scan signal SC1(n), second scan signal SC2(n), third scan signal SC3(n), fourth scan signal SC4(n), sixth scan signal SC6(n), and seventh scan signal SC7(n)) to each scan signal line, and drive the pixel 180B (pixel circuit 181B) electrically connected to each scan signal line. For example, the fourth scan signal SC4(n) and the scan signal line 333 supplied with the fourth scan signal SC4(n) are called scan signals and scan signal lines.

[0342] The structure of control circuit 120B other than that described in "3-1. Structure of control circuit 120B" is the same as that of control circuit 120.

[0343] A constant voltage power supply line (SVS) is sometimes referred to as a control voltage power supply line, and a constant voltage power supply line (VSH) is sometimes referred to as a control voltage.

[0344] [3-2. Pixel 180B Structure]

[0345] Reference Figure 29 as well as Figure 31 This section provides an overview of pixel 180B and pixel circuit 181B.

[0346] The pixel circuit 181B is connected to the scan signal lines 335 and 336, and the constant voltage power supply line SVS.

[0347] A constant voltage VSH is supplied to the constant voltage power supply line SVS. For example, the constant voltage power supply line SVS is electrically connected to the connection wiring 342, which is different from the initialization voltage power supply line SVI, the reference voltage power supply line SVR, the drive power supply line PVDD, and the reference voltage line PVSS. Alternatively, the constant voltage power supply line SVS can also be one of the connection wirings 342. For example, the constant voltage VSH can be supplied from an external device to the IC chip 110, or it can be supplied from the IC chip 110 to multiple pixels 180B (pixel circuits 181B) via the connection wiring 342 and the constant voltage power supply line SVS. Furthermore, although not shown in the figure, the constant voltage VSH can also be supplied to multiple pixels 180B (pixel circuits 181B) by connecting the constant voltage power supply line SVS from an external device via the FPC 200, the terminal portion 150, and the connection wiring 341 without passing through the IC chip 110 and the connection wiring 342.

[0348] The gate electrode 642 of the fourth transistor T4 is electrically connected to the scan signal line 336. As described above, a seventh scan signal SC7(n) is supplied to the scan signal line 336. The fourth transistor T4 uses the seventh scan signal SC7(n) to control its switching. In other words, the fourth transistor T4 is controlled by the seventh scan signal SC7(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the seventh scan signal SC7(n) is LO, the fourth transistor T4 becomes non-conducting; when the signal supplied to the seventh scan signal SC7(n) is HI, the fourth transistor T4 becomes conducting. Furthermore, the seventh scan signal SC7(n) is sometimes referred to as the seventh control signal.

[0349] The gate electrode 672 of the seventh transistor T7 is electrically connected to the scan signal line 331, which is supplied with the second scan signal SC2(n). The seventh transistor T7 uses the second scan signal SC2(n) to control the switch. In other words, the seventh transistor T7 is controlled by the second scan signal SC2(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the second scan signal SC2(n) is LO, the seventh transistor T7 becomes non-conducting; when the signal supplied to the second scan signal SC2(n) is HI, the seventh transistor T7 becomes conducting.

[0350] The ninth transistor T9 has the function of turning on the fourth node N4 and the constant voltage power supply line SVS to supply a constant voltage VSH to the fourth node N4. The ninth transistor T9 includes a gate electrode 692, a first electrode 694, and a second electrode 696. The gate electrode 692 is electrically connected to the scan signal line 335. The first electrode 694 is electrically connected to the fourth node N4, the first electrode 654 of the fifth transistor T5, the second electrode 636 of the third transistor T3, and the second electrode 626 of the second transistor T2. The second electrode 696 is electrically connected to the constant voltage power supply line SVS. As described above, a sixth scan signal SC6(n) is supplied to the scan signal line 335. The ninth transistor T9 uses the sixth scan signal SC6(n) to control the switch. In other words, the ninth transistor T9 is controlled by the sixth scan signal SC6(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the sixth scan signal SC6(n) is LO, the ninth transistor T9 is in a non-conducting state; when the signal supplied to the sixth scan signal SC6(n) is HI, the ninth transistor T9 is in a conducting state. Furthermore, the sixth scan signal SC6(n) is sometimes referred to as the third control signal.

[0351] The structure and function of pixel circuit 181B, other than those described in “3-2. Structure of pixel 180B”, are the same as those of pixel circuit 181.

[0352] [3-3. Driving method of pixel circuit 181B]

[0353] Reference Figure 32 , Figure 35 This describes the driving method of the display device 30. As needed, [the method will be adjusted accordingly]. Figures 1-31 Explain the same or similar structures. The horizontal axis of the sequence diagram represents time.

[0354] The driving method of the display device 30 includes and Figure 4 The same period applies to the driving method of the display device 10 according to the first embodiment shown.

[0355] During a horizontal period (horizontal period HRP) in the driving method of the display device 30, pixel 180B (pixel circuit 181B) is input with a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a sixth scan signal SC6(n), a seventh scan signal SC7(n), and an image data signal SL(m) including a data signal VDATA. For example, pixel 180B (pixel circuit 181B) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), the sixth scan signal SC6(n), and the seventh scan signal SC7(n). The image data signal SL(m) is input to the selected pixel 180B (pixel circuit 181B) according to the timing of each signal. The same operation is performed on all pixels 180B (pixel circuit 181B), and based on the image data signal SL(m) input to all pixels 180B (pixel circuit 181B), an image equivalent to the current frame of 1 FRAME is displayed in the display area 22 of the display device 10.

[0356] For example, Figures 32-35 The signals supplied to each frame and the voltages (potentials) supplied to each node in the timing diagram shown are illustrated in Table 2.

[0357]

[0358] For example, as shown in Table 2, voltage VH (HI) is 10V, voltage VL (LO) is -3V, constant voltage VSH is 6V, driving voltage VDDEL is 8V, reference voltage VSSEL is 0V, voltage VM is 5V, and voltage VN is -5V. That is, the reference voltage VREF is different from the initialization voltage VINI. Both the reference voltage VREF and the initialization voltage VINI are greater than the reference voltage VSSEL and less than the driving voltage VDDEL. The other voltage settings are the same as those shown in Table 1 described in "1-5. Driving Method of Display Device 10".

[0359] [3-3-1. First Example of a Driving Method for Display Device 30]

[0360] Reference Figure 32 Table 2 illustrates a first example of the driving method for the display device 30. This first example of the driving method for the display device 30, like the first example of the driving method for the display device 10 according to the first embodiment, includes the step of displaying images of different colors in consecutive frames.

[0361] Similar to the first example of the driving method for the display device 10 according to the first embodiment, an image data signal SL(m) including a data signal VDATA is input to each pixel 180B (pixel circuit 181B) according to each period. The data signal VDATA is analog data containing a voltage of VSIGL or higher and a voltage of VSIGH or lower. For example, during period PWR, the voltage supplied to the selected pixel 180B (pixel circuit 181B) is supplied to the image data signal SL(m). For example, during periods other than period PWR, voltages other than those supplied to the selected pixel 180B (pixel circuit 181B) are supplied to the data signal VDATA.

[0362] The emission period PEM of K-1stFRAME is the period during which pixel 180B (pixel circuit 181B) emits light according to the potential difference Vgs of the second transistor T2 (voltage supplied to the second node N2 (voltage V(N2)) - voltage supplied to the third node N3 (voltage V(N3))). For example, pixel 180 (pixel circuit 181) emits red light, and white light is emitted by using three pixels: pixel 180 emitting red light, pixel 180 emitting blue light, and pixel 180 emitting green light.

[0363] For example, during the PEM of the K-1stFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to the selected pixel 180B (pixel circuit 181B). The first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), the sixth scan signal SC6(n), and the seventh scan signal SC7(n) are supplied with LO, and the second scan signal SC2(n) is supplied with HI. The first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are in the off state, and the fifth transistor T5 and the seventh transistor T7 are in the on state. In addition, for example, the voltage supplied to the third node N3 is 0V, the voltage supplied to the second node N2 is voltage Vnl (e.g., 4V), and the potential difference Vgs is 4V. Therefore, the second transistor T2 is in the on state, enabling the current Ion, based on the potential difference Vgs and Vds corresponding to the voltage VSIGH input in the HRP during the K-1stFRAME horizontal period, to flow from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. As a result, the light-emitting element OLED emits light. Furthermore, the voltage supplied to the first node N1 becomes 2V through capacitive coupling based on the capacitor element CV and the capacitor element CD. For example, pixel 180B (pixel circuit 181B) emits red light, and white light is emitted by using three pixels: pixel 180B emitting red light, pixel 180B emitting blue light, and pixel 180B emitting green light.

[0364] During the period following the emission period PEM of K-1stFRAME, between the emission period PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with a voltage equal to the voltage of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181). First, the second scan signal SC2(n) changes from being supplied with HI to being supplied with LO. When the second scan signal SC2(n) is supplied with LO, the third scan signal SC3(n) changes from being supplied with LO to being supplied with HI. When the third scan signal SC3(n) is supplied with HI, the first scan signal SC1(n) and the sixth scan signal SC6(n) change from being supplied with LO to being supplied with HI. The fourth scan signal SC4(n) and the seventh scan signal SC7(n) are in the state of being supplied with LO.

[0365] As a result, during the period between the PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the fifth transistor T5 and the seventh transistor T7 change from the on state to the off state, and the current Ion no longer flows from the driving power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. The eighth transistor T8 changes from the off state to the on state, and the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes 0V, and the light-emitting element OLED stops emitting light. In addition, the sixth transistor T6 changes from the off state to the on state, and the voltage supplied to the first node N1 is supplied with the reference voltage VREF (2V, voltage Vnq), maintaining the voltage Vnq. The third transistor T3 and the ninth transistor T9 change from the off state to the on state, the fourth transistor T4 and the first transistor T1 remain in the off state, the second node N2 and the fourth node N4 are turned on, and a constant voltage VSH (6V, voltage Vnr) is supplied to the second node N2 (the gate electrode 622 of the second transistor T2) and the fourth node N4 (the second electrode 626 of the second transistor T2). Furthermore, if the potential difference Vgs becomes 6V (6V-0V), the second transistor T2 is in the conducting state, and the voltage supplied to the third node N3 (the first electrode 624 of the second transistor T2) and the sixth node N6 (the second electrode 616 of the first transistor T1) begins to rise. However, since the fourth transistor T4 is in the cutoff state, the current does not flow continuously, and the voltage supplied to the third node N3 (the first electrode 624 of the second transistor T2) and the sixth node N6 (the second electrode 616 of the first transistor T1) remains at around Vnp (3V), and the drive of the display device 30 shifts from the period PIN to the period PVH.

[0366] As described above, in the intermediate PIN, the second node N2 and the fourth node N4 are initialized with a constant voltage VSH, and the first node N1 is initialized with a reference voltage VREF. At this time, since the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are in the off state, the constant voltage power supply line SVS and the initialization voltage power supply line SVI are not conducting, nor are the constant voltage power supply line SVS, the drive power supply line PVDD, and the reference voltage line PVSS. Therefore, the current flowing between the power lines in the intermediate PIN is cut off, thus suppressing the increase in power consumption of the display device 30.

[0367] In the period PVH following the period PIN, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to the selected pixel 180B (pixel circuit 181B). The sixth scan signal SC6(n) changes from being supplied with HI to being supplied with LO. When the sixth scan signal SC6(n) is supplied with LO, the seventh scan signal SC7(n) changes from being supplied with LO to being supplied with HI. The other scan signals are in the same state as the period PIN. The ninth transistor T9 changes from the on state to the off state, the fourth transistor T4 changes from the off state to the on state, and the other transistors are in the same state as the period PIN.

[0368] As a result, during PVH, the third node N3 (sixth node N6) is supplied with an initialization voltage VINI (3V, voltage Vnp). The voltage supplied to the third node N3 (sixth node N6) becomes voltage Vnp, the second transistor T2 is in the on state, and current Ion flows through it. The voltage supplied to the first node N1 maintains voltage Vnq. Furthermore, since the fifth transistor T5 and the seventh transistor T7 are in the off state, the fourth transistor T4 is in the on state, and the ninth transistor T9 is in the off state, the voltage supplied to the second node N2 and the fourth node N4 is released. Current flows from the second node N2 and the fourth node N4 to the initialization voltage power line SVI, and the voltage supplied to the second node N2 and the fourth node N4 gradually decreases from voltage Vnr (discharge). When the potential difference Vgs between the voltage supplied to the second node N2 and the fourth node N4 and the voltage supplied to the third node N3 (sixth node N6) becomes the threshold voltage VTH, the second transistor T2 becomes the off state. At this time, the third node N3 (sixth node N6) is supplied with an initialization voltage VINI (3V), so the voltage supplied to the second node N2 and the fourth node N4 when the potential difference Vgs becomes the threshold voltage VTH is voltage Vnl (e.g., 4V).

[0369] As described above, during the PVH period, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0370] During the period between period PVH and period PWR, or within period PWR, the image data signal SL(m) (data signal VDATA) is supplied with voltage VSIGH (e.g., 4V, voltage Vnl). First, the first scan signal SC1(n) changes from being supplied with HI to being supplied with LO. When the first scan signal SC1(n) is supplied with LO, the seventh scan signal SC7(n) changes from being supplied with HI to being supplied with LO. When the seventh scan signal SC7(n) is supplied with LO, the fourth scan signal SC4(n) changes from being supplied with LO to being supplied with HI. The third scan signal SC3(n) is supplied with HI, and the second scan signal SC2(n) and the sixth scan signal SC6(n) are supplied with LO. The first transistor T1 changes from the off state to the on state, and the third transistor T3 and the fourth transistor T4 change from the on state to the off state. The other transistors are in the same state as during period PVH. The second node N2 is supplied with a voltage VSIGH (e.g., 4V, voltage Vnl), maintaining a voltage Vnl (e.g., 4V). The voltage supplied to the first node N1 maintains a voltage Vnq (referencing voltage VREF, 2V). The voltage supplied to the third node N3 (sixth node N6) rises from voltage Vnp to voltage VSIGH (e.g., 4V, voltage Vnl) to become voltage Vnl (e.g., 4V). At this time, the capacitor element CD maintains the potential difference (2V with reference to the sixth node N6) by maintaining a charge equivalent to the potential difference between Vnq (referencing voltage VREF, 2V) supplied to the first node N1 and the voltage Vnl (e.g., 4V) supplied to the third node N3 (sixth node N6). Furthermore, the potential difference Vgs is 0V, and the second transistor T2 is in the off state.

[0371] As described above, during the PWR period, a data signal VDATA is written to pixel 180 (pixel circuit 181). Additionally, the capacitor element CD maintains the voltage contained in the data signal VDATA.

[0372] During the period following PWR, the third scan signal SC3(n) changes from being supplied with HI to being supplied with LO. The sixth transistor T6 and the eighth transistor T8 change from being on to being off. Other scan signals and other transistors become the same as during period PWR. The voltage supplied to the second node N2 and the voltage supplied to the third node N3 (sixth node N6) maintains the voltage Vnl, the potential difference Vgs remains 0V, and the voltage supplied to the first node N1, which is capacitively coupled through capacitor elements CV and CD, maintains the voltage Vnq.

[0373] During the light-emitting period PEM of KthFRAME following the period PWR of KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181). Additionally, the second scan signal SC2(n) changes from being supplied with LO to being supplied with HI. Consequently, the fifth transistor T5 and the seventh transistor T7 change from the off state to the on state. Other scan signals and other transistors are in the same state as during the period following the period PWR of KthFRAME. With the fifth transistor T5 and the seventh transistor T7 on, the first electrode 32 of the light-emitting element OLED and the second electrode 626 (fourth node N4) of the second transistor T2 are turned on. Since the third node N3 is connected to the reference voltage VSSEL, the voltage supplied to the second node N2 and the voltage supplied to the third node N3 (sixth node N6) decreases from voltage Vnl to 0V, and the voltage supplied to the first node N1 decreases from voltage Vnq to voltage Vnd (-2V). That is, the potential difference Vgs is the sum of the potential difference maintained by capacitor CD and capacitor CV (initial voltage VINI (3V) - voltage of data signal VDATA (voltage VSIGH, 4V) + threshold voltage VTH (1V) = 0V). The potential difference Vgs of pixel 180B (pixel circuit 181B) containing voltage VSIGH in data signal VDATA is 0V, the second transistor T2 is in the off state, so the drain current Ion does not flow. As a result, the light-emitting element OLED does not emit light. As a result, pixel 180 (pixel circuit 181) that emits red light becomes black. In addition, similarly to pixel 180 that emits red light, pixel 180 that emits blue light and pixel 180 that emits green light also do not emit light, so a black color is formed by using three pixels: pixel 180 that emits red light, pixel 180 that emits blue light, and pixel 180 that emits green light.

[0374] The reference voltage VSSEL in display device 30 is 0V, which is a higher potential than the reference voltage VSSEL (-2V) in display device 10. Therefore, the difference between the write potential of display device 30 and the reference voltage VSSEL becomes smaller than that of display device 10. As a result, the potential change during the transition from writing to light emission in display device 30 becomes smaller than that in display device 10, enabling display device 30 to consume less power than display device 10. Furthermore, display device 30 includes a structure that supplies a constant voltage VSH to the second node N2 and the fourth node N4. As a result, during the periodic pin operation, display device 30 can ensure that the voltage rise of the first node N1, the second node N2, and the third node N3 (sixth node N6) is lower than that of the first node N1, the second node N2, and the third node N3 (sixth node N6) in display device 10. Furthermore, during the period from the period PWR to the period PEM, the display device 30 can reduce the voltage drop of the first node N1, the second node N2, and the third node N3 (sixth node N6) compared to that of the display device 10. Therefore, the display device 30 can reduce the power consumption in the period PIN and the power consumption during the period from the period PWR to the period PEM compared to the display device 10.

[0375] [3-3-2. A Second Example of a Driving Method for the Display Device 30]

[0376] Reference Figure 33 This describes a second example of the driving method for the display device 30. The driving method shown in this second example of the display device 30, like the second example of the driving method for the display device 10 according to the first embodiment, includes the step of displaying an image of the same color (white) in consecutive frames. The method can be adjusted as needed. Figures 1-32 Explain the same or similar structures.

[0377] The voltages (potentials) of each node during the light-emitting period PEM of K-1thFRAME to the period PVH of K-1thFRAME, and during the period between the period PVH of K-1thFRAME and the period PWR of K-1thFRAME, are the same as the structure described in "3-3-1. First Example of Driving Method of Display Device 30". Furthermore, the structure of each scan signal in each period and the operation of each transistor are the same as the structure described in "3-3-1. First Example of Driving Method of Display Device 30". Therefore, the same structure as described in "3-3-1. First Example of Driving Method of Display Device 30" will be described as needed. In addition, the image data signal SL(m) is supplied with a data signal VDATA containing VSIGL (0V) corresponding to white during the period PWR of K-1thFRAME, and is supplied with the same data signal VDATA as the structure described in "3-3-1. First Example of Driving Method of Display Device 30" during periods other than the period PWR of K-1thFRAME.

[0378] During the light emission period PEM of K-1stFRAME, similar to the structure described in "3-3-1. First Example of Driving Method of Display Device 30", pixel 180 (pixel circuit 181) emits red light, and white light is emitted by using three pixels: pixel 180 that emits red light, pixel 180 that emits blue light, and pixel 180 that emits green light.

[0379] In the period PIN of KthFRAME, similar to the structure described in "3-3-1. First Example of Driving Method of Display Device 30", the second node N2 and the fourth node N4 are initialized by a constant voltage VSH, and the first node N1 is initialized by a reference voltage VREF.

[0380] In the period PVH following the period PIN, similar to the structure described in "3-3-1. First Example of Driving Method of Display Device 30", the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0381] During the period between period PVH and period PWR, or within period PWR, the image data signal SL(m) (data signal VDATA) is supplied with a voltage VSIGL (0V). The voltage supplied to the second node N2 is maintained by a voltage Vnl (e.g., 4V), and the voltage supplied to the first node N1 is maintained by a voltage Vnq (reference voltage VREF, 2V). The voltage supplied to the third node N3 (sixth node N6) gradually decreases from voltage Vnp (initial voltage VINI, 3V) to 0V (voltage VSIGL). At this time, the capacitor element CD maintains the potential difference (2V) by holding a charge equivalent to the potential difference between the voltage Vnq supplied to the first node N1 (reference voltage VREF, 2V) and the 0V (voltage VSIGL) supplied to the third node N3 (sixth node N6). Furthermore, capacitor element CV maintains the potential difference (referenced to first node N1, 2V) by maintaining a charge equivalent to the potential difference between the voltage Vnl (e.g., 4V) supplied to the second node N2 and the voltage Vnq (reference voltage VREF, 2V) supplied to the first node N1. That is, the potential difference Vgs is the sum of the potential differences maintained by capacitor element CD and capacitor element CV connected in series, which is 4V.

[0382] As described above, during the PWR period, a data signal VDATA is written to pixel 180 (pixel circuit 181). Additionally, the capacitor element CD maintains the voltage contained in the data signal VDATA.

[0383] During the period following PWR, the voltage supplied to the first node N1 maintains the voltage Vnq (referencing voltage VREF, 2V), the voltage supplied to the second node N2 maintains the voltage Vnl (e.g., 4V), and the voltage supplied to the third node N3 (sixth node N6) maintains 0V. Similarly to PWR, during the period following PWR, capacitor CD maintains the potential difference (2V based on the sixth node N6) by maintaining a charge equivalent to the potential difference between the voltage supplied to the first node N1 and the voltage supplied to the third node N3 (sixth node N6), and capacitor CV maintains the potential difference (2V based on the first node N1) by maintaining a charge equivalent to the potential difference between the voltage supplied to the second node N2 (e.g., 4V) and the voltage supplied to the first node N1 (2V). That is, the potential difference Vgs is the sum of the potential differences maintained by the series-connected capacitors CD and CV, which is 4V.

[0384] During the light-emitting period PEM of KthFRAME following the period PWR of KthFRAME, the potential difference Vgs during and after the period PWR is maintained by two capacitor elements CD and CV, becoming the sum of the potential difference maintained by capacitor element CD and capacitor element CV (initial voltage VINI (3V) - voltage contained in data signal VDATA (voltage VSIGL, 0V) + threshold voltage VTH (1V) = 4V). That is, based on data signal VDATA and the corrected threshold voltage, pixel 180B (pixel circuit 181B) can display an image. When data signal VDATA contains voltage VSIGL, the potential difference Vgs is 4V, the second transistor T2 is in the on state, so current Ion flows from the driving power line PVDD to the light-emitting element OLED and the reference voltage line PVSS, and the light-emitting element OLED emits light. For example, a red light-emitting pixel 180B, a blue light-emitting pixel 180B, and a green light-emitting pixel 180B emit light respectively, and white is formed by using the three pixels that emit red light, blue light, and green light.

[0385] The second example of the driving method for the display device 30 has the same effect as that described in "3-3-1. The first example of the driving method for the display device 30".

[0386] [3-3-3. A third example of a driving method for the display device 30]

[0387] Reference Figure 34 This describes a third example of the driving method for the display device 30. The driving method shown in this third example of the driving method for the display device 30, like the third example of the driving method for the display device 10 according to the first embodiment, includes the step of displaying an image of the same color (black) in consecutive frames. The method can be adjusted as needed. Figures 1-33 Explain the same or similar structures.

[0388] The voltages (potentials) of each node in the PEM during the light-emitting periods of KthFRAME (PVH) to KthFRAM (PEM) are the same as those described in "3-3-1. First Example of Driving Method for Display Device 30". Furthermore, the structures of each scan signal in each period and the operation of each transistor are the same as those described in "3-3-1. First Example of Driving Method for Display Device 30". Therefore, the same structures as those described in "3-3-1. First Example of Driving Method for Display Device 30" will be described as needed.

[0389] During the light emission period of the K-1stFRAME in the PEM, for example, the voltage supplied to the first node N1 is Vnd (-2V). Meanwhile, the voltages supplied to the second node N2 and the third node N3 (sixth node N6) are 0V, and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, the drain current Ion does not flow, and the OLED does not emit light.

[0390] As a result, pixel 180B (pixel circuit 181B) that emits red light becomes black. In addition, similar to pixel 180B that emits red light, pixels 180B that emit blue light and pixels 180B that emit green light also do not emit light. Therefore, black is formed by using three pixels: pixel 180B that emits red light, pixel 180B that emits blue light, and pixel 180B that emits green light.

[0391] During the period following the light-emitting period PEM of K-1stFRAME, between the light-emitting period PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the potential difference between the first electrode 32 and the second electrode 34 of the OLED light-emitting element becomes 0V. The voltage supplied to the first node N1 rises from voltage Vnd (-2V) to voltage Vnq (referencing voltage VREF, 2V) to become voltage Vnq. The second node N2 and the fourth node N4 are turned on, and the voltage supplied to the second node N2 (gate electrode 622 of the second transistor T2) and the fourth node N4 (second electrode 626 of the second transistor T2) rises from 0V to voltage VSH (6V, voltage Vnr) to become voltage Vnr. In addition, the voltage supplied to the third node N3 (first electrode 624 of the second transistor T2) and the sixth node N6 (second electrode 616 of the first transistor T1) rises from voltage Vnd (-2V). However, since the fourth transistor T4 is in the off state, the current does not flow continuously, and the voltage supplied to the third node N3 (the first electrode 624 of the second transistor T2) and the sixth node N6 (the second electrode 616 of the first transistor T1) remains at around voltage Vnp (3V), and the drive of the display device 30 shifts from the period PIN to the period PVH.

[0392] As described above, during the period PIN, the second node N2 and the fourth node N4 are initialized by the drive voltage VDDEL, and the first node N1 is initialized by the reference voltage VREF.

[0393] In the period PVH following the period PIN, similar to the structure described in "3-3-1. First Example of Driving Method of Display Device 30", the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0394] During the period PWR following the period PVH, a data signal VDATA is written to the pixel 180B (pixel circuit 181B) in the same manner as described in "3-3-1. First Example of Driving Method for Display Device 30". Additionally, the capacitor element CD maintains the voltage contained in the data signal VDATA.

[0395] During the light-emitting period PEM of the KthFRAME following the PWR period and the period after the PWR period, the pixel circuit 181B operates in the same manner as the structure described in "3-3-1. First Example of Driving Method for Display Device 30". The potential difference Vgs is 0V, the second transistor T2 is in the off state, so the drain current Ion does not flow, and the light-emitting element OLED does not emit light. As a result, black is formed by using three pixels: pixel 180B that emits red light, pixel 180B that emits blue light, and pixel 180B that emits green light.

[0396] The third example of the driving method of the display device 10 has the same effect as that described in "3-3-1. The first example of the driving method of the display device 30".

[0397] [3-3-4. Fourth example of a driving method for display device 30]

[0398] Reference Figure 35 This describes a fourth example of the driving method for the display device 30. The driving method shown in this fourth example of the driving method for the display device 30, like the fourth example of the driving method for the display device 10 according to the first embodiment, includes the step of displaying images of different colors in consecutive frames. The method can be adjusted as needed. Figures 1-34 Explain the same or similar structures.

[0399] The voltages (potentials) of each node in the light-emitting period PEM of K-1stFRAME to the light-emitting period PVH of KthFRAME, the structure of each scan signal, and the operation of each transistor are the same as those described in "3-3-3. Third Example of Driving Method for Display Device 30". Furthermore, the voltages (potentials) of each node in the light-emitting period PEM of KthFRAME (later than the KthFRAME's PVH), the structure of each scan signal, and the operation of each transistor are the same as those described in "3-3-2. Second Example of Driving Method for Display Device 30". Therefore, their description is omitted here.

[0400] The fourth example of the driving method for the display device 30 has the same effect as that described in "3-3-1. The first example of the driving method for the display device 30".

[0401] [4. Fourth Implementation Method]

[0402] Reference Figure 4 , Figure 29 , Figures 36-41 This section provides an overview of the display device according to the fourth embodiment. Figure 36 This is a schematic diagram showing the input signal to pixel 180C (pixel circuit 181C) according to the fourth embodiment. Figure 37 This is a circuit diagram showing the structure of pixel circuit 181C. Figures 38-41 This is a timing diagram of display device 30.

[0403] The display device according to the fourth embodiment includes a... Figure 29 The display device 30 of the third embodiment shown has the same structure. The display device of the fourth embodiment includes a pixel 180C (pixel circuit 181C). Specifically, the display device of the fourth embodiment includes the structures shown in (16) to (21) below. The main difference is that the structures shown in (16) to (21) are different from the structure of the display device 30 of the third embodiment.

[0404] (16) It has the structure and function obtained by replacing the pixel 180B (pixel circuit 181B) of the display device 30 according to the third embodiment with the pixel 180C (pixel circuit 181C), and the structure and function associated with the pixel 180C (pixel circuit 181C) are different from the structure and function associated with the pixel 180B (pixel circuit 181B).

[0405] (17) The electrical connection between control circuit 120 and pixel 180C (pixel circuit 181C) is different from the electrical connection between control circuit 120B and pixel 180B (pixel circuit 181B).

[0406] (18) The gate electrode 692 of the ninth transistor T9 is electrically connected to the scan signal line 330, and the first scan signal SC1(n) supplied to the scan signal line 330 is supplied to the gate electrode 692 of the ninth transistor T9. In addition, the timing of the fall and rise of the first scan signal SC1(n) is different from the timing of the fall and rise of the first scan signal SC1(n) involved in the third embodiment.

[0407] (19) The gate electrode 642 of the fourth transistor T4 is electrically connected to the scan signal line 335, and the sixth scan signal SC6(n) supplied to the scan signal line 335 is supplied to the gate electrode 642 of the fourth transistor T4. Therefore, the display device according to the fourth embodiment does not include the scan signal line 336 and the seventh scan signal SC7(n) supplied to the scan signal line 336 according to the third embodiment.

[0408] (20) An additional reset voltage power supply line SVRE, to which a reset voltage VRES is supplied, is added. The reset voltage power supply line SVRE is electrically connected to the second electrode 696 of the ninth transistor T9. Thus, the display device according to the fourth embodiment does not include the constant voltage VSH and the constant voltage power supply line SVS to which the constant voltage VSH is supplied, as in the third embodiment.

[0409] (21) The electrical connection between the first transistor T1, capacitor element CV and capacitor element CD and the transistors of each node is different from the electrical connection between the first transistor T1, capacitor element CV and capacitor element CD and the transistors of each node in pixel 180B (pixel circuit 181B).

[0410] The structures other than those shown in (16) to (21) of the display device according to the fourth embodiment, and the structures other than those associated with the structures shown in (16) to (21) of the display device according to the fourth embodiment, are the same structures as those of the display device 30 according to the third embodiment. When describing the structure and function of the display device according to the fourth embodiment, the same structures and functions as those of the display device 30 according to the third embodiment will be described as needed.

[0411] [4-1. Structure of Pixel 180C]

[0412] Reference Figure 29 , Figure 36 as well as Figure 37 This section provides an overview of pixel 180C and pixel circuit 181C.

[0413] Pixel circuit 181C is connected to the reset voltage power supply line SVRE. Pixel circuit 181C is not connected to scan signal line 336 or constant voltage power supply SVS.

[0414] A reset voltage VRES is supplied to the reset voltage power line SVRE. For example, the reset voltage power line SVRE is electrically connected to connection wiring 342, which is different from the initialization voltage power line SVI, reference voltage power line SVR, drive power line PVDD, and reference voltage line PVSS. Alternatively, the reset voltage power line SVRE can also be one of the connection wirings 342. For example, the reset voltage VRES can be supplied from an external device to the IC chip 110, or from the IC chip 110 via connection wiring 342 and the reset voltage power line SVRE to multiple pixels 180C (pixel circuits 181C). Furthermore, although not shown in the figure, the reset voltage VRES can be supplied to multiple pixels 180C (pixel circuits 181C) from an external device via FPC 200, terminal unit 150, and connection wiring 341 without going through IC chip 110 and connection wiring 342, and can also be connected to the reset voltage power line SVRE.

[0415] For example, the first transistor T1 is a selection transistor. The first transistor T1 has the function of supplying an image data signal SL(m) to the second node N2. Additionally, the first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scan signal line 333. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, the first electrode 634 of the third transistor T3, and the second electrode 54 of the capacitor element CD. A fourth scan signal SC4(n) is supplied to the scan signal line 333. The fourth scan signal SC4(n) is used to control the switching of the first transistor T1. In other words, the first transistor T1 is controlled by the fourth scan signal SC4(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the fourth scan signal SC4(n) is LO, the first transistor T1 becomes non-conducting. When the signal supplied to the fourth scan signal SC4(n) is HI, the first transistor T1 becomes in the on state.

[0416] The gate electrode 642 of the fourth transistor T4 is electrically connected to the scan signal line 335. As described above, a sixth scan signal SC6(n) is supplied to the scan signal line 335. The fourth transistor T4 uses the sixth scan signal SC6(n) to control its switching. In other words, the fourth transistor T4 is controlled by the sixth scan signal SC6(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the sixth scan signal SC6(n) is LO, the fourth transistor T4 becomes non-conducting; when the signal supplied to the sixth scan signal SC6(n) is HI, the fourth transistor T4 becomes conducting.

[0417] The ninth transistor T9 has the function of turning on the fourth node N4 and the reset voltage power supply line SVRE to supply the reset voltage VRES to the fourth node N4. The ninth transistor T9 includes a gate electrode 692, a first electrode 694, and a second electrode 696. The gate electrode 692 is electrically connected to the scan signal line 330. The first electrode 694 is electrically connected to the fourth node N4, the first electrode 654 of the fifth transistor T5, the second electrode 636 of the third transistor T3, and the second electrode 626 of the second transistor T2. The second electrode 696 is electrically connected to the reset voltage power supply line SVRE. As described above, a first scan signal SC1(n) is supplied to the scan signal line 330. The ninth transistor T9 uses the first scan signal SC1(n) to control the switch. In other words, the ninth transistor T9 is controlled by the first scan signal SC1(n) to be in a conducting state (on state) and a non-conducting state (off state). When the signal supplied to the first scan signal SC1(n) is LO, the ninth transistor T9 becomes non-conducting; when the signal supplied to the first scan signal SC1(n) is HI, the ninth transistor T9 becomes conducting.

[0418] The capacitor element CV has the function of maintaining (storing) a charge equivalent to the threshold voltage VTH of the second transistor T2. Furthermore, the sixth node N6 of the pixel circuit 181C is connected to the third node N3, and in the display device according to the fourth embodiment, the threshold voltage VTH is obtained from the first electrode 624 (source electrode) side of the second transistor T2. The capacitor element CV includes a first electrode 42 and a second electrode 44. The first electrode 42 is electrically connected to the third node N3 (sixth node N6), the first electrode 624 of the second transistor T2, the second electrode 646 of the fourth transistor T4, and the second electrode 676 of the seventh transistor T7. The second electrode 44 is electrically connected to the first node N1, the second electrode 666 of the sixth transistor T6, and the first electrode 52 of the capacitor element CV.

[0419] The capacitor element CD holds (preserves) the data voltage (VSIGL, reference) contained in the image data signal SL(m) supplied to the second node N2. Figure 38 ) and above and voltage VSIGH (refer to) Figure 38 The capacitor element CD comprises a first electrode 52 and a second electrode 54. (The voltage below the specified value is used to measure the charge.)

[0420] Except for the structure and function described in “4-1. Structure of Pixel 180C”, the structure and function of pixel circuit 181C are the same as those of pixel circuit 181B.

[0421] [4-2. Driving method for display device according to the fourth embodiment]

[0422] Reference Figures 38-41 This section describes the driving method for the display device (pixel circuit 181C) according to the fourth embodiment. The method is adjusted as needed. Figures 1-37 Explain the same or similar structures. The horizontal axis of the sequence diagram represents time.

[0423] The driving method for the display device according to the fourth embodiment includes... Figure 4 The same period applies to the driving method of the display device 10 according to the first embodiment shown.

[0424] In a horizontal period (horizontal period HRP) of the driving method for the display device according to the fourth embodiment, a pixel 180C (pixel circuit 181C) is input with an image data signal SL(m) comprising a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a sixth scan signal SC6(n), and a data signal VDATA. For example, the pixel 180C (pixel circuit 181C) is selected based on the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the sixth scan signal SC6(n). The image data signal SL(m) is input to the selected pixel 180C (pixel circuit 181C) according to the timing of each signal. The same operation is performed on all pixels 180C (pixel circuit 181C), and based on the image data signal SL(m) input to all pixels 180C (pixel circuit 181C), an image equivalent to the current frame of 1 FRAME is displayed in the display area 22 of the display device 10.

[0425] For example, Figures 38-41 The signals supplied to each frame and the voltages (potentials) supplied to each node in the timing diagram shown are illustrated in Table 3.

[0426]

[0427] For example, as shown in Table 3, the voltage VSIGH is 4V, the voltage VSIGL is 0V, the initialization voltage VINI is -2V, the reference voltage VREF is 2.2V, and the reset voltage VRES is 1V. That is, the reset voltage VRES, the reference voltage VREF, and the initialization voltage VINI are all different. The reset voltage VRES and the reference voltage VREF are greater than the reference voltage VSSEL and less than the drive voltage VDDEL. The initialization voltage VINI is less than the reference voltage VSSEL and the drive voltage VDDEL. The other voltage settings are the same as those shown in Table 1 described in "1-5. Driving Method of Display Device 10".

[0428] [4-2-1. First example of a driving method for a display device according to the fourth embodiment]

[0429] Reference Figure 38 Table 3 illustrates a first example of the driving method for the display device according to the fourth embodiment. The first example of the driving method for the display device according to the fourth embodiment, like the first example of the driving method for the display device 10 according to the first embodiment, includes the step of displaying images of different colors in consecutive frames. The method may be modified as needed. Figures 1-37 Explain the same or similar structures.

[0430] Similar to the first example of the driving method for the display device 10 according to the first embodiment, an image data signal SL(m) containing a data signal VDATA is input to each pixel 180C (pixel circuit 181C) according to each period. The data signal VDATA is analog data containing a voltage of VSIGL or higher and a voltage of VSIGH or lower. For example, in period PWR, a voltage of VSIGL or higher and a voltage of VSIGH or lower is selected using a selection signal (not shown) and supplied to the image data signal SL(m). For example, in periods other than period PWR, the data signal VDATA is supplied with voltages other than those supplied to the selected pixel 180C (pixel circuit 181C).

[0431] The emission period PEM of K-1stFRAME is the period during which pixel 180C (pixel circuit 181C) emits light according to the potential difference Vgs of the second transistor T2 (voltage supplied to the second node N2 (voltage V(N2)) - voltage supplied to the third node N3 (voltage V(N3))). For example, pixel 180C (pixel circuit 181C) emits red light, and white light is emitted by using three pixels: pixel 180C emitting red light, pixel 180C emitting blue light, and pixel 180C emitting green light.

[0432] For example, during the PEM (Power Emitting Mode) of the K-1stFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to a node other than the selected pixel 180C (pixel circuit 181C). The first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the sixth scan signal SC6(n) are supplied with LO, and the second scan signal SC2(n) is supplied with HI. The first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are in the off state, while the fifth transistor T5 and the seventh transistor T7 are in the on state. Additionally, for example, the voltage supplied to the third node N3 is 0V, the voltage supplied to the second node N2 is voltage Vnl (e.g., 4V), and the potential difference Vgs is 4V. Therefore, the second transistor T2 is in the on state, enabling the current Ion, based on the potential difference Vgs and Vds corresponding to the voltage VSIGH input in the HRP during the K-1stFRAME horizontal period, to flow from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. As a result, the light-emitting element OLED emits light. Furthermore, the voltage supplied to the first node N1 becomes voltage Vnu (2.2V, reference voltage VREF) through capacitive coupling based on capacitor elements CV and CD. For example, pixel 180C (pixel circuit 181C) emits red light, and white light is emitted by using three pixels: pixel 180C emitting red light, pixel 180C emitting blue light, and pixel 180C emitting green light.

[0433] During the period following the emission period PEM of K-1stFRAME, between the emission period PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with a voltage equal to the voltage of the data signal VDATA supplied to the selected pixel 180 (pixel circuit 181). First, the second scan signal SC2(n) changes from being supplied with HI to being supplied with LO. When the second scan signal SC2(n) is supplied with LO, the third scan signal SC3(n) changes from being supplied with LO to being supplied with HI. When the third scan signal SC3(n) is supplied with HI, the sixth scan signal SC6(n) changes from being supplied with LO to being supplied with HI. The first scan signal SC1(n) and the fourth scan signal SC4(n) are in the state of being supplied with LO.

[0434] As a result, during the period between the PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the fifth transistor T5 and the seventh transistor T7 change from the on state to the off state, and the current Ion no longer flows from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. The eighth transistor T8 changes from the off state to the on state, the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes 0V, and the light-emitting element OLED stops emitting light. The sixth transistor T6 changes from the off state to the on state, the first node N1 is supplied with the reference voltage VREF (2.2V, voltage Vnu), and the voltage Vnu is maintained. The fourth transistor T4 changes from the off state to the on state, the third node N3 (sixth node N6) is supplied with the initialization voltage VINI (-2V, voltage Vnd), and becomes the voltage Vnd. The first transistor T1, the third transistor T3, the fifth transistor T5, and the ninth transistor T9 remain in the off state. The voltage supplied to the second node N2 (the gate electrode 622 of the second transistor T2) is maintained at voltage Vnl (e.g., 4V). If the potential difference Vgs becomes 6V (4V - (-2V)), the second transistor T2 is in the on state, but since the fifth transistor T5 is in the off state, current will not flow continuously. Therefore, the voltage supplied to the fourth node N4 becomes voltage Vnd (-2V).

[0435] As described above, during the period PIN, the third node N3 (sixth node N6) and the fourth node N4 are initialized by the initialization voltage VINI, and the first node N1 is initialized by the reference voltage VREF.

[0436] In the period PVH following the period PIN, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to the selected pixel 180C (pixel circuit 181C). The sixth scan signal SC6(n) changes from being supplied with HI to being supplied with LO. When the sixth scan signal SC6(n) is supplied with LO, the first scan signal SC1(n) changes from being supplied with LO to being supplied with HI. The other scan signals are in the same state as the period PIN. The third transistor T3 and the ninth transistor T9 change from the off state to the on state, the fourth transistor T4 changes from the on state to the off state, and the other transistors are in the same state as the period PIN.

[0437] As a result, during the PVH period, the third transistor T3 and the ninth transistor T9 are in the on state, the second node N2, the fourth node N4, and the reset voltage power line SVRE are on, and the second node N2 and the fourth node N4 are supplied with the reset voltage VRES (1V, voltage Vno), becoming voltage Vno. The first node N1 maintains voltage Vnq. Meanwhile, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are in the off state, the second transistor T2 is in the on state, and current Ion flows through it. The fourth transistor T4 becomes the off state, thus the third node N3 is released, and current Ion flows in the third node N3 (sixth node N6), charging the third node N3 (sixth node N6) and raising its potential. When the potential difference Vgs between the voltage supplied to the second node N2 and the fourth node N4 and the voltage supplied to the third node N3 (sixth node N6) becomes the threshold voltage VTH, the second transistor T2 becomes the off state. At this point, since a reset voltage VRES (1V, voltage Vno) is supplied to the second node N2 and the fourth node N4, the voltage supplied to the third node N3 (sixth node N6) is 0V when the potential difference Vgs becomes the threshold voltage VTH. That is, the potential of the third node N3 becomes the reset voltage VRES (1V, voltage Vno) minus the threshold voltage VTH. The threshold voltage VTH may deviate during manufacturing; for example, if the threshold voltage VTH is 1.1V, the potential of the third node N3 may become -0.1V. Correction of the threshold voltage VTH is achieved through operations within the PVH during this period.

[0438] As described above, during the PVH period, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV holds a charge equivalent to the threshold voltage VTH.

[0439] During the period between period PVH and period PWR, or within period PWR, the image data signal SL(m) (data signal VDATA) is supplied with voltage VSIGL (0V). First, the first scan signal SC1(n) changes from being supplied with HI to being supplied with LO. When the first scan signal SC1(n) is supplied with LO, the fourth scan signal SC4(n) changes from being supplied with LO to being supplied with HI. The third scan signal SC3(n) is supplied with HI, and the second scan signal SC2(n) and the sixth scan signal SC6(n) are supplied with LO. The first transistor T1 changes from the off state to the on state, and the third transistor T3 and the ninth transistor T9 change from the on state to the off state. The other transistors are in the same state as during period PVH. The voltage supplied to the second node N2 decreases from voltage Vno to voltage VSIGL (0V) and becomes 0V due to the application of the voltage VSIGL (0V) of the image data signal SL(m) (data signal VDATA). The voltage supplied to the first node N1 maintains voltage Vnu (reference voltage VREF, 2.2V), and the voltage supplied to the third node N3 (sixth node N6) maintains 0V. At this time, the capacitor element CD maintains the potential difference (based on the first node N1, -2.2V) by maintaining a charge equivalent to the potential difference between Vnu (reference voltage VREF, 2.2V) supplied to the first node N1 and 0V supplied to the second node N2. In addition, the capacitor element CV maintains the potential difference (based on the sixth node N6, 2.2V) by maintaining a charge equivalent to the potential difference between Vnu (reference voltage VREF, 2.2V) supplied to the first node N1 and 0V supplied to the third node N3 (sixth node N6). The sum of the potential difference maintained by capacitor CD and capacitor CV (-2.2V + 2.2V) is 0V, that is, the potential difference Vgs becomes 0V, and the second transistor T2 is in the off state.

[0440] As described above, during the PWR period, a data signal VDATA is written to pixel 180C (pixel circuit 181C). Additionally, the capacitor element CD maintains the voltage contained in the data signal VDATA.

[0441] During the period following PWR, the fourth scan signal SC4(n) changes from being supplied with HI to being supplied with LO. When the fourth scan signal SC4(n) is supplied with LO, the third scan signal SC3(n) changes from being supplied with HI to being supplied with LO. The first transistor T1, the sixth transistor T6, and the eighth transistor T8 change from being on to being off. Other scan signals and other transistors are in the same state as during PWR. The voltage supplied to the first node N1 is maintained at voltage Vnu (reference voltage VREF, 2.2V), and the voltage supplied to the second node N2 and the third node N3 (sixth node N6) is maintained at 0V. The potential difference obtained by combining capacitor elements CD and CV (the potential difference between the second node N2 and the third node N3) is maintained at 0V. That is, the potential difference Vgs is 0V, and the second transistor T2 is in the off state.

[0442] During the light-emitting period PEM of KthFRAME following the period PWR of KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to the selected pixel 180C (pixel circuit 181C). Additionally, the second scan signal SC2(n) changes from being supplied with LO to being supplied with HI. Consequently, the fifth transistor T5 and the seventh transistor T7 change from the off state to the on state. Other scan signals and other transistors are in the same state as during the period following the period PWR of KthFRAME. With the fifth transistor T5 and the seventh transistor T7 on, the first electrode 32 of the light-emitting element OLED and the second electrode 626 (fourth node N4) of the second transistor T2 are turned on. Since the seventh transistor T7 is on, the third node N3 (sixth node N6) is connected to the reference voltage VSSEL, the voltage supplied to the third node N3 (sixth node N6) becomes 0V, and the second node N2 is maintained at 0V through the capacitive coupling of the capacitor elements CD and CV. Furthermore, the first node N1 is also maintained at 2.2V through the capacitive coupling of capacitor elements CD and CV. Additionally, for example, if the threshold voltage TVH is 1V (set value) due to manufacturing defects, the voltage supplied to the third node N3 (sixth node N6) remains unchanged at 0V even when the seventh transistor T7 is turned on. If the threshold voltage TVH is 1.1V due to manufacturing defects, the voltage supplied to the third node N3 (sixth node N6) becomes -0.1V, the seventh transistor T7 turns on, and the voltage supplied to the third node N3 (sixth node N6) changes from -0.1V to 0V. The potential difference Vgs is the sum of the potential difference maintained by capacitor element CD and the potential difference maintained by capacitor element CV (the voltage of the data signal VDATA (voltage VSIGL, 0V) - reset voltage VRES (1V) + threshold voltage VTH (1V) = 0V). The data signal VDATA contains a voltage VSIGL. The potential difference Vgs of pixel 180C (pixel circuit 181C) is 0V, the second transistor T2 is in the off state, and therefore the current Ion does not flow. Consequently, the OLED light-emitting element does not emit light. As a result, pixel 180C (pixel circuit 181C) emitting red light becomes black. Similarly, pixels 180C emitting blue light and green light also do not emit light; therefore, a black image is formed by using three pixels: red-emitting pixel 180C, blue-emitting pixel 180C, and green-emitting pixel 180C.

[0443] The reference voltage VSSEL in the display device according to the fourth embodiment is 0V. The display device according to the fourth embodiment includes a structure that supplies a reset voltage VRES to the second node N2 and the fourth node N4. Based on the reset voltage VRES, information (data) of a threshold voltage VTH is applied to the low potential side of the potential difference Vgs of the second transistor T2, and a voltage (data) of a data signal VDATA is applied to the high potential side of the potential difference Vgs of the second transistor T2. The light-emitting element OLED is disposed on the drain side (driving voltage VDDEL side) opposite to the potential difference Vgs side of the second transistor T2. As a result, the voltage variation (potential variation) of the first node N1, the second node N2, and the third node N3 (sixth node N6) can be minimized during the period PWR to the light-emitting period PEM. Therefore, the display device according to the fourth embodiment can suppress power consumption from the period PWR to the period PEM, and can minimize the voltage loss caused by the reduction of the write voltage during light emission due to the charge redistribution caused by the gate capacitance of the second transistor T2 based on the potential change of the second node N2.

[0444] [4-2-2. A second example of the driving method for the display device according to the fourth embodiment]

[0445] Reference Figure 39 This section describes a second example of the driving method for the display device according to the fourth embodiment. The driving method shown in the second example of the display device according to the fourth embodiment, like the second example of the driving method for the display device 10 according to the first embodiment, includes the step of displaying an image of the same color (white) in consecutive frames. The method may be adjusted as needed. Figures 1-38 Explain the same or similar structures.

[0446] The voltages (potentials) of each node during the light-emitting period PEM of K-1thFRAME to the period PVH of K-1thFRAME, and during the period between the period PVH of K-1thFRAME and the period PWR of K-1thFRAME, are the same as the structure described in "4-2-1. First Example of the Driving Method of the Display Device According to the Fourth Embodiment". Furthermore, the structure of each scan signal and the operation of each transistor during each period are the same as the structure described in "4-2-1. First Example of the Driving Method of the Display Device According to the Fourth Embodiment". Therefore, the same structure as described in "4-2-1. First Example of the Driving Method of the Display Device According to the Fourth Embodiment" will be described as needed. In addition, the image data signal SL(m) is supplied with a data signal VDATA including VSIGH (4V) corresponding to white during the period PWR of K-1thFRAME, and is supplied with the same data signal VDATA as the structure described in "4-2-1. First Example of the Driving Method of the Display Device According to the Fourth Embodiment" during periods other than the period PWR of K-1thFRAME.

[0447] During the light emission period PEM of K-1stFRAME, similar to the structure described in "4-2-1. First Example of the Driving Method of the Display Device According to the Fourth Embodiment", pixel 180C (pixel circuit 181C) emits red light, and white light is emitted by using three pixels: pixel 180C that emits red light, pixel 180C that emits blue light, and pixel 180C that emits green light.

[0448] In the period PIN of KthFRAME, similar to the structure described in "4-2-1. First Example of Display Device According to Fourth Embodiment", the third node N3 (sixth node N6) is initialized by initialization voltage VINI, and the first node N1 is initialized by reference voltage VREF.

[0449] In the period PVH following the period PIN, similar to the structure described in "4-2-1. First Example of Display Device According to Fourth Embodiment", the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV retains a charge equivalent to the threshold voltage VTH.

[0450] During the period between period PVH and period PWR, or during period PWR, the image data signal SL(m) (data signal VDATA) is supplied with a voltage VSIGH (4V). The voltage supplied to the second node N2 rises from voltage Vno to voltage VSIGH (e.g., 4V, voltage Vnl) to become voltage Vnl, the voltage supplied to the first node N1 maintains voltage Vnu (reference voltage VREF, 2.2V), and the voltage supplied to the third node N3 (sixth node N6) maintains 0V. At this time, the capacitor element CD maintains the potential difference (1.8V with reference to the first node N1) by maintaining a charge equivalent to the potential difference between the voltage Vnu (reference voltage VREF, 2.2V) supplied to the first node N1 and the voltage Vnl (e.g., 4V, voltage VSIGH) supplied to the second node N2. Furthermore, the capacitor element CV maintains the potential difference (based on the sixth node N6, 2.2V) by maintaining a charge equivalent to the potential difference between the voltage Vnu supplied to the first node N1 (reference voltage VREF, 2.2V) and the 0V supplied to the third node N3 (sixth node N6). That is, the potential difference Vgs is 4V.

[0451] As described above, during the PWR period, a data signal VDATA is written to pixel 180C (pixel circuit 181C). Additionally, the capacitor element CD maintains the voltage contained in the data signal VDATA.

[0452] During the period following PWR, the voltage supplied to the first node N1 is maintained at voltage Vnu (reference voltage VREF, 2.2V), the voltage supplied to the second node N2 is maintained at voltage Vnl (e.g., 4V), and the voltage supplied to the third node N3 (sixth node N6) is maintained at 0V. Similarly to PWR, during the period following PWR, capacitor CD maintains the potential difference (1.8V based on the first node N1) by maintaining a charge equivalent to the potential difference between the voltage supplied to the first node N1 and the voltage supplied to the third node N3 (sixth node N6), and capacitor CV maintains the potential difference (2.2V based on the sixth node N6) by maintaining a charge equivalent to the potential difference between the voltage supplied to the first node N1 and the voltage supplied to the third node N3 (sixth node N6). That is, the potential difference Vgs is 4V.

[0453] During the light-emitting period PEM of KthFRAME following the period PWR of KthFRAME, the potential difference Vgs becomes the sum of the potential difference held by capacitor element CD and capacitor element CV (voltage of data signal VDATA (voltage VSHIGH, 4V) - reset voltage VRES (1V) + threshold voltage VTH (1V) = 4V). The data signal VDATA includes a potential difference Vgs of 4V for pixel 180C (pixel circuit 181C) with voltage VSIGH. The second transistor T2 is in the on state, so current Ion flows from the driving power line PVDD to the light-emitting element OLED and the reference voltage line PVSS, and the light-emitting element OLED emits light. For example, pixel 180C that emits red light, pixel 180C that emits blue light, and pixel 180C that emits green light emit light respectively, and white is formed by using three pixels that emit red light, blue light, and green light.

[0454] The second example of the display device according to the fourth embodiment has the same effect as that described in "4-2-1. The first example of the display device according to the fourth embodiment".

[0455] [3rd Example of a Display Device According to the Fourth Embodiment]

[0456] Reference Figure 40 This section describes a third example of the display device according to the fourth embodiment. The driving method shown in the third example of the display device according to the fourth embodiment is similar to the third example of the driving method of the display device 10 according to the first embodiment, including the step of displaying an image of the same color (black) in consecutive frames. The method may be adjusted as needed. Figures 1-39 Explain the same or similar structures.

[0457] The voltages (potentials) of each node in the PEM during the light-emitting periods of KthFRAME (PVH) to KthFRAM (Pulse Phase I) are the same as those described in "4-2-1. First Example of a Display Device According to the Fourth Embodiment". Furthermore, the structures of each scan signal in each period and the operation of each transistor are the same as those described in "4-2-1. First Example of a Display Device According to the Fourth Embodiment". Therefore, the same structures as those described in "4-2-1. First Example of a Display Device According to the Fourth Embodiment" will be described as needed.

[0458] During the light emission period of the K-1stFRAME in the PEM, the voltage supplied to the first node N1 is voltage Vnu (referencing voltage VREF, 2.2V). Meanwhile, the voltage supplied to the second node N2 and the third node N3 (sixth node N6) is 0V, and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, the current Ion does not flow, and the OLED does not emit light.

[0459] As a result, pixel 180C (pixel circuit 181C) that emits red light becomes black. In addition, similar to pixel 180C that emits red light, pixel 180C that emits blue light and pixel 180C that emits green light also do not emit light. Therefore, black is formed by using three pixels: pixel 180C that emits red light, pixel 180C that emits blue light, and pixel 180C that emits green light.

[0460] During the period following the light-emitting period PEM of K-1stFRAME, between the light-emitting period PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the potential difference between the first electrode 32 and the second electrode 34 of the OLED light-emitting element becomes 0V. The first node N1 is supplied with a reference voltage VREF (2.2V, voltage Vnu) to maintain voltage Vnu. The third node N3 (sixth node N6) is supplied with an initialization voltage VINI (-2V, voltage Vnd), and the voltage supplied to the third node N3 (sixth node N6) becomes voltage Vnd. The voltage supplied to the second node N2 (gate electrode 622 of the second transistor T2) remains at 0V. If the potential difference Vgs becomes 2V (0V - (-2V)), then the second transistor T2 is in the conducting state, and the voltage supplied to the fourth node N4 becomes voltage Vnd (-2V).

[0461] As described above, during the period PIN, the third node N3 (sixth node N6) and the fourth node N4 are initialized by the initialization voltage VINI, and the first node N1 is initialized by the reference voltage VREF.

[0462] In the PVH period following the PIN period, the second node N2 and the fourth node N4 are supplied with a reset voltage VRES (1V, voltage Vno), and the voltage supplied to the second node N2 and the fourth node N4 becomes voltage Vno. The first node N1 maintains voltage Vnq. Additionally, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are in the off state, the second transistor T2 is in the on state, and current Ion flows through it. The fourth transistor T4 becomes the off state, thereby releasing the third node N3. Current Ion flows in the third node N3 (sixth node N6), and the third node N3 (sixth node N6) is charged, causing its potential to rise. When the potential difference Vgs between the voltage supplied to the second node N2 and the fourth node N4 and the voltage supplied to the third node N3 (sixth node N6) becomes the threshold voltage VTH, the second transistor T2 becomes the off state. At this time, since a reset voltage VRES (1V, voltage Vno) is supplied to the second node N2 and the fourth node N4, the voltage supplied to the third node N3 (sixth node N6) is 0V when the potential difference Vgs becomes the threshold voltage VTH.

[0463] As described above, during the PVH period, similar to the structure described in "4-2-1. First Example of Display Device According to Fourth Embodiment", the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 the same as the threshold voltage VTH, and the capacitor element CV retains a charge equivalent to the threshold voltage VTH.

[0464] During the period PWR following the period PVH, a data signal VDATA is written to the pixel 180C (pixel circuit 181C) in the same manner as the structure described in "4-2-1. First Example of a Display Device According to the Fourth Embodiment". Additionally, the capacitor element CD maintains the voltage contained in the data signal VDATA.

[0465] During the light-emitting period PEM of the KthFRAME following the PWR period and the period after the PWR period, the pixel circuit 181C operates in the same manner as the structure described in "4-2-1. First Example of a Display Device According to the Fourth Embodiment". The potential difference Vgs is 0V, the second transistor T2 is in the off state, so the drain current Ion does not flow, and the light-emitting element OLED does not emit light. As a result, black is formed by using three pixels: pixel 180C that emits red light, pixel 180C that emits blue light, and pixel 180C that emits green light.

[0466] The third example of the display device according to the fourth embodiment has the same effect as that described in "4-2-1. The first example of the display device according to the fourth embodiment".

[0467] [4-2-4. A fourth example of a display device according to the fourth embodiment]

[0468] Reference Figure 41 This section describes a fourth example of the display device according to the fourth embodiment. The driving method shown in the fourth example of the display device according to the fourth embodiment is similar to the fourth example of the driving method of the display device 10 according to the first embodiment, including the step of displaying images of different colors in consecutive frames. The method can be adjusted as needed. Figures 1-40 Explain the same or similar structures.

[0469] The voltages (potentials) of each node in the light-emitting period PEM of K-1stFRAME to the light-emitting period PVH of KthFRAME, the structure of each scan signal, and the operation of each transistor are the same as those described in "3rd Example of Display Device According to Fourth Embodiment 4-2-3". Furthermore, the voltages (potentials) of each node in the light-emitting period PEM of KthFRAME (later than the KthFRAME's PVH), the structure of each scan signal, and the operation of each transistor are the same as those described in "2nd Example of Display Device According to Fourth Embodiment 4-2-2". Therefore, the description is omitted here.

[0470] The fourth example of the display device according to the fourth embodiment has the same effect as that described in "4-2-1. The first example of the display device according to the fourth embodiment".

[0471] As embodiments of the present invention, the above-described embodiments or parts thereof can be appropriately combined to implement them as long as they do not contradict each other.

[0472] Even if other effects are different from those brought about by the various embodiments described above, the effects that are clearly defined according to the description in this specification, or the effects that can be easily predicted by those skilled in the art, are of course understood to be effects brought about by the present invention.

[0473] Explanation of reference numerals in the attached figures

[0474] 10. Display device; 20. Display device; 22. Display area; 24. Peripheral area; 26. Terminal area; 30. Display device; 32. First electrode; 34. Second electrode; 42. First electrode; 44. Second electrode; 52. First electrode; 54. Second electrode; 100. Array substrate; 101. Substrate; 101A. First surface; 101B. Second surface; 110. IC chip; 111. Shift register; 112. Shift register; 120. Control circuit; 120A. Control circuit; 120B. Control circuit; 121. Substrate layer; 122. Semiconductor layer; 122A. Semiconductor layer; 122B. Semiconductor layer; 122C. Semiconductor layer; 122D. Semiconductor layer; 122E 122F, Semiconductor layer; 123, Channel region; 124A, Impurity region; 125, Gate insulating layer; 126, Conductive layer; 127A, Gate wiring; 127B, Gate wiring; 127C, Gate wiring; 127D, Gate wiring; 127E, Gate wiring; 127F, Gate wiring; 127G, Gate wiring; 128, Insulating layer; 130, Shift register circuit; 130A, Shift register circuit; 130B, Shift register circuit; 131, Insulating layer; 132, Conductive layer; 132A, First wiring; 132B, First wiring; 132C, First wiring; 132D, First wiring; 132E, First wiring; 132F, First wiring; 132G First wiring; 132H, First wiring; 132I, First wiring; 132J, First wiring; 132K, First wiring; 132L, First wiring; 135A, First contact hole opening; 135B, First contact hole opening; 135C, First contact hole opening; 135D, First contact hole opening; 135E, First contact hole opening; 135F, First contact hole opening; 135G, First contact hole opening; 135H, First contact hole opening; 135I, First contact hole opening; 135J, First contact hole opening; 135K, First contact hole opening; 135L, First contact hole opening; 135M, First contact hole opening; 135N, First contact hole opening ; 135O, First contact hole opening; 135P, First contact hole opening; 136, Insulating layer; 138, Second contact hole opening; 138A, Organic insulating film opening; 138B, Organic insulating film opening; 138C, Second contact hole opening; 138D, Second contact hole opening; 138E, Second contact hole opening; 138F, Second contact hole opening; 138G, Second contact hole opening; 138H, Second contact hole opening; 138I, Second contact hole opening; 139, Conductive layer; 140A, Second wiring; 140B, Second wiring; 140C, Second wiring; 140D, Second wiring; 140E, Second wiring; 141, Insulating layer; 143, Cathode electrode;144. First layer; 145. Second layer; 146. Third layer; 147. Contact hole opening; 147A. Contact hole opening; 148. Functional layer; 149. Common electrode; 150. Terminal portion; 152. First inorganic insulating layer; 154. Organic insulating layer; 156. Second inorganic insulating layer; 158. Cover film; 160. Scan driver circuit; 160A. Scan driver; 160B. Scan driver circuit; 165. Sealing film; 170, Array section; 180, Pixel; 180A, Pixel; 180B, Pixel; 180C, Pixel; 181, Pixel circuit; 181A, Pixel circuit; 181B, Pixel circuit; 181C, Pixel circuit; 200, Flexible printed circuit board; 321, Image data signal line; 322, Image data signal line; 323, Image data signal line; 330, Scan signal line; 331, Scan signal line; 332 333, Scan signal line; 334, Scan signal line; 335, Scan signal line; 336, Scan signal line; 341, Connecting wiring; 342, Connecting wiring; 612, Gate electrode; 614, First electrode; 616, Second electrode; 622, Gate electrode; 624, First electrode; 626, Second electrode; 632, Gate electrode; 634, First electrode; 636, Second electrode; 642, Gate electrode; 644, First electrode; 646, Second electrode; 652, Gate electrode; 654, First electrode; 656, Second electrode; 662, Gate electrode; 664, First electrode; 666, Second electrode; 672, Gate electrode; 674, First electrode; 676, Second electrode; 682, Gate electrode; 684, First electrode; 686, Second electrode; 692, Gate electrode; 694, First electrode; 696, Second electrode.

Claims

1. A display device, characterized in that, Multiple pixels are arranged in a matrix in a first direction and a second direction intersecting the first direction. The display device includes: The image data signal line supplied with data voltage, the second terminal of the second capacitor element, and the second terminal of the fourth transistor; An initialization voltage power supply line that is supplied with initialization voltage; The reference voltage power supply line supplied with the reference voltage and the first terminal of the second capacitor element; A reference voltage line supplied with a reference voltage; and A power supply line supplied with a constant voltage, the first terminal of the first capacitor element, the first terminal of the fifth transistor, and the first terminal of the light-emitting element. The plurality of pixels respectively include: The first transistor is controlled by the first control signal and is electrically connected between the image data signal line and the second terminal of the second capacitor element; The second transistor has a gate electrode electrically connected to a first terminal of the first capacitor element, and is electrically connected between the second terminal of the fourth transistor, which is electrically connected to the second terminal of the second capacitor element, and the first terminal of the fifth transistor. The third transistor is controlled by the second control signal and is electrically connected between the first terminal of the first capacitor element and the first terminal of the fifth transistor. The fourth transistor is controlled by a third control signal and is electrically connected between the initialization voltage power supply line and the first terminal of the second transistor. The fifth transistor is controlled by the fourth control signal and is electrically connected between the second terminal of the second transistor and the first terminal of the light-emitting element; The sixth transistor, controlled by the fifth control signal, is electrically connected between the reference voltage power supply line and the first terminal of the second capacitor element; The seventh transistor, controlled by the sixth control signal, is electrically connected between the reference voltage line and the second terminal of the fourth transistor; The eighth transistor, controlled by the fifth control signal, is electrically connected between the power line and the first terminal of the light-emitting element; The first capacitor element is electrically connected between the first terminal of the second capacitor element and the gate electrode; The second capacitor element is electrically connected between the second terminal of the first capacitor element and the second terminal of the first transistor; and The light-emitting element is electrically connected between the power line and the second terminal of the fifth transistor.

2. The display device according to claim 1, characterized in that, The second control signal also serves as the third control signal.

3. The display device according to claim 2, characterized in that, The display device further includes a control circuit, which outputs the first control signal, the second control signal, the fourth control signal, the fifth control signal, and the sixth control signal. The control circuit is configured to control the second capacitor element to maintain a potential difference equivalent to the data voltage after the first capacitor element is maintained at a potential difference equivalent to the threshold voltage of the second transistor.

4. The display device according to claim 1, characterized in that, The display device further includes a ninth transistor, which uses the sixth control signal to control a switch and is electrically connected between the second terminal of the second capacitor element and the second terminal of the fourth transistor. The second control signal also serves as the third control signal and the fifth control signal.

5. The display device according to claim 4, characterized in that, The display device further includes a control circuit, which outputs the first control signal, the second control signal, the fourth control signal, and the sixth control signal. The control circuit is configured to control the data voltage by simultaneously maintaining the first capacitor element at a potential difference equivalent to the threshold voltage of the second transistor and maintaining the second capacitor element at a potential difference equivalent to the data voltage.

6. The display device according to claim 5, characterized in that, The control circuit is configured to control the operation in such a way that, prior to the simultaneous execution, the first control signal is used to turn on the first transistor and supply the data voltage to the second terminal of the second capacitor element.

7. The display device according to claim 5, characterized in that, The control circuit includes a shift register circuit and a scan driver circuit electrically connected to the shift register circuit. The scan driver circuit is configured to be controlled in such a way that, based on the output signal output by the shift register circuit, a plurality of first control signals, second control signals, fourth control signals, and sixth control signals with different timings are generated for each of the plurality of adjacent pixels in the second direction.

8. The display device according to claim 1, characterized in that, The display device further includes a ninth transistor, which uses a seventh control signal to control a switch and is electrically connected between a control voltage power supply line supplied with a control voltage different from the initialization voltage and the second terminal of the second transistor. The fourth control signal also serves as the sixth control signal.

9. The display device according to claim 8, characterized in that, The display device further includes a control circuit, which outputs the first control signal, the second control signal, the third control signal, the fourth control signal, the fifth control signal, and the seventh control signal. The control circuit is configured to control the second capacitor element to maintain a potential difference equivalent to the data voltage after the first capacitor element is maintained at a potential difference equivalent to the threshold voltage of the second transistor.

10. The display device according to claim 9, characterized in that, The control circuit is configured to control the first transistor to a cutoff state using the first control signal before maintaining a potential difference equivalent to the threshold voltage of the second transistor in the first capacitor element; to a cutoff state using the third control signal; to a cutoff state using the fourth control signal; to a cutoff state using the fourth control signal; to a turn-on state using the fifth control signal; and to supply the reference voltage to the first terminal of the second capacitor element; to a turn-on state using the second control signal; and to a turn-on state using the seventh control signal; and to supply the control voltage to the gate electrode and the second terminal of the second transistor.

11. A display device, characterized in that, Multiple pixels are arranged in a matrix in a first direction and a second direction intersecting the first direction. The display device includes: The image data signal line supplied with data voltage, the first terminal of the first capacitor element, and the second terminal of the fourth transistor; An initialization voltage power supply line that is supplied with initialization voltage; The reference voltage power supply line supplied with the reference voltage and the second terminal of the first capacitor element; A reference voltage line supplied with a reference voltage; A power supply line supplied with a constant voltage, the second terminal of the second capacitor element, the first terminal of the fifth transistor, and the first terminal of the light-emitting element; and The reset voltage power supply line is supplied with a reset voltage. The plurality of pixels respectively include: The first transistor is controlled by the first control signal and is electrically connected between the image data signal line and the second terminal of the second capacitor element; The second transistor has a gate electrode electrically connected to the second terminal of the second capacitor element and electrically connected between the second terminal of the fourth transistor and the first terminal of the fifth transistor; The third transistor is controlled by the second control signal and is electrically connected between the gate electrode and the first terminal of the fifth transistor; The fourth transistor, controlled by the third control signal, is electrically connected between the initialization voltage power supply line and the first terminal of the second transistor; The fifth transistor, controlled by the fourth control signal, is electrically connected between the second terminal of the second transistor and the first terminal of the light-emitting element; The sixth transistor, controlled by the fifth control signal, is electrically connected between the reference voltage power supply line and the second terminal of the first capacitor element; The seventh transistor, controlled by the fourth control signal, is electrically connected between the reference voltage line and the second terminal of the fourth transistor; The eighth transistor, controlled by the fifth control signal, is electrically connected between the power line and the first terminal of the light-emitting element; The ninth transistor, controlled by the second control signal, is electrically connected between the reset voltage power supply line and the first terminal of the fifth transistor; The second capacitor element is electrically connected between the second terminal of the first capacitor element and the gate electrode; A first capacitor element is electrically connected between a first terminal of the second capacitor element and a second terminal of the fourth transistor; and The light-emitting element is electrically connected between the power line and the second terminal of the fifth transistor.

12. The display device according to claim 11, characterized in that, The display device further includes a control circuit, which outputs the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal. The control circuit is configured to control the second capacitor element to maintain a potential difference equivalent to the data voltage after the first capacitor element is maintained at a potential difference equivalent to the threshold voltage of the second transistor.

13. The display device according to claim 1 or 11, characterized in that, The reference voltage is different from the initialization voltage. The reference voltage and the initial voltage are greater than the base voltage and less than the constant voltage.

14. The display device according to claim 1 or 11, characterized in that, The data voltage is an analog voltage that is above a first voltage and below a second voltage that is greater than the first voltage. The reference voltage is the intermediate potential between the first voltage and the second voltage.

15. The display device according to claim 1 or 11, characterized in that, The capacitance of the second capacitor element is greater than the capacitance of the first capacitor element.

16. The display device according to claim 1, characterized in that, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are n-channel field-effect transistors. The channel regions of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor each have an oxide semiconductor.

17. The display device according to any one of claims 4, 8, and 11, characterized in that, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are n-channel field-effect transistors. The channel regions of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor each have an oxide semiconductor.

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