Vertical cavity surface emitting laser structure and preparation method thereof

Abstract

The invention discloses a vertical-cavity surface-emitting laser structure and a preparation method thereof, and relates to the technical field of semiconductor optoelectronic devices, and the vertical-cavity surface-emitting laser structure comprises a substrate, a first distributed Bragg reflector, an n-type layer, a multi-quantum well layer, an electron blocking layer, a p-type layer, an n-type semiconductor limiting layer, an insulation current limiting layer, and a current expansion layer. A second distributed Bragg reflector and an electrode; according to the invention, the n-type semiconductor limiting layer with a larger forbidden bandwidth is introduced into the p-type layer below the insulating current limiting layer, and a heterojunction barrier and a built-in electric field formed by the n-type semiconductor limiting layer and the p-type layer are utilized to prevent transverse leakage of carriers, so that the loss of the carriers in a non-active region is reduced; therefore, the output light power of the laser is improved and the threshold current is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor optoelectronic device technology, specifically relating to a vertical cavity surface-emitting laser structure and its fabrication method. Background Technology

[0002] Vertical-cavity surface-emitting lasers (VCSELs) are widely used in laser displays, optical storage, and optical communications due to their advantages such as low threshold current, high modulation rate, and easy integration. While the industrial fabrication of GaAs / InP-based long-wavelength VCSELs is nearing maturity, short-wavelength VCSELs based on GaN semiconductor materials urgently need improvement in areas such as high threshold current and low lasing power.

[0003] In GaN-based vertical-cavity surface-emitting lasers (VCSELs), the electrodes are located on the side of a Bragg mirror. Current must be transported laterally to the confinement aperture, where carriers recombine and emit photons in the active region. Therefore, efficiently confining carriers within the active region is an effective way to improve laser performance. Currently, using a dielectric (such as SiO2) insulating layer to form a current-confinement aperture can achieve lateral current injection, and the scheme is relatively simple and easy to implement. However, the voltage division characteristics of SiO2 as an insulating layer cause lateral band bending at the edge of the insulating aperture, leading to hole leakage out of the current-confinement aperture and reducing laser gain. Simultaneously, the electric field formed at the p-GaN / SiO2 interface forces holes to drift out of the aperture, worsening current confinement and reducing hole injection efficiency and laser power. Therefore, developing novel structures that can efficiently suppress lateral carrier leakage and are compatible with GaN-based material systems is an effective way to improve the performance of GaN-based VCSELs. Summary of the Invention

[0004] To address at least one of the aforementioned technical problems of gallium nitride-based vertical cavity surface-emitting lasers in the prior art, this invention provides a vertical cavity surface-emitting laser structure and its fabrication method, which can effectively suppress the lateral leakage of holes from the vertical cavity surface-emitting laser to the outside of the aperture, improve the laser output power, and reduce the threshold current.

[0005] According to one aspect of the present invention, a vertical-cavity surface-emitting laser is provided, comprising: Substrate; The first distributed Bragg mirror located on the substrate; The n-type layer located on the side of the first distributed Bragg mirror furthest from the substrate; The active region located on the side of the n-type layer furthest from the substrate; An electron blocking layer located on the side of the active region away from the substrate; The p-type layer located on the side of the electron blocking layer away from the substrate; An n-type semiconductor current limiting layer located inside the p-type layer, the bandgap of the n-type semiconductor current limiting layer being greater than that of the p-type layer, the thickness of the n-type semiconductor current limiting layer being less than that of the p-type layer, the n-type semiconductor current limiting layer surrounding the edge of the p-type layer in a circle, the area of the positive projection of the n-type semiconductor current limiting layer in the vertical direction being less than the area of the positive projection of the p-type layer in the vertical direction, and the p-type layer and the n-type semiconductor current limiting layer contacting to form a heterojunction p-n junction; An insulating current limiting layer located on the side of the p-type layer away from the substrate; A current spreading layer located on the side of the p-type layer and the insulating current limiting layer away from the substrate; A second distributed Bragg reflector located on the side of the current spreading layer away from the substrate.

[0006] Furthermore, the thickness of the n-type semiconductor current limiting layer is less than the thickness of the p-type layer between the insulating current limiting layer and the electron blocking layer.

[0007] Furthermore, the n-type semiconductor current limiting layer is in a closed ring shape, the insulating current limiting layer is in a closed ring shape, the shape of the central through hole of the ring-shaped n-type semiconductor current limiting layer is the same as the transverse cross-sectional shape of the central through hole of the insulating current limiting layer, the cross-sectional shape is selected from one of a circle, an ellipse, a rectangle or other polygons, and the characteristic dimension of the cross-sectional shape is 0.1 - 1000 μm.

[0008] Furthermore, the n-type semiconductor current limiting layer is n-Al x Ga 1-x N (0 < x ≤ 1), and the doping concentration is 1×10 14 ~ 1×10 21 cm -3 .

[0009] Furthermore, the p-type layer is p-GaN, with a thickness of 1 - 500 nm and a doping concentration of 1×10 14 ~ 1×10 21 cm -3 .

[0010] Optionally, the p-GaN can be a single-layer structure or a multi-layer structure.

[0011] Optionally, the p-type layer is a composite structure of p-GaN and p-AlInGaN.

[0012] Furthermore, the positive projection of the insulating current limiting layer in the vertical direction completely overlaps with the positive projection of the n-type semiconductor current limiting layer in the vertical direction.

[0013] Furthermore, the insulating current limiting layer is an annular insulating dielectric layer, which is selected from one of SiO2, AlN, SiN, Al2O3, HfO2, and Ta2O5.

[0014] Furthermore, the active region is a multi-quantum-well structure, which is an InGaN / GaN multi-quantum-well structure, including 1 to 30 cycles of InGaN quantum wells and GaN barrier layers, wherein the thickness of the InGaN quantum wells is 1 to 10 nm and the thickness of the barrier layers is 2 to 40 nm.

[0015] Furthermore, the first and second distributed Bragg reflectors can be composed of alternating semiconductor or dielectric layers, with a period number of 1 to 200. The periodic material of the semiconductor layer Bragg reflector is selected from AlN / GaN, AlGaN / GaN, and AlInN / GaN, while the periodic material of the dielectric layer Bragg reflector is selected from TiO2 / SiO2, HfO2 / SiO2, Ta2O5 / SiO2, and ZrO2 / SiO2. The periodic materials of the first and second distributed Bragg reflectors can be the same or different.

[0016] According to another aspect of the present invention, a method for fabricating the above-described vertical-cavity surface-emitting laser is provided, comprising: A first distributed Bragg mirror is formed on the substrate; An n-type layer is formed on the side of the first distributed Bragg mirror away from the substrate; An active region is formed on the side of the n-type layer away from the substrate; An electron blocking layer is formed on the side of the active region away from the substrate; A first p-type layer is formed on the side of the electron blocking layer away from the substrate; A mesa is formed around the edge of the first p-type layer on the side away from the substrate. The depth of the mesa is less than the thickness of the first p-type layer, and the vertical projection area of ​​the mesa is less than the vertical projection area of ​​the first p-type layer. An n-type semiconductor current limiting layer is formed at the mesa location, and the thickness of the n-type semiconductor current limiting layer is less than the mesa depth. A second p-type layer is covered on the side of the n-type semiconductor current-limiting layer away from the substrate, and the band gap of the n-type semiconductor current-limiting layer is greater than the band gap of the first p-type layer and the second p-type layer; An insulating current limiting layer is formed on the side of the second p-type layer away from the substrate, and the surface of the insulating current limiting layer on the side away from the substrate is flush with the surface of the first p-type layer that is not covered by the insulating current limiting layer on the side away from the substrate. A current spreading layer is formed on the side of the first p-type layer and the insulating current limiting layer away from the substrate; A second distributed Bragg reflector is formed on the side of the current spreading layer away from the substrate.

[0017] Further, the n-type semiconductor current confinement layer is n-Al x Ga 1-x N (0 < x ≤ 1), and the thickness of the n-Al x Ga 1-x N is less than the thickness of the p-type layer between the insulating current confinement layer and the electron blocking layer; the doping concentration of the n-Al x Ga 1-x N is 1×10 14 ~ 1×10 21 cm -3 .

[0018] Further, the n-type semiconductor current confinement layer is in a closed ring shape, the insulating current confinement layer is an annular insulating dielectric layer, the shape of the central through hole of the n-type semiconductor current confinement layer is the same as the transverse cross-sectional shape of the central through hole of the insulating current confinement layer, the cross-sectional shape is selected from one of a circle, an ellipse, a rectangle or other polygons, the characteristic dimension of the cross-sectional shape is 0.1~1000 μm, and the orthographic projection of the insulating current confinement layer in the vertical direction completely overlaps with the orthographic projection of the n-type semiconductor current confinement layer in the vertical direction.

[0019] As can be seen from the above technical solutions, the beneficial effects of the present invention are as follows: (1) Efficiently restricting the lateral diffusion of holes: The vertical cavity surface emitting laser structure and its manufacturing method provided by the present invention insert an n-type semiconductor current confinement layer in the p-type layer, and use the hetero p-n junction formed by the contact between the n-type semiconductor current confinement layer and the p-type layer to construct "barrier walls" in the longitudinal and lateral directions, accurately blocking the leakage of holes to the device edge and significantly improving the utilization rate of holes.

[0020] (2) Improving the hole injection efficiency: The vertical cavity surface emitting laser structure and its manufacturing method provided by the present invention accurately align the central through hole of the annular n-type semiconductor current confinement layer with the central through hole of the insulating current confinement layer, providing a directional longitudinal injection channel for holes, guiding the holes to be efficiently injected into the active region, and improving the hole injection efficiency.

[0021] (3) Significantly improving the device performance: Compared with the traditional vertical cavity surface emitting laser structure, the vertical cavity surface emitting laser with a carrier lateral transport confinement structure provided by the present invention benefits from the improvement of the hole injection efficiency and the reduction of carrier loss, and the radiative recombination efficiency of the active region is significantly improved, resulting in a significant increase in the output optical power of the laser; the reduction of the lateral leakage of holes significantly reduces the injection current required for the device to reach the laser oscillation threshold, that is, the threshold current is reduced; the reduction of the lateral leakage of holes also reduces the power consumption and heat generation of the device.

[0022] (4) High structural stability: n-Al x Ga 1-x The growth conditions of the N-layer are well compatible with those of the p-GaN layer, which helps to ensure the crystal quality of the device. Attached Figure Description

[0023] To more clearly illustrate the structure of the present invention, a detailed description is provided below in conjunction with the accompanying drawings (the drawings are only schematic diagrams of the structure and do not represent actual dimensions).

[0024] Figure 1 is a schematic diagram of the structure of a GaN-based vertical cavity surface-emitting laser according to an embodiment of the present invention.

[0025] Figure 2 is a schematic diagram of part of the fabrication process of a GaN-based vertical cavity surface-emitting laser in one embodiment of the present invention.

[0026] Figure 3 is a schematic diagram of the orthographic projection of the n-type semiconductor current confinement layer in the vertical direction according to an embodiment of the present invention.

[0027] Figure 4 is a comparison of the output optical power of a GaN-based vertical cavity surface-emitting laser in one embodiment of the present invention with the output optical power of a conventional GaN-based vertical cavity surface-emitting laser without an n-type semiconductor current-limiting layer.

[0028] Figure 5 is a comparison of the lateral hole distribution in the third quantum well of a GaN-based vertical cavity surface-emitting laser in one embodiment of the present invention and the lateral hole distribution in the third quantum well of a conventional GaN-based vertical cavity surface-emitting laser without an n-type semiconductor current-limiting layer. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0030] Figure 1This is a schematic diagram of a vertical cavity surface-emitting laser (VCSEL) according to an embodiment of the present invention, comprising, from bottom to top, the following layers stacked sequentially: a substrate 1; a first distributed Bragg mirror 2 located on the substrate 1; an n-type layer 3 located on the side of the first distributed Bragg mirror 2 away from the substrate 1; an active region 4 located on the side of the n-type layer 3 away from the substrate 1; an electron blocking layer 5 located on the side of the active region 4 away from the substrate 1; a p-type layer 6 located on the side of the electron blocking layer 5 away from the substrate 1; and an n-type semiconductor current-limiting layer 7 located inside the p-type layer 6, wherein the thickness of the n-type semiconductor current-limiting layer 7 is less than the thickness of the p-type layer between the electron blocking layer 5 and the insulating current-limiting layer 8, and the n-type semiconductor current-limiting layer 7 surrounds the p-type layer 6. Around the perimeter, the orthogonal projection area of ​​the n-type semiconductor current confinement layer 7 in the vertical direction is smaller than that of the p-type layer 6 in the vertical direction. The p-type layer 6 and the n-type semiconductor current confinement layer 7 are in contact to form a pn junction. An insulating current confinement layer 8 is located on the side of the p-type layer 6 away from the substrate 1. The orthogonal projection of the insulating current confinement layer 8 in the vertical direction completely overlaps with the orthogonal projection of the n-type semiconductor current confinement layer 7 in the vertical direction. A current spreading layer 9 is located on the side of the p-type layer 6 and the insulating current confinement layer 8 away from the substrate 1. A second distributed Bragg reflector 10 is located on the side of the current spreading layer 9 away from the substrate 1. A p-type electrode 11 covers part of the surface of the current spreading layer 9. An n-type electrode 12 covers part of the surface of the n-type layer 3.

[0031] The substrate 1 is selected from any one of sapphire, GaN, SiC, Si, GaAs, and glass.

[0032] The first distributed Bragg reflector 2 is composed of alternating layers of AlN / GaN, AlGaN / GaN, or AlInN / GaN, with a periodicity of 1 to 200. The second distributed Bragg reflector 10 is composed of alternating layers of TiO2 / SiO2, HfO2 / SiO2, Ta2O5 / SiO2, or ZrO2 / SiO2, with a periodicity of 1 to 200. The periodic thickness of the materials constituting the first and second distributed Bragg reflectors 2 and 10 both satisfy λ / 4n1 + λ / 4n2, where λ is the lasing wavelength of the laser, n1 is the refractive index of material 1, and n2 is the refractive index of material 2, to achieve high reflectivity (reflectivity ≥ 99%) and ensure effective oscillation of light within the vertical cavity of the device. For example, the periodicity of the first distributed Bragg reflector is one of 15, 18, 20, 24, 26, or 30, the thickness of GaN is 40 to 60 nm, and the thickness of AlN is 50 to 70 nm. The second distributed Bragg mirror has a logarithm of 10, 12, 14, 15, or 18, and the thickness of Ta2O5 is 40–60 nm and the thickness of SiO2 is 60–80 nm.

[0033] The n-type layer 3 is an n-GaN layer with a thickness of 300~600 nm and a Si doping concentration of 1×10⁻⁶. 18 5×10 18 9×10 18 cm -3 One of them.

[0034] The active region 4 is a multi-quantum well structure. The multi-quantum well structure is In... x Ga 1-x Periodic structures formed by alternating deposition of N and GaN materials, with a periodicity ranging from 1 to 30. x Ga 1-x Nitrogen (N) is used as the quantum well layer, with a thickness of 1–10 nm, while GaN is used as the barrier layer, with a thickness of 2–40 nm. Charge carriers radiatively recombine in the active region to generate laser light, based on the In composition of the quantum well. x Depending on the specific characteristics, the laser's lasing wavelength range is adjustable from 350 to 750 nm.

[0035] The electron blocking layer 5 is selected from a material with a band gap wider than that of the quantum barrier material. The thickness of the electron blocking layer 5 is 5~100 nm. The electron blocking layer 5 has a high potential barrier and can prevent electrons from escaping from the active region into the p-type layer. For example, the quantum barrier material is GaN, and the electron blocking layer material is p-Al. x Ga 1-x N layer, p-Al x Ga 1-x The N-layer has an Al composition of 0.18, a thickness of 20 nm, and a Mg doping concentration of 1 × 10⁻⁶. 17 5×10 17 8×10 17 1×10 18 cm -3 One of them.

[0036] The p-type layer 6 can be a single-layer p-GaN layer or a multi-layer p-GaN layer. The p-type layer can also be a composite structure of p-GaN and p-AlInGaN. In some embodiments, the p-type layer 6 is a p-GaN layer, which includes a heavily doped p-type layer located near the current spreading layer. The doping element is Mg, and the hole concentration is 5 × 10⁻⁶. 17 ~5×10 19 cm -3 The thickness ranges from 1 to 500 nm. For example, p-type layer 6 is a p-GaN layer, which consists of two parts. The first part is close to the active region 4, with a thickness of 150 nm and a hole concentration of 8 × 10⁻⁶. 17 cm -3 The second part is located far from the active region 4, with a thickness of 20 nm and a hole concentration of 3 × 10⁴.18 ~8×10 19 cm -3 。

[0037] The p-type layer 6 further includes an n-type semiconductor current limiting layer 7, and the n-type semiconductor current limiting layer 7 is of an annular structure; the n-type semiconductor current limiting layer n-Al x Ga 1-x N (0 < x ≤ 1), for example, x = 0.2, 0.3, 0.4, 0.6, 0.8; the thickness of n-Al x Ga 1-x N is 1~150 nm, for example, the thickness is 20, 30, 50, 70, 90, 120, 150 nm; the doping concentration of Si is 1×10 14 ~1×10 21 cm -3 , for example, the doping concentration is 8×10 14 , 5×10 15 , 3×10 16 , 6×10 17 , 2×10 18 , 3×10 19 , 5×10 20 , 1×10 21 [[ID=3‎8]] cm -3 ; the upper and lower surfaces of n-Al x Ga 1-x N are both wrapped by the p-GaN layer, forming a "p-GaN / n-Al x Ga 1-x N / p-GaN" sandwich structure, and the n-type semiconductor current limiting layer and the p-type layer contact to form a heterojunction p-n junction, and the heterojunction p-n junction barrier is used to suppress the longitudinal and lateral transport of carriers.

[0038] Specifically, the structural parameters of the annular n-Al x Ga 1-x N current limiting layer meet the following requirements: (1) Geometric shape: It is a closed ring, and the shape of the central through hole is the same as the transverse cross-sectional shape of the central through hole of the insulating current limiting layer 8, which can be circular, regular hexagon or other polygons, and the characteristic size of the central through hole is 0.1~1000 μm. For example, the shape of the central through hole is circular, and the diameter of the circle is 0.1~1000 μm.

[0039] (2) Doping characteristics: It is n-type doping, the doping element is Si, and the doping concentration is 1×10 14 ~1×10 21 cm -3 .

[0040] The insulating current limiting layer 8 is located on the side of the p-type layer away from the substrate. The insulating current limiting layer 8 has a closed annular structure, and the shape of its central via is consistent with the cross-sectional shape of the n-type semiconductor current limiting layer 7. It can be circular, hexagonal, or other polygonal, and the characteristic size of the central via is 0.1~1000 μm. For example, annular n-Al... x Ga 1-x The central via of both the N-current limiting layer and the annular insulating current limiting layer is circular, with a diameter of 0.1~100 μm.

[0041] The insulating current limiting layer 8 is an insulating dielectric layer, selected from one of SiO2, AlN, SiN, Al2O3, HfO2, and Ta2O5. The orthographic projection of the insulating current limiting layer 8 in the vertical direction completely overlaps with the orthographic projection of the n-type semiconductor current limiting layer 7 in the vertical direction.

[0042] The current spreading layer 9 is selected from one of ITO, AZO, GZO, FTO, and IZO, with a thickness of 1~500 nm. The current spreading layer is used to uniformly spread the current injected by the p-type electrode into the p-type layer.

[0043] The vertical cavity surface-emitting laser with a carrier lateral confinement structure provided by the present invention further includes a p-electrode 11 and an n-electrode 12; the p-electrode 11 is located on a portion of the surface of the current spreading layer 9 away from the substrate 1; the n-electrode 12 is located on a portion of the surface of the n-type layer 3 away from the substrate, forming an ohmic contact with the n-type layer 3. Optionally, the p-electrode is a Ni / Au alloy structure, and the n-electrode is a Ti / Al / Ni / Au alloy structure.

[0044] This invention also provides a method for fabricating the aforementioned vertical-cavity surface-emitting laser, which is now combined with... Figure 1 , Figure 2 and Figure 3 The preparation method is described below, including: S1: Form a first distributed Bragg mirror 2 on substrate 1; S2: An n-type layer 3 is formed on the side of the first distributed Bragg mirror 2 away from the substrate 1; S3: An active region 4 is formed on the side of the n-type layer 3 away from the substrate 1; S4: An electron blocking layer 5 is formed on the side of the active region 4 away from the substrate 1; S5: A first p-type layer 61 is formed on the side of the electron blocking layer 5 away from the substrate 1, such as Figure 2 As shown in (a); S6: A mesa is formed around the edge of the first p-type layer 61 on the side away from the substrate. The depth of the mesa is less than the thickness of the first p-type layer 61, and the projected area of ​​the mesa in the vertical direction is less than the projected area of ​​the first p-type layer 61 in the vertical direction. Figure 2 As shown in (b); S7: An n-type semiconductor current limiting layer 7 is formed at the mesa location, wherein the thickness of the n-type semiconductor current limiting layer 7 is less than the depth of the mesa, such as... Figure 2 As shown in (c); S8: A second p-type layer 62 is formed on the side of the n-type semiconductor current-limiting layer 7 away from the substrate 1, such as... Figure 2 As shown in (d), the band gap of the n-type semiconductor current confinement layer 7 is greater than the band gap of the p-type layer 6; S9: An insulating current limiting layer 8 is formed on the side of the second p-type layer 62 away from the substrate 1. The insulating current limiting layer 8 is flush with the surface of the p-type layer 6, which is not covered by the insulating current limiting layer 8, on the side away from the substrate 1. Figure 2 As shown in (e); S10: A current spreading layer 9 is formed on the side of the p-type layer 6 and the insulating current limiting layer 8 away from the substrate 1; S11: A second distributed Bragg mirror 10 is formed on the side of the current spreading layer 9 away from the substrate 1.

[0045] In step S6, a mesa is formed around the edge of the first p-type layer 61 using photolithography and etching methods, and the mesa exposes part of the surface of the first p-type layer.

[0046] In step S7, an n-type semiconductor current confinement layer 7 is formed on the first p-type layer 61 using MOCVD or MBE methods. The n-type semiconductor current confinement layer 7 is an n-Al x Ga 1-x N(0) <x≤1),n-Al x Ga 1-x The thickness of N is 1~150 nm, and the doping concentration of Si is 1×10⁻⁶. 14 ~1×10 21 cm -3 The n-type semiconductor current-limiting layer and the p-type layer are contacted to form a heterogeneous pn junction, which uses the heterogeneous pn junction barrier to suppress the longitudinal and lateral transport of charge carriers.

[0047] Furthermore, the n-type semiconductor current limiting layer 7 is a closed ring, and the shape of its central via is consistent with the transverse cross-sectional shape of the central via of the insulating current limiting layer 8. The cross-sectional shape is selected from one of a circle, ellipse, rectangle, or other polygon, and the characteristic size of the central via is 0.1~1000 μm. For example, the central via of the n-type semiconductor current limiting layer 7 is circular, such as... Figure 3 As shown, the characteristic size d of the central through hole is 0.1~100 μm.

[0048] Furthermore, the insulating current limiting layer 8 is made of an insulating dielectric material selected from one of SiO2, AlN, SiN, Al2O3, HfO2, and Ta2O5.

[0049] Furthermore, the vertical projection of the insulating current limiting layer 8 completely overlaps with the vertical projection of the n-type semiconductor current limiting layer 7.

[0050] Furthermore, the n-type layer 3 is an n-GaN layer with a thickness of 300~600 nm and a Si doping concentration of 1×10⁻⁶. 14 ~1×10 21 cm -3 .

[0051] Furthermore, the active region 4 is selected from an InGaN / GaN multi-quantum-well structure, and the multi-quantum-well structure is an InGaN multi-quantum-well structure. x Ga 1-x Periodic structures formed by alternating deposition of N and GaN materials, with a period logarithm of 1~30, In x Ga 1-x The thickness of the N quantum well layer is 1~10 nm, and the thickness of the GaN barrier layer is 2~40 nm.

[0052] Furthermore, the electron blocking layer 5 is selected from a material with a band gap wider than that of the quantum barrier material, for example, the quantum barrier material is GaN and the electron blocking layer material is p-Al. x Ga 1-x N, the thickness of electron blocking layer 5 is 5~50 nm, p-Al x Ga 1-x The N-layer has an Al composition of 0.01–0.5, is doped with Mg, and has a hole concentration of 1 × 10⁻⁶. 16 ~1×10 19 cm -3 .

[0053] Furthermore, p-type layer 6 can be a single-layer p-GaN layer, or it can be a multi-layer p-GaN layer, or a composite structure of p-GaN and p-AlInGaN. For example, p-type layer 6 can be a p-GaN layer including a heavily doped p-type layer located near the current spreading layer, with Mg as the dopant and a hole concentration of 1 × 10⁻⁶. 16 ~1×10 20 cm -3 The thickness ranges from 1 to 500 nm. For example, p-type layer 6 is a p-GaN layer, which consists of two parts. The first part is close to the active region 4 and has a thickness of 150 nm. The Mg doping concentration is 8 × 10⁻⁶. 17 cm -3 The second part, located far from the active region 4, has a thickness of 20 nm and a Mg doping concentration of 3 × 10⁻⁶. 18 ~8×10 19 cm -3 .

[0054] Furthermore, the current spreading layer 9 is selected from one of ITO, AZO, GZO, FTO, and IZO, with a thickness of 1~500 nm.

[0055] Furthermore, both the first distributed Bragg reflector 2 and the second distributed Bragg reflector 10 are composed of alternating semiconductor or dielectric layers with a period number of 1 to 200. For example, the first distributed Bragg reflector 2 is composed of alternating AlN / GaN layers with a period number of 10 to 60; the second distributed Bragg reflector 10 is composed of alternating Ta2O5 / SiO2 layers with a period number of 5 to 30.

[0056] In other embodiments, the periodic material of the first distributed Bragg reflector 2 is one of AlGaN / GaN and AlInN / GaN, and the periodic material of the second distributed Bragg reflector 10 is selected from one of TiO2 / SiO2, HfO2 / SiO2, and ZrO2 / SiO2.

[0057] The method for fabricating a vertical-cavity surface-emitting laser provided by the present invention further includes the steps of forming an n-type electrode 12 and a p-type electrode 11. When fabricating the n-type electrode 12, a mesa of the n-type layer 3 needs to be formed by photolithography and etching, exposing a portion of the surface of the n-type layer 3, and the n-type electrode 12 is formed on the side of the n-type layer 3 away from the substrate 1. When fabricating the p-type electrode 11, a second distributed Bragg mirror 10 needs to be etched using photolithography and etching, exposing a portion of the surface of the current spreading layer 9, and the p-type electrode 11 is formed on the side of the current spreading layer 9 away from the substrate 1.

[0058] The vertical-cavity surface-emitting laser fabrication method provided by this invention uses MOCVD or MBE processes to grow the epitaxial layer, which includes an n-type layer, an active region, an electron blocking layer, a p-type layer, and an n-type semiconductor current-confining layer. The growth processes for the first distributed Bragg mirror, the second distributed Bragg mirror, and the insulating current-confining layer are selected from ALD, CVD, MOCVD, MBE, magnetron sputtering, etc. The growth process for the current-spreading layer is selected from ALD, CVD, magnetron sputtering, pulsed laser deposition, etc.

[0059] Figure 4 The diagram shows a comparison of the output optical power of a vertical-cavity surface-emitting laser (VCSEL) structure according to an embodiment of the present invention with that of a conventional GaN-based VCSEL without an n-type semiconductor current-limiting layer. With an injection current of 10 mA, the output optical power of the conventional structure without an n-type semiconductor current-limiting layer is 3.72 mW, and the threshold current is 3.66 mA. The structure with n-Al... 0.15 Ga 0.85 The vertical-cavity surface-emitting laser with an N-current-confined layer achieves an output optical power of 5.09 mW and a threshold current reduction to 3.06 mA. It can be seen that the laser provided by this invention increases the output optical power by 36.83% and reduces the threshold current by 0.60 mA compared to lasers with conventional structures; this demonstrates that the present invention possesses n-Al... 0.15 Ga 0.85 The optoelectronic performance of vertical cavity surface-emitting lasers with N-lateral current-limited structures is greatly improved.

[0060] Figure 5 The diagram shows a comparison between the lateral hole distribution in the third quantum well of a GaN-based vertical-cavity surface-emitting laser (VCSEL) according to an embodiment of the present invention and the lateral hole distribution in the third quantum well of a conventional GaN-based VCSEL without an n-type semiconductor current-confining layer. In this embodiment, the quantum well closest to the electron blocking layer 5 is the third quantum well. The results show that, compared with the conventional structure, the n-Al... 0.15 Ga 0.85 The hole concentration within the aperture of the vertical-cavity surface-emitting laser with the N-current confinement layer is increased, which also indicates that n-Al 0.15 Ga 0.85 The pn junction formed by the N-type current-limiting layer and the p-type layer can effectively block holes from leaking to the device edge, thereby significantly improving the utilization rate of holes.

[0061] The above description is only used to illustrate the present invention and is not intended to limit the implementation method of the present invention in any way. Therefore, any modifications or alterations made to the present invention based on the shape, structure, features and basic ideas described herein should fall within the scope of intellectual property rights intended to be protected by the present invention.

Claims

1. A vertical-cavity surface-emitting laser structure, characterized in that, include: Substrate; A first distributed Bragg reflector located on the substrate; An n-type layer located on the side of the first distributed Bragg mirror away from the substrate; The active region located on the side of the n-type layer away from the substrate; An electron blocking layer located on the side of the active region away from the substrate; The p-type layer located on the side of the electron blocking layer away from the substrate; An n-type semiconductor current-limiting layer is located inside the p-type layer. The band gap of the n-type semiconductor current-limiting layer is larger than that of the p-type layer. The thickness of the n-type semiconductor current-limiting layer is smaller than that of the p-type layer. The n-type semiconductor current-limiting layer surrounds the edge of the p-type layer. The vertical projection area of ​​the n-type semiconductor current-limiting layer is smaller than that of the p-type layer. The p-type layer and the n-type semiconductor current-limiting layer are in contact to form a heterojunction pn junction. An insulating current-limiting layer is located on the side of the p-type layer away from the substrate, and the orthogonal projection of the insulating current-limiting layer in the vertical direction completely overlaps with the orthogonal projection of the n-type semiconductor current-limiting layer in the vertical direction. A current spreading layer located on the side of the p-type layer and the insulating current limiting layer away from the substrate; A second distributed Bragg reflector located on the side of the current spreading layer away from the substrate.

2. The vertical-cavity surface-emitting laser structure according to claim 1, characterized in that: The n-type semiconductor current limiting layer is n-Al x Ga 1-x N (0 < x ≤ 1), and the doping concentration of the n-Al x Ga 1-x N is 1×10 14 ~ 1×10 21 cm -3 . The thickness of the n-Al x Ga 1-x N is less than the thickness of the p-type layer between the insulating current limiting layer and the electron blocking layer.

3. The vertical-cavity surface-emitting laser structure according to claim 1, characterized in that: The p-type layer is p-GaN, and the p-GaN layer includes a heavily doped p-type layer, which is located close to the current spreading layer.

4. The vertical-cavity surface-emitting laser according to claim 1, characterized in that: The n-type semiconductor current limiting layer is in the form of a closed ring. The shape of the central via of the closed ring is consistent with the transverse cross-sectional shape of the central via of the insulating current limiting layer. The cross-sectional shape is selected from one of a circle, an ellipse, a rectangle, or other polygons. The characteristic size of the central via is 0.1~1000 μm.

5. The vertical-cavity surface-emitting laser structure according to claim 1, characterized in that: The insulating current limiting layer is an annular insulating dielectric layer, and the characteristic size of the central through hole in the annular insulating dielectric layer is 0.1~1000 μm.

6. The vertical-cavity surface-emitting laser structure according to claim 1, characterized in that: The active region is a multi-quantum-well structure, which is an InGaN / GaN quantum well structure, including 1 to 30 cycles of InGaN quantum wells and GaN barrier layers.

7. The vertical-cavity surface-emitting laser structure according to claim 1, characterized in that: Both the first and second distributed Bragg reflectors are composed of alternating semiconductor or dielectric layers with a period number of 1 to 200.

8. A method for fabricating a vertical-cavity surface-emitting laser, characterized in that, include: A first distributed Bragg mirror is formed on the substrate; An n-type layer is formed on the side of the first distributed Bragg mirror away from the substrate; An active region is formed on the side of the n-type layer away from the substrate; An electron blocking layer is formed on the side of the active region away from the substrate; A first p-type layer is formed on the side of the electron blocking layer away from the substrate; A mesa is formed around the edge of the first p-type layer on the side away from the substrate. The depth of the mesa is less than the thickness of the first p-type layer, and the vertical projection area of ​​the mesa is less than the vertical projection area of ​​the first p-type layer. An n-type semiconductor current limiting layer is formed at the mesa location, wherein the thickness of the n-type semiconductor current limiting layer is less than the depth of the mesa. A second p-type layer is formed on the side of the n-type semiconductor current-limiting layer away from the substrate, and the bandgap width of the n-type semiconductor current-limiting layer is greater than the bandgap width of the first p-type layer and the bandgap width of the second p-type layer; An insulating current limiting layer is formed on the side of the second p-type layer away from the substrate, and the surface of the insulating current limiting layer on the side away from the substrate is flush with the surface of the first p-type layer on the side away from the substrate. A current spreading layer is formed on the side of the first p-type layer and the insulating current limiting layer away from the substrate; A second distributed Bragg reflector is formed on the side of the current spreading layer away from the substrate.

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