Vertical cavity surface emitting laser structure and preparation method thereof

Abstract

The invention discloses a vertical cavity surface emitting laser structure and a preparation method thereof, and relates to the technical field of semiconductor optoelectronic devices. The vertical cavity surface emitting laser comprises a substrate, a first distributed Bragg reflector, an n-type layer, a multi-quantum well layer, an electron blocking layer, a p-type layer, an n-type semiconductor current limiting layer with gradually changed components, an insulation current limiting layer, a current expansion layer, a second distributed Bragg reflector and an electrode, according to the invention, the n-type semiconductor current limiting layer with gradually changed components is introduced into the p-type layer below the insulating current limiting layer, and the lateral leakage of carriers is prevented by using a heterojunction barrier formed by the n-type semiconductor current limiting layer and the p-type layer and a built-in electric field, so that the loss of the carriers in a non-active region is reduced; therefore, the output light power of the laser is improved and the threshold current is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor optoelectronic device technology, specifically relating to a vertical cavity surface-emitting laser structure and its fabrication method. Background Technology

[0002] Vertical-cavity surface-emitting lasers (VCSELs) are widely used in laser displays, optical storage, and optical communications due to their advantages such as low threshold current, high modulation rate, and easy integration. While the industrial fabrication of GaAs / InP-based long-wavelength VCSELs is nearing maturity, short-wavelength VCSELs based on GaN semiconductor materials urgently need improvement in areas such as high threshold current and low lasing power.

[0003] In GaN-based vertical-cavity surface-emitting lasers (VCSELs), the electrodes are located on the side of a Bragg mirror. Current must be transported laterally to the confinement aperture, where carriers recombine and emit photons in the active region. Therefore, efficiently confining carriers within the active region is an effective way to improve laser performance. Currently, using a dielectric (such as SiO2) insulating layer to form a current-confinement aperture can achieve lateral current injection, and the scheme is relatively simple and easy to implement. However, the voltage division characteristics of SiO2 as an insulating layer cause lateral band bending at the edge of the insulating aperture, leading to hole leakage out of the current-confinement aperture and reducing laser gain. Simultaneously, the electric field formed at the p-GaN / SiO2 interface forces holes to drift out of the aperture, worsening current confinement and reducing hole injection efficiency and laser power. Therefore, developing novel structures that can efficiently suppress lateral carrier leakage and are compatible with GaN-based material systems is an effective way to improve the performance of GaN-based VCSELs. Summary of the Invention

[0004] To address at least one of the aforementioned technical problems of gallium nitride-based vertical cavity surface-emitting lasers in the prior art, this invention provides a vertical cavity surface-emitting laser structure and its fabrication method, which can effectively suppress the lateral leakage of holes from the vertical cavity surface-emitting laser to the outside of the aperture, improve the laser output power, and reduce the threshold current.

[0005] According to one aspect of the present invention, a vertical-cavity surface-emitting laser is provided, comprising: Substrate; The first distributed Bragg mirror located on the substrate; The n-type layer located on the side of the first distributed Bragg mirror furthest from the substrate; The active region located on the side of the n-type layer furthest from the substrate; An electron blocking layer located on the side of the active region away from the substrate; The p-type layer located on the side of the electron blocking layer away from the substrate; An n-type semiconductor current confinement layer with a gradually changing composition is located inside the p-type layer. The thickness of the n-type semiconductor current confinement layer is less than that of the p-type layer. The n-type semiconductor current confinement layer surrounds the edge of the p-type layer. The vertical projection area of ​​the n-type semiconductor current confinement layer is less than that of the p-type layer. The p-type layer and the n-type semiconductor current confinement layer are in contact to form a heterojunction. An insulating current-limiting layer is located on the side of the p-type layer away from the substrate, and the vertical projection area of ​​the insulating current-limiting layer is greater than or equal to the vertical projection area of ​​the n-type semiconductor current-limiting layer. A current spreading layer located on the side of the p-type layer and the insulating current limiting layer away from the substrate; A second distributed Bragg reflector located on the side of the current spreading layer away from the substrate.

[0006] Furthermore, the thickness of the n-type semiconductor current-limiting layer is less than the thickness of the p-type layer between the insulating current-limiting layer and the electron blocking layer.

[0007] Furthermore, the n-type semiconductor current limiting layer is a closed ring, and the shape of its central via is consistent with the transverse cross-sectional shape of the central via of the insulating current limiting layer. The cross-sectional shape is selected from one of a circle, an ellipse, a rectangle, or other polygons, and the characteristic size of the central via is 0.1~1000 μm.

[0008] Furthermore, the n-type semiconductor current confinement layer is a compositionally graded n-Al. x1→x2 Ga y1→y2 N, where 0 ≤ x 1< x 2≤1,0≤ y 2< y 1≤1, x 1+ y 1=1, x 2+ y 2=1, the doping concentration is 1×10 14 ~ 1×10 21 cm -3 .

[0009] Optionally, the n-type semiconductor current confinement layer is an n-Al material with a linearly graded composition of Al and Ga elements. x1→ x2 Ga y1→y2 N(0≤) x 1< x 2≤1,0≤ y 2< y 1≤1, x 1+ y 1=1, x 2+ y2=1).

[0010] Optionally, the n-type semiconductor current confinement layer is an n-Al layer with a nonlinearly graded composition of Al and Ga elements. x1→x2 Ga y1→y2 N(0≤) x 1< x 2≤1,0≤ y 2< y 1≤1, x 1+ y 1=1, x 2+ y 2=1).

[0011] Furthermore, the p-type layer is p-GaN with a thickness of 1~500 nm and a doping concentration of 1×10⁻⁶. 14 ~ 1×10 21 cm -3 p-GaN can be a single-layer structure or a multi-layer structure, and the p-type layer can also be a composite structure of p-GaN and p-AlInGaN.

[0012] Optionally, the p-type layer is p-GaN, and the doping concentration of the p-GaN layer is non-uniform, with the doping concentration of the p-GaN layer near the current spreading layer being higher than that of the p-GaN layer near the electron blocking layer.

[0013] Furthermore, the insulating current limiting layer is an annular insulating dielectric layer, selected from one of SiO2, AlN, SiN, Al2O3, HfO2, and Ta2O5, with a characteristic size of 0.1~1000 μm for the central via. The size of the central via of the insulating current limiting layer is less than or equal to the size of the central via of the n-type semiconductor current limiting layer.

[0014] Furthermore, the active region is a multi-quantum-well structure, which is an InGaN / GaN multi-quantum-well structure, including 1 to 30 cycles of InGaN quantum wells and GaN barrier layers, wherein the thickness of the InGaN quantum wells is 1 to 10 nm and the thickness of the barrier layers is 2 to 40 nm.

[0015] Furthermore, the first and second distributed Bragg reflectors are composed of alternating semiconductor or dielectric layers with a period number of 1 to 200. The periodic material of the semiconductor layer Bragg reflector is selected from AlN / GaN, AlGaN / GaN, and AlInN / GaN, while the periodic material of the dielectric layer Bragg reflector is selected from TiO2 / SiO2, HfO2 / SiO2, Ta2O5 / SiO2, and ZrO2 / SiO2. The periodic materials of the first and second distributed Bragg reflectors can be the same or different.

[0016] According to another aspect of the present invention, a method for fabricating the above-described vertical-cavity surface-emitting laser is provided, comprising: A first distributed Bragg mirror is formed on the substrate; An n-type layer is formed on the side of the first distributed Bragg mirror away from the substrate; An active region is formed on the side of the n-type layer away from the substrate; An electron blocking layer is formed on the side of the active region away from the substrate; A first p-type layer is formed on the side of the electron blocking layer away from the substrate; An n-type semiconductor current-confining layer is formed on the side of the first p-type layer away from the substrate. The n-type semiconductor current-confining layer is an n-Al. x1→x2 Ga y1→y2 N, where 0 ≤ x 1< x 2≤1,0≤ y 2< y 1≤1, x 1+ y 1=1, x 2+ y 2 = 1; A first opening is formed in the n-type semiconductor current-limiting layer, and the first opening exposes a portion of the surface of the first p-type layer; A second p-type layer is grown at the first opening. The second p-type layer fills the entire first opening and covers the entire surface of the first p-type layer and the n-type semiconductor current confinement layer away from the substrate. The n-type semiconductor current confinement layer surrounds the edge of the second p-type layer. The p-type layer and the n-type semiconductor current confinement layer contact to form a heterojunction. A second annular opening is formed around the edge of the second p-type layer. The longitudinal depth of the second opening is less than the thickness of the second p-type layer at the edge. The projected area of ​​the second opening in the vertical direction is greater than or equal to the projected area of ​​the n-type semiconductor current limiting layer in the vertical direction. An insulating current limiting layer is filled at the second opening. The insulating current limiting layer surrounds the edge of the second p-type layer. The surface of the insulating current limiting layer away from the substrate and a portion of the surface of the second p-type layer away from the substrate are flush. A current spreading layer is formed on the side of the second p-type layer and the insulating current limiting layer away from the substrate; A second distributed Bragg mirror is formed on the side of the current spreading layer away from the substrate.

[0017] Furthermore, the n-type semiconductor current confinement layer is a compositionally graded n-Al. x1→x2 Ga y1→y2 N, where 0 ≤ x 1< x 2≤1,0≤ y 2< y 1≤1, x 1+ y 1=1, x 2+ y 2=1, the n-Al x1→x2 Ga y1→y2 The thickness of N is less than the thickness of the p-type layer between the insulating current-limiting layer and the electron-blocking layer, wherein the n-Al x1→x2 Ga y1→y2 The N doping concentration is 1×10 14 ~ 1×10 21 cm -3 .

[0018] Furthermore, the first p-type layer and the second p-type layer can be a single-layer structure or a composite structure, and the materials of the first p-type layer and the second p-type layer are selected from p-GaN or p-AlInGaN.

[0019] Furthermore, the n-type semiconductor current limiting layer is a closed ring, and the insulating current limiting layer is a ring-shaped insulating dielectric layer. The vertical projection area of ​​the insulating current limiting layer is greater than or equal to the vertical projection area of ​​the n-type semiconductor current limiting layer.

[0020] Optionally, the shape of the central via of the n-type semiconductor current limiting layer is consistent with the transverse cross-sectional shape of the central via of the insulating current limiting layer. The cross-sectional shape is selected from one of the following: circle, ellipse, rectangle or other polygon. The characteristic size of the central via is 0.1~1000 μm.

[0021] As can be seen from the above technical solution, the beneficial effects of the present invention are as follows: (1) The vertical cavity surface-emitting laser structure and its fabrication method provided by the present invention, by inserting compositionally graded n-Al into the p-type layer x1→x2 Ga y1→y2 N(0≤) x 1< x 2≤1,0≤ y 2< y 1≤1, x 1+ y1=1, x 2+ y 2=1) Current confinement layer, utilizing n-Al x1→x2 Ga y1→y2 The heterojunction formed by the contact between the N-type current-confining layer and the p-type layer constructs "potential barriers" in both the longitudinal and lateral directions. This is achieved through the interaction of n-Al... x1→x2 Ga y1→y2 As the Al content in N increases, the potential barrier height gradually increases.

[0022] (2) The vertical cavity surface-emitting laser structure provided by the present invention utilizes a ring-shaped insulating current-limiting layer and a ring-shaped n-Al x1→x2 Ga y1→y2 The N-current confinement layer works synergistically to provide a directional longitudinal injection channel for holes, guiding holes to be injected efficiently into the active region and improving hole injection efficiency.

[0023] (3) The n-Al provided by the present invention x1→x2 Ga y1→y2 The N-current confinement layer can be achieved by adjusting the epitaxial growth parameters and has good compatibility with the p-GaN layer, which helps to ensure the crystal quality of the device.

[0024] (4) Compared with the traditional vertical cavity surface-emitting laser structure, the vertical cavity surface-emitting laser provided by the present invention benefits from the improved hole injection efficiency and reduced carrier loss, and the active region radiative recombination efficiency is significantly improved, which greatly improves the output optical power of the laser; the reduction of hole lateral leakage greatly reduces the injection current required for the device to reach the laser oscillation threshold, that is, the threshold current is reduced; the reduction of hole lateral leakage also reduces the power consumption and heat generation of the device. Attached Figure Description

[0025] To more clearly illustrate the structure of the present invention, a detailed description is provided below in conjunction with the accompanying drawings (the drawings are only schematic diagrams of the structure and do not represent actual dimensions).

[0026] Figure 1 is a schematic diagram of the structure of a GaN-based vertical cavity surface-emitting laser according to an embodiment of the present invention.

[0027] Figure 2 is a schematic diagram of part of the fabrication process of a GaN-based vertical cavity surface-emitting laser in one embodiment of the present invention.

[0028] Figure 3 is a schematic diagram of the orthographic projection of the n-type semiconductor current confinement layer in the vertical direction according to an embodiment of the present invention.

[0029] Figure 4 is a comparison of the output optical power of a GaN-based vertical cavity surface-emitting laser in one embodiment of the present invention with the output optical power of a conventional GaN-based vertical cavity surface-emitting laser without an n-type semiconductor current-limiting layer.

[0030] Figure 5 is a comparison of the lateral hole distribution in the third quantum well of a GaN-based vertical cavity surface-emitting laser in one embodiment of the present invention and the lateral hole distribution in the third quantum well of a conventional GaN-based vertical cavity surface-emitting laser without an n-type semiconductor current-limiting layer. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0032] Figure 1 This is a schematic diagram of a vertical cavity surface-emitting laser (VCSEL) according to an embodiment of the present invention, comprising, from bottom to top, the following layers stacked sequentially: a substrate 1; a first distributed Bragg mirror 2 located on the substrate 1; an n-type layer 3 located on the side of the first distributed Bragg mirror 2 away from the substrate 1; an active region 4 located on the side of the n-type layer 3 away from the substrate 1; an electron blocking layer 5 located on the side of the active region 4 away from the substrate 1; a p-type layer 6 located on the side of the electron blocking layer 5 away from the substrate 1; and an n-type semiconductor current-limiting layer 7 located inside the p-type layer 6, wherein the thickness of the n-type semiconductor current-limiting layer 7 is less than the thickness of the electron blocking layer 5. The thickness of the p-type layer between the sub-blocking layer 5 and the insulating current limiting layer 8; the n-type semiconductor current limiting layer 7 surrounds the edge of the p-type layer 6; the p-type layer 6 and the n-type semiconductor current limiting layer 7 are in contact to form a pn junction; the insulating current limiting layer 8 is located on the side of the p-type layer 6 away from the substrate 1; the current spreading layer 9 is located on the side of the p-type layer 6 and the insulating current limiting layer 8 away from the substrate 1; the second distributed Bragg reflector 10 is located on the side of the current spreading layer 9 away from the substrate 1; the p-type electrode 11 covers part of the surface of the current spreading layer 9; the n-type electrode 12 covers part of the surface of the n-type layer 3.

[0033] The substrate 1 is selected from any one of sapphire, GaN, SiC, Si, GaAs, and glass.

[0034] The first distributed Bragg reflector 2 is composed of alternating layers of AlN / GaN, AlGaN / GaN, or AlInN / GaN, with a periodicity of 1 to 200. The second distributed Bragg reflector 10 is composed of alternating layers of TiO2 / SiO2, HfO2 / SiO2, Ta2O5 / SiO2, or ZrO2 / SiO2, with a periodicity of 1 to 200. The periodic thickness of the materials constituting the first and second distributed Bragg reflectors 2 and 10 both satisfy λ / 4n1 + λ / 4n2, where λ is the lasing wavelength of the laser, n1 is the refractive index of material 1, and n2 is the refractive index of material 2. For example, the first distributed Bragg mirror 2 has a logarithm of 15, 18, 20, 24, 26, or 30, and the GaN thickness is 40-60 nm and the AlN thickness is 50-70 nm; the second distributed Bragg mirror 10 has a logarithm of 10, 12, 14, 15, or 18, and the Ta2O5 thickness is 40-60 nm and the SiO2 thickness is 60-80 nm.

[0035] The n-type layer 3 is an n-GaN layer with a thickness of 300~600 nm and a Si doping concentration of 1×10⁻⁶. 18 ~9×10 18 cm -3 For example, the Si doping concentration is 1×10⁻⁶. 18 5×10 18 9×10 18 cm -3 One of them.

[0036] The active region 4 is a multi-quantum well structure. The multi-quantum well structure is In... x Ga 1-x Periodic structures formed by alternating deposition of N and GaN materials, with a periodicity ranging from 1 to 30. x Ga 1-x Nitrogen (N) is used as the quantum well layer, with a thickness of 1–10 nm, while GaN is used as the barrier layer, with a thickness of 2–30 nm. Charge carriers radiatively recombine in the active region to generate laser light, based on the In composition of the quantum well. x Depending on the specific characteristics, the lasing wavelength range of the laser can be adjusted from 350 to 750 nm.

[0037] The electron blocking layer 5 is selected from a material with a band gap wider than that of the quantum barrier material. The thickness of the electron blocking layer 5 is 5~100 nm. The electron blocking layer 5 has a high potential barrier and can prevent electrons from escaping from the active region into the p-type layer. For example, the electron blocking layer 5 is p-Al. x Ga 1-x N layer, p-Al x Ga 1-xThe N-layer has an Al composition of 0.18 and a thickness of 20 nm, while the Mg doping concentration is 1 × 10⁻⁶. 17 5×10 17 8×10 17 1×10 18 cm -3 One of them.

[0038] The p-type layer 6 can be a single-layer p-GaN layer or a multi-layer p-GaN layer. In some embodiments, the doping concentration of the p-GaN layers is non-uniform, with the doping concentration of the p-GaN layers near the current spreading layer 9 being higher than that of the p-GaN layers near the electron blocking layer 5. For example, the p-type layer 6 is a p-GaN layer including a heavily doped p-type layer near the current spreading layer, with Mg as the dopant and a hole concentration of 5 × 10⁻⁶. 17 ~5×10 19 cm -3 The thickness ranges from 1 to 500 nm. For example, p-type layer 6 is a p-GaN layer, which consists of two parts. The first part is close to the active region, with a thickness of 150 nm and a hole concentration of 8 × 10⁻⁶. 17 cm -3 The second part is far from the active region, with a thickness of 20 nm and a hole concentration of 3 × 10⁻⁶. 18 ~8×10 19 cm -3 In some embodiments, the p-type layer can also be a composite structure of p-GaN and p-AlInGaN.

[0039] The p-type layer 6 also includes an n-type semiconductor current confinement layer 7, which has a ring structure; the n-type semiconductor current confinement layer 7 is an n-Al with linearly graded composition. x1→x2 Ga y1→y2 N, where 0 ≤ x 1< x 2≤1,0≤ y 2< y 1≤1, x 1+ y 1=1, x 2+ y 2 = 1, for example, x 1. x 2. y 1. y The value of 2 is: x 1=0、 x 2 = 0.3 y 1=1、 y 2 = 0.7, or x 1 = 0.05 x 2 = 0.35y 1 = 0.95 y 2 = 0.65, or x 1 = 0.1 x 2 = 0.4 y 1 = 0.9 y 2 = 0.6, or x 1=0、 x 2 = 0.5 y 1=1、 y 2=0.5; n-Al x1→x2 Ga y1→y2 Both the upper and lower surfaces of N are encapsulated by a p-GaN layer 6, forming a "p-GaN / n-Al" structure. x1→x2 Ga y1→y2 The sandwich structure of "N / p-GaN" features an n-type semiconductor current confinement layer 7 and a p-type layer 6 forming a heterojunction, which utilizes the heterojunction barrier to suppress the longitudinal and lateral transport of charge carriers; n-Al x1→x2 Ga y1→y2 The thickness of N ranges from 1 to 150 nm, for example, thicknesses of 5, 10, 20, 30, 50, 70, 100, 120, and 150 nm; the doping concentration of Si is 1 × 10⁻⁶. 14 ~1×10 21 cm -3 For example, a doping concentration of 5 × 10 14 8×10 15 5×10 16 7×10 17 4×10 18 3×10 19 2×10 20 1×10 21 cm -3 .

[0040] In other embodiments, the n-type semiconductor current confinement layer can also be an n-Al layer with a nonlinearly graded composition of Al and Ga elements. x1→x2 Ga y1→y2 N(0≤) x 1< x 2≤1,0≤ y 2< y 1≤1, x 1+ y 1=1, x 2+ y 2=1).

[0041] The insulating current limiting layer 8 is an annular insulating dielectric layer with a central hole size of 0.1~1000 μm. The insulating dielectric layer is selected from one of SiO2, AlN, SiN, Al2O3, HfO2, and Ta2O5.

[0042] Specifically, the ring-shaped n-Al x1→x2 Ga y1→y2 The structural parameters of the N current confinement layer meet the following requirements: (1) The geometry is a closed ring, and the shape of its central through hole is consistent with the cross-sectional shape of the central through hole of the insulating current confinement layer 8. It can be a circle, a regular hexagon or other polygons, and the characteristic size of the central through hole is 0.1~1000 μm; (2) The doping characteristic is n-type doping, the doping element is Si, and the doping concentration is 1×10 14 ~1×10 21 cm -3 (3) The Al component increases monotonically along the growth direction, and the Ga component decreases monotonically; (4) The positive projection area of ​​the n-type semiconductor current confinement layer 7 in the vertical direction is less than or equal to the positive projection area of ​​the insulation current confinement layer 8 in the vertical direction.

[0043] The current spreading layer 9 is selected from ITO, AZO, GZO, FTO, and IZO, and has a thickness of 1~500 nm. The current spreading layer 9 is used to uniformly spread the current injected by the p-type electrode 11 into the p-type layer 6.

[0044] The vertical-cavity surface-emitting laser provided by the present invention further includes a p-electrode layer 11 and an n-electrode layer 12; the p-electrode layer 11 is located on a portion of the surface of the current spreading layer 9 away from the substrate 1; the n-electrode layer 12 is located on a portion of the surface of the n-type layer 3 away from the substrate, forming an ohmic contact with the n-type layer 3. In some embodiments, the p-electrode layer 11 is a Ni / Au alloy structure, and the n-electrode layer 12 is a Ti / Al / Ni / Au alloy structure.

[0045] This invention also provides a method for fabricating the vertical-cavity surface-emitting laser in the above embodiments, combined with... Figure 1 , Figure 2 and Figure 3 The preparation method is described below, including: S1: Form a first distributed Bragg mirror 2 on substrate 1; S2: An n-type layer 3 is formed on the side of the first distributed Bragg mirror 2 away from the substrate 1; S3: An active region 4 is formed on the side of the n-type layer 3 away from the substrate 1; S4: An electron blocking layer 5 is formed on the side of the active region 4 away from the substrate 1; S5: A first p-type layer 61 is formed on the side of the electron blocking layer 5 away from the substrate 1, such as Figure 2 As shown in (a); S6: An n-type semiconductor current confinement layer 7 is formed on the side of the first p-type layer 61 away from the substrate 1. The n-type semiconductor current confinement layer 7 is an n-Al layer with a graded composition. x1→x2 Gay1→y2 N(0≤) x 1< x 2≤1,0≤ y 2< y 1≤1, x 1+ y 1=1, x 2+ y 2=1), such as Figure 2 As shown in (b); S7: A first opening is formed at the n-type semiconductor current-limiting layer 7, the first opening exposing a portion of the surface of the first p-type layer 61, such as... Figure 2 As shown in (c); S8: A second p-type layer 62 is grown at the first opening. The second p-type layer 62 fills the entire first opening and covers the entire surface of the first p-type layer 61 and the n-type semiconductor current confinement layer 7 on the side away from the substrate 1. The n-type semiconductor current confinement layer 7 surrounds the edge of the p-type layer 6. The vertical projection area of ​​the n-type semiconductor current confinement layer 7 is smaller than the vertical projection area of ​​the p-type layer 6. The p-type layer 6 and the n-type semiconductor current confinement layer 7 contact to form a pn junction. Figure 2 As shown in (d); S9: A second annular opening is formed on the p-type layer 62. The depth of the second opening in the longitudinal direction is less than the thickness of the second p-type layer at the edge. The second opening surrounds the edge of the p-type layer 62. The maximum width of the second opening in the lateral direction is greater than or equal to the maximum width of the annular n-type semiconductor current limiting layer 7. Figure 2 As shown in (e); S10: An insulating current-limiting layer 8 is grown at the second opening of the p-type layer 62. The insulating current-limiting layer 8 fills the entire second opening and surrounds the edge of the p-type layer 6. The surface of the insulating current-limiting layer 8 away from the substrate is flush with a portion of the surface of the p-type layer 62 away from the substrate. Figure 2 As shown in (f); S11: A current spreading layer 9 is formed on the side of the p-type layer 62 and the insulating current limiting layer 8 away from the substrate 1; S12: A second distributed Bragg mirror 10 is formed on the side of the current spreading layer 9 away from the substrate 1.

[0046] In step S6, MOCVD or MBE methods are used to achieve compositionally graded n-Al on the p-type layer 6 by controlling the ratio of Al source to Ga source. x1→x2 Ga y1→y2 N(0≤) x 1< x 2≤1,0≤ y 2< y 1≤1, x 1+ y1=1, x 2+ y 2=1). n-Al x1→ x2 Ga y1→y2 The thickness of N is 1~150 nm, and the doping concentration of Si is 1×10⁻⁶. 14 ~1×10 21 cm -3 n-Al x1→x2 Ga y1→y2 The composition of Al and Ga in N can be linearly or non-linearly gradual.

[0047] In step S7, a first opening is formed in the n-type semiconductor current confinement layer 7 using photolithography and etching methods. The first opening exposes a portion of the surface of the first p-type layer 61, and the n-type semiconductor current confinement layer 7 is in the form of a closed ring.

[0048] In step S8, a second p-type layer 62 is grown at the first opening using MOCVD or MBE methods. The second p-type layer fills the entire opening and covers the entire surface of the first p-type layer 61 and the n-type semiconductor current confinement layer 7 on the side away from the substrate. The n-type semiconductor current confinement layer and the p-type layer contact to form a heterojunction, which uses the heterojunction barrier to suppress the longitudinal and lateral transport of charge carriers.

[0049] In step S10, an insulating current-limiting layer 8 is grown using CVD or ALD methods and the second opening is filled. The surface of the insulating current-limiting layer 8 away from the substrate is flush with the surface of the p-type layer 62 away from the substrate. The annular insulating current-limiting layer 8 is an insulating dielectric layer, and the material is selected from SiO2, AlN, and Al2O3. 3、 One of HfO2 and Ta2O5. The characteristic size of the central via in the insulating current limiting layer is 0.1~1000 μm, and the vertical projection area of ​​the insulating current limiting layer 8 is greater than or equal to the vertical projection area of ​​the n-type semiconductor current limiting layer 7.

[0050] Furthermore, the transverse cross-sectional shape of the central via of the n-type semiconductor current limiting layer 7 and the insulating current limiting layer 8 is consistent. The cross-sectional shape is selected from one of a circle, ellipse, rectangle, or other polygon, and the characteristic size of the closed annular central via is 0.1~1000 μm. For example, the cross-sectional shape of the central via of the n-type semiconductor current limiting layer 7 is circular, such as... Figure 3 As shown, the diameter d ranges from 0.1 to 1000 μm.

[0051] Furthermore, the n-type layer 3 is an n-GaN layer with a thickness of 300~600 nm and a Si doping concentration of 1×10⁻⁶. 14 ~1×10 21cm -3 .

[0052] Furthermore, the active region 4 is selected from an InGaN / GaN multi-quantum-well structure, and the multi-quantum-well structure is an InGaN multi-quantum-well structure. x Ga 1-x Periodic structures formed by alternating deposition of N and GaN materials, with a period logarithm of 1~30, In x Ga 1-x The thickness of the N quantum well layer is 1~10 nm, and the thickness of the GaN barrier layer is 2~30 nm.

[0053] Furthermore, the electron blocking layer 5 is selected from a material with a band gap wider than that of the quantum barrier material. For example, the quantum barrier material is GaN, and the electron blocking layer material is p-Al. x Ga 1-x N, the thickness of electron blocking layer 5 is 5~50 nm, p-Al x Ga 1-x The N-layer has an Al composition of 0.01–0.5%, is doped with Mg, and has a hole concentration of 1 × 10⁻⁶. 16 ~1×10 19 cm -3 .

[0054] Furthermore, the p-type layer 6 can be a single p-GaN layer or multiple p-GaN layers. For example, the p-type layer 6 is a p-GaN layer with uneven doping concentration, where the doping concentration is higher near the current spreading layer. The doping element is Mg, and the hole concentration is 1×10⁻⁶. 16 ~1×10 20 cm -3 The thickness ranges from 1 to 500 nm. For example, p-type layer 6 is a p-GaN layer, which consists of two parts. The first part is close to the active region and has a thickness of 150 nm. The Mg doping concentration is 8 × 10⁻⁶. 17 cm -3 The second part is far from the active region, with a thickness of 20 nm, and a Mg doping concentration of 3 × 10⁻⁶. 18 ~8×10 19 cm -3 In some other embodiments, the p-type layer 6 is a composite structure of p-GaN and p-AlInGaN.

[0055] Furthermore, both the first distributed Bragg reflector 2 and the second distributed Bragg reflector 10 are composed of alternating semiconductor or dielectric layers with a period number of 1 to 200. The first distributed Bragg reflector 2 is composed of alternating AlN / GaN layers with a period number of 10 to 60; the second distributed Bragg reflector 10 is composed of alternating Ta2O5 / SiO2 layers with a period number of 5 to 30. In some embodiments, the periodic material of the first distributed Bragg reflector 2 is one of AlGaN / GaN and AlInN / GaN, and the periodic material of the second distributed Bragg reflector 10 is selected from one of TiO2 / SiO2, HfO2 / SiO2, and ZrO2 / SiO2.

[0056] The method for fabricating a vertical-cavity surface-emitting laser according to an embodiment of the present invention further includes the steps of forming an n-type electrode 12 and a p-type electrode 11. When fabricating the n-type electrode 12, a mesa of the n-type layer 3 needs to be formed by photolithography and etching, exposing a portion of the surface of the n-type layer 3, and the n-type electrode 12 is formed on the side of the n-type layer 3 away from the substrate 1. When fabricating the p-type electrode 11, a second distributed Bragg mirror 10 needs to be etched using photolithography and etching, exposing a portion of the surface of the current spreading layer 9, and the p-type electrode 11 is formed on the side of the current spreading layer 9 away from the substrate 1.

[0057] The vertical-cavity surface-emitting laser fabrication method provided by this invention uses MOCVD or MBE processes to grow the epitaxial layer, which includes an n-type layer, an active region, an electron blocking layer, a p-type layer, and an n-type semiconductor current-confining layer. The growth processes for the first distributed Bragg mirror, the second distributed Bragg mirror, and the insulating current-confining layer are selected from ALD, CVD, MOCVD, MBE, magnetron sputtering, etc. The growth process for the current-spreading layer is selected from ALD, CVD, magnetron sputtering, pulsed laser deposition, etc.

[0058] Figure 4 The image shown is an embodiment of the present invention containing n-Al x1→x2 Ga y1→y2 N( x 1 =0, x 2 =0.3, y 1 =1, y 2=0.7) Comparison of output optical power between a current-confined vertical-cavity surface-emitting laser (VCSEL) structure and a conventional GaN-based VCSEL without an n-type semiconductor current-confined layer. At an injection current of 10 mA, the output optical power of the conventional structure without an n-type semiconductor current-confined layer is 3.72 mW, and the threshold current is 3.66 mA; the output optical power of the structure with a linearly graded compositional n-Al is... 0→0.3 Ga 1→0.7 The vertical-cavity surface-emitting laser with an N-current-confined layer achieves an output optical power of 5.83 mW and a threshold current reduction to 2.93 mA. It can be seen that the laser provided by this invention increases the output optical power by 56.72% and reduces the threshold current by 0.73 mA compared to lasers with conventional structures; this demonstrates the effectiveness of the n-Al laser of this invention. x1→x2 Ga y1→y2 The optoelectronic performance of vertical cavity surface-emitting lasers with N-lateral current-limited structures is greatly improved.

[0059] Figure 5 The image shown is an embodiment of the present invention containing n-Al x1→x2 Ga y1→y2 N( x 1 =0, x 2 =0.3, y 1 =1, y 2 =0.7) Comparison of the lateral hole distribution in the third quantum well of a GaN-based vertical-cavity surface-emitting laser with a current-confined layer and a conventional GaN-based vertical-cavity surface-emitting laser without an n-type semiconductor current-confined layer. In this embodiment, the quantum well closest to the electron blocking layer 5 is the third quantum well. The results show that, compared with the conventional ordinary structure, n-Al with linearly graded composition... 0→0.3 Ga 1→0.7 The hole concentration within the aperture of the vertical-cavity surface-emitting laser with the N-current confinement layer is increased, which also indicates that n-Al x1→x2 Ga y1→y2 The pn junction formed by the N-type current-limiting layer and the p-type layer can effectively block holes from leaking to the device edge, thereby significantly improving the utilization rate of holes.

[0060] The above description is only used to illustrate the present invention and is not intended to limit the implementation method of the present invention in any way. Therefore, any modifications or alterations made to the present invention based on the shape, structure, features and basic ideas described herein should fall within the scope of intellectual property rights intended to be protected by the present invention.

Claims

1. A vertical-cavity surface-emitting laser structure, characterized in that, include: Substrate; A first distributed Bragg reflector located on the substrate; An n-type layer located on the side of the first distributed Bragg mirror away from the substrate; The active region located on the side of the n-type layer away from the substrate; An electron blocking layer located on the side of the active region away from the substrate; The p-type layer located on the side of the electron blocking layer away from the substrate; An n-type semiconductor current-confining layer is located inside the p-type layer. The band gap of the n-type semiconductor current-confining layer increases monotonically along the material growth direction. The thickness of the n-type semiconductor current-confining layer is less than the thickness of the p-type layer. The n-type semiconductor current-confining layer surrounds the edge of the p-type layer. The vertical projection area of ​​the n-type semiconductor current-confining layer is less than the vertical projection area of ​​the p-type layer. The p-type layer and the n-type semiconductor current-confining layer are in contact to form a heterojunction pn junction. An insulating current limiting layer is located on the side of the p-type layer away from the substrate. The insulating current limiting layer surrounds the edge of a portion of the p-type layer, and the surface of the insulating current limiting layer on the side away from the substrate is flush with the surface of the p-type layer on the side away from the substrate. A current spreading layer located on the side of the p-type layer and the insulating current limiting layer away from the substrate; A second distributed Bragg reflector located on the side of the current spreading layer away from the substrate.

2. The vertical-cavity surface-emitting laser structure according to claim 1, characterized in that: The n-type semiconductor current confinement layer is an n-Al alloy with a linearly graded composition of Al and Ga elements. x1→x2 Ga y1→y2 N, where 0 ≤ x 1< x 2≤1,0≤ y 2< y 1≤1, x 1+ y 1=1, x 2+ y 2=1, the n-Al x1→x2 Ga y1→y2 The N doping concentration is 1×10 14 ~ 1×10 21 cm -3 The n-Al x1→x2 Ga y1→y2 The thickness of N is less than the thickness of the p-type layer between the insulating current limiting layer and the electron blocking layer.

3. The vertical-cavity surface-emitting laser structure according to claim 1, characterized in that: The n-type semiconductor current confinement layer is an n-Al alloy with a nonlinearly graded composition of Al and Ga elements. x1→x2 Ga y1→y2 N, where 0 ≤ x 1< x 2≤1,0≤ y 2< y 1≤1, x 1+ y 1=1, x 2+ y 2=1, the n-Al x1→x2 Ga y1→y2 The N doping concentration is 1×10 14 ~ 1×10 21 cm -3 .

4. The vertical-cavity surface-emitting laser structure according to claim 1, characterized in that: The p-type layer is p-GaN, and the doping concentration of the p-GaN layer is non-uniform, with the doping concentration of the p-GaN layer near the current spreading layer being higher than that of the p-GaN layer near the electron blocking layer.

5. The vertical-cavity surface-emitting laser according to claim 1, characterized in that: The n-type semiconductor current limiting layer and the insulating current limiting layer form a closed ring, and the vertical projection area of ​​the ring insulating current limiting layer is greater than or equal to the vertical projection area of ​​the n-type semiconductor current limiting layer.

6. The vertical-cavity surface-emitting laser according to claim 1, characterized in that: The n-type semiconductor current limiting layer and the insulating current limiting layer form a closed ring. The shape of the central through-hole of the closed ring is consistent with the transverse cross-sectional shape of the central through-hole of the insulating current limiting layer. The cross-sectional shape is selected from one of a circle, an ellipse, a rectangle, or other polygons. The characteristic size of the annular central through-hole is 0.1~1000 μm. The size of the central through-hole of the insulating current limiting layer is less than or equal to the size of the central through-hole of the n-type semiconductor current limiting layer.

7. The vertical-cavity surface-emitting laser structure according to claim 1, characterized in that: The active region is a multi-quantum-well structure, which is an InGaN / GaN quantum well structure, including 1 to 30 cycles of InGaN quantum wells and GaN barrier layers.

8. The vertical-cavity surface-emitting laser structure according to claim 1, characterized in that: Both the first and second distributed Bragg reflectors are composed of alternating semiconductor or dielectric layers with a period number of 1 to 200.

9. A method for fabricating a vertical-cavity surface-emitting laser, characterized in that, include: A first distributed Bragg mirror is formed on the substrate; An n-type layer is formed on the side of the first distributed Bragg mirror away from the substrate; An active region is formed on the side of the n-type layer away from the substrate; An electron blocking layer is formed on the side of the active region away from the substrate; A first p-type layer is formed on the side of the electron blocking layer away from the substrate; An n-type semiconductor current-confining layer is formed on the side of the first p-type layer away from the substrate. The n-type semiconductor current-confining layer is a compositionally graded n-Al. x1→x2 Ga y1→y2 N, where 0 ≤ x 1< x 2≤1,0≤ y 2< y 1≤1, x 1+ y 1=1, x 2+ y 2 = 1; A first opening is formed in the n-type semiconductor current-limiting layer, the opening exposing a portion of the surface of the first p-type layer; A second p-type layer is grown at the first opening location. The second p-type layer fills the entire first opening and covers the entire surface of the first p-type layer and the n-type semiconductor current confinement layer away from the substrate. The n-type semiconductor current confinement layer surrounds the edge of the first p-type layer. The p-type layer and the n-type semiconductor current confinement layer contact to form a heterojunction. A second annular opening is formed around the edge of the second p-type layer. The longitudinal depth of the second opening is less than the thickness of the thinnest part of the second p-type layer. The projected area of ​​the second opening in the vertical direction is greater than or equal to the projected area of ​​the n-type semiconductor current limiting layer in the vertical direction. An insulating current limiting layer is filled at the second opening. The insulating current limiting layer surrounds the edge of the second p-type layer, and the surface of the insulating current limiting layer away from the substrate is flush with a portion of the surface of the second p-type layer away from the substrate. A current spreading layer is formed on the side of the second p-type layer and the insulating current limiting layer away from the substrate; A second distributed Bragg reflector is formed on the side of the current spreading layer away from the substrate.

Images