Delay-locked loop circuit and method of operation

Abstract

The invention relates to a delay-locked loop circuit and an operation method, the delay-locked loop circuit is used for providing an output clock signal to a bidirectional data control pin, and the delay-locked loop circuit comprises a first delay line used for delaying an input clock signal to generate the output clock signal; the second delay line is used for receiving the output clock signal and delaying the output clock signal to generate a feedback clock signal; the phase comparator is used for comparing according to the phase of the input clock signal and the phase of the feedback clock signal so as to adjust the delay of the first delay line; and a control circuit controlling the second delay line to adjust a delay of the second delay line to be aligned with a delay of the offline driver on the bidirectional data pin.

Description

Technical Field

[0001] This invention relates to a circuit and a method, and more particularly to a delay phase-locked loop circuit and its operation method. Background Technology

[0002] In existing memory standards, the AC parameter (tDQSCK) is provided to the bidirectional data control pin (DQS) and used to specify the alignment with the clock signal (CK). Therefore, generating an accurate tDQSCK has become an important consideration in the memory industry. Summary of the Invention

[0003] This invention provides a delay phase-locked loop circuit and its operation method, which can generate an accurate output clock signal.

[0004] The delay-locked loop (PLL) circuit of the present invention provides an output clock signal to a bidirectional data control pin. The PLL circuit includes: a first delay line for delaying an input clock signal to generate an output clock signal; a second delay line for receiving the output clock signal and delaying it to generate a feedback clock signal; a phase comparator for comparing the phases of the input clock signal and the feedback clock signal to adjust the delay of the first delay line; and a control circuit for controlling the second delay line to align its delay with the delay of the offline driver on the bidirectional data pin.

[0005] The operating method of this invention is applied to a delay-locked loop (DLL) circuit that provides an output clock signal to a bidirectional data strobe (DQS) pin. The operating method includes: delaying an input clock signal via a first delay line of the DLL circuit to generate an output clock signal; receiving the output clock signal via a second delay line of the DLL circuit and delaying the output clock signal by a first delay length to generate a feedback clock signal; comparing the phases of the input clock signal and the feedback clock signal via a phase comparator of the DLL circuit to generate a first comparison result signal; generating a first delay adjustment signal via a first control circuit of the DLL circuit based on the first comparison result signal to adjust the delay of the first delay line; and generating a second delay adjustment signal via the second control circuit of the DLL circuit to the second delay line, aligning the first delay length generated by the second delay line with the second delay length of the offline driver on the bidirectional data strobe pin.

[0006] The delay phase-locked loop circuit and operation method of the present invention can use a second delay line to simulate the delay of the offline driver, thereby effectively avoiding the direct use of the copy driver of the offline driver in the feedback path of the delay phase-locked loop circuit, and thus effectively reducing the power consumption generated by the delay phase-locked loop circuit and operation method. Attached Figure Description

[0007] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0008] Figure 1 This is a circuit block diagram of the delay phase-locked loop circuit according to Embodiment 1 of the present invention;

[0009] Figure 2A This is a circuit block diagram of the second control circuit in Embodiment 1 of the present invention;

[0010] Figure 2B A truth table correspondence diagram of the second comparison result signal and the second delay adjustment signal in Embodiment 1 of the present invention is shown;

[0011] Figure 3 This is a schematic diagram of the operating waveform of the second control circuit in Embodiment 1 of the present invention;

[0012] Figure 4 This is a circuit diagram of the second delay line and a feedback selection circuit according to Embodiment 1 of the present invention;

[0013] Figure 5A This is a flowchart of an operation method of the present invention;

[0014] Figure 5B for Figure 5A A detailed flowchart of the first step. Detailed Implementation

[0015] Figure 1 This is a circuit block diagram of a delay-locked loop (DLL) circuit 1 according to an embodiment of the present invention. The DLL circuit 1 can be applied in a memory to provide an output clock signal to a bidirectional data control pin. Generally speaking, the DLL circuit 1 includes a first receiver 10, a first delay line 11, a phase comparator 12, a first control circuit 13, a second receiver 14, a second delay line 15, and a second control circuit 16. The DLL circuit 1 can receive an input clock signal Clkin to generate an output clock signal Clkout, which serves as the clock signal tDQSCK in the memory system and meets the relevant standards of DDR3.

[0016] The delay-locked loop circuit 1 can adjust and lock the delay between the input clock signal Clkin and the output clock signal Clkout through feedback. Since the delay-locked loop circuit 1 provides the output clock signal Clkout to the bidirectional data control pin, in order to take into account the delay of the offline driver on the bidirectional data control pin and ensure that the output signal from the output clock signal Clkin to the output signal of the offline driver meets the relevant standards, the second delay line 15 in the delay-locked loop circuit 1 is controlled by the second control circuit 16. This allows the first delay length generated by the second delay line 15 to be adjusted to be the same as or close to the second delay length of the offline driver. Consequently, the phase comparator 12 compares the clock signal Clkin2 generated by the input clock signal Clkin with the clock signal Clkfb' generated by the feedback clock signal Clkfb. Through the joint operation of the phase comparator 12 and the first control circuit 13, the delay generated by the first delay line 11 is adjusted, thereby locking the delay between the input clock signal Clkin and the output clock signal Clkout within a preset delay range. Furthermore, after the delay phase-locked loop circuit 1 completes the locking of the output clock signal Clkout, the second control circuit 16 can be turned off to further save the power consumption of the delay phase-locked loop circuit 1.

[0017] The first receiver 10 receives the input clock signal Clkin and generates clock signals Clkin1 and Clkin2, which are then provided to the first delay line 11 and the phase comparator 12, respectively. The input clock signal Clkin and the clock signals Clkin1 and Clkin2 may be in phase or have a phase difference with a preset delay. For example, the first receiver 10 may be composed of a buffer or other suitable circuitry to provide clock signals Clkin1 and Clkin2 with preset delays. The first delay line 11 may have multiple delay units connected in series and can adjust the delay of its output clock signal Clkout, i.e., the time difference between the input clock signal Clkin and the output clock signal Clkout, according to the first delay adjustment signal DA1.

[0018] Furthermore, the output clock signal Clkout is provided to the second delay line 15. The second delay line 15 is controlled by the second control circuit 16, causing it to produce a delay that is the same as or similar to that of the offline driver. Next, the input clock signal Clkin and the feedback clock signal Clkfb are output as clock signals Clkin2 and Clkfb by the first receiver 10 and the second receiver 14, respectively, and provided to the phase comparator 12. The phase comparator 12 compares the phase or delay of the clock signals Clkin2 and Clkfb to generate a first comparison result signal including a ramp signal VU and a ramp signal VD, which in turn controls the first control circuit 13 to generate a first delay adjustment signal DA1 to the first delay line 11, thereby adjusting the delay of the output clock signal Clkout accordingly. Since the second delay line 15 is controlled by the second control circuit 15 and has a delay that is the same as or similar to that of the offline driver, the adjustment of the output clock signal Clkout can take into account the delay of the offline driver, thus conforming to the relevant standards of the memory. In addition, after locking the output clock signal Clkout, the second control circuit 16 can be turned off to further save the power consumption of the delay phase-locked loop circuit 1.

[0019] Figure 2A This is a circuit block diagram of the second control circuit 16 according to Embodiment 1 of the present invention. The second control circuit 16 includes an inverter INV1, a copy driver 160, a third delay line 162, and a detection circuit 161. The copy driver 160 can copy the circuit structure of the lower driver, therefore the copy drive signal init1 generated by the copy driver 160 has the same or similar delay as the lower driver. The third delay line 162 has multiple third delay line units 1621 to 1624 connected in series, and the third delay line 162 receives the same input signal as the copy driver 160, so that the third delay line units 1621 to 1624 are used to generate third delay line output signals init21 to init24 with different delay lengths. The detection circuit 161 is coupled to the copy driver 160 and the third delay line 162. It compares the copy drive signal init1 generated by the copy driver 160 with the third delay line output signals init21 to init24 generated by the third delay line 162. The circuit selects a third delay line unit from the third delay line units 1621 to 1624 and generates a second delay adjustment signal DA2 based on the selected third delay line unit. In the above description, although the second delay line 15 has four interconnected second delay line units 161 to 164, those skilled in the art can certainly make variations according to different applications. Therefore, different numbers of second delay line units are also within the scope of variations.

[0020] The copy driver 160 has the same delay as the offline driver. Therefore, the detection circuit 161 can determine a selected third delay line unit by comparing the copy drive signal init1 with the third delay line output signals init21 to init24. The output signal of the selected third delay line unit has a delay or phase close to that of the copy drive signal init1. In other words, the comparison process of the detection circuit 161 can be regarded as determining whether the delay generated by the copy driver 160 can be simulated or replaced by the delay of several third delay line units. Therefore, after the selected third delay line unit in the third delay line 162 is determined, the second control circuit 16 can generate a corresponding second delay adjustment signal DA2 to provide the number of the selected third delay line unit to the second delay line 15. Furthermore, the second delay line 15 and the third delay line 162 can have the same circuit structure. That is, the second delay line 15 is also formed by multiple second delay line units connected in series, and the circuit structure of each second delay line unit is the same as that of each third delay line unit 1621 to 1624. In this way, the second delay line 15 can select the same number of second delay line units according to the second delay adjustment signal DA2 to generate the feedback clock signal Clkfb, which has the same or similar delay as the offline driver.

[0021] Figure 3 This is a schematic diagram of the operating waveform of the second control circuit 16 in Embodiment 1 of the present invention. Please refer to the following... Figure 2A and Figure 3 Please refer to the following explanatory paragraphs to understand the operation of the second control circuit 16 in generating the second delay adjustment signal DA2.

[0022] When the second control circuit 16 receives a restart signal rst indicating a switch from a low voltage level to a high voltage level, it signifies that the delay phase-locked loop circuit 1 has been started or restarted. Consequently, the second controller 16 will be correspondingly turned on or enabled to operate, setting the delay generated by the second delay line 15. Following the start or restart of the phase-locked loop circuit 1, a start pulse signal init is provided to the second control circuit 16. Driven by the inverter INV1, the copy driver 160 and the third delay line 162 can respectively generate a copy drive signal init1 and third delay line output signals init21 to init24. The detection circuit 162 compares the copy drive signal init1 with the third delay line output signals init21 to init24, selecting the one closest to the copy drive signal init1 from the third delay line output signals init21 to init24 as the selected third delay line output signal. Selecting the closest signal to the replication drive signal init1 can refer to choosing the closest third delay line output signal from init21 to init24, which are either leading or lagging behind the replication drive signal init1, as the selected third delay line output signal. Furthermore, the third delay line unit that generates this selected third delay line output signal can also be selected as the selected third delay line unit. Accordingly, the detection circuit 161 can generate second comparison result signals C21 to C24 according to the comparison process, convert them into a second delay adjustment signal DA2 via the decoder 1610, and finally provide them to the second delay line 15 according to the drive of the phase-locked loop circuit start signal dll_st.

[0023] Specifically, the detection circuit 161 includes multiple comparison circuits 1611-1614, respectively coupled to the copy driver 160 and the corresponding third delay line units 1621-1624, to compare the copy drive signal init1 with the corresponding third delay line output signals init21-init24 to generate multiple second comparison result signals C21-C24. Each comparison circuit 1611-1614 can be a latch circuit, including a first NAND gate NG1 and a second NAND gate NG2. The first input terminal of the first NAND gate NG1 is coupled to the output terminal of the copy driver 160, and the second input terminal of the first NAND gate NG1 is coupled to the output terminal of the second NAND gate NG2. The output terminal of the first NAND gate NG1 generates the comparison signal. Furthermore, the first input terminal of the second NAND gate NG2 is coupled to the output terminal of the first NAND gate NG1, and the second input terminal of the second NAND gate NG2 is coupled to the output terminal of the corresponding third delay line unit.

[0024] Figure 2BA truth table diagram showing the correspondence between the second comparison result signals C21-C24 and the second delay adjustment signal DA2 in Embodiment 1 of the present invention is illustrated. The second comparison result signals C21-C24 generated by the detection circuit 161 have a thermometer code data format. In the second comparison result signals C21-C24, the phase relationship between the output signals init21-init24 of the third delay line at each stage and the replication drive signal init1 is represented, with a value of 1 indicating a leading position and a value of 0 indicating a lagging position. Therefore, the values ​​1111-1000 of the second comparison result signals C21-C24 represent different phase relationships. Figure 3 In this embodiment, since the negative edge of the copy drive signal init1 falls between the third delay line output signals init22 and init23, the second comparison result signals C21 to C24 generated by the comparison circuits 1611 to 1614 have a value of 1100. Further, the decoder 1610 can convert the second comparison result signals C21 to C24 of the thermometer code into a second delay adjustment signal DA2 of one-hot encoding. The decoder 1610 receives the second comparison result signals C21 to C24 with a value of 1100, converts them into the second delay adjustment signal DA2 with a value of 0100, and provides the second delay adjustment signal DA2 to the second delay line 15 under the drive of the phase-locked loop circuit start signal dll_st.

[0025] Figure 4 This is a circuit diagram of a second delay line 15 and a feedback selection circuit 17 according to an embodiment of the present invention. The second delay line 15 includes a series of multiple second delay line units 1511 to 1514 connected in series. More specifically, the second delay line 15 has the same circuit structure as the third delay line 162, and each second delay line unit 1511 to 1514 is identical to the third delay line units 1621 to 1624, thus having the same or similar delay. The feedback selection circuit 17 has multiple switching circuits TG1 to TG4, respectively coupled to the output terminals of the second delay line units 1511 to 1514, and selectively outputs one of the second delay line output signals Clkfb1 to Clkfb4 as a feedback clock signal Clkfb according to each bit of the second delay adjustment signal DA2. For example, the switching circuits TG1 to TG4 may be transmission gates, controlled by the corresponding bits of the second delay adjustment signal DA2 and the inverted second delay adjustment signal DA2b.

[0026] After the second control circuit 16 determines how many second delay line units to use to simulate the delay of the subsequent copy driver, the second control circuit 16 can generate a second delay adjustment signal DA2 carrying the quantity information. The second delay adjustment signal DA2 can be provided to the feedback selection circuit 17, so that the feedback selection circuit 17 selects the selected second delay line output signal from the second delay line output signals Clkfb1 to Clkfb4 and outputs it as the feedback clock signal Clkfb.

[0027] exist Figure 3 In the embodiment, when the feedback selection circuit 17 receives the second delay adjustment signal DA2 with a value of 0100, the switching circuit TG2 is turned on by the second delay adjustment signal DA2 bit with a value of 1 [2], so that the second delay line output signal Clkfb2 is selected as the selected second delay line output signal and output as the feedback clock signal Clkfb. In this way, the second delay line 15 can select the feedback clock signal Clkfb under the selection of the feedback selection circuit 17, which has the same or similar delay as the offline driver.

[0028] Finally, after the delay-locked loop circuit 1 completes locking, the second control circuit 16 can be shut down accordingly. Instead of directly setting a copy driver on the feedback path of the delay-locked loop circuit 1, the delay-locked loop circuit 1 chooses to serially arrange the second delay line units on the feedback path, and achieves a delay similar to or the same as the offline driver by appropriately selecting the number of second delay line units in the second delay line 15. In this way, by appropriately selecting the implementation method of the second delay line units (e.g., forming them as inverters), the same effect can be achieved with lower power consumption than the copy driver, and the second control circuit 16 is shut down after the output clock signal Clkout is locked, thus effectively reducing the power consumption of the delay-locked loop circuit 1.

[0029] Figure 5A This is a flowchart of an operation method of the present invention. Figure 5A The operation method shown can be applied to Figure 1The delay-locked loop circuit 1 includes steps S50-54. In step S50, the input clock signal Clkin is delayed by the first delay line 11 to generate the output clock signal Clkout. In step S51, the output clock signal Clkout is received by the second delay line 15, and the output clock signal Clkout is delayed by a first delay length to generate the feedback clock signal Clkfb. In step S52, the second control circuit 16 generates a second delay adjustment signal DA2 to the second delay line 15, aligning the first delay length generated by the second delay line 15 with the second delay length of the offline driver on the bidirectional data pin. In step S53, the phase comparator 12 compares the phases of the input clock signal Clkin and the feedback clock signal Clkfb to generate a first comparison result signal. In step S54, the first control circuit 13 generates a first delay adjustment signal DA1 based on the first comparison result signal to adjust the delay of the first delay line 11. Specifically, since the delay phase-locked loop circuit 1 has a loop circuit structure, the flowchart above does not specify the execution order of each step; they can be executed simultaneously or according to a preset order. For details of each step, please refer to the description of the delay phase-locked loop circuit 1 in the paragraph above, which will not be repeated here.

[0030] Figure 5B for Figure 5A Detailed flowchart of step S52 in the middle section. Figure 5B The detailed flowchart can be drawn by Figure 1The second control circuit 16 executes the steps S520 to S525. In step S520, the delay phase-locked loop circuit 1 is first started or restarted. In step S521, the second control circuit 16 receives a restart signal rst, thereby enabling each comparison circuit 1611 to 1614. In step S522, the second control circuit 16 receives a start pulse signal init, causing the copy driver 160 and the third delay line 162 to generate copy drive signal init1 and third delay line output signals init21 to init24, respectively. In step S523, the detection circuit 161 compares the phase of the copy drive signal init1 with the phase of the third delay line output signals init21 to init24 to find the closest selected third delay line output signal. In step S524, according to the drive of the phase-locked loop circuit start signal dll_st, the detection circuit 161 outputs the second delay adjustment signal DA2 to the second delay line 15, causing the second delay line 15 to generate a delay that is the same as or similar to that of the lower driver. In step S525, after the loop circuit 1 is locked, the second control circuit 16 can be correspondingly turned off or controlled to standby state to reduce power consumption until the restart signal rst is received next time, and then the loop of steps S521 to S525 is executed again to set the delay of the second delay line 15.

[0031] In summary, the delay-locked loop circuit and operating method of the present invention can achieve a delay similar to or the same as that of the offline driver by connecting adjustable second delay line units in series on the feedback path and appropriately selecting the number of second delay line units connected in series. In this way, by appropriately selecting the implementation method of the second delay line units, the same effect can be achieved with lower power consumption than the replication driver, and the second control circuit is shut down after the output clock signal is locked, thus effectively reducing the power consumption of the delay-locked loop circuit.

Claims

1. A delay phase-locked loop circuit for providing an output clock signal to a bidirectional data control pin, characterized in that, The delay phase-locked loop circuit includes: The first delay line is used to delay the input clock signal to generate the output clock signal; The second delay line is used to receive the output clock signal and delay the output clock signal by a first delay length to generate a feedback clock signal; A phase comparator is used to compare the phases of the input clock signal and the feedback clock signal to generate a first comparison result signal; A first control circuit is configured to generate a first delay adjustment signal based on the first comparison result signal, so as to adjust the delay of the first delay line; and A second control circuit is configured to generate a second delay adjustment signal to the second delay line, such that the first delay length generated by the second delay line is aligned with the second delay length of the offline driver on the bidirectional data pin.

2. The delay phase-locked loop circuit according to claim 1, wherein the second control circuit is turned on when the delay phase-locked loop circuit is started or restarted, and is turned off after the output clock signal is locked.

3. The delay phase-locked loop circuit according to claim 1, wherein the second delay line includes a plurality of second delay line units connected in series to generate a plurality of second delay line output signals with different delays, and the second control circuit selects a selected second delay line unit from the plurality of second delay line units by means of the second delay adjustment signal, so as to select the selected second delay line output signal generated by the selected second delay line unit as the feedback clock signal.

4. The delay-locked loop circuit according to claim 3, wherein the second control circuit comprises: A copy driver is used to generate a copy drive signal, which has the same delay as the offline driver; The third delay line has multiple third delay line units connected in series, and the multiple third delay line units respectively generate multiple third delay line output signals with different delay lengths; as well as A detection circuit is used to compare the copy drive signal and the output signals of the plurality of third delay lines to select a selected third delay line unit from the plurality of third delay line units, and to generate the second delay adjustment signal based on the selected third delay line unit.

5. The delay-locked loop circuit of claim 4, wherein when the delay-locked loop circuit is activated, a start pulse signal is provided to the copy driver to generate the copy drive signal, and the start pulse signal is provided to the third delay line to cause the plurality of third delay line units of the third delay line to generate the plurality of third delay line output signals respectively, and the detection circuit compares the copy drive signal with the plurality of third delay line output signals to select the selected third delay line unit from the plurality of third delay line units that has a delay close to the copy drive signal.

6. The delay phase-locked loop circuit according to claim 4, wherein the second delay line has the same circuit structure as the third delay line, and each second delay line unit and each third delay line unit also have the same circuit structure.

7. The delay-locked loop circuit according to claim 5, wherein the detection circuit comprises: Multiple comparison circuits are respectively coupled to the copy driver and the corresponding third delay line unit to compare the copy driver signal with the corresponding third delay line output signal to generate multiple second comparison result signals.

8. The delay phase-locked loop circuit according to claim 7, wherein each of the comparison circuits is a latch circuit, comprising a first NAND gate and a second NAND gate. The first input of the first NAND gate is coupled to the output of the copy driver, the second input of the first NAND gate is coupled to the output of the second NAND gate, and the output of the first NAND gate generates a comparison signal. The first input terminal of the second NAND gate is coupled to the output terminal of the first NAND gate, and the second input terminal of the second NAND gate is coupled to the output terminal of the corresponding third delay line unit.

9. The delay phase-locked loop circuit according to claim 3 further includes: The feedback selection circuit includes multiple switching circuits, each coupled to the output of the multiple second delay line units. The multiple switching circuits are controlled by multiple bits of the second delay adjustment signal. The feedback selection circuit selects the selected second delay line unit based on the multiple bits of the second delay adjustment signal and provides the selected second delay line output signal generated by the selected second delay line unit as the feedback clock signal to the phase comparator.

10. An operating method applied to a delay-locked loop circuit that provides an output clock signal to a bidirectional data control pin, characterized in that, The operation method includes: The input clock signal is delayed by the first delay line of the delay phase-locked loop circuit to generate the output clock signal; The output clock signal is received through the second delay line of the delay phase-locked loop circuit, and the output clock signal is delayed by a first delay length to generate a feedback clock signal; The phase comparator of the delay phase-locked loop circuit compares the phases of the input clock signal and the feedback clock signal to generate a first comparison result signal. The first control circuit of the delay phase-locked loop circuit generates a first delay adjustment signal based on the first comparison result signal to adjust the delay of the first delay line; and The second control circuit of the delay phase-locked loop circuit generates a second delay adjustment signal to the second delay line, so that the first delay length generated by the second delay line is aligned with the second delay length of the offline driver on the bidirectional data pin.

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