SC-LDPC code-based coding and decoding method and communication device

Abstract

The invention provides an SC-LDPC code-based coding and decoding method and a communication device, and the method comprises the steps: determining the column number kb1 of a first sub-code information column according to a target code rate and a column number set of sub-code information columns; determining an LDPC matrix according to the column number kb1 of the first sub-code information column; according to the SC-LDPC matrix, SC-LDPC coding is carried out on the information bit sequence, a code word sequence is obtained, and kb1, kb2 and L are all positive integers. According to the method, the column number of the sub-code information columns corresponding to different code rates is determined, the SC-LDPC matrix used for encoding the information bit sequence is determined through the column number of the sub-code information columns, adaptation of SC-LDPC codes to different code rates is achieved, and the requirements of different code rates are met.

Description

Technical Field

[0001] This application relates to the field of channel coding. More specifically, it relates to a coding and decoding method and a communication device based on spatially coupled low-density parity check (SC-LDPC) codes. Background Technology

[0002] Spatially coupled low-density parity check (SC-LDPC) codes connect multiple low-density parity check (LDPC) block codes together in a spatially coupled manner, forming a coupled chain. This coupling structure allows SC-LDPC codes to utilize information from adjacent block codes during decoding, thus achieving excellent decoding performance. Since the code rate of each subcode in an SC-LDPC code is fixed, the overall code rate of the SC-LDPC code is also fixed. Therefore, enabling SC-LDPC codes to support different code rates is currently a hot research topic. Summary of the Invention

[0003] This application provides a coding and decoding method based on SC-LDPC codes, aiming to adapt SC-LDPC codes to different code rates.

[0004] Firstly, an encoding method based on SC-LDPC codes is provided. This method can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), a component in the transmitting device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0005] The method includes: determining the number of columns kb1 of the first sub-code information column based on the target code rate and the set of column numbers of the sub-code information column; determining the SC-LDPC matrix based on the number of columns kb1 of the first sub-code information column; and performing SC-LDPC encoding on the information bit sequence based on the SC-LDPC matrix to obtain a codeword sequence, wherein kb1, kb2 and L are all positive integers.

[0006] It should be understood that the SC-LDPC matrix in this application can be the parity check matrix H of the SC-LDPC code. sc The parity check matrix B of the QC SC-LDPC code or the generator matrix of the SC-LDPC code, etc.

[0007] In the above technical solution, the number of columns kb1 of the first sub-code information column is determined according to the target code rate, and the SC-LDPC matrix used to encode the information bit sequence is further determined according to the number of columns kb1 of the first sub-code information column. This method can determine the number of columns of the corresponding sub-code information column based on different code rates, and determine the SC-LDPC matrix used to encode the information bit sequence according to the number of columns of the sub-code information column, thereby realizing the adaptation of SC-LDPC code to different code rates and meeting the requirements of different code rates.

[0008] In some implementations of the first aspect, determining the SC-LDPC matrix based on the number of columns kb1 of the first subcode information column includes: determining the length k of the first subcode information and the coupling length L of the SC-LDPC matrix based on the number of columns kb1 of the first subcode information column and the target information length K; determining a boost value based on the number of columns kb1 of the first subcode information column and the length k of the first subcode information; and determining the SC-LDPC matrix based on the number of columns kb1 of the first subcode information column, the boost value, and the coupling length L, wherein K, k, and L are all positive integers.

[0009] Based on the above technical solution, a specific implementation method is given for determining the SC-LDPC matrix according to the number of columns kb1 of the first subcode information column.

[0010] In some implementations of the first aspect, determining the SC-LDPC matrix based on the number of columns kb1 of the first subcode information column includes: determining the length k of the first subcode information and the coupling length L of the SC-LDPC matrix based on the number of columns kb1 of the first subcode information column and the target information length K; determining a boosting value based on the number of columns kb1 of the first subcode information column and the length k of the first subcode information; determining the number of columns kb2 of the second subcode information column based on the length k of the first subcode information and the boosting value; and determining the SC-LDPC matrix based on the number of columns kb2 of the second subcode information column, the boosting value, and the coupling length L, wherein K, k, kb2, and L are all positive integers.

[0011] Based on the above technical solution, another specific implementation method is given for determining the SC-LDPC matrix according to the number of columns kb1 of the first subcode information column.

[0012] In some implementations of the first aspect, the method further includes: determining a first rate matching number M1 and a first rate matching method based on the number of columns kb1 of the first subcode information column, and punching or shortening the codeword sequence according to the first rate matching number M1 and the first rate matching method, wherein the number of columns of the subcode information column included in the subcode base matrix corresponding to the codeword sequence after the first rate matching is kb1, and the first rate matching includes the first rate matching number M1 and the first rate matching method.

[0013] Alternatively, it can be understood as follows: the number of columns kb1 of the first subcode information column is used to determine the first rate matching number M1 and the first rate matching method. During the encoding process, the codeword sequence is obtained by punching or shortening the codeword sequence after the first rate matching number M1 and the first rate matching method. The number of columns of the subcode information column included in the subcode base matrix corresponding to the codeword sequence after the first rate matching is the number of columns kb1 of the first subcode information column.

[0014] In some implementations of the first aspect, the number of columns kb1 of the first subcode information column satisfies:

[0015] or

[0016] Where ceil represents rounding up, floor represents rounding down, R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures.

[0017] In some implementations of the first aspect, the rounding up calculation method corresponds to the shortening rate matching method, and the rounding down calculation method corresponds to the punching rate matching method.

[0018] In some implementations of the first aspect, if or The minimum value kb in the set of column numbers less than the subcode information column min When, kb1 = kb min ;like or The maximum value kb in the set of column numbers greater than the subcode information column max When, kb1 = kb max .

[0019] In some implementations of the first aspect, the number of punctures P1 in the first rate matching satisfies: The shortening number S1 in the first rate matching satisfies: Where ceil represents rounding up, R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures.

[0020] In some implementations of the first aspect, the method further includes: determining a second rate matching number M2 and a second rate matching method based on the number of columns kb2 of the second subcode information column, and punching or shortening the code subsequence according to the second rate matching number M2 and the second rate matching method, wherein the number of columns of the subcode information column included in the subcode base matrix corresponding to the codeword sequence after the second rate matching is kb2, and the second rate matching includes the second rate matching number M2 and the second rate matching method.

[0021] Alternatively, it can be understood as follows: the number of columns kb2 of the second subcode information column is used to determine the second rate matching number M2 and the second rate matching method. During the encoding process, the codeword sequence is obtained by punching or shortening the codeword sequence after the second rate matching number M2 and the second rate matching method. The number of columns of the subcode information column included in the subcode base matrix corresponding to the codeword sequence after the second rate matching is the number of columns kb2 of the second subcode information column.

[0022] In some implementations of the first aspect, the number of columns kb2 of the second subcode information column satisfies:

[0023] or, or,

[0024] Where ceil represents rounding up, floor represents rounding down, and Zc represents the boost value.

[0025] In some implementations of the first aspect, the rounding up calculation method corresponds to the shortening in the rate matching, and the rounding down calculation method corresponds to the punching in the rate matching.

[0026] In some implementations of the first aspect, if or, or, The minimum value kb in the set of column numbers less than the subcode information column min When, kb2 = kb min ;like or, or, The maximum value kb in the set of column numbers greater than the subcode information column max When, kb2 = kb max .

[0027] In some implementations of the first aspect, the number of punctures P2 in the second rate matching satisfies: The shortening number S2 in the second rate matching satisfies: Where ceil represents rounding up, R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures.

[0028] In some implementations of the first aspect, determining the number of columns kb1 of the first subcode information column based on the target code rate and the set of column numbers of the subcode information column includes: determining the number of columns kb1 of the first subcode information column based on the target code rate, the number of rows C of the subcode base matrix and the predefined rate matching number M, where C is a positive integer and P is an integer.

[0029] In some implementations of the first aspect, determining the boost value based on the number of columns kb1 of the first sub-code information column and the length k of the first sub-code information includes: determining the boost value based on the number of columns kb1 of the first sub-code information column and the length k of the second sub-code information. de The boost value is determined by a set of boost values, wherein the length of the second code sub-information is used to determine the length k of the first code sub-information.

[0030] In some implementations of the first aspect, the length K of the second subcode information de The first function f(x) is used to determine the length k of the first subcode information, and the length k of the first subcode information satisfies:

[0031]

[0032] Where p is a positive integer, k1, k2, ..., k p All are positive integers, and k1 <k2<…<k p K1, K2, ..., K p-1 All are positive integers, and K1 <K2<…<K p-1 .

[0033] In some implementations of the first aspect, the first function includes the parameter K. i and k i And satisfy:

[0034]

[0035] Where w1 and w2 represent the range of the decoding window length corresponding to the first function, and w1≤w2, w1, w2, K i and k i All are positive integers.

[0036] In some implementations of the first aspect, w1≤10, w2≥20.

[0037] In some implementations of the first aspect, the length k of the first subcode information belongs to a set of first subcode information lengths, which is determined by a set of column numbers and a set of promotion values ​​for the subcode information columns.

[0038] Secondly, a decoding method based on SC-LDPC code is provided. This method can be executed by a receiving device. Unless otherwise specified, the term "receiving device" in this application can refer to the receiving device itself (e.g., network device, terminal device), a component in the receiving device (e.g., processor, chip, or chip system), or a logic module or software that can implement all or part of the functions of the receiving device.

[0039] The method includes: determining the number of columns kb1 of the first sub-code information column based on the target code rate and the set of column numbers of the sub-code information column; determining the SC-LDPC matrix based on the number of columns kb1 of the first sub-code information column; and performing SC-LDPC decoding on the symbol sequence number based on the SC-LDPC matrix to obtain the information bit sequence, wherein kb1 is a positive integer.

[0040] For the beneficial effects of the second aspect, please refer to the description of the first aspect, which will not be repeated here.

[0041] In some implementations of the second aspect, determining the SC-LDPC matrix based on the number of columns kb1 of the first sub-code information column includes: determining the length k of the first sub-code information and the coupling length L of the LDPC code based on the number of columns kb1 of the first sub-code information column and the target information length K; determining a boost value based on the number of columns kb1 of the first sub-code information column and the length k of the first sub-code information; and determining the SC-LDPC matrix based on the number of columns kb1 of the first sub-code information column, the boost value, and the coupling length L, wherein K, k, and L are all positive integers.

[0042] In some implementations of the second aspect, determining the SC-LDPC matrix based on the number of columns kb1 of the first subcode information column includes: determining the length k of the first subcode information and the coupling length L of the SC-LDPC matrix based on the number of columns kb1 of the first subcode information column and the target information length K; determining a boosting value based on the number of columns kb1 of the first subcode information column and the length k of the first subcode information; determining the number of columns kb2 of the second subcode information column based on the length k of the first subcode information and the boosting value; and determining the SC-LDPC matrix based on the number of columns kb2 of the second subcode information column, the boosting value, and the coupling length L, wherein kb2, K, k, and L are all positive integers.

[0043] In some implementations of the second aspect, the method further includes: determining a first solution rate matching number M1 based on the column number kb1 of the first subcode information column, and performing a first solution rate matching on the symbol sequence according to the first solution rate matching number M1.

[0044] Alternatively, it can be understood that the column number kb1 of the first subcode information column is used to determine the first solution rate matching number M1. During the decoding process, the symbol sequence is de-rate matched based on the first solution rate matching number M1.

[0045] In some implementations of the second aspect, the number of columns kb1 of the first subcode information column satisfies:

[0046] or

[0047] Where ceil represents rounding up, floor represents rounding down, R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures.

[0048] In some implementations of the second aspect, the rounding up calculation method corresponds to the shortening rate matching method, and the rounding down calculation method corresponds to the punching rate matching method.

[0049] In some implementations of the second aspect, if or The minimum value kb in the set of column numbers less than the subcode information column min When, kb1 = kb min ;like or The maximum value kb in the set of column numbers greater than the subcode information column max When, kb1 = kb max .

[0050] In some implementations of the second aspect, the first solution rate matching number M1 is equal to P1 or S1.

[0051] Where ceil represents rounding up, R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures.

[0052] In some implementations of the second aspect, the method further includes: determining a second solution rate matching number M2 based on the column number kb2 of the second subcode information column, and performing a second solution rate matching on the symbol sequence according to the second rate matching number M2.

[0053] Alternatively, it can be understood that the number of columns kb2 of the second subcode information column is used to determine the second solution rate matching number M2. During the decoding process, the symbol sequence is de-rate matched based on the second solution rate matching number M2.

[0054] In some implementations of the second aspect, the number of columns kb2 of the second subcode information column satisfies:

[0055] or, or,

[0056] Where ceil represents rounding up, floor represents rounding down, and Zc represents the boost value.

[0057] In some implementations of the second aspect, if or, or, The minimum value kb in the set of column numbers less than the subcode information column min When, kb2 = kb min like or, or, The maximum value kb in the set of column numbers greater than the subcode information column max When, kb2 = kb max .

[0058] In some implementations of the second aspect, the second solution rate matching number M2 is equal to P2 or S2.

[0059]

[0060] Where ceil represents rounding up, R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures.

[0061] In some implementations of the second aspect, determining the number of columns kb1 of the first subcode information column based on the target code rate and the set of column numbers of the subcode information column includes: determining the number of columns kb1 of the first subcode information column based on the target code rate, the number of rows C of the subcode base matrix and the predefined rate matching number M, where C is a positive integer and P is an integer.

[0062] In some implementations of the second aspect, determining the boost value based on the number of columns kb1 of the first sub-code information column and the length k of the first sub-code information includes: determining the boost value based on the number of columns kb1 of the first sub-code information column and the length k of the second sub-code information. de The boost value is determined by a set of boost values, wherein the length of the second code sub-information is used to determine the length k of the first code sub-information.

[0063] In some implementations of the second aspect, the length K of the second subcode information de The first function f(x) is used to determine the length k of the first subcode information, and the length k of the first subcode information satisfies:

[0064]

[0065] Where p is a positive integer, k1, k2, ..., k p All are positive integers, and k1 <k2<…<k p K1, K2, ..., K p-1 All are positive integers, and K1 <K2<…<K p-1 .

[0066] In some implementations of the second aspect, the first function includes the parameter K. i and k i And satisfy:

[0067]

[0068] Where w1 and w2 represent the range of the decoding window length corresponding to the first function, and w1≤w2, w1, w2, K i and k i All are positive integers.

[0069] In some implementations of the second aspect, w1≤10, w2≥20.

[0070] In some implementations of the second aspect, the length k of the first subcode information belongs to the set of first subcode information lengths, which is determined by the set of the number of columns of the subcode information columns and the set of promotion values.

[0071] Thirdly, a communication apparatus is provided for performing the method provided by any of the above aspects or their implementations. Specifically, the apparatus may include units and / or modules for performing the method provided by any of the above aspects or their implementations, such as processing units and / or transceiver units.

[0072] In one implementation, the device is either a transmitting device or a receiving device. When the device is a transmitting device or a receiving device, the transceiver unit can be a transceiver, an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0073] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device. When the device is a chip, chip system, or circuit used in a transmitting or receiving device, the transceiver unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0074] Fourthly, a communication device is provided, comprising: a memory for storing a program; and at least one processor for executing the computer program or instructions stored in the memory to perform the method provided in any of the foregoing aspects or their implementations.

[0075] In one implementation, the device is either a transmitting device or a receiving device.

[0076] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device.

[0077] Fifthly, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to obtain a computer program or instructions stored in a memory via the communication interface to execute the method provided in any of the foregoing aspects or their implementations. The communication interface may be implemented in hardware or software.

[0078] In one implementation, the device further includes the memory.

[0079] Sixthly, a processor is provided for executing the methods provided in the above aspects.

[0080] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0081] In a seventh aspect, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including methods for performing any of the foregoing aspects or their implementations.

[0082] Eighthly, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the method provided in any of the foregoing aspects or their implementations.

[0083] Ninthly, a chip is provided, comprising a processor and a communication interface. The processor reads instructions stored in a memory through the communication interface and executes the methods provided in any of the above aspects or their implementations. The communication interface can be implemented in hardware or software.

[0084] Optionally, as one implementation, the chip also includes a memory that stores computer programs or instructions. The processor is used to execute the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the processor is used to perform the methods provided by any of the above aspects or their implementations.

[0085] When the method provided in this application is executed by a chip, this application does not limit the specific number of chips implementing the method. For example, it can be executed by one chip, or by two or more chips. Furthermore, when the number of chips implementing the method is two or more, the chip manufacturers are not limited; they can be from the same manufacturer or different manufacturers.

[0086] In a tenth aspect, a computer program is provided that, when run on a computer, causes the methods provided by any of the foregoing aspects or their implementations to be executed.

[0087] Eleventhly, a communication system is provided, including at least one of the transmitting end device or receiving end device described above. Attached Figure Description

[0088] Figure 1 This is a schematic diagram of a network architecture that can be applied to embodiments of this application.

[0089] Figure 2 This is a schematic diagram of the parity check matrix H of an LDPC.

[0090] Figure 3 This is a Tanner plot of the parity-check matrix H of an LDPC.

[0091] Figure 4 This is a schematic diagram of the structure of the parity check matrix.

[0092] Figure 5 This is a schematic diagram of the information transmission process.

[0093] Figure 6 This is a schematic flowchart of a coding and decoding method 600 based on SC-LDPC codes provided in an embodiment of this application.

[0094] Figure 7 This is a schematic diagram illustrating the coding performance simulation of SC-LDPC codes provided in an embodiment of this application.

[0095] Figure 8This is a schematic block diagram of the communication device 1000 provided in the embodiments of this application.

[0096] Figure 9 A schematic block diagram of a communication device 1100 provided in an embodiment of this application. Detailed Implementation

[0097] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0098] The terms "for indicating" or "instruction" can include both direct and indirect indication, or they can be explicit and / or implicit. The various numerical designations such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, such as distinguishing different messages or different information. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device; this application does not limit the specific implementation method. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. The words "exemplary," "for example," "exemplary," "as another example," etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. "At least one" means one or more, while "more" means two or more. "At most one" means one or zero. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple. Descriptions relating to network element A sending messages, information, or data to network element B, and network element B receiving messages, information, or data from network element A, aim to specify which network element the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other network elements. Descriptions such as "when…", "in the case of…", "if", and "if" indicate that the device will take corresponding action under certain objective circumstances, not a time limit, nor requiring the device to perform a judgment action during implementation, nor implying any other limitations. Phrases such as "corresponding to…", "correspondingly", and equivalent expressions indicate a correspondence between the preceding and following elements, which may include indirect correspondence. For example, corresponding to a certain objective situation, the device will directly or indirectly take corresponding action, without requiring the corresponding action to immediately follow that objective situation.

[0099] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0100] The following describes a communication system to which embodiments of this application can be applied.

[0101] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, long term evolution-advanced (LTE-A) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0102] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0103] Figure 1 This is a schematic diagram of a network architecture applicable to embodiments of this application. For example... Figure 1 As shown, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 This document uses only uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as examples. In uplink data transmission, the sending device is the terminal device and the receiving device is the network device; conversely, in downlink data transmission, the sending device is the network device and the receiving device is the terminal device. Furthermore, the applicability of the embodiments of this application to other communication scenarios is not limited; for example, they can also be applied to sidelink communication.

[0104] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0105] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home-evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, RAN equipment including CU and DU nodes, RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes, or, in a cloud radio access network (CRAN) scenario, wireless controllers, relay stations, vehicle-mounted equipment, and wearable devices. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in future communication networks, or equipment performing base station functions in future communication networks. A base station may support networks with the same or different access technologies, without limitation.

[0106] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0107] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0108] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, URLLC (ultrareliable low-latency communication) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0109] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0110] To facilitate understanding of the solutions in this application, the terminology used in this application will be introduced first.

[0111] 1. Low-density parity check (LDPC) code

[0112] LDPC codes are linear block codes with a sparse parity-check matrix. When the code length is long, the number of zero elements in the LDPC parity-check matrix far exceeds the number of non-zero elements; in other words, the row and column weights of the parity-check matrix are very small compared to the LDPC code length. Specifically, an LDPC code with an information bit sequence of length k and a code length of n can be uniquely determined by its parity-check matrix or generator matrix. This information bit sequence can be the payload bit sequence or a bit sequence with added cyclic redundancy check (CRC) bits; this application does not impose any limitation on this.

[0113] In 1981, Tanner represented the codewords of LDPC graphically, and this type of graph is now called a Tanner graph. There is a one-to-one correspondence between the Tanner graph and the parity-check matrix. The Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes; the other type consists of parity nodes, representing parity constraints. Each parity node represents a parity constraint. The following section will discuss this in conjunction with... Figure 1 and Figure 2 Please provide an explanation.

[0114] Figure 2 This is a schematic diagram of the parity check matrix H of LDPC.

[0115] Figure 2 In the diagram, {Vi} represents the set of variable nodes, and {Ci} represents the set of check nodes. Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. Figure 1 In the diagram, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner diagram.

[0116] Figure 3 This is the Tanner plot of the parity-check matrix H of LDPC.

[0117] like Figure 3As shown, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size M rows and N columns, the Tanner graph contains two types of nodes: N variable nodes and M parity nodes. The N variable nodes correspond to the N columns of the parity-check matrix H, and the M parity nodes correspond to the M rows of the parity-check matrix H. A loop in the Tanner graph consists of interconnected vertices, with one vertex serving as both the start and end point, and each loop traversing each node only once. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC; the parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to each parity bit in the LDPC. The connection between the two types of nodes corresponds to the value of an element in the H matrix. For example, if there is a connection between the i-th parity node and the j-th variable node, the element (i,j) in the H matrix has a value of 1; if there is no connection, the corresponding element is 0. The connection between variable nodes and parity nodes can also be called an edge. There is a connection between the verification node and the variable node, which can also be described as: there is a connection relationship between the verification node and the variable node.

[0118] 2. Quasi-cyclic low-density parity check (QC-LDPC) code

[0119] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be achieved using a simple feedback shift register, reducing the encoding complexity of LDPC. When the code length is long, the parity-check matrix H of an LDPC can become very large; therefore, H is usually represented in blocks: the complete parity-check matrix H is considered as consisting of multiple Z... c ×Z c The complete parity check matrix H is generated from a submatrix. Specifically, the complete parity check matrix H can be generated from an exponential matrix H. b H indicates b Each element in the array corresponds to a Z. c ×Z c The submatrices, each of which can be represented by a single cyclically shifted bit, greatly reduce the storage space required for the complete parity check matrix H. The exponential matrix H... b The elements in it can also be called quasi-cyclic (QC) blocks.

[0120] Based on the exponential matrix H b And increase size Z c (lifting size) can be used to transform the exponential matrix H b Expanded into a complete parity-check matrix H for encoding or decoding. Zc (lifting size) can also be called expansion factor, lifting factor, lifting value, expansion value, expansion coefficient, etc. In this application, the lifting value is used as the description.

[0121] For example, the exponent matrix H of a QC-LDPC of size m*n b As shown below:

[0122]

[0123] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, with elements Let Z represent the cyclic permutation matrix, where i represents the cyclic shift value, and 0 ≤ i ≤ Z. c -1, where i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0124] Here, Z is used. c =4. Taking i=0 / 1 / 2 / 3 as an example, let's illustrate circular shift. They are shown below:

[0125]

[0126] For example, the exponent matrix H b In addition to using "-1" to represent zero elements, there are other ways to represent them, such as using "-" or null values ​​to represent a matrix of all zeros.

[0127] 3. Spatially Coupled Low Density Parity Check (SC-LDPC) Code

[0128] The parity check matrix H of SC-LDPC sc As shown below:

[0129]

[0130] Among them, H sc It is constructed by coupling L groups of sub-codes (sub-codes or sub-matrices). Each group of sub-codes in the L groups is identical, and each group of sub-codes in the L groups includes w+1 sub-codes, which can be represented as H0, H1, ..., H w Each subcode H i Given an M*N matrix, we can derive H from this. sc The size of the matrix is ​​[M*(w+L)]*(N*L). Here, L is called the coupling length and w is called the coupling width.

[0131] For example, each subcode H i The structure can be referenced Figure 1 The verification matrix H is shown.

[0132] Specifically, if the w+1 subcodes in each group of L subcodes are the same, it is called a time-invariant SC-LDPC code; if the w+1 subcodes in each group of L submatrices are different, it is called a time-varying SC-LDPC code.

[0133] It should be understood that some rows in the last Mw row of the above parity check matrix can be truncated, which can reduce the impact of truncating the SC-LDPC code on the code rate.

[0134] 4. Quasi-cyclic spatially-coupled lowdensity parity check (QC SC-LDPC) code

[0135] The QC SC-LDPC verification matrix B is shown below:

[0136]

[0137] Here, B is constructed by coupling L groups of sub-codes. Each group of sub-codes in the L groups of sub-matrices is identical, and each group of sub-codes in the L groups of sub-codes includes w+1 sub-codes, which can be represented as B0, B1, ..., B w Each subcode B i Given an m*n matrix, we can derive H from this. sc The size of the matrix is ​​[m*(w+L)]*(n*L). Here, L is called the coupling length and w is called the coupling width.

[0138] For example, each subcode B i The construction can refer to the exponential matrix H of QC-LDPC of size m*n shown above. b .

[0139] Specifically, if the w+1 subcodes in each group of L subcodes are the same, it is called a time-invariant QC SC-LDPC code; if the w+1 subcodes in each group of L subcodes are different, it is called a time-varying QC SC-LDPC code.

[0140] It should be understood that some rows in the last mw row of the above parity check matrix can be truncated, which can reduce the impact of truncating the QCSC-LDPC code on the code rate.

[0141] 5. Non-zero elements and zero elements

[0142] In this application, zero elements in the check matrix indicate that there is no connection between the variable node and the check node. Non-zero elements in the check matrix indicate that there is a connection between the variable node and the check node.

[0143] This application does not limit the specific representation of zero and non-zero elements. For example, in the exponential matrix H b In a matrix, "-1" can be used to represent a zero element, and "non-negative value" can be used to represent a non-zero element. Similarly, in a parity check matrix H, "0" can be used to represent a zero element, and "1" can be used to represent a non-zero element.

[0144] For ease of description, the following text will use "0" to represent zero elements and "1" to represent non-zero elements.

[0145] 6. Column weight and row weight

[0146] For a column of a matrix, column weight refers to the number of non-zero elements contained in that column. For a row of a matrix, row weight refers to the number of non-zero elements contained in that row. For example, ... Figure 1 As shown, the column weight of the first column of the parity check matrix H is 2, and the row weight of the first row is 4. For example, consider the exponent matrix H mentioned above. b The column weight of the first column is 4, and the row weight of the first row is 20.

[0147] 7. Basic Structure of the Check Matrix

[0148] like Figure 4 As shown in (a), the parity-check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include... Figure 4 As shown in (b), parts A and B are defined, where part A corresponds to information bits (or information digits, etc.), and part B is a square matrix corresponding to core check bits (or core check digits). Part B can also be the region corresponding to check columns with a column weight greater than 1. A region of all zeros can correspond to... Figure 4 The C part of (b) is an all-zero matrix. The incremental redundancy region can correspond to Figure 4 Part D of (b). The Laptian-like region can correspond to Figure 4 The E part of (b) can be an identity matrix or a lower triangular matrix, corresponding to the parity bits of the low code rate extension.

[0149] Figure 4The LDPC code shown employs a "raptor-like" base matrix structure, which can be progressively extended from a high-rate kernel matrix to a low-rate matrix, thus flexibly supporting encoding at various code rates. In practical applications, such as... Figure 4 As shown in (a), the first X rows and first Y columns of the parity check matrix can be extracted. As the bitrate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands. The difference between X and Y represents the number of information columns.

[0150] 8. Information Transmission Process

[0151] Figure 5 This is a diagram illustrating the information transmission process. For example... Figure 5 As shown, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery before reaching the destination, completing the transmission of information from the source to the destination. Figure 5 The processing shown in the upper layer (including source coding, channel coding, and modulation) is performed at the transmitting end (i.e., the coding device described below), while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed at the receiving end (i.e., the decoding device described below).

[0152] The embodiments of this application mainly involve Figure 5 The diagram shows source coding, channel coding, channel decoding, and source recovery.

[0153] As described in the background section, SC-LDPC codes connect multiple LDPC block codes together through spatial coupling, forming a coupled chain. This coupling structure allows SC-LDPC codes to utilize information from adjacent block codes during decoding, thus achieving excellent decoding performance. The code rate of each sub-code within an SC-LDPC code is fixed, resulting in a fixed overall code rate.

[0154] Due to the aforementioned technical issues, SC-LDPC codes cannot achieve different code rates by adding additional parity bits. To enable SC-LDPC codes to adapt to different code rates and meet the encoding requirements of different code rates, this application provides a coding and decoding method based on SC-LDPC codes, which allows SC-LDPC codes to adapt to different code rates.

[0155] Figure 6 A schematic flowchart of an SC-LDPC code-based encoding and decoding method 600 provided in this application. The method includes the following steps.

[0156] It is understood that method 600 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to implement this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. Among them, the sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0157] 610, The sending device obtains the information bit sequence.

[0158] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, then the sending device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0159] The process of the transmitting device acquiring the information bit sequence can refer to: the transmitting device performing source encoding on the source symbols to generate the information bit sequence; or, the transmitting device acquiring the information bit sequence can also refer to: the transmitting device receiving the information bit sequence from other communication devices. This application does not limit the method of acquiring the information bit sequence.

[0160] 620, The transmitting device determines the SC-LDPC matrix.

[0161] It should be understood that the SC-LDPC matrix determined by the transmitting device can be the parity check matrix H of the SC-LDPC code. sc The parity-check matrix B of the QC-LDPC code, the parity-check matrix H of the LDPC code, or the exponent matrix H of the QC-LDPC code. b However, this application does not limit this.

[0162] It should also be understood that the sending device may determine the SC-LDPC matrix through the following steps:

[0163] Step 1: The transmitting device determines the number of columns kb1 of the first sub-code information column based on the target code rate and the set of column numbers of the sub-code information column.

[0164] It should be understood that the code rate is the ratio between the number of information bits and the number of transmitted bits. This target code rate can be predefined by the system for both the sending and receiving devices. Assuming there is a mapping relationship between the information bit sequence and the target code rate, the sending device, after acquiring the information bit sequence, can determine the target code rate corresponding to that information bit sequence based on the predefined mapping relationship. Alternatively, the target code rate can be pre-configured by higher-layer signaling, medium access control (MAC) layer, or downlink physical layer signals. Or, the target code rate can be directly acquired or calculated by the sending (or receiving) device.

[0165] It should also be understood that the set of column numbers for the subcode information column (or simply KB) includes the number of column numbers of the information columns supported by the subcode. For example, the set of column numbers for the subcode information column may include one or more of {1, 2, 3, ..., 11}.

[0166] The subcode information column can be understood as follows: in SC-LDPC codes, the SC-LDPC code is composed of multiple LDPC subcodes through spatial coupling. Here, "subcode" can refer to the basic LDPC code block that constitutes the SC-LDPC code, such as the parity-check matrix H of the SC-LDPC code mentioned above. sc All H corresponding to each column in i This forms a subcode, which can be time-related; for example, column t is the subcode for time t. This H i They share information columns. Each subcode column contains information bits and parity bits, which correspond to information bits and parity bits respectively. Together, they constitute the codeword of the LDPC code. In the LDPC code, the information bits (or information columns) correspond to the information columns of the parity check matrix. The parity bits are calculated based on the information bits and the parity check matrix of the LDPC code and are used for error detection and correction at the receiving end.

[0167] It should also be understood that the number of columns kb1 of the first subcode information column can be interpreted as the parity check matrix H corresponding to the SC-LDPC code mentioned above. sc The number of information columns in the base matrix corresponding to each column of subcode in the L-group subcode.

[0168] In one possible implementation, the transmitting device can determine the number of columns kb1 of the first subcode information column based on the target code rate, the number of rows C of the subcode base matrix, and the predefined rate matching number M, where C is a positive integer and P is an integer.

[0169] It should be understood that the number of rows C of the subcode base matrix can be 1, 2, or 3, etc. The predefined rate matching number M of the subcode can be 0 or other positive integers. The predefined rate matching number can be a predefined number of punctures.

[0170] It should also be understood that after the transmitting device determines the number of columns kb1 of the first subcode information column, it can also determine the first rate matching number M1 and the first rate matching method based on the number of columns kb1. The transmitting device then performs rate matching (or first rate matching) on ​​the codeword sequence determined in subsequent step 630 based on the first rate matching method and the first rate matching number M1. The first rate matching includes the first rate matching number M1 and the first rate matching method, which includes puncturing or shortening, and M1 is an integer.

[0171] It should also be understood that the number of columns of the subcode information column in the subcode base matrix corresponding to the codeword sequence after the first rate matching is the number of columns of the first subcode information column, kb1.

[0172] As an example, the number of columns kb1 of the first sub-code information column can satisfy the following formula, such as:

[0173] or

[0174] Where ceil represents rounding up, floor represents rounding down, R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures.

[0175] Assumption or The minimum value kb in the set of columns less than the subcode information column min The column number of the first sub-code information column is kb1 = kb min ; Assumption or The maximum value kb in the set of columns greater than the subcode information column. max The column number of the first sub-code information column is kb1 = kb max .

[0176] Optional, the In this case, the first rate matching method can be shortened, meaning the transmitting device can determine a shortening value beyond the predefined rate matching number based on the specific value of kb1. For example, the value of the first rate matching number M1 is equal to the additional shortening value S1, which can satisfy: Based on the calculation method of S1, it can be known that S1≥0, and when kb1 <kb max When S1 < 1.

[0177] Optional, the In this case, the first rate matching method can be puncturing, meaning the transmitting device can determine the puncturing value beyond the predefined rate matching number based on the specific value of kb1. For example, the value of the first rate matching number M1 is equal to the value of the additional puncturing P1, and P1 can satisfy: Based on the calculation method of P1, we know that P1≥0, and when kb1>kb min When P1 < 1.

[0178] It should be understood that in the first rate matching method described above, the specific position of the puncturing can be after the fixed puncturing column corresponding to the codeword sequence, and puncturing can be performed sequentially; or, it can be at the last position of the sub-code base map corresponding to the codeword sequence, and puncturing can be performed in reverse order. Similarly, in the first rate matching method described above, the specific position of the shortening can start from the first position of the non-punctured information column of the sub-code base map and shorten sequentially; or, it can be at the last position of the information column of the sub-code base map and shorten in reverse order.

[0179] Step 2: The transmitting device determines the SC-LDPC matrix based on the column number kb1 of the first subcode information column.

[0180] For example, the transmitting device determines the number of columns kb1 of the first subcode information column according to step 1 above, and the transmitting device can further determine the SC-LDPC matrix based on the number of columns kb1 of the first subcode information column.

[0181] The following section will provide a detailed explanation of how the transmitting device determines the SC-LDPC matrix based on the number of columns kb1 of the first subcode information column, using two examples.

[0182] Example 1:

[0183] Step 2.1: The transmitting device determines the length k of the first sub-code information and the coupling length L of the SC-LDPC code based on the number of columns kb1 of the first sub-code information column and the length K of the target information.

[0184] It should be understood that after the transmitting device determines the number of columns kb1 of the first sub-code information column, the transmitting device can further determine the length k of the first sub-code information and the coupling length L of the SC-LDPC code based on the number of columns kb1 of the first sub-code information column and the target information length K.

[0185] Here, the subcode information length k refers to the information length of each subcode in the SC-LDCP code, which can be understood as the parity check matrix H mentioned above. sc The information length of each subcode. For example, the parity check matrix H in the example above. scThe information length of H0 can be determined by multiplying the number of information columns of H0 by the lifting value of the basis matrix corresponding to H0.

[0186] In this context, the coupling length L of the SC-LDPC code can be understood as the total number of columns in the parity-check matrix corresponding to the SC-LDPC code. For example, the H corresponding to the SC-LDPC code mentioned above... sc It is constructed by coupling L groups of subcodes, where L is the coupling length and is a positive integer.

[0187] The target information length K is the length of the transmitted information bits. The transmitted information bits may include CRC bits and payload bits, or the transmitted information bits may include payload bits but not CRC bits. The target information length K may be pre-configured by higher-layer signaling, MAC layer, or downlink physical layer signals; or the target information length K may be directly obtained or calculated by the sending device (or receiving device).

[0188] It should be understood that the detailed explanation of how the transmitting device determines the length k of the first sub-code information based on the number of columns kb1 of the first sub-code information column and the target information length K can be found in the detailed explanation in subsequent step 2.2. The detailed explanation of how the transmitting device determines the coupling length L of the SC-LDPC code can be found in existing solutions, and will not be repeated here.

[0189] Step 2.2: The sending device determines the boost value based on the number of columns kb1 of the first subcode information column and the length k of the first subcode information.

[0190] For example, the boost value can be determined by dividing the length k of the first subcode information by the number of columns kb1 of the first subcode information. For example, the boost value = k / kb1.

[0191] In one possible implementation, the length k of the first subcode information is determined by the transmitting device from a set of first subcode information lengths based on the number of columns kb1 of the first subcode information column and the target information length K. The first subcode information length kb1 belongs to the set of first subcode information lengths, which is determined by the set of the number of columns of the first subcode information column and the set of boost values.

[0192] It is understandable that the set of lengths for the first subcode information is determined based on the set of column numbers and the set of lift values ​​for the first subcode information. For example, the lengths of the subcode information included in this set of lengths for the first subcode information can satisfy: kb × Zc, where kb belongs to the set of lengths for the first subcode information KB, and Zc belongs to the set of lift values ​​Z. The length of the first subcode information kb1 belongs to the set of lengths for the first subcode information KB. That is, the lift value determined by the transmitting device based on the lengths of the first subcode information kb1 and k, which belong to the set of lengths for the first subcode information KB, belongs to the set of lift values.

[0193] In another possible implementation, the sending device can determine the number of columns kb1 of the first subcode information column and the length K of the second subcode information column. de The lift value is determined by the lift value set. The length K of the second subcode information is [not specified]. de Used to determine the length k of the first subcode information.

[0194] It should be understood that this set of lift values ​​can be predefined by the system / protocol, and the set of lift values ​​Z can be represented as {Z1,…,Z}. max}

[0195] It should be understood that the length K of this second subcode information de It can be predefined or preconfigured by the system / protocol, or the length K of the second subcode information. de It can also be sent from the receiving device to the sending device. The length K of this second sub-code information is... de This can be related to the maximum information length that the decoder can process, for example, the length K of the second subcode information. de The value of is less than or equal to the maximum information length that the decoder can process.

[0196] As an example, the transmitting device can determine the length K of the second subcode information. de The length k of the first subcode information is determined by the first function f(x), where the length k of the first subcode information can satisfy:

[0197]

[0198] Where p is a positive integer, k1, k2, ..., k p All are positive integers, and k1 <k2<…<k p K1, K2, ..., K p-1 All are positive integers, and K1 <K2<…<K p-1 .

[0199] Wherein, k in the first function f(x) i This K represents the length of the different first subcode information. iThis indicates different lengths of the second subcode information. Taking the piecewise function as an example, the length of the second subcode information for each segment or each interval corresponds to a length of the first subcode information.

[0200] Optionally, the first function includes the parameter K. i and k i And parameter K i and k i satisfy:

[0201]

[0202] Where w1 and w2 represent the range of the decoding window length corresponding to the first function, and w1≤w2, w1, w2, K i and k i All are positive integers. For example, w1≤10, w2≥20.

[0203] It should be understood that the first function f(x) can be the form of the piecewise function mentioned above, or the first function f(x) can be in other forms, such as the first function f(x) can also be equivalent to a table, or the mapping relationship between the length range of the second subcode information and the length of the first character code information. This application does not limit the specific form of the first function.

[0204] It should also be understood that the specific parameters in the first function f(x) can be designed based on the decoding complexity of the decoder of the receiving device. For example, the specific parameters in the first function f(x) may be different for different decoding complexities, or the specific values ​​of the specific parameters may be different.

[0205] It should also be understood that the sending device is based on the length K of the second subcode information. de Determine the length k of the first subcode information, and determine the lift value from the lift value set Z based on the length k and the number of columns kb1 of the first subcode information. Assume that... Then the promotion value is the smallest promotion value in the set of promotion values.

[0206] Step 2.3: The transmitting device determines the SC-LDPC matrix based on the number of columns kb1 of the first subcode information column, the boost value, and the coupling length L.

[0207] It should be understood that the transmitting device further determines the SC-LDPC matrix based on the number of columns kb1 of the first subcode information column determined in step 1 above, the coupling length L determined in step 2.1, and the boost value determined in step 2.2.

[0208] Example 2:

[0209] Step 2.4: The transmitting device determines the length k of the first sub-code information and the coupling length L of the SC-LDPC code based on the number of columns kb1 of the first sub-code information column and the length K of the target information.

[0210] It should be understood that after the transmitting device determines the number of columns kb1 of the first sub-code information column, the transmitting device can further determine the length k of the first sub-code information and the coupling length L of the SC-LDPC code based on the number of columns kb1 of the first sub-code information column and the target information length K.

[0211] Step 2.5: The sending device determines the boost value based on the number of columns kb1 of the first subcode information column and the length k of the first subcode information.

[0212] It should be understood that steps 2.4 and 2.5 above are similar to steps 2.1 and 2.2 in Example 1 above. For detailed information, please refer to the detailed descriptions in steps 2.1 and 2.2 above.

[0213] Step 2.6: The sending device determines the number of columns kb2 of the second subcode information based on the length k of the first subcode information and the boost value.

[0214] The number of columns kb2 in the second subcode information column is used to determine the SC-LDPC matrix. This number kb2 can also be used for second rate matching of the codeword sequence. This second rate matching includes puncturing or shortening.

[0215] In one possible implementation, the number of columns kb2 of the second subcode information column can satisfy:

[0216] or, or,

[0217] Where ceil represents rounding up, floor represents rounding down, and Zc represents the boost value.

[0218] Optionally, the second rate matching method corresponding to the rounding up calculation method is shortening, that is, the... The second rate matching method corresponding to the column number kb2 of the obtained second subcode information column is shortening. The second rate matching method corresponding to the rounding down calculation method is punching, that is, the... The second rate matching method corresponding to the number of columns kb2 of the obtained second subcode information column is punching.

[0219] It should be understood that, assuming or, or, The minimum value kb in the set of columns less than the subcode information column min At that time, kb2 = kbmin ; and assume or, or, The maximum value kb in the set of columns greater than the subcode information column. max At that time, kb2 = kb max .

[0220] As an example, suppose the number of columns kb2 of the second subcode information column is based on It is determined that the second rate matching method corresponding to the column number kb2 of the second subcode information column is shortening. The second rate matching number M2 is the value S2 of this shortening, and S2 can satisfy:

[0221]

[0222] Where R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures. Based on the calculation formula satisfied by S2 above, it can be seen that S2≥0, and when kb2 <kb max In this case, S2 < 1.

[0223] As another example, suppose the number of columns kb2 of the second sub-code information column is based on It is confirmed that the second rate matching method corresponding to the column number kb2 of the second subcode information column is puncturing. The second rate matching number M2 is the puncturing value P2, which can satisfy:

[0224]

[0225] Where R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures. Based on the calculation formula satisfied by S2 above, it can be seen that P2≥0, and when kb2>kb min In this case, P2 < 1.

[0226] It should be understood that the transmitting device performs a second rate matching on the codeword sequence obtained in subsequent step 630 based on the determined number of columns kb2 of the second sub-code information column. The second rate matching includes a second rate matching number M2 and a second rate matching method. Alternatively, it can be understood that the transmitting device punches or shortens the codeword sequence obtained in step 630 based on the number of columns kb2 of the second sub-code information column, where the number of columns corresponding to the punched or shortened codeword sequence is kb2.

[0227] It should also be understood that the number of columns kb2 of the second sub-code information column is based on The method by which the number of columns kb2 of the second subcode information column performs rate matching with the codeword sequence determined in step 2.5 above is not limited in this application.

[0228] It should also be understood that the punching positions corresponding to the aforementioned additional punching count can be sequentially punched after the fixed punching column corresponding to the codeword sequence; or, they can be punched in reverse order at the last position of the subcode base diagram corresponding to the codeword sequence. Similarly, the shortening positions corresponding to the aforementioned additional shortening count can be sequentially shortened starting from the first position of the non-punched information column of the subcode base diagram; or, they can be shortened in reverse order at the last position of the information column of the subcode base diagram.

[0229] Step 2.7: The transmitting device determines the LDPC matrix based on the number of columns k of the second subcode information column, the boost value, and the coupling length L.

[0230] 630. The transmitting device performs SC-LDPC encoding on the information bit sequence according to the SC-LDPC matrix to determine the codeword sequence.

[0231] It should be understood that after determining the SC-LDPC matrix, the transmitting device performs SC-LDPC encoding on the information bit sequence based on the SC-LDPC matrix to obtain the codeword sequence. Specifically, the detailed process of encoding the information bit sequence based on the SC-LDPC matrix can be found in the detailed description of existing schemes, and will not be repeated here.

[0232] 640, The sending device transmits a symbol sequence.

[0233] It is understandable that a symbol sequence can be a rate-matched sequence or a modulated sequence. For example, the transmitting device performs rate matching on the codeword sequence, then modulates the rate-matched sequence to obtain a symbol sequence, and then maps the modulated symbol sequence onto physical resources for transmission.

[0234] In one possible implementation, the transmitting device can perform a first rate matching on the codeword sequence, or the transmitting device can perform a first rate matching and a second rate matching on the codeword sequence. The transmitting device modulates the sequence obtained after rate matching (first rate matching, or first rate matching and second rate matching) to obtain a symbol sequence, and then maps the modulated symbol sequence onto physical resources for transmission.

[0235] For a detailed description of the first rate matching and the second rate matching, please refer to the description in step 620 above.

[0236] 650, the transmitting device sends a symbol sequence to the receiving device. Correspondingly, the receiving device receives the symbol sequence from the transmitting device.

[0237] It is understandable that the symbol sequence #1 sent by the transmitting device and the symbol sequence #2 received by the receiving device may be different because channel noise signals may be introduced during the transmission of the symbol sequence.

[0238] 660. The receiving device decodes the symbol sequence according to the SC-LDPC matrix to obtain the information bit sequence.

[0239] The SC-LDPC matrix used for decoding by the receiving device is the same as the SC-LDPC matrix used for encoding by the transmitting device. The specific method by which the receiving device determines the SC-LDPC check matrix can be found in the description on the transmitting device side, and will not be detailed here.

[0240] In one possible implementation, when the receiving device decodes the symbol sequence, it determines a first solution rate matching number M1 based on the column number kb1 of the first subcode information column, and performs a first solution rate matching on the symbol sequence according to the first solution rate matching number M1. The specific steps by which the receiving device determines the column number kb1 of the first subcode information column are similar to those by the transmitting device, and can be found in the detailed description of Example 1 in step 620 above.

[0241] In one possible implementation, when the receiving device decodes the symbol sequence, it determines the second solution rate matching number M2 based on the column number kb2 of the second subcode information column, and performs second solution rate matching on the symbol sequence according to the second solution rate matching number M2. The specific steps for the receiving device to determine the column number kb2 of the second subcode information column are similar to those for the transmitting device, as detailed in Example 2 of step 620 above.

[0242] It should be understood that the detailed process of solving rate matching can be found in the detailed descriptions of existing schemes, and will not be elaborated upon here.

[0243] Based on the above Figure 6 The method shown, Figure 7 A simulation diagram illustrating the distance capacity of an SC-LDPC code at different code rates is shown. The method provided in this application achieves flexible code rates for SC-LDPC codes by filtering the number of columns in the sub-code information column. Figure 7 The vertical axis corresponds to the distance (dB) between different bit rates and capacities, and the horizontal axis corresponds to different bit rates, based on Figure 7 It can be seen that the rate-to-capacity gap (GAP) of each SC-LDPC code provided in this application is within 0.1dB, which is better than the rate-to-capacity gap of 5G-LDPC at the same rate.

[0244] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0245] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0246] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the device (transmitting device or receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0247] The above text combined Figures 1 to 7 The present application provides a detailed description of the method embodiments, which will be discussed below in conjunction with... Figure 8 and Figure 9 This describes an embodiment of the apparatus described in this application. It is understood that, in order to achieve the functions described in the above embodiments, Figure 8 and Figure 9 The apparatus includes hardware structures and / or software modules corresponding to perform various functions. Those skilled in the art will readily recognize that, based on the units and method steps described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0248] Figure 8 and Figure 9 The diagram illustrates the possible structures of apparatuses provided for embodiments of this application. These apparatuses can be used to implement the functions of the transmitting or receiving devices in the above method embodiments, and thus also achieve the beneficial effects of the above method embodiments.

[0249] Figure 8 This is a schematic block diagram of the communication device 1000 provided in an embodiment of this application. Figure 8 As shown, the device 1000 may include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside world, and the processing unit 1020 is used for data processing. The communication unit 1010 may also be referred to as a communication interface or a transceiver unit.

[0250] In one possible design, the device 1000 can implement the steps or processes corresponding to those performed by the transmitting device in the above method embodiments, wherein the processing unit 1020 is used to perform processing-related operations of the transmitting device in the above method embodiments, and the communication unit 1010 is used to perform transmission-related operations of the transmitting device in the above method embodiments.

[0251] In another possible design, the device 1000 can implement the steps or processes corresponding to those performed by the receiving device in the above method embodiments, wherein the communication unit 1010 is used to perform the receiving-related operations of the receiving device in the above method embodiments, and the processing unit 1020 is used to perform the processing-related operations of the receiving device in the above method embodiments.

[0252] It is understood that the device 1000 here is embodied in the form of a functional unit. The term "unit" here can refer to an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor, etc.) and memory for executing one or more software or firmware programs, integrated logic circuitry, and / or other suitable components supporting the described functions. In an alternative example, those skilled in the art will understand that the device 1000 may specifically be the transmitting end device in the above embodiments, used to execute the various processes and / or steps corresponding to the transmitting end device in the above method embodiments; or, the device 1000 may specifically be the receiving end device in the above embodiments, used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiments. To avoid repetition, further details are omitted here.

[0253] The apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the transmitting device in the above-described method, or the apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the receiving device in the above-described method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the communication unit can be replaced by a transceiver (e.g., the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as processing units, can be replaced by a processor, respectively executing the transmission and reception operations and related processing operations in each method embodiment.

[0254] Furthermore, the aforementioned communication unit can also be a transceiver circuit (e.g., it may include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In embodiments of this application, Figure 8The device mentioned can be the receiving or transmitting device in the foregoing embodiments, or it can be a chip or a chip system, such as a system on a chip (SoC). The communication unit can be an input / output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. No limitations are imposed here.

[0255] Figure 9 This is a schematic block diagram of a communication device 1100 provided in an embodiment of this application. The device 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is used to execute instructions to control the transceiver 1120 to transmit and / or receive signals.

[0256] Optionally, the device 1100 may further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 via an internal connection path. The memory 1130 stores instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In one possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the transmitting device in the above method embodiments. In another possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the receiving device in the above method embodiments.

[0257] Optionally, the memory 1130 may be integrated into the processor 1110.

[0258] In one possible scenario, device 1100 includes at least one processor with integrated memory, and other memory besides the memory integrated on the processor.

[0259] It is understood that the device 1100 can specifically be the transmitting or receiving device in the above embodiments, or it can be a chip or a chip system. Correspondingly, the transceiver 1120 can be the transceiver circuit of the chip, which is not limited here. Specifically, the device 1100 can be used to execute the various steps and / or processes corresponding to the transmitting or receiving device in the above method embodiments.

[0260] Optionally, the memory 1130 may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may include non-volatile random access memory. For example, the memory may also store device type information. The processor 1110 may be used to execute instructions stored in the memory, and when the processor 1110 executes instructions stored in the memory, the processor 1110 is used to perform the various steps and / or processes of the method embodiments corresponding to the transmitting or receiving devices described above.

[0261] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0262] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor in the embodiments of this application can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0263] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0264] Optionally, the memory (e.g., 1130) in this embodiment may be integrated into the processor (e.g., 1110).

[0265] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0266] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0267] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by a transmitting or receiving device in any method embodiment are performed.

[0268] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0269] In addition, this application also provides a communication system, including the transmitting end device and the receiving end device in the embodiments of this application.

[0270] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0271] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0272] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0273] It is understood that the term "embodiment" used throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, various embodiments throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0274] It can also be understood that in this application, "when," "if," and "if" all refer to the network element making corresponding processing under certain objective circumstances, and are not time-limited, nor do they require the network element to make a judgment when it is implemented, nor do they mean that there are other limitations.

[0275] It can also be understood that in the various embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it can also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

Claims

1. An encoding method based on SC-LDPC codes, characterized in that, The method includes: Based on the target code rate and the set of column numbers of the subcode information column, determine the column number kb1 of the first subcode information column, where kb1 is a positive integer; The SC-LDPC matrix is ​​determined based on the column number kb1 of the first subcode information column; Based on the SC-LDPC matrix, the information bit sequence is encoded using SC-LDPC to obtain a codeword sequence.

2. The method according to claim 1, characterized in that, The SC-LDPC matrix is ​​determined based on the column number kb1 of the first subcode information column, including: Based on the number of columns kb1 of the first subcode information column and the target information length K, determine the length k of the first subcode information and the coupling length L of the SC-LDPC matrix; The boost value is determined based on the number of columns kb1 of the first subcode information column and the length k of the first subcode information; The SC-LDPC matrix is ​​determined based on the column number kb1 of the first subcode information column, the lift value, and the coupling length L. Where K, k, and L are all positive integers.

3. The method according to claim 1, characterized in that, The SC-LDPC matrix is ​​determined based on the column number kb1 of the first subcode information column, including: Based on the number of columns kb1 of the first subcode information column and the target information length K, determine the length k of the first subcode information and the coupling length L of the SC-LDPC matrix; The boost value is determined based on the number of columns kb1 of the first subcode information column and the length k of the first subcode information; Based on the length k of the first subcode information and the boost value, determine the number of columns kb2 of the second subcode information column; Based on the column number kb2 of the second subcode information column, the lift value, and the coupling length L, the SC-LDPC matrix is ​​determined. Where K, k, kb2 and L are all positive integers.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: Based on the column number kb1 of the first sub-code information column, a first rate matching number M1 and a first rate matching method are determined, and the codeword sequence is punched or shortened according to the first rate matching number M1 and the first rate matching method. Wherein, the number of columns of the subcode information columns included in the subcode base matrix corresponding to the codeword sequence after the first rate matching is kb1, and the first rate matching includes the first rate matching number M1 and the first rate matching method.

5. The method according to claim 4, characterized in that, The number of columns kb1 of the first subcode information column satisfies: or Where ceil represents rounding up, floor represents rounding down, R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures.

6. The method according to claim 5, characterized in that, like or The minimum value kb in the set of column numbers less than the subcode information column min When, kb1 = kb min ; like or The maximum value kb in the set of column numbers greater than the subcode information column max When, kb1 = kb max .

7. The method according to any one of claims 4 to 6, characterized in that, The number of holes P1 in the first rate matching satisfies: The shortening number S1 in the first rate matching satisfies: Where ceil represents rounding up, R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures.

8. The method according to any one of claims 3 to 7, characterized in that, The method further includes: Based on the column number kb2 of the second subcode information column, determine the second rate matching number M3 and the second rate matching method, and then punch or shorten the code sequence according to the second rate matching number M2 and the second rate matching method. Wherein, the subcode base matrix corresponding to the codeword sequence after the second rate matching includes a subcode information column number of kb2. The second rate matching includes the second rate matching number M2 and the second rate matching method.

9. The method according to claim 8, characterized in that, The number of columns kb2 of the second subcode information column satisfies: or, or, Where ceil represents rounding up, floor represents rounding down, and Zc represents the boost value.

10. The method according to claim 9, characterized in that, like or, or, The minimum value kb in the set of column numbers less than the subcode information column min When, kb2 = kb min ; like or, or, The maximum value kb in the set of column numbers greater than the subcode information column max When, kb2 = kb max .

11. The method according to any one of claims 8 to 10, characterized in that, The number of holes P2 in the second rate matching satisfies: The shortening number S2 in the second rate matching satisfies: Where ceil represents rounding up, R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures.

12. A decoding method based on SC-LDPC codes, characterized in that, The method includes: Based on the target code rate and the set of column numbers of the subcode information column, determine the column number kb1 of the first subcode information column, where kb1 is a positive integer; The SC-LDPC matrix is ​​determined based on the column number kb1 of the first subcode information column; Based on the SC-LDPC matrix, the symbol sequence is SC-LDPC decoded to obtain the information bit sequence.

13. The method according to claim 12, characterized in that, The SC-LDPC matrix is ​​determined based on the column number kb1 of the first subcode information column, including: Based on the number of columns kb1 of the first subcode information column and the target information length K, determine the length k of the first subcode information and the coupling length L of the SC-LDPC matrix; The boost value is determined based on the number of columns kb1 of the first subcode information column and the length k of the first subcode information; The SC-LDPC matrix is ​​determined based on the column number kb1 of the first subcode information column, the lift value, and the coupling length L. Where K, k, and L are all positive integers.

14. The method according to claim 12, characterized in that, The SC-LDPC matrix is ​​determined based on the column number kb1 of the first subcode information column, including: Based on the number of columns kb1 of the first subcode information column and the target information length K, determine the length k of the first subcode information and the coupling length L of the SC-LDPC matrix; The boost value is determined based on the number of columns kb1 of the first subcode information column and the length k of the first subcode information; Based on the length k of the first subcode information and the boost value, determine the number of columns kb2 of the second subcode information column; The SC-LDPC matrix is ​​determined based on the column number kb2 of the second subcode information column, the lift value, and the coupling length L. Where kb2, K, k, and L are all positive integers.

15. The method according to any one of claims 12 to 14, characterized in that, The method further includes: Based on the column number kb1 of the first subcode information column, the first solution rate matching number M1 is determined, and the symbol sequence is subjected to first solution rate matching according to the first solution rate matching number M1.

16. The method according to claim 15, characterized in that, The number of columns kb1 of the first subcode information column satisfies: or Where ceil represents rounding up, floor represents rounding down, R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures.

17. The method according to claim 16, characterized in that, like or The minimum value kb in the set of column numbers less than the subcode information column min When, kb1 = kb min ; like or The maximum value kb in the set of column numbers greater than the subcode information column max When, kb1 = kb max .

18. The method according to any one of claims 15 to 16, characterized in that, The first solution rate matching number M1 is equal to either P1 or S1. Where ceil represents rounding up, R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures.

19. The method according to any one of claims 14 to 18, characterized in that, The method further includes: Based on the column number kb2 of the second subcode information column, the second solution rate matching number M2 is determined, and the symbol sequence is subjected to second solution rate matching according to the second rate matching number M2.

20. The method according to claim 19, characterized in that, The number of columns kb2 of the second subcode information column satisfies: or, or, Where ceil represents rounding up, floor represents rounding down, and Zc represents the boost value.

21. The method according to claim 20, characterized in that, like or, or, The minimum value kb in the set of column numbers less than the subcode information column min When, kb2 = kb min ; like or, or, The maximum value kb in the set of column numbers greater than the subcode information column max When, kb2 = kb max .

22. The method according to any one of claims 19 to 21, characterized in that, The second solution rate matching number M2 is equal to either P2 or S2. Where ceil represents rounding up, R represents the target code rate, C represents the number of rows in the subcode base matrix, and P represents the predefined number of punctures.

23. The method according to any one of claims 1 to 22, characterized in that, Determining the number of columns kb1 of the first sub-code information column based on the target code rate and the set of column numbers of the sub-code information column includes: Based on the target code rate, the number of rows C of the subcode base matrix, and the predefined rate matching number M, determine the number of columns kb1 of the first subcode information column. Where C is a positive integer and P is an integer.

24. The method according to any one of claims 2 to 23, characterized in that, The lift value is determined based on the number of columns kb1 of the first subcode information column and the length k of the first subcode information, including: Based on the column number kb1 of the first subcode information column, the length K of the second subcode information... de And a set of boost values, to determine the boost value, The second code information length is used to determine the length k of the first code information.

25. The method according to claim 24, characterized in that, The second subcode information length K de The first function f(x) is used to determine the length k of the first subcode information, and the length k of the first subcode information satisfies: Where p is a positive integer, k1, k2, ..., k p All are positive integers, and k1 <k2<…<k p K1, K2, ..., K p-1 All are positive integers, and K1 <K2<…<K p-1 .

26. The method according to any one of claims 1 to 25, characterized in that, The length k of the first subcode information belongs to the set of first subcode information lengths, which is determined by the set of column numbers and the set of promotion values ​​of the subcode information columns.

27. A communication device, characterized in that, Including processor and interface circuitry, The interface circuit is used to receive signals and transmit the signals to the processor or send signals processed by the processor to cause the processor to perform the method as described in any one of claims 1 to 26.

28. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions that, when executed by a communication device, enable the method as described in any one of claims 1 to 26 to be implemented.

29. A computer program product, characterized in that, Includes a computer program, which, when run, enables the method as described in any one of claims 1 to 26 to be implemented.

30. A chip, characterized in that, The chip includes a processor and a communication interface. The processor reads instructions stored in the memory through the communication interface to implement the method as described in any one of claims 1 to 26.

Images