Ka-band radio frequency microsystem digital prototype

Abstract

The invention provides a Ka-band radio frequency microsystem digital prototype, which relates to the technical field of radio frequency integrated microsystems, and comprises four branches, the first branch and the second branch are respectively connected with two output ends of a first power divider, the third branch and the fourth branch are respectively connected with two output ends of a second power divider, and the fourth branch is connected with two output ends of a third power divider. The input ends of the first power divider and the second power divider are respectively connected with two output ends of the third power divider, and the input end of the third power divider is connected with the common end; each branch comprises two sub-paths, one sub-path is sequentially connected in series by a first receiving end driving amplifier, a first phase shifter, a second receiving end driving amplifier and an attenuator, and the other sub-path is sequentially connected in series by a second phase shifter and a transmitting end driving amplifier. According to the method, the radio frequency microsystem digital prototype is established by establishing the chip circuit model, so that the circuit can be simplified, the operation efficiency of a computer can be improved, and a prior condition is provided for the research of a large-scale complex network.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated microsystems technology, and more particularly to a digital prototype of a Ka-band radio frequency microsystem. Background Technology

[0002] With the deepening of informatization, communication equipment needs to possess anti-interference performance, secure communication capabilities, good electromagnetic compatibility, and superior vibration and shock resistance, placing high demands on communication reliability. As technology continues to advance, the ability to operate effectively in complex environments and extract more information is a key characteristic of modern communication equipment. This requires equipment to possess excellent integrated, multi-functional, multi-target, high data rate, high precision, anti-clutter, and anti-interference capabilities in microwave and millimeter-wave monolithic chips. Radio frequency (RF) front-end chips are indispensable in wireless equipment, with microwave devices such as filters, low-noise amplifiers, and phase-locked loops being essential components. In the past decade or so, the driving force of the radar detection and wireless communication industries, along with advancements in process technology, has spurred the rapid development of RF front-end chips, evolving from discrete devices to single-function microwave and millimeter-wave monolithic integrated circuits, and then to multi-functional microwave and millimeter-wave monolithic chips.

[0003] As integrated circuits become increasingly larger and more integrated, most existing circuit simulation programs, limited by storage space and computation time, are unable to meet the needs of analyzing and designing large networks or systems containing integrated circuits. Summary of the Invention

[0004] This invention provides a Ka-band radio frequency microsystem digital prototype to address the problem that most current EDA (Electronic Design Automation) tools are limited by hardware performance and computation time, making it difficult to analyze and design large networks or systems containing integrated circuits. The technical solution is as follows: In a first aspect, embodiments of the present invention provide a Ka-band radio frequency microsystem digital prototype, the Ka-band radio frequency microsystem digital prototype comprising four branches: the first branch and the second branch are respectively connected to the two output terminals of a first power divider, the third branch and the fourth branch are respectively connected to the two output terminals of a second power divider, the input terminal of the first power divider and the input terminal of the second power divider are respectively connected to the two output terminals of a third power divider, and the input terminal of the third power divider is connected to a common terminal; Each branch includes two sub-paths, which are connected to the power divider via a single-pole triple-throw switch. One sub-path consists of a first receiving-end driver amplifier, a first phase shifter, a second receiving-end driver amplifier, and an attenuator connected in series. The other sub-path consists of a second phase shifter and a transmitting-end driver amplifier connected in series.

[0005] Optionally, the first receiving end drive amplifier or the second receiving end drive amplifier includes: inductors L1, L2, L3, L4, L5, L6, capacitors C1, C2, C3, C4, resistors R1, R2, R3 and a transistor NMOS1; One end of inductor L1 is used to receive radio frequency input signals, and the other end is connected to one end of capacitor C1; The other end of capacitor C1 is connected to resistor R1, capacitor C2, and resistor R2 respectively; The other end of resistor R1 is connected in series with inductor L2, which is used to receive the gate bias voltage. After capacitor C2 and resistor R2 are connected in parallel, they are connected to one end of capacitor C3 and the gate of NMOS1, respectively. The other end of capacitor C3 is connected in series with inductor L3 and resistor R3, and then connected to the drain of NMOS1 and inductor L4 respectively. The source of NMOS1 is grounded; The other end of inductor L4 is connected to inductor L5 and capacitor C4 respectively. Inductor L5 is used to receive the drain bias voltage. The other end of capacitor C4 is connected in series with inductor L6, and the other end of inductor L6 is used to output the radio frequency signal.

[0006] Optionally, the transmitter driver amplifier includes inductors L7, L8, L9, L10, L11, L12, L13, capacitors C5, C6, C7, C8, C9, C10, C11, resistors R4, R5, R6, R7, and transistors NMOS2 and NMOS3. One end of capacitor C5 is used to receive radio frequency input signals, and the other end is connected to capacitor C6 and inductor L7 respectively. The other end of inductor L7 is grounded. After capacitor C7 and resistor R4 are connected in parallel, one end is connected to the other end of capacitor C6, and the other end is connected to resistor R5 and the gate of NMOS2 respectively. The other end of resistor R5 is connected in series with inductor L8, which is used to receive the gate bias voltage. The source of NMOS2 is grounded, and the drain is connected to inductor L9 and capacitor C8 respectively; inductor L9 is used to receive the drain bias voltage. The other end of capacitor C8 is connected to inductor L10 and capacitor C9 respectively, and the other end of inductor L10 is grounded. After capacitor C10 and resistor R6 are connected in parallel, one end is connected to the other end of capacitor C9, and the other end is connected to resistor R7 and the gate of NMOS3 respectively. The other end of resistor R7 is connected in series with inductor L11, which is used to receive the gate bias voltage. The source of NMOS3 is grounded, and the drain is connected to inductor L12 and capacitor C11 respectively. Inductor L12 is used to receive the drain bias voltage. The other end of capacitor C11 is connected to inductor L13, and the connection point between the two is used to output the radio frequency output signal.

[0007] Optionally, the first phase shifter or the second phase shifter includes multiple phase shifting units with different phase shift amounts, namely a first phase shifting unit achieving a 5.625° phase shift, a second phase shifting unit achieving an 11.25° phase shift, a third phase shifting unit achieving a 22.5° phase shift, a fourth phase shifting unit achieving a 45° phase shift, a fifth phase shifting unit achieving a 90° phase shift, and a sixth phase shifting unit achieving a 180° phase shift; the third phase shifting unit, the second phase shifting unit, the fifth phase shifting unit, the fourth phase shifting unit, the first phase shifting unit, and the sixth phase shifting unit are connected in series sequentially; wherein: The first phase-shifting unit, the second phase-shifting unit, the third phase-shifting unit, and the fourth phase-shifting unit adopt a T-type phase-shifting topology. The fifth phase-shifting unit and the sixth phase-shifting unit adopt a switch-selective path-type phase-shifting topology.

[0008] Optionally, the third phase-shifting unit includes inductors L14, L15, and L16, resistors R8, R9, and R10, and NMOS4, NMOS5, and NMOS6; wherein: Resistor R8 is used to receive digital signal V3P, and the other end is connected to the gate of NMOS4. The source of NMOS4 is used to receive RF input signal and is also connected to inductor L14. The drain of NMOS4 is connected to inductor L15 and the source of NMOS7 in the second phase shift unit. One end of inductor L14 receives the radio frequency input signal, and the other end is connected to the drain of NMOS5; One end of inductor L15 is connected to the drain of NMOS4, and the other end is also connected to the drain of NMOS5; The gate of NMOS5 is connected to resistor R9, and the other end of resistor R9 is used to receive the digital signal V3P. The source of NMOS5 is connected to the drain of NMOS6 and inductor L16, respectively. The gate of NMOS6 is connected to resistor R10. The other end of resistor R10 is used to receive the digital signal V3N. The other end of inductor L16 is connected to the source of NMOS6, and the source of NMOS6 is grounded.

[0009] Optionally, the sixth phase-shifting unit includes inductors L29, L30, and L31, capacitors C15 and C16, resistors R24, R25, R26, and R27, and NMOS20, NMOS21, NMOS22, and NMOS23; wherein: Resistor R24 ​​is used to receive digital signal V6P, and the other end is connected to the gate of NMOS20. Resistor R25 is used to receive digital signal V6N, and the other end is connected to the gate of NMOS21. The drain of NMOS20 is connected to inductor L29, and the source is connected to the source of NMOS21. The drain of NMOS21 is connected to capacitor C16. The other end of inductor L29 is connected to inductor L30 and capacitor C15 respectively, and the other end of capacitor C15 is grounded. The other end of capacitor C16 is connected to inductor L31 and capacitor C17 respectively, with the other end of inductor L31 grounded; the other end of inductor L30 is connected to the drain of NMOS22, and the other end of capacitor C17 is connected to the drain of NMOS23. The source of NMOS22 is connected to the source of NMOS23. The gate of NMOS22 is connected to resistor R26. The other end of resistor R26 is used to receive digital signal V6P. The gate of NMOS23 is connected to resistor R27. The other end of resistor R27 is used to receive digital signal V6N.

[0010] Optionally, the single-pole three-throw switch includes an inductor L32 and three channel branches, which are connected in parallel and have the same circuit structure. For any given channel branch, including resistors R28, R29, R30, inductor L33, and transistors NMOS24, NMOS25, and NMOS26; where: Resistor R28 is used to receive the digital signal VnP, and its other end is connected to the gate of NMOS24; The source of NMOS24 is connected to inductor L32, and the drain is connected to the drain of NMOS25, the drain of NMOS26, and inductor L33, respectively. The source of the NMOS25 is grounded, and the gate is connected to resistor R29. Resistor R29 is used to receive the digital signal VnN. The source of the NMOS26 is grounded, and the gate is connected to resistor R30. Resistor R30 is used to receive the digital signal VnN. The other end of inductor L33 is used to output radio frequency signals; n is 1, 2, or 3.

[0011] Optionally, the attenuator includes six attenuation units: a first attenuation unit achieving 0.5dB attenuation, a second attenuation unit achieving 1dB attenuation, a third attenuation unit achieving 2dB attenuation, a fourth attenuation unit achieving 4dB attenuation, a fifth attenuation unit achieving 8dB attenuation, and a sixth attenuation unit achieving 16dB attenuation; wherein the circuit structures of the first, second, third, fourth, and fifth attenuation units all adopt a parallel T-type attenuation structure; and the circuit structure of the sixth attenuation unit adopts a Π-type attenuation structure.

[0012] Optionally, the T-type attenuation structure includes two structural forms, namely structural form one and structural form two; wherein: Structure type one includes: resistors R54, R55, R56, R57, R58, transistors NMOS40, NMOS41, and capacitor C22; Resistor R54 is used to receive the digital signal VnP, and the other end is connected to the gate of NMOS40; The source of NMOS40 is connected to the drain of NMOS37 and resistor R55, respectively, and the drain of NMOS40 is connected to the source of NMOS42 and resistor R56, respectively. The other ends of resistors R55 and R56 are both connected to the drain of NMOS41; The gate series resistor R57 of the NMOS41 is used to receive the digital signal VnN. The source of the NMOS41 is connected in series with a resistor R58 and a capacitor C22, and the other end of the capacitor C22 is grounded. n is 1 or 2; Compared to structure form one, structure form two also includes a parallel resistor introduced in the main circuit to adjust the attenuation of the attenuation unit.

[0013] Optionally, the Π-type attenuation structure includes resistors R48, R49, R50, R51, R52, and R53, transistors NMOS37, NMOS38, and NMOS39, and C20 and C21; R48 is used to receive the digital signal V6P, and the other end is connected to the gate of NMOS37; The source of NMOS37 is connected to the drain of NMOS35, resistor R49, and drain of NMOS38, respectively. The drain of NMOS37 is connected to the source of NMOS40, the other end of resistor R49, and drain of NMOS39, respectively. The source of the NMOS38 is connected in series with resistor R52 and capacitor C20, and the other end of capacitor C20 is grounded. The source of the NMOS39 is connected in series with resistor R53 and capacitor C21, and the other end of capacitor C21 is grounded. The gate of the NMOS38 is connected to one end of the resistor R50, and the gate of the NMOS39 is connected to one end of the resistor R51. The other end of the resistor R50 is connected to the other end of the resistor R51, and both are used to receive the digital signal V6N.

[0014] Secondly, embodiments of the present invention provide a method for establishing a digital prototype of a Ka-band radio frequency microsystem, comprising: Based on the reference architecture of the beamforming chip, multiple minimum functional units are obtained by decomposition. Establish a macro model corresponding to each smallest functional unit; The established macro model is built, debugged, and simulated in ADS according to the reference architecture of the beamforming chip to ensure that its performance meets the error requirements of the chip's actual test data, thereby completing the construction of the digital prototype.

[0015] Optionally, the beamforming chip is a Ka-band silicon-based four-channel analog beamforming chip, and the plurality of minimum functional units include: a receiver driver amplifier, a transmitter driver amplifier, a digitally controlled phase shifter, a single-pole triple-throw switch, an attenuator, and a power divider.

[0016] The beneficial effects of the above-mentioned technical solution of the present invention are: The Ka-band radio frequency microsystem digital prototype provided in this invention simplifies circuitry and improves computer operating efficiency by establishing a chip circuit model, thus providing prior conditions for the research of large and complex networks. In the macroscopic application of the circuit model, modeling and simulation allow for the use of different reference circuits without altering component functions, saving circuit costs. At the microscopic level, the established circuit model exhibits good portability and is easy to combine with different circuits. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the circuit structure of a digital prototype of a Ka-band radio frequency microsystem disclosed in an embodiment of the present invention; Figure 2 This is a schematic diagram of the circuit structure of the receiving end driving amplifier in an embodiment of the present invention; Figure 3 This is a schematic diagram of the circuit structure of the transmitter driver amplifier in an embodiment of the present invention; Figure 4 This is a schematic diagram of the circuit structure of the numerically controlled phase shifter in an embodiment of the present invention; Figure 5 This is a schematic diagram of the circuit structure of a single-pole three-throw switch in an embodiment of the present invention; Figure 6 This is a schematic diagram of the circuit structure of the attenuator in an embodiment of the present invention; Figure 7 This is a flowchart of a method for establishing a digital prototype of a Ka-band radio frequency microsystem disclosed in an embodiment of the present invention.

[0018] RDA: Receiver driver amplifier; TDA: Transmitter driver amplifier; PS: Phase shifter; SP3T: Single-pole three-throw switch; ATT: Attenuator; COM: Public terminal. Detailed Implementation

[0019] To make the technical problems, technical solutions, and advantages of this invention clearer, a detailed description will be provided below in conjunction with the accompanying drawings and specific embodiments. In the following description, specific details such as particular configurations and components are provided merely to aid in a comprehensive understanding of the embodiments of this invention. Therefore, those skilled in the art should understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this invention. Furthermore, for clarity and brevity, descriptions of known functions and structures have been omitted.

[0020] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0021] In various embodiments of the present invention, it should be understood that the sequence number of each process described below does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0022] To address the limitations of most existing circuit simulation programs in terms of storage space and computation time, which make them unsuitable for analyzing and designing large-scale networks or systems containing integrated circuits, this invention proposes establishing a chip circuit model and subsequently creating a digital prototype of a radio frequency microsystem. This simplifies the circuit, improves computer efficiency, and provides prior conditions for the research of large and complex networks. In the macroscopic application of the circuit model, modeling and simulation allow for the use of different reference circuits without altering component functions, saving circuit costs. At the microscopic level, the established circuit model offers good portability and facilitates combination with different circuits.

[0023] This invention provides a Ka-band radio frequency (RF) microsystem digital prototype. The reference architecture of this Ka-band RF microsystem digital prototype is a 32-38GHz silicon-based four-channel analog beamforming chip. The chip integrates driver amplifiers, six-bit phase shifters, six-bit attenuators, and power dividers. The schematics of each unit circuit of the digital prototype were built in Cadance, ported to ADS Dynamic Link for macro-model encapsulation, and the overall digital prototype was modeled. Figure 1 As shown, the digital prototype structure of the Ka-band radio frequency microsystem provided in this embodiment of the invention includes four branches. The first branch 01 and the second branch 02 are respectively connected to the two output terminals of the first power divider 03. The third branch 04 and the fourth branch 05 are respectively connected to the two output terminals of the second power divider 06. The input terminal of the first power divider 03 and the input terminal of the second power divider 06 are respectively connected to the two output terminals of the third power divider 07. The input terminal of the third power divider 07 is connected to the common terminal COM. Each branch includes two sub-paths, which are connected to the power divider via a single-pole triple-throw switch. One sub-path consists of a first receiver driver amplifier RDA1, a first phase shifter PS1, a second receiver driver amplifier RDA2, and an attenuator ATT connected in series. The other sub-path consists of a second phase shifter PS2 and a transmitter driver amplifier TDA connected in series.

[0024] according to Figure 1 The digital prototype reference architecture shown is decomposed into individual minimum functional units, such as receiver driver amplifiers, transmitter driver amplifiers, power dividers, attenuators, and phase shifters, and a circuit model corresponding to each unit is established. The established circuit models are then built and debugged in ADS according to the chip architecture to ensure that their performance meets the error requirements of the test data, thereby completing the construction of the digital prototype.

[0025] It should be noted that the circuit structures of the first receiving-end driver amplifier RDA1 and the second receiving-end driver amplifier RDA2 are identical, as are the circuit structures of the first phase shifter PS1 and the second phase shifter PS2. The serial numbers and names are only for distinguishing different components; their circuit structures are essentially the same.

[0026] Furthermore, the applicant provided a description of the circuit structure schematics corresponding to each smallest functional unit.

[0027] 1. Receiver driver amplifier In this embodiment of the invention, the receiver-side driver amplifier adopts a two-stage structure. First, the output stage is designed to ensure that the linearity meets the specifications, and then the gain of the first stage is designed to ensure that the overall gain meets the requirements. Impedance conjugate matching is performed at the input and output terminals to give the driver amplifier sufficiently good return loss performance. The schematic diagram of the receiver-side driver amplifier circuit is shown in Figure 2.

[0028] The receiver-side driver amplifier includes inductors L1, L2, L3, L4, L5, and L6; capacitors C1, C2, C3, and C4; resistors R1, R2, and R3; and a transistor NMOS1. Specifically, one end of inductor L1 receives the RF input signal, and the other end is connected to capacitor C1. The other end of capacitor C1 is connected to resistors R1, C2, and R2. The other end of resistor R1 is connected in series with inductor L2, which receives the gate bias voltage of the receiver-side driver amplifier. Capacitor C2 is connected in parallel with resistor R2 and then connected to capacitor C3 and the gate of NMOS1. Capacitor C3 is connected in series with inductor L3 and resistor R3 and then connected to the drain of NMOS1 and inductor L4. The source of NMOS1 is grounded. The other end of inductor L4 is connected to inductor L5 and capacitor C4 respectively. Inductor L5 is used to receive the drain bias voltage of the receiver driver amplifier. The other end of capacitor C4 is connected in series with inductor L6. The other end of inductor L6 is used to output the RF output signal after being amplified by the receiver driver amplifier.

[0029] 2. Transmitter driver amplifier In this embodiment of the invention, the transmitter driver amplifier adopts a two-stage structure. The output stage is designed first to ensure linearity and output power, and then the gain of the first stage is designed to achieve the required overall gain. To further improve the output power, partial power matching is used at the output, sacrificing some return performance to obtain higher output power. The schematic diagram of the transmitter driver amplifier circuit is shown in Figure 3.

[0030] The transmitter driver amplifier includes inductors L7, L8, L9, L10, L11, L12, and L13; capacitors C5, C6, C7, C8, C9, C10, and C11; resistors R4, R5, R6, and R7; and transistors NMOS2 and NMOS3. Specifically, one end of capacitor C5 receives the RF input signal, and the other end is connected to both capacitor C6 and inductor L7. The other end of inductor L7 is grounded. One end of capacitor C7 connected in parallel with resistor R4 is connected to the other end of capacitor C6, and the other end is connected to both resistor R5 and the gate of NMOS2. The other end of resistor R5 is connected in series with inductor L8, which receives the gate bias voltage of the transmitter driver amplifier. The source of NMOS2 is grounded, and its drain is connected to both inductor L9 and capacitor C8. Inductor L9 receives the drain bias voltage of the transmitter driver amplifier. The other end of capacitor C8 is connected to both inductor L10 and capacitor C9. The other end of inductor L10 is grounded. Capacitor C10 is connected in parallel with resistor R6, one end of which is connected to the other end of capacitor C9. The other end is connected to resistor R7 and the gate of NMOS3. The other end of resistor R7 is connected in series with inductor L11, which receives the gate bias voltage of the transmitter driver amplifier. The source of NMOS3 is grounded, and its drain is connected to inductor L12 and capacitor C11. Inductor L12 receives the drain bias voltage of the transmitter driver amplifier. The other end of capacitor C11 is connected to inductor L13, and the connection point is used to output the amplified RF output signal from the transmitter driver amplifier.

[0031] 3. Phase shifter In this embodiment of the invention, the phase shifter (also called a digitally controlled phase shifter) is composed of a switching transistor and passive components. By controlling the on / off state of the switch, the signal travels through different paths, generating different phases. The difference between the two phases is the phase shift. A digitally controlled phase shifter can be realized by cascading phase shifting units with different phase shift amounts. These phase shifting units adopt the form of high-pass and low-pass filters, composed of lumped elements, and can achieve wideband phase shifts. The 5.625°, 11.25°, 22.5°, and 45° phase shift states adopt a T-type phase shift topology, while the 90° and 180° phase shift states adopt a switch-selective path type phase shift topology. The circuit structure schematic diagram of the digitally controlled phase shifter is shown in Figure 4.

[0032] Figure 4In this circuit, V1P and V1N are a pair of inverted digital signals used to control the on / off state of the switches in the 5.625° phase shift unit, achieving different phase shifts. When V1P is low and V1N is high, the 5.625° phase shift unit is on, and the phase shifter will produce a 5.625° phase shift; when V1P is high and V1N is low, the 5.625° phase shift unit is off, and no phase shift is produced. Similarly, V2P and V2N are a pair of inverted digital signals, V3P and V3N are a pair of inverted digital signals, V4P and V4N are a pair of inverted digital signals, V5P and V5N are a pair of inverted digital signals, and V6P and V6N are a pair of inverted digital signals. V2P~V6P and V2N~V6N are used to control the phase shifting units at 11.25°, 22.5°, 45°, 90°, and 180°, respectively. The phase shifting unit is activated when VnP (n=1,2,3,4,5,6) is low, generating the corresponding phase shift. RFin is the RF input signal of the digitally controlled phase shifter, and RFout is the RF output signal after phase shifting by the digitally controlled phase shifter.

[0033] In this embodiment of the invention, the numerically controlled phase shifter includes six phase shifting units: a first phase shifting unit corresponding to V1P and V1N, used to achieve a 5.625° phase shift; a second phase shifting unit corresponding to V2P and V2N, used to achieve an 11.25° phase shift; a third phase shifting unit corresponding to V3P and V3N, used to achieve a 22.5° phase shift; a fourth phase shifting unit corresponding to V4P and V4N, used to achieve a 45° phase shift; a fifth phase shifting unit corresponding to V5P and V5N, used to achieve a 90° phase shift; and a sixth phase shifting unit corresponding to V6P and V6N, used to achieve a 180° phase shift. The circuit structures of the first, second, third, and fourth phase shifting units are identical, all employing a T-type phase shifting topology. The circuit structures of the fifth and sixth phase shifting units are identical, both employing a switch-selection path type phase shifting topology. The third, second, fifth, and fourth phase shifting units, along with the first and sixth phase shifting units, are connected in series sequentially.

[0034] The applicant uses the circuit structures of the third and sixth phase-shifting units as examples for description; the circuit structures of other phase-shifting units are the same and can be referenced. Figure 4 As shown, the applicant will not elaborate further.

[0035] The third phase-shifting unit includes inductors L14, L15, and L16, resistors R8, R9, and R10, and NMOS4, NMOS5, and NMOS6. Specifically, resistor R8 receives the digital signal V3P, and its other end is connected to the gate of NMOS4. The source of NMOS4 receives the RF input signal and is also connected to inductor L14. The drain of NMOS4 is connected to both inductor L15 and the source of NMOS7 in the second phase-shifting unit.

[0036] One end of inductor L14 receives the RF input signal, and the other end is connected to the drain of NMOS5. One end of inductor L15 is connected to the drain of NMOS4, and the other end is also connected to the drain of NMOS5. The gate of NMOS5 is connected to resistor R9, and the other end of resistor R9 is used to receive the digital signal V3P. The source of NMOS5 is connected to the drain of NMOS6 and inductor L16. The gate of NMOS6 is connected to resistor R10, and the other end of resistor R10 is used to receive the digital signal V3N. The other end of inductor L16 is connected to the source of NMOS6, and the source of NMOS6 is grounded.

[0037] The sixth phase-shifting unit includes inductors L29, L30, and L31; capacitors C15 and C16; resistors R24, R25, R26, and R27; and NMOS20, NMOS21, NMOS22, and NMOS23. Specifically, resistor R24 ​​receives the digital signal V6P and its other end is connected to the gate of NMOS20. Resistor R25 receives the digital signal V6N and its other end is connected to the gate of NMOS21. The drain of NMOS20 is connected to inductor L29, and its source is connected to the source of NMOS21. The drain of NMOS21 is connected to capacitor C16. The other end of inductor L29 is connected to inductor L30 and capacitor C15, with the other end of capacitor C15 grounded. The other end of capacitor C16 is connected to inductor L31 and capacitor C17, with the other end of inductor L31 grounded. The other end of inductor L30 is connected to the drain of NMOS22, and the other end of capacitor C17 is connected to the drain of NMOS23. The source of NMOS22 is connected to the source of NMOS23. The gate of NMOS22 is connected to resistor R26, the other end of which is used to receive the digital signal V6P. The gate of NMOS23 is connected to resistor R27, the other end of which is used to receive the digital signal V6N.

[0038] 4. Single-pole three-throw switch (SP3T) In this embodiment of the invention, one branch of the single-pole three-throw switch is connected to a 50Ω load, enabling the component to switch from standby to load state. Each branch of the SP3T is a reflective switch in a series-parallel-parallel configuration, which can simultaneously meet the requirements of low insertion loss and high isolation. The circuit diagram of the single-pole three-throw switch is shown below. Figure 5 As shown.

[0039] Figure 5 In the middle, V in For the common input and output terminals of the radio frequency signals of a single-pole three-throw switch, V out1 ~V out3 These are the RF signal input and output terminals for channels 1 through 3, respectively. In practical applications, when the transceiver is in transmit mode, V...in It is the radio frequency signal input terminal, V out1 It is the RF signal output terminal; when the transceiver is in receiving mode, V out3 It is the radio frequency signal input terminal, V in This is the RF signal output terminal. V1P and V1N are a pair of inverted digital signals used to control the switching on and off of the switch transistor in channel 1. When V1P is high and V1N is low, channel 1 is on; when V1P is low and V1N is high, channel 1 is off. Similarly, V2P and V3P, and V2N and V3N, are used to control the on and off of channels 2 and 3.

[0040] One end of the inductor L32 in the single-pole triple-throw switch is used to receive radio frequency signals, and the other end is connected in parallel with the three channel branches (channel 1, channel 2, and channel 3). Since the circuit structure of the three channel branches connected in parallel is the same, and can be referenced... Figure 5 As shown, the applicant will describe the circuit structure of the first channel branch as an example, and will not elaborate on the circuit structures of other channels.

[0041] The first channel branch corresponds to the inverted digital signals V1P and V1N, including resistors R28, R29, and R30, inductor L33, and NMOS24, NMOS25, and NMOS26. Specifically, resistor R28 receives the digital signal V1P, and its other end is connected to the gate of NMOS24. The source of NMOS24 is connected to inductor L32, and its drain is connected to the drain of NMOS25, the drain of NMOS26, and inductor L33, respectively. The source of NMOS25 is grounded, and its gate is connected to resistor R29, which receives the digital signal V1N. The source of NMOS26 is grounded, and its gate is connected to resistor R30, which receives the digital signal V1N. The other end of inductor L33 is used to output the RF signal.

[0042] The second channel circuit corresponding to the V2P and V2N inverted digital signals, and the third channel circuit corresponding to the V3P and V3N inverted digital signals, have the same circuit structure as the first channel circuit corresponding to the V1P and V1N inverted digital signals, and the three channels are connected in parallel.

[0043] 5. Attenuator In this embodiment of the invention, the attenuator is composed of a switching transistor, a resistor, and a microstrip line. By controlling the on / off state of the switch, the signal travels along different paths, resulting in different insertion losses. The difference between the two paths is the attenuation. The monolithic attenuator consists of various basic attenuation levels. The 0.5dB, 1dB, 2dB, 4dB, and 8dB attenuations employ a parallel T-type attenuation structure, while the 16dB attenuation uses a Π-type attenuation structure. The circuit diagram of the attenuator is shown in Figure 6.

[0044] Figure 6 In this diagram, V1P and V1N are a pair of inverted digital signals used to control the switching on and off of the switches in the 0.5dB attenuation unit, achieving different attenuation levels. When V1P is low and V1N is high, the 0.5dB attenuation unit is on, and the attenuator will produce 0.5dB attenuation; when V1P is high and V1N is low, the 0.5dB attenuation unit is off, and no attenuation occurs. Similarly, V2P~V6P and V2N~V6N are used to control the 1dB, 2dB, 4dB, 8dB, and 16dB attenuation units, respectively, and the attenuation unit is on when VnP (n=1,2,3,4,5,6) is low, producing the corresponding attenuation. RFin is the RF input signal of the attenuator, and RFout is the RF output signal after attenuation by the attenuator.

[0045] In this embodiment of the invention, the attenuator includes six attenuation units: a first attenuation unit achieving 0.5dB attenuation, a second attenuation unit achieving 1dB attenuation, a third attenuation unit achieving 2dB attenuation, a fourth attenuation unit achieving 4dB attenuation, a fifth attenuation unit achieving 8dB attenuation, and a sixth attenuation unit achieving 16dB attenuation. The circuit structures of the first, second, third, fourth, and fifth attenuation units achieving 0.5dB, 1dB, 2dB, 4dB, and 8dB attenuation are all parallel T-type attenuation structures, while the circuit structure of the sixth attenuation unit achieving 16dB attenuation is a Π-type attenuation structure.

[0046] For the parallel T-type attenuation structure: the T-type attenuation structures corresponding to V1P and V2P are completely identical, and the T-type attenuation structures corresponding to V3P, V4P, and V5P are also completely identical. However, there are slight differences between the T-type attenuation structures corresponding to V1P and V2P and those corresponding to V3P, V4P, and V5P. Figure 7 As shown, taking the T-type attenuation structure corresponding to V1P as an example, resistor R54 is used to receive the digital signal V1P, and its other end is connected to the gate of NMOS40. The source of NMOS40 is connected to the drain of NMOS37 and resistor R55, and the drain of NMOS40 is connected to the source of NMOS42 and resistor R56. The other ends of resistors R55 and R56 are both connected to the drain of NMOS41. The gate of NMOS41 is connected in series with resistor R57, and the other end of resistor R57 is used to receive the digital signal V1N. The source of NMOS41 is connected in series with resistor R58 and capacitor C22, and the other end of capacitor C22 is grounded. The T-type attenuation structure corresponding to V2P is completely consistent with the T-type attenuation structure corresponding to V1P, and the applicant will not elaborate further.

[0047] Compared to the T-type attenuation structures corresponding to V1P and V2P, such as Figure 6As shown, the T-type attenuation structures corresponding to V3P, V4P, and V5P introduce parallel resistors R38 / R60 / R66 in the main circuit. The purpose of this is to adjust the attenuation amount of the attenuation unit.

[0048] For the Π-type attenuation structure: [combined] Figure 6 As shown, R48 is used to receive the digital signal V6P, and its other end is connected to the gate of NMOS37. The source of NMOS37 is connected to the drain of NMOS35, resistor R49, and the drain of NMOS38. The drain of NMOS37 is connected to the source of NMOS40, the other end of resistor R49, and the drain of NMOS39. The source of NMOS38 is connected in series with resistor R52 and capacitor C20, with the other end of capacitor C20 grounded. The source of NMOS39 is connected in series with resistor R53 and capacitor C21, with the other end of capacitor C21 grounded. The gate of NMOS38 is connected to one end of resistor R50, and the gate of NMOS39 is connected to one end of resistor R51. The other ends of resistor R50 and resistor R51 are connected together, and both are used to receive the digital signal V6N.

[0049] The circuit structures (i.e. circuit models) corresponding to each of the above minimum functional units, as well as the digital prototypes built in ADS according to the chip architecture, have all met the error requirements of the test data (actual measured data) after simulation verification.

[0050] The Ka-band radio frequency microsystem digital prototype provided in this invention simplifies circuitry, improves computer operating efficiency, and provides prior conditions for the research of large and complex networks. Furthermore, the digital prototype allows for the replacement of components with different reference circuits without altering their functionality, reducing circuit costs. The established micro-circuit model also exhibits high portability and can be easily combined with different circuits.

[0051] Based on the Ka-band radio frequency microsystem digital prototype provided in the foregoing embodiments of the present invention, the present invention also provides a method for establishing a Ka-band radio frequency microsystem digital prototype, such as... Figure 7 As shown. Using Figure 7 The method shown can be used to build a digital prototype of a Ka-band radio frequency microsystem. This method for building a Ka-band radio frequency microsystem digital prototype includes: Step 101: Based on the reference architecture of the beamforming chip, decompose it into multiple minimum functional units.

[0052] In this embodiment of the invention, the beamforming chip is specifically a 32-38GHz silicon-based four-channel analog beamforming chip. This chip integrates driver amplifiers (including receiver and transmitter driver amplifiers), a six-position phase shifter, a six-position attenuator, a digitally controlled phase shifter, a single-pole three-throw switch, a power divider, and other unit circuits.

[0053] In practical applications, a reference architecture for beamforming chips can be obtained based on the physical chip and datasheet. Furthermore, the chip's performance requirements are analyzed using the datasheet, and the functions of the multi-functional chip are studied and analyzed. Based on the functions of the multi-functional chip, a corresponding test plan is established, and the overall chip undergoes high-volume DC and RF functional measurements to collect its performance data. Then, for the chip that has completed functional analysis and data measurement, a preliminary chip topology that meets the performance requirements (e.g., [missing information]) is determined based on its performance indicators. Figure 1 (as shown in the diagram) Finally, the multifunctional circuit is decomposed based on the test data, that is, the chip topology is decomposed into a single minimum functional unit, such as a driver amplifier, phase shifter, attenuator, power divider and other minimum functional units.

[0054] Step 102: Establish the macro model corresponding to each smallest functional unit.

[0055] In practical applications, the digital prototype must meet the functional modeling requirements of the beamforming chip. The schematics of each unit circuit of the digital prototype were built in Cadance, then ported to ADS Dynamic Link for macro-model encapsulation, and the overall digital prototype was modeled.

[0056] It is important to note that in practical applications, the circuit structure of the initially determined smallest functional unit needs to be manually debugged and optimized according to the schematic diagram to ensure that the circuit meets the performance requirements. Only after the circuit meets the performance requirements should it be modeled.

[0057] Step 103: The established macro model is built, debugged, and simulated in ADS according to the reference architecture of the beamforming chip to ensure that its performance meets the error requirements of the chip's actual test data, thereby completing the construction of the digital prototype.

[0058] For the circuit models of each established minimum functional unit, the model is built, debugged and simulated in ADS according to the reference architecture of the beamforming chip to ensure that its performance meets the error requirements of the actual chip measurement data, thereby ensuring that the established digital prototype can correspond one-to-one with the actual chip measurement performance.

[0059] Finally, the digital prototype of the verified multifunctional chip circuit was packaged and verified to obtain the digital prototype of the Ka-band RF microsystem.

[0060] It should be noted that the packaged digital prototype also needs to be verified to confirm whether the performance of the digital prototype before and after packaging is consistent.

[0061] This invention employs a chip circuit model and digital prototype approach. Based on the analysis of system capability indicators, architecture, operation mode, and information flow, simulation models of each key component are established, and a digital prototype system tailored to system requirements analysis is constructed. This allows for convenient verification of the engineering's rationality and feasibility. By establishing a chip circuit model and subsequently building a digital prototype of the radio frequency microsystem, circuitry can be simplified, computer operating efficiency improved, and prior conditions provided for the research of large and complex networks. In the macroscopic application of the circuit model, modeling and simulation allow for the use of different reference circuits without altering component functions, saving circuit costs. At the microscopic level, establishing a circuit model offers good portability and facilitates combination with different circuits.

[0062] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A digital prototype of a Ka-band radio frequency microsystem, characterized in that, The Ka-band radio frequency microsystem digital prototype includes four branches: the first branch and the second branch are respectively connected to the two output terminals of the first power divider, the third branch and the fourth branch are respectively connected to the two output terminals of the second power divider, the input terminal of the first power divider and the input terminal of the second power divider are respectively connected to the two output terminals of the third power divider, and the input terminal of the third power divider is connected to a common terminal. Each branch includes two sub-paths, which are connected to the power divider via a single-pole triple-throw switch. One sub-path consists of a first receiving-end driver amplifier, a first phase shifter, a second receiving-end driver amplifier, and an attenuator connected in series. The other sub-path consists of a second phase shifter and a transmitting-end driver amplifier connected in series.

2. The Ka-band radio frequency microsystem digital prototype according to claim 1, characterized in that, The first receiving end drive amplifier or the second receiving end drive amplifier includes: inductors L1, L2, L3, L4, L5, L6, capacitors C1, C2, C3, C4, resistors R1, R2, R3 and a transistor NMOS1; One end of inductor L1 is used to receive radio frequency input signals, and the other end is connected to one end of capacitor C1; The other end of capacitor C1 is connected to resistor R1, capacitor C2, and resistor R2 respectively; The other end of resistor R1 is connected in series with inductor L2, which is used to receive the gate bias voltage. After capacitor C2 and resistor R2 are connected in parallel, they are connected to one end of capacitor C3 and the gate of NMOS1, respectively. The other end of capacitor C3 is connected in series with inductor L3 and resistor R3, and then connected to the drain of NMOS1 and inductor L4 respectively. The source of NMOS1 is grounded; The other end of inductor L4 is connected to inductor L5 and capacitor C4 respectively. Inductor L5 is used to receive the drain bias voltage. The other end of capacitor C4 is connected in series with inductor L6, and the other end of inductor L6 is used to output the radio frequency signal.

3. The Ka-band radio frequency microsystem digital prototype according to claim 1, characterized in that, The transmitter driver amplifier includes inductors L7, L8, L9, L10, L11, L12, and L13; capacitors C5, C6, C7, C8, C9, C10, and C11; resistors R4, R5, R6, and R7; and transistors NMOS2 and NMOS3. One end of capacitor C5 is used to receive radio frequency input signals, and the other end is connected to capacitor C6 and inductor L7 respectively. The other end of inductor L7 is grounded. After capacitor C7 and resistor R4 are connected in parallel, one end is connected to the other end of capacitor C6, and the other end is connected to resistor R5 and the gate of NMOS2 respectively. The other end of resistor R5 is connected in series with inductor L8, which is used to receive the gate bias voltage. The source of NMOS2 is grounded, and the drain is connected to inductor L9 and capacitor C8 respectively; inductor L9 is used to receive the drain bias voltage. The other end of capacitor C8 is connected to inductor L10 and capacitor C9 respectively, and the other end of inductor L10 is grounded. After capacitor C10 and resistor R6 are connected in parallel, one end is connected to the other end of capacitor C9, and the other end is connected to resistor R7 and the gate of NMOS3 respectively. The other end of resistor R7 is connected in series with inductor L11, which is used to receive the gate bias voltage. The source of NMOS3 is grounded, and the drain is connected to inductor L12 and capacitor C11 respectively. Inductor L12 is used to receive the drain bias voltage. The other end of capacitor C11 is connected to inductor L13, and the connection point between the two is used to output the radio frequency output signal.

4. The Ka-band radio frequency microsystem digital prototype according to claim 1, characterized in that, The first phase shifter or the second phase shifter includes multiple phase shifting units with different phase shift amounts, namely a first phase shifting unit achieving a 5.625° phase shift, a second phase shifting unit achieving an 11.25° phase shift, a third phase shifting unit achieving a 22.5° phase shift, a fourth phase shifting unit achieving a 45° phase shift, a fifth phase shifting unit achieving a 90° phase shift, and a sixth phase shifting unit achieving a 180° phase shift; the third phase shifting unit, the second phase shifting unit, the fifth phase shifting unit, the fourth phase shifting unit, the first phase shifting unit, and the sixth phase shifting unit are connected in series sequentially; wherein: The first phase-shifting unit, the second phase-shifting unit, the third phase-shifting unit, and the fourth phase-shifting unit adopt a T-type phase-shifting topology. The fifth phase-shifting unit and the sixth phase-shifting unit adopt a switch-selective path-type phase-shifting topology.

5. The Ka-band radio frequency microsystem digital prototype according to claim 4, characterized in that, The third phase-shifting unit includes inductors L14, L15, and L16, resistors R8, R9, and R10, and NMOS4, NMOS5, and NMOS6; wherein: Resistor R8 is used to receive digital signal V3P, and the other end is connected to the gate of NMOS4. The source of NMOS4 is used to receive RF input signal and is also connected to inductor L14. The drain of NMOS4 is connected to inductor L15 and the source of NMOS7 in the second phase shift unit. One end of inductor L14 receives the radio frequency input signal, and the other end is connected to the drain of NMOS5; One end of inductor L15 is connected to the drain of NMOS4, and the other end is also connected to the drain of NMOS5; The gate of NMOS5 is connected to resistor R9, and the other end of resistor R9 is used to receive the digital signal V3P. The source of NMOS5 is connected to the drain of NMOS6 and inductor L16, respectively. The gate of NMOS6 is connected to resistor R10. The other end of resistor R10 is used to receive the digital signal V3N. The other end of inductor L16 is connected to the source of NMOS6, and the source of NMOS6 is grounded.

6. The Ka-band radio frequency microsystem digital prototype according to claim 4, characterized in that, The sixth phase-shifting unit includes inductors L29, L30, and L31; capacitors C15 and C16; resistors R24, R25, R26, and R27; and NMOS20, NMOS21, NMOS22, and NMOS23; wherein: Resistor R24 ​​is used to receive digital signal V6P, and the other end is connected to the gate of NMOS20. Resistor R25 is used to receive digital signal V6N, and the other end is connected to the gate of NMOS21. The drain of NMOS20 is connected to inductor L29, and the source is connected to the source of NMOS21. The drain of NMOS21 is connected to capacitor C16. The other end of inductor L29 is connected to inductor L30 and capacitor C15 respectively, and the other end of capacitor C15 is grounded. The other end of capacitor C16 is connected to inductor L31 and capacitor C17 respectively, with the other end of inductor L31 grounded; the other end of inductor L30 is connected to the drain of NMOS22, and the other end of capacitor C17 is connected to the drain of NMOS23. The source of NMOS22 is connected to the source of NMOS23. The gate of NMOS22 is connected to resistor R26. The other end of resistor R26 is used to receive digital signal V6P. The gate of NMOS23 is connected to resistor R27. The other end of resistor R27 is used to receive digital signal V6N.

7. The Ka-band radio frequency microsystem digital prototype according to claim 1, characterized in that, The single-pole three-throw switch includes an inductor L32 and three channel branches, which are connected in parallel and have the same circuit structure. For any given channel branch, including resistors R28, R29, R30, inductor L33, and transistors NMOS24, NMOS25, and NMOS26; where: Resistor R28 is used to receive the digital signal VnP, and its other end is connected to the gate of NMOS24; The source of NMOS24 is connected to inductor L32, and the drain is connected to the drain of NMOS25, the drain of NMOS26, and inductor L33, respectively. The source of the NMOS25 is grounded, and the gate is connected to resistor R29. Resistor R29 is used to receive the digital signal VnN. The source of the NMOS26 is grounded, and the gate is connected to resistor R30. Resistor R30 is used to receive the digital signal VnN. The other end of inductor L33 is used to output radio frequency signals; n is 1, 2, or 3.

8. The Ka-band radio frequency microsystem digital prototype according to claim 1, characterized in that, The attenuator includes six attenuation units: a first attenuation unit achieving 0.5dB attenuation, a second attenuation unit achieving 1dB attenuation, a third attenuation unit achieving 2dB attenuation, a fourth attenuation unit achieving 4dB attenuation, a fifth attenuation unit achieving 8dB attenuation, and a sixth attenuation unit achieving 16dB attenuation. The circuit structures of the first, second, third, fourth, and fifth attenuation units are all parallel T-type attenuation structures, while the circuit structure of the sixth attenuation unit is a Π-type attenuation structure.

9. The Ka-band radio frequency microsystem digital prototype according to claim 8, characterized in that, The T-shaped attenuation structure includes two structural forms, namely structural form one and structural form two; wherein: Structure type one includes: resistors R54, R55, R56, R57, R58, transistors NMOS40, NMOS41, and capacitor C22; Resistor R54 is used to receive the digital signal VnP, and the other end is connected to the gate of NMOS40; The source of NMOS40 is connected to the drain of NMOS37 and resistor R55, respectively, and the drain of NMOS40 is connected to the source of NMOS42 and resistor R56, respectively. The other ends of resistors R55 and R56 are both connected to the drain of NMOS41; The gate series resistor R57 of the NMOS41 is used to receive the digital signal VnN. The source of the NMOS41 is connected in series with a resistor R58 and a capacitor C22, and the other end of the capacitor C22 is grounded. n is 1 or 2; Compared to structure form one, structure form two also includes a parallel resistor introduced in the main circuit to adjust the attenuation of the attenuation unit.

10. The Ka-band radio frequency microsystem digital prototype according to claim 8, characterized in that, The Π-type attenuation structure includes resistors R48, R49, R50, R51, R52, and R53, transistors NMOS37, NMOS38, and NMOS39, and C20 and C21. R48 is used to receive the digital signal V6P, and the other end is connected to the gate of NMOS37; The source of NMOS37 is connected to the drain of NMOS35, resistor R49, and drain of NMOS38, respectively. The drain of NMOS37 is connected to the source of NMOS40, the other end of resistor R49, and drain of NMOS39, respectively. The source of the NMOS38 is connected in series with resistor R52 and capacitor C20, and the other end of capacitor C20 is grounded. The source of the NMOS39 is connected in series with resistor R53 and capacitor C21, and the other end of capacitor C21 is grounded. The gate of the NMOS38 is connected to one end of the resistor R50, and the gate of the NMOS39 is connected to one end of the resistor R51. The other end of the resistor R50 is connected to the other end of the resistor R51, and both are used to receive the digital signal V6N.

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