Data receiving method and device of direct current control and protection device

Abstract

The invention discloses a data receiving method and a data receiving device for a direct current control and protection device, which are used for solving the technical problems of insufficient time sequence tolerance, low frame synchronization reliability and low resource efficiency in the prior art. The method comprises the following steps: acquiring an original input signal transmitted to a direct current control and protection device, and performing secondary synchronization processing on the original input signal to obtain a steady-state input signal; performing effective edge detection on the steady-state input signal in combination with a window counting mechanism, and performing data bit decoding according to the type and position of the detected effective edge; and synchronously triggering real-time frame header detection, immediately triggering state conversion after the frame header detection is passed, starting to count received data bits obtained by decoding, and transferring successfully received data to a buffer register of the direct current control and protection device according to frames.

Description

Technical Field

[0001] This invention relates to the field of power system data processing technology, and in particular to a data receiving method for a DC control and protection device, a data receiving device for a DC control and protection device, an electronic device, and a storage medium. Background Technology

[0002] As a core component of the power system, the communication reliability of DC control and protection devices directly impacts power grid security. Traditional parallel communication suffers from drawbacks such as complex wiring, high cost, and susceptibility to interference. Ordinary serial communication struggles to balance transmission rate and reliability in complex electromagnetic environments. Manchester encoding, with its self-synchronization characteristics and excellent clock recovery capabilities, is widely used in power communication. However, its traditional decoding schemes have significant shortcomings.

[0003] Currently, the main approaches used are the traditional Manchester decoding scheme based on shift registers and an improved scheme based on oversampling. The former recovers the clock through a phase-locked loop and samples at the midpoint of the clock. However, this method is sensitive to timing jitter, and clock recovery is difficult under strong interference (or complex electromagnetic environments), and frame synchronization reliability is limited, making it prone to decoding errors. The latter uses multiple sampling and digital filtering to improve anti-interference capabilities. However, this approach consumes a lot of resources and has high processing latency, making it difficult to meet the low latency requirements of DC control and protection.

[0004] Traditional technologies suffer from the following drawbacks: First, limited timing tolerance, with signal edge jitter easily leading to decoding errors. Second, the current frame header detection uses a simple bit-matching method, which is prone to false synchronization or missed synchronization under continuous interference, resulting in insufficient frame synchronization reliability. Third, the anti-interference mechanism is imperfect, with limited ability to suppress transient pulses and continuous noise unique to power systems. Furthermore, while oversampling improvements enhance decoding reliability, they consume excessive logic resources and power, leading to low resource efficiency. These shortcomings restrict the communication performance of DC control and protection devices in complex scenarios such as ultra-high voltage. Therefore, a new data reception scheme that balances reliability, real-time performance, and resource efficiency is urgently needed. Summary of the Invention

[0005] This invention provides a data receiving method for a DC control and protection device, a data receiving device for a DC control and protection device, an electronic device, and a storage medium, which are used to solve or partially solve the technical problems of insufficient timing tolerance, low frame synchronization reliability, and low resource efficiency in the current related technologies.

[0006] This invention provides a data receiving method for a DC control and protection device, the method comprising:

[0007] The original input signal transmitted to the DC control and protection device is acquired, and the original input signal is processed by two-stage synchronization to obtain a steady-state input signal;

[0008] The steady-state input signal is subjected to effective edge detection using a window counting mechanism, and data bits are decoded based on the type and position of the detected effective edge.

[0009] Synchronous triggering of real-time frame header detection; upon passing frame header detection, immediately triggering state transition, starting to count the received decoded data bits, and transferring the successfully received data frame by frame to the buffer register of the DC control and protection device.

[0010] Optionally, a signal synchronization chain is formed by a first synchronous flip-flop and a second synchronous flip-flop connected in series; the step of performing two-stage synchronization processing on the original input signal to obtain a steady-state input signal includes:

[0011] The original input signal is input to the first synchronous flip-flop, and sampled at the rising edge of the current clock cycle of the system clock to obtain a preliminary sampled signal;

[0012] In the next clock cycle, the initial sampling signal is passed to the second synchronous flip-flop, and sampling is performed on the rising edge of the next clock cycle to obtain a steady-state input signal.

[0013] Optionally, the window counting mechanism means that each data bit is evenly divided into 10 clock cycles, and 10 clock cycles are used as a cycle when detecting data bits; the effective edge detection of the steady-state input signal in combination with the window counting mechanism includes:

[0014] Within each cycle, level transitions are identified by comparing the synchronization data values ​​of the steady-state input signal in the current clock cycle with those in the previous clock cycle.

[0015] When a change in the synchronization data value is detected for the first time within the cycle, an edge detection flag is set, and the first level transition and its corresponding position identified within the cycle are determined as the valid edge corresponding to the cycle.

[0016] Optionally, the step of decoding data bits based on the detected valid edge type and position includes:

[0017] For each detected valid edge, data bits are decoded according to the valid edge type and position, and a data validity flag is set;

[0018] When the valid edge type is a rising edge transition, the data bit at the corresponding position of the valid edge is decoded as logic '0';

[0019] When the valid edge type is a falling edge transition, the data bit at the corresponding position of the valid edge is decoded as logic '1'.

[0020] Optionally, the synchronous triggering of real-time frame header detection, upon passing frame header detection, immediately triggers a state transition, including:

[0021] When data bit decoding is started, real-time frame header detection is triggered synchronously. The received data bits are stored in real time using a 16-bit shift register, and the stored data bits are compared with the preset target frame header.

[0022] When a data bit is detected that completely matches the preset target frame header, the frame header detection is deemed successful, and a state transition is immediately triggered, changing from the idle state to the data receiving state.

[0023] Optionally, the step of starting to count the decoded data bits received and transferring the successfully received data frame by frame to the buffer register of the DC control and protection device includes:

[0024] In the data receiving state, start counting the decoded data bits received and track the receiving progress using a bit counter;

[0025] Each time 16 bits of complete data are successfully received, a frame validity flag is set, and the 16 bits of complete data are treated as a valid data frame.

[0026] The valid data frame is transferred to the buffer register of the DC control and protection device.

[0027] Optionally, the method further includes:

[0028] Upon successful reception of each valid data frame, the current data reception state is immediately switched to idle state, and real-time frame header detection is triggered to detect the frame header of the next valid data frame.

[0029] The present invention also provides a data receiving device for a DC control and protection device, comprising:

[0030] An input synchronization processing unit is used to acquire the original input signal transmitted to the DC control and protection device, and to perform secondary synchronization processing on the original input signal to obtain a steady-state input signal;

[0031] The data decoding unit is used to perform effective edge detection on the steady-state input signal by combining a window counting mechanism, and to perform data bit decoding according to the detected effective edge type and position.

[0032] The data receiving unit is used to synchronously trigger real-time frame header detection. After passing the frame header detection, it immediately triggers a state transition, starts counting the received decoded data bits, and transfers the successfully received data frame by frame to the buffer register of the DC control and protection device.

[0033] The present invention also provides an electronic device, the device comprising a processor and a memory:

[0034] The memory is used to store program code and transmit the program code to the processor;

[0035] The processor is used to execute the data receiving method of the DC control and protection device as described above, according to the instructions in the program code.

[0036] The present invention also provides a computer-readable storage medium for storing program code for executing the data receiving method of the DC control and protection device as described in any of the preceding claims.

[0037] As can be seen from the above technical solutions, the present invention has the following advantages:

[0038] A data receiving method for a DC control and protection device is provided. First, the original input signal transmitted to the DC control and protection device is acquired and subjected to two-stage synchronization processing to obtain a steady-state input signal. Then, a window counting mechanism is used to detect effective edges of the steady-state input signal, and data bits are decoded based on the detected effective edge type and position. Real-time frame header detection is triggered synchronously. Upon successful frame header detection, a state transition is immediately triggered, counting of the received decoded data bits begins, and successfully received data is transferred frame by frame to the buffer register of the DC control and protection device. On one hand, a window counter-based synchronization mechanism is designed to replace the traditional phase-locked loop scheme, improving decoding robustness under signal jitter environments. On the other hand, a multi-level frame header verification strategy is constructed, using shift registers for real-time comparison and target frame header matching, enhancing the reliability of frame synchronization. Simultaneously, by optimizing the decoding architecture, resource consumption is reduced while ensuring anti-interference capability, meeting the low latency and high real-time performance requirements of the DC control and protection device. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A flowchart illustrating the steps of a data receiving method for a DC control and protection device;

[0041] Figure 2 A schematic diagram of the overall process for data receiving method of a DC control and protection device;

[0042] Figure 3 This is a structural block diagram of a data receiving device for a DC control and protection device. Detailed Implementation

[0043] This invention provides a data receiving method for a DC control and protection device, a data receiving device for a DC control and protection device, an electronic device, and a storage medium, which are used to solve or partially solve the technical problems of insufficient timing tolerance, low frame synchronization reliability, and low resource efficiency in the current related technologies.

[0044] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0045] As an example, for data reception and decoding in DC control and protection devices, the current main approaches are the traditional Manchester decoding scheme based on shift registers and an improved scheme based on oversampling. The former recovers the clock through a phase-locked loop and samples at the midpoint of the clock. However, this method is sensitive to timing jitter, and clock recovery is difficult under strong interference (or complex electromagnetic environments), and frame synchronization reliability is limited, making decoding errors prone to occur. The latter uses multiple sampling and digital filtering to improve anti-interference capabilities. However, this approach consumes significant resources and has high processing latency, making it difficult to meet the low-latency requirements of DC control and protection devices.

[0046] Traditional technologies suffer from the following drawbacks: First, limited timing tolerance, with signal edge jitter easily leading to decoding errors. Second, the current frame header detection uses a simple bit-matching method, which is prone to false synchronization or missed synchronization under continuous interference, resulting in insufficient frame synchronization reliability. Third, the anti-interference mechanism is imperfect, with limited ability to suppress transient pulses and continuous noise unique to power systems. Furthermore, while oversampling improvements enhance decoding reliability, they consume excessive logic resources and power, leading to low resource efficiency. These shortcomings restrict the communication performance of DC control and protection devices in complex scenarios such as ultra-high voltage. Therefore, a new data reception scheme that balances reliability, real-time performance, and resource efficiency is urgently needed.

[0047] Therefore, one of the core inventive points of this invention is to address the shortcomings of current technologies by providing a high-speed data reception method for DC control and protection devices. On one hand, a synchronization mechanism based on a window counter is designed to replace the traditional phase-locked loop scheme, improving decoding robustness under signal jitter conditions. On the other hand, a multi-level frame header verification strategy is constructed, enhancing the reliability of frame synchronization through real-time comparison and target frame header matching using shift registers. Simultaneously, the decoding architecture is optimized to reduce resource consumption while ensuring anti-interference capabilities, meeting the requirements of DC control and protection devices for low latency and high real-time performance.

[0048] This invention aims to provide a high-speed data reception method for a DC control and protection device. Its core lies in constructing a complete serial data reception and decoding system. Depending on its function, this system mainly comprises five core parts: an input synchronization module, an edge detection and decoding module, a frame header detection module, a status control module, and a data output module. The modules within the system work collaboratively to achieve the entire process from serial data reception and Manchester decoding to parallel data output.

[0049] The input synchronization module is primarily responsible for securely synchronizing the input serial data signal (RXport) to the system clock domain, avoiding metastability issues. The edge detection and decoding module achieves reliable Manchester code decoding through a window counting mechanism. The frame header detection module compares the target frame header in real-time using a shift register to determine the trigger position for state transitions. The state control module uses a finite state machine (FSM) to control the state transitions throughout the receiving process. The data output module is responsible for outputting real-time data and valid frame data, and provides corresponding output verification mechanisms to avoid false alarms from partial or erroneous data.

[0050] Based on the content described in the preceding embodiments, refer to Figure 1 The diagram illustrates a flowchart of a data receiving method for a DC control and protection device according to an embodiment of the present invention, which may specifically include the following steps:

[0051] Step 101: Obtain the original input signal transmitted to the DC control and protection device, and perform two-stage synchronization processing on the original input signal to obtain a steady-state input signal;

[0052] This step mainly involves performing input synchronization actions to achieve metastability prevention design.

[0053] The input synchronization module employs a two-stage synchronizer design. The specific implementation is as follows:

[0054] The signal synchronization chain consists of two cascaded D flip-flops. When an external serial data signal is input, it first enters the first-stage synchronization flip-flop and is sampled on the rising edge of the system clock. Subsequently (i.e., after a full clock cycle), in the next clock cycle, the processed signal output from the first-stage synchronization flip-flop is passed to the second-stage synchronization flip-flop for sampling. That is, after the first-stage synchronization flip-flop samples, a full system clock cycle passes before the second-stage synchronization flip-flop starts sampling. This design effectively eliminates metastability issues and ensures the stability of the input signal within the system clock domain. The data signal processed by the two-stage synchronization chain is then passed to the subsequent edge detection module for further processing.

[0055] In the reset state, the synchronizer output is cleared to zero, ensuring the system starts from a known state. Specifically, in the reset state, the synchronizer output is cleared to zero, meaning that during system initialization or reset, the synchronizer forces its output signal to zero or low. This operation ensures the system starts from a definite, known state, avoiding abnormal or unstable system startup due to uncertain synchronizer output. In this way, the system can be reliably initialized, ensuring the correctness and consistency of subsequent operations.

[0056] More specifically, the data transmission path of the signal synchronization chain is as follows: the original input signal enters the first-stage synchronization processing, the output of the first-stage synchronization processing is passed to the second-stage synchronization processing, and the output of the second-stage synchronization processing is passed to subsequent processing modules. In other words, in a standard two-stage synchronizer design, the data passed to the second-stage synchronization trigger is the data output after being sampled and latched by the first-stage synchronization trigger, rather than the original external input signal.

[0057] The specific data flow for the second-level synchronization process is as follows:

[0058] First-stage sampling: An asynchronous external serial data signal (async_in) is connected to the data input (D) of the first D flip-flop (DFF1). On the rising edge of the system clock (clk), DFF1 samples the instantaneous level of async_in and generates a preliminary synchronized but potentially metastable signal at its output (Q1).

[0059] Second-stage sampling: The output (Q1) of the first D flip-flop is directly connected to the data input (D) of the second D flip-flop (DFF2). On the next rising edge of clk, DFF2 samples the signal of Q1 and generates a fully stable signal (sync_out) synchronized to the system clock domain at its output (Q2) for use by subsequent circuits.

[0060] The connection between two synchronous flip-flops can be understood as a direct series connection, with clock synchronization. Specifically, there is a direct and close connection between the two synchronous flip-flops, which together form a standard "two-stage synchronizer" circuit module.

[0061] For structural association, the two are connected in series in the circuit, that is, the output (Q) of the first flip-flop is directly connected to the input (D) of the second flip-flop.

[0062] In clock-correlated scenarios, the two flip-flops are actually driven by the same system clock (clk) (but corresponding to different clock cycles). Both are updated on the exact same rising edge of the clock, ensuring operational synchronization.

[0063] For example, this embodiment of the invention provides a detailed timing process example. Assume the system clock period is T. At a certain rising edge t0, DFF1 samples the external input signal at that time, and the output Q1 begins to change (it may require a metastable recovery time to stabilize). During the entire clock period T after t0, the output Q1 of DFF1 has sufficient time to recover from the possible metastable state and stabilize to a defined logic level (0 or 1). At the next rising edge t0 + T, DFF2 samples the now stable Q1 value and outputs a stable, clean synchronization signal Q2.

[0064] Based on the foregoing description, in its specific implementation, this invention employs a signal synchronization chain consisting of a first synchronous flip-flop and a second synchronous flip-flop connected in series. The process of performing two-stage synchronization processing on the original input signal to obtain a steady-state input signal can include: inputting the original input signal to the first synchronous flip-flop, sampling it at the rising edge of the current clock cycle of the system clock to obtain a preliminary sampled signal; and in the next clock cycle, passing the preliminary sampled signal to the second synchronous flip-flop, sampling it at the rising edge of the next clock cycle to obtain the steady-state input signal.

[0065] The above design achieves the goal of "trading time for stability." The first-stage synchronous flip-flop handles the asynchronous signal and experiences the metastability risk. The second-stage synchronous flip-flop, after the metastability risk has been largely eliminated, "resamples" the already stable signal, thereby outputting a signal that is safe for subsequent synchronization circuits.

[0066] Step 102: Perform effective edge detection on the steady-state input signal using a window counting mechanism, and decode the data bits based on the detected effective edge type and position;

[0067] This invention provides a window counting and edge detection mechanism. Specifically, the window counter module uses a 4-bit wide counter that cycles between 0 and 9, corresponding to 10 clock cycles for each data bit. The main working principle of the window counter includes the following points:

[0068] A. Periodic Cycle. During detection, the counter starts from 0 and increments, automatically returning to zero after reaching a maximum value of 9, forming a continuous periodic cycle.

[0069] B. Window Division. Each data bit is evenly divided into 10 sampling windows (clock cycles) to provide a time reference for edge detection.

[0070] C. Synchronization Control. The window counter provides a precise time reference for edge detection and data decoding.

[0071] The edge detection module identifies level transitions by comparing the synchronization data values ​​of the current cycle with those of the previous cycle. Its specific detection logic includes the following points:

[0072] D. Edge indicator. Set the edge detection flag when a change in synchronization data is detected.

[0073] E. Transition Direction Determination. During data decoding, the data bit value is primarily decoded based on the transition direction. A rising edge is decoded as '0', and a falling edge is decoded as '1'.

[0074] F. Single detection within the window. In each loop cycle (corresponding to 10 clock cycles), only the first edge is identified as a valid edge to avoid repeated detection.

[0075] The purpose of setting a single-time detection within the window is that during data transmission, there may be consecutive '0's or consecutive '1's in the data stream. According to Manchester encoding rules, the level needs to be expressed through a series of changes: "5 cycles of high level, 5 cycles of low level, then 5 cycles of high level, then 5 cycles of low level". In this case, within a 10-clock-cycle window, both rising and falling edges may be detected. For consistency, only the first edge in the serial port is taken as the valid edge.

[0076] Based on the preceding discussion, the window counting mechanism presented in this embodiment of the invention can be represented as each data bit being uniformly divided into 10 clock cycles, with 10 clock cycles serving as a loop cycle during data bit detection. In a specific implementation, the process of detecting effective edges of the steady-state input signal using the window counting mechanism can include: within each loop cycle, identifying level transitions by comparing the synchronization data values ​​of the steady-state input signal in the current clock cycle with those in the previous clock cycle; when a change in the synchronization data value is detected for the first time within the loop cycle, setting an edge detection flag, and determining the first identified level transition and its corresponding position within the loop cycle as the effective edge corresponding to the loop cycle.

[0077] In the implementation of Manchester decoding, the Manchester decoding module decodes data bits based on the detected valid edge type and position. The specific rules are as follows:

[0078] For rising edge transitions (i.e., from low to high): decoded as logic '0', corresponding to the "first 5 cycles low, last 5 cycles high" encoding rule of the transmitting end.

[0079] For a falling edge transition (i.e., from high level to low level): it is decoded as logic '1', corresponding to the encoding rule of "high level for the first 5 cycles, low level for the next 5 cycles" at the transmitting end.

[0080] During the decoding process, each valid edge triggers the following operations: setting the data validity flag, shifting the decoded data into the data shift register, and updating the real-time data output.

[0081] Based on the preceding discussion, in a specific implementation, the data bit decoding process according to the detected valid edge type and position can include: for each detected valid edge, data bit decoding is performed according to the valid edge type and position of the valid edge, and a data validity flag is set; wherein, when the valid edge type is a rising edge transition, the data bit at the corresponding position of the valid edge is decoded as logic '0'; when the valid edge type is a falling edge transition, the data bit at the corresponding position of the valid edge is decoded as logic '1'.

[0082] Step 103: Synchronously trigger real-time frame header detection. Once the frame header detection is passed, immediately trigger a state transition, start counting the received decoded data bits, and transfer the successfully received data frame by frame to the buffer register of the DC control and protection device.

[0083] This invention also provides a frame header detection and status control mechanism, as well as a data output and verification mechanism.

[0084] Specifically, for the frame header detection and state control mechanism, the frame header detection module uses a 16-bit shift register to store the received data bits in real time and compares them with the preset target frame header. When a perfect match is detected, a state transition is immediately triggered.

[0085] In this embodiment of the invention, the state control module adopts a finite state machine design, which mainly includes the following two key states:

[0086] Idle state (IDLE): The initial state of the system. In this state, frame header detection continues, and output data is updated in real time (but the frame validity flag is not set). When a complete frame header is detected (i.e., the frame header detection can completely match), the system immediately switches to the data receiving state.

[0087] Data Reception Status (DATA_RECV): In this status, the system begins counting the received data bits, tracking the reception progress using a bit counter. Every 16 bits of complete valid data received, a frame valid flag (frame_valid) is set, indicating that a complete data frame has been received, and the 16 bits of complete valid data are considered a valid data frame.

[0088] In practical applications, state transition conditions strictly follow these rules:

[0089] From IDLE to DATA_RECV: header_shift_reg == FRAME_HEADER

[0090] From DATA_RECV to IDLE: Automatic conversion, returning to idle state immediately after successfully receiving a frame.

[0091] For the data output and verification mechanism, the data output module can provide two levels of output interfaces. Specifically:

[0092] Real-time data output (frame_data): Displays the contents of the shift register in real time during idle state, facilitating monitoring and debugging.

[0093] Valid frame output: In data reception mode, when the bit counter reaches 15 (i.e., after receiving 16 bits of data), the contents of the data shift register are output to frame_data, and the frame_valid signal is set at the same time to indicate that a valid data frame is ready.

[0094] By setting up an output verification mechanism, it can be ensured that a valid flag is triggered only when a complete and correct data frame is received, thus avoiding false alarms for partial or incorrect data.

[0095] Based on the preceding discussion, the synchronous triggering of real-time frame header detection in this step, and the immediate triggering of the state transition process after passing the frame header detection, may include: when data bit decoding is started, synchronous triggering of real-time frame header detection, using a 16-bit shift register to store the received data bits in real time, and comparing the stored data bits with the preset target frame header; when it is detected that there is a data bit that completely matches the preset target frame header, it is determined that the frame header detection has passed, and the state transition is immediately triggered, changing from the idle state to the data receiving state.

[0096] Furthermore, the implementation process of starting to count the received decoded data bits and transferring the successfully received data to the buffer register of the DC control and protection device in frames may include: in the data receiving state, starting to count the received decoded data bits and tracking the receiving progress through a bit counter; setting a frame valid flag for every 16 bits of complete data successfully received and treating the 16 bits of complete data as a valid data frame; and transferring the valid data frame to the buffer register of the DC control and protection device.

[0097] In some embodiments, after each successful reception of a valid data frame, the current data reception state is immediately switched to an idle state, and real-time frame header detection is triggered to detect the frame header of the next valid data frame.

[0098] This invention provides a high-speed data reception method for a DC control and protection device. On one hand, a window counter-based synchronization mechanism is designed to replace the traditional phase-locked loop (PLL) scheme, improving decoding robustness under signal jitter conditions. On the other hand, a multi-level frame header verification strategy is constructed, enhancing the reliability of frame synchronization through real-time comparison with shift registers and matching with the target frame header. Simultaneously, the decoding architecture is optimized, reducing resource consumption while ensuring anti-interference capabilities, thus meeting the low latency and high real-time performance requirements of the DC control and protection device.

[0099] The technical solution provided in this invention avoids reliance on a phase-locked loop (PLL) in terms of anti-interference capability by employing a window counting mechanism and an edge detection scheme. Specifically, the target frame header detection mechanism, which uses edge detection within a fixed period window and real-time comparison with a shift register, effectively overcomes the timing sensitivity caused by signal edge jitter and the false synchronization phenomenon easily generated under continuous interference, significantly improving decoding robustness under signal jitter environments. Regarding synchronization reliability, the constructed multi-level frame header verification strategy ensures accurate frame synchronization through precise bit comparison, effectively preventing false synchronization and missed synchronization. In terms of resource efficiency, the optimized decoding architecture significantly reduces resource consumption while maintaining performance. Replacing the complex digital PLL with simple counter logic significantly reduces the amount of logic resources used. Regarding real-time performance assurance, the streamlined processing flow and deterministic state transitions ensure low-latency data processing, fully meeting the stringent real-time requirements of DC control and protection devices.

[0100] For better explanation, refer to Figure 2 This diagram illustrates the overall flow of a data receiving method for a DC control and protection device according to an embodiment of the present invention. It should be noted that this embodiment only provides a brief description of the general flow of data receiving in a DC control and protection device. The specific implementation process of each step can be understood by referring to the relevant content in the foregoing embodiments, and will not be elaborated upon here. It is understood that the present invention does not impose any limitations on this.

[0101] Step 201: Obtain the original input signal transmitted to the DC control and protection device, input the original input signal to the first synchronous flip-flop, obtain the preliminary sampling signal by sampling, and transmit the preliminary sampling signal to the second synchronous flip-flop in the next clock cycle to obtain the steady-state input signal by sampling;

[0102] Step 202: Combine the window counting mechanism to perform effective edge detection on the steady-state input signal. For each detected effective edge, decode the data bits according to the effective edge type and position, and set the data valid flag.

[0103] Step 203: When data bit decoding is started, real-time frame header detection is triggered synchronously. The received data bits are stored in real time using a 16-bit shift register, and the stored data bits are compared with the preset target frame header.

[0104] Step 204: When it is detected that there is a data bit that completely matches the preset target frame header, it is determined that the frame header detection has passed, and a state transition is immediately triggered, changing from the idle state to the data receiving state;

[0105] Step 205: In the data receiving state, start counting the decoded data bits received, and track the receiving progress using a bit counter;

[0106] Step 206: For each successful reception of 16 bits of complete data, set a frame valid flag, treat the 16 bits of complete data as a valid data frame, and transfer the valid data frame to the buffer register of the DC control and protection device.

[0107] Reference Figure 3 The diagram illustrates a structural block diagram of a data receiving device for a DC control and protection device according to an embodiment of the present invention, which may specifically include:

[0108] The input synchronization processing unit 301 is used to acquire the original input signal transmitted to the DC control and protection device, and to perform secondary synchronization processing on the original input signal to obtain a steady-state input signal;

[0109] The data decoding unit 302 is used to perform effective edge detection on the steady-state input signal in conjunction with the window counting mechanism, and to perform data bit decoding according to the detected effective edge type and position;

[0110] The data receiving unit 303 is used to synchronously trigger real-time frame header detection. After passing the frame header detection, it immediately triggers a state transition, starts counting the received decoded data bits, and transfers the successfully received data frame by frame to the buffer register of the DC control and protection device.

[0111] In one optional embodiment, a signal synchronization chain is formed by a first synchronous flip-flop and a second synchronous flip-flop connected in series; the input synchronization processing unit 301 includes:

[0112] A primary synchronization processing unit is used to input the original input signal to the first synchronization trigger and sample it at the rising edge of the current clock cycle of the system clock to obtain a preliminary sampled signal;

[0113] The secondary synchronization processing unit is used to transmit the preliminary sampling signal to the second synchronization flip-flop in the next clock cycle, and to sample it at the rising edge of the next clock cycle to obtain a steady-state input signal.

[0114] In one optional embodiment, the window counting mechanism means that each data bit is evenly divided into 10 clock cycles, and 10 clock cycles are used as a cycle when detecting data bits; the data decoding unit 302 includes:

[0115] The level transition recognition unit is used to identify level transitions by comparing the synchronization data values ​​of the steady-state input signal in the current clock cycle with those in the previous clock cycle within each cycle.

[0116] The effective edge determination unit is used to set an edge detection flag when a change in the synchronization data value is detected for the first time in the cycle, and to determine the first level transition and corresponding position identified in the cycle as the effective edge corresponding to the cycle.

[0117] In one alternative embodiment, the data decoding unit 302 includes:

[0118] A data bit decoding unit is used to decode data bits for each detected valid edge according to the valid edge type and position of the valid edge, and set a data valid flag;

[0119] When the valid edge type is a rising edge transition, the data bit at the corresponding position of the valid edge is decoded as logic '0';

[0120] When the valid edge type is a falling edge transition, the data bit at the corresponding position of the valid edge is decoded as logic '1'.

[0121] In one optional embodiment, the data receiving unit 303 includes:

[0122] The frame header comparison unit is used to synchronously trigger real-time frame header detection when data bit decoding is started. It uses a 16-bit shift register to store the received data bits in real time and compares the stored data bits with the preset target frame header.

[0123] The state transition execution unit is used to determine that the frame header detection has passed when it is detected that there are data bits that completely match the preset target frame header, and immediately trigger the state transition to change from the idle state to the data receiving state.

[0124] In one optional embodiment, the data receiving unit 303 includes:

[0125] The data bit counting unit is used to start counting the decoded data bits received in the data receiving state and to track the receiving progress through the bit counter;

[0126] The valid data frame determination unit is used to set a frame valid flag and treat the 16 bits of complete data as a valid data frame whenever 16 bits of complete data are successfully received.

[0127] A valid data frame transfer unit is used to transfer the valid data frame to the buffer register of the DC control and protection device.

[0128] In one alternative embodiment, the device further includes:

[0129] The idle state transition unit is used to immediately switch the current data reception state to the idle state after each successful reception of a valid data frame, and at the same time trigger real-time frame header detection to detect the frame header of the next valid data frame.

[0130] As the device embodiment is basically similar to the method embodiment, it is described in a relatively simple way. For relevant details, please refer to the description of the method embodiment above.

[0131] It should be noted that, in order to enable those skilled in the art to better distinguish data of the same type but with different actual meanings, the embodiments of the present invention use "first" and "second" to distinguish and describe some technical features. "First" and "second" are only used to distinguish data and have no other special meaning. It is understood that the present invention does not impose any limitations on them.

[0132] This invention also provides an electronic device, which includes a processor and a memory:

[0133] The memory is used to store program code and transfer the program code to the processor;

[0134] The processor is used to execute the data receiving method of the DC control and protection device according to the instructions in the program code of any embodiment of the present invention.

[0135] This invention also provides a computer-readable storage medium for storing program code for executing the data receiving method of the DC control and protection device according to any embodiment of this invention.

[0136] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0137] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this invention are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0138] In the embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between devices or units through some interfaces, and may be electrical, mechanical, or other forms.

[0139] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0140] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0141] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0142] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data receiving method for a DC control and protection device, characterized in that, include: The original input signal transmitted to the DC control and protection device is acquired, and the original input signal is processed by two-stage synchronization to obtain a steady-state input signal; The steady-state input signal is subjected to effective edge detection using a window counting mechanism, and data bits are decoded based on the type and position of the detected effective edge. Synchronous triggering of real-time frame header detection; upon passing frame header detection, immediately triggering state transition, starting to count the received decoded data bits, and transferring the successfully received data frame by frame to the buffer register of the DC control and protection device.

2. The data receiving method of the DC control and protection device according to claim 1, characterized in that, A signal synchronization chain is formed by connecting a first synchronous flip-flop and a second synchronous flip-flop in series; the step of performing two-stage synchronization processing on the original input signal to obtain a steady-state input signal includes: The original input signal is input to the first synchronous flip-flop, and sampled at the rising edge of the current clock cycle of the system clock to obtain a preliminary sampled signal; In the next clock cycle, the initial sampling signal is passed to the second synchronous flip-flop, and sampling is performed on the rising edge of the next clock cycle to obtain a steady-state input signal.

3. The data receiving method of the DC control and protection device according to claim 1, characterized in that, The window counting mechanism means that each data bit is evenly divided into 10 clock cycles, and when performing data bit detection, 10 clock cycles are used as a cycle. The method of combining window counting mechanism to perform effective edge detection on the steady-state input signal includes: Within each cycle, level transitions are identified by comparing the synchronization data values ​​of the steady-state input signal in the current clock cycle with those in the previous clock cycle. When a change in the synchronization data value is detected for the first time within the cycle, an edge detection flag is set, and the first level transition and its corresponding position identified within the cycle are determined as the valid edge corresponding to the cycle.

4. The data receiving method of the DC control and protection device according to claim 1, characterized in that, The step of decoding data bits based on the detected valid edge type and position includes: For each detected valid edge, data bits are decoded according to the valid edge type and position, and a data validity flag is set; When the valid edge type is a rising edge transition, the data bit at the corresponding position of the valid edge is decoded as logic '0'; When the valid edge type is a falling edge transition, the data bit at the corresponding position of the valid edge is decoded as logic '1'.

5. The data receiving method of the DC control and protection device according to claim 1, characterized in that, The synchronous triggering of real-time frame header detection, upon successful frame header detection, immediately triggers a state transition, including: When data bit decoding is started, real-time frame header detection is triggered synchronously. The received data bits are stored in real time using a 16-bit shift register, and the stored data bits are compared with the preset target frame header. When a data bit is detected that completely matches the preset target frame header, the frame header detection is deemed successful, and a state transition is immediately triggered, changing from the idle state to the data receiving state.

6. The data receiving method of the DC control and protection device according to any one of claims 1 to 5, characterized in that, The process of starting to count the decoded data bits received and transferring successfully received data frame by frame to the buffer register of the DC control and protection device includes: In the data receiving state, start counting the decoded data bits received and track the receiving progress using a bit counter; Each time 16 bits of complete data are successfully received, a frame validity flag is set, and the 16 bits of complete data are treated as a valid data frame. The valid data frame is transferred to the buffer register of the DC control and protection device.

7. The data receiving method of the DC control and protection device according to claim 6, characterized in that, Also includes: Upon successful reception of each valid data frame, the current data reception state is immediately switched to idle state, and real-time frame header detection is triggered to detect the frame header of the next valid data frame.

8. A data receiving device for a DC control and protection device, characterized in that, include: An input synchronization processing unit is used to acquire the original input signal transmitted to the DC control and protection device, and to perform secondary synchronization processing on the original input signal to obtain a steady-state input signal; The data decoding unit is used to perform effective edge detection on the steady-state input signal by combining a window counting mechanism, and to perform data bit decoding according to the detected effective edge type and position. The data receiving unit is used to synchronously trigger real-time frame header detection. After passing the frame header detection, it immediately triggers a state transition, starts counting the received decoded data bits, and transfers the successfully received data frame by frame to the buffer register of the DC control and protection device.

9. An electronic device, characterized in that, The device includes a processor and a memory: The memory is used to store program code and transmit the program code to the processor; The processor is used to execute the data receiving method of the DC control and protection device according to any one of claims 1-7 according to the instructions in the program code.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store program code for executing the data receiving method of the DC control and protection device according to any one of claims 1-7.

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