Wiring board

Abstract

The invention provides a wiring substrate which has high quality. According to one embodiment, a wiring board includes a multilayer core substrate and a build-up layer. The multilayer core substrate includes a central insulating layer, first and second resin substrates, first and second outer insulating layers, a via conductor, first and second surface conductor layers, and first and second connection conductors. The multilayer core substrate is provided with components. The through hole conductor is composed of a through hole, a first through hole conductor and a second through hole conductor. A first opening penetrating through the first resin substrate is formed, a first non-electrode surface of the first member is disposed on the central insulating layer exposed from the first opening, and a first electrode surface is connected by a first connection conductor of the first outer insulating layer. A second opening penetrating through the second resin substrate is formed, a second non-electrode surface of the second member is disposed on the central insulating layer exposed from the second opening, and a second electrode surface is connected by a second connection conductor of the second outer insulating layer.

Description

Technical Field

[0001] The technology disclosed in this specification relates to wiring substrates. Background Technology

[0002] Patent Document 1 discloses a printed wiring board comprising: a multilayer core substrate; an electronic component having an opening from a first side to a second side of the multilayer core substrate and housed within the opening; and a laminate formed on the multilayer core substrate, comprising an interlayer resin insulating layer. It also discloses that the gap between the substrate and the component within the opening of the multilayer core substrate is filled with resin or the like.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2015-185564

[0004] [The issue of patent document 1]

[0005] In the printed wiring board of Patent Document 1, the opening is a through-hole extending from the first surface of the multilayer core substrate to the second surface. Therefore, it is considered that a certain amount of resin needs to be filled into the gap between the substrate and the component within the opening. In addition, if the filled resin is insufficient, it will also cause the undesirable situation of gaps being generated within the opening. Conversely, if the filled resin is excessive, it will cover the component, and it is considered that the formation of vias with the component will not be smooth. Summary of the Invention

[0006] The wiring substrate of the present invention has a multilayer core substrate and a multilayer laminate formed on the multilayer core substrate by insulating layers and conductor layers. The multilayer core substrate includes multiple insulating layers, through-hole conductors, a first surface conductor layer, a second surface conductor layer, a first connection conductor, and a second connection conductor, and components are disposed on the multilayer core substrate. The multilayer insulating layers are composed of a central insulating layer, a first resin substrate, a second resin substrate, a first outer insulating layer, and a second outer insulating layer. The first resin substrate is formed on a first surface of the central insulating layer, the first outer insulating layer is formed on the first resin substrate, and the first surface conductor layer is formed on the first outer insulating layer. The second resin substrate is formed on a second surface of the central insulating layer, the second outer insulating layer is formed on the second resin substrate, and the second surface conductor layer is formed on the second outer insulating layer. The through-hole conductor is composed of a through-hole, a first via conductor, and a second via conductor. The through-hole is a hole penetrating the first resin substrate, the central insulating layer, and the second resin substrate; an inner wall conductor layer is formed on the inner wall of the hole; a first cover conductor is formed on the first resin substrate; and a second cover conductor is formed on the second resin substrate. The first via conductor is formed in a hole penetrating the first outer insulating layer and exposing the first cover conductor, connecting the first surface conductor layer and the first cover conductor. The second via conductor is formed in a hole penetrating the second outer insulating layer and exposing the second cover conductor, connecting the second surface conductor layer and the second cover conductor. The component includes a first component and a second component. The first component is composed of a first electrode surface and a first non-electrode surface opposite to the first electrode surface. The second component is composed of a second electrode surface and a second non-electrode surface opposite to the second electrode surface. A first opening penetrating the first resin substrate is formed. The first non-electrode surface of the first component is disposed on the first surface of the central insulating layer exposed from the first opening. The first electrode surface is connected by the first connecting conductor of the first outer insulating layer. A second opening penetrating the second resin substrate is formed. The second non-electrode surface of the second component is disposed on the second surface of the central insulating layer exposed from the second opening. The second electrode surface is connected by the second connecting conductor of the second outer insulating layer.

[0007] In the wiring substrate of this embodiment, a first opening for housing a first component penetrates a first resin substrate, and a second opening for housing a second component penetrates a second resin substrate, but does not penetrate a multilayer core substrate. This reduces the amount of resin used to fill the gap between the substrate filling the first opening and the first component, and the gap between the substrate filling the second opening and the second component. Furthermore, a through-hole penetrates the first resin substrate, the central insulating layer, and the second resin substrate. Compared to conventional methods, the length of the through-hole is shortened, resulting in stable signal transmission within the through-hole. Additionally, by using a multilayer core substrate, there are no limitations on the thickness or other properties of the embedded components, enabling wider application. Attached Figure Description

[0008] Figure 1 This is a schematic cross-sectional view of the wiring substrate of an embodiment.

[0009] Figure 2 yes Figure 1 Enlarged view of Part II.

[0010] Figure 3A This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0011] Figure 3B This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0012] Figure 3C This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0013] Figure 3D This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0014] Figure 3E This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0015] Figure 3F This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0016] Figure 3G This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0017] Figure 3H This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0018] Figure 3I This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0019] Figure 3JThis is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0020] Figure 3K This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0021] Figure 4 This is a schematic cross-sectional view of the wiring substrate modified in Example 1.

[0022] Figure 5A This is a cross-sectional view schematically illustrating the manufacturing method of the wiring substrate of modified Example 2.

[0023] Figure 5B This is a cross-sectional view schematically illustrating the manufacturing method of the wiring substrate of modified Example 2.

[0024] Figure 5C This is a cross-sectional view schematically illustrating the manufacturing method of the wiring substrate of modified Example 2.

[0025] Figure 5D This is a cross-sectional view schematically illustrating the manufacturing method of the wiring substrate of modified Example 2.

[0026] Label Explanation

[0027] 1: Wiring substrate; 10: Central insulating layer; 20: First resin substrate; 21: First inner conductor layer; 22: First inner conductor layer; 23: First cover conductor; 24: First component placement conductor layer; 25: First opening; 30: Second resin substrate; 31: Second inner conductor layer; 32: Second inner conductor layer; 33: Second cover conductor; 34: Second component placement conductor layer; 35: Second opening; 40: First outer insulating layer; 41: First surface conductor layer; 42: First via conductor; 43: First connection conductor; 50: Second outer insulating layer; 51: Second surface conductor layer; 52: Second via conductor; 53: Second connecting conductor; 60: Through hole; 60a: Through hole; 61: Inner wall conductor layer; 62: Filler; 70: First component; 71: First electrode surface; 72: First non-electrode surface; 73: First embedded resin; 80: Second component; 81: Second electrode surface; 82: Second non-electrode surface; 83: Second embedded resin; 90: Multilayer insulating layer; 91: Through hole conductor; 100: Multilayer core substrate; 110: First stacked layer; 120: Second stacked layer. Detailed Implementation

[0028] [Wiring substrate 1 in the embodiment]

[0029] Figure 1 This is a cross-sectional view showing the wiring substrate 1 according to an embodiment. Figure 1As shown, the wiring substrate 1 has a multilayer core substrate 100, a first stacked layer 110, and a second stacked layer 120. The first stacked layer 110 is formed on a first surface 100F of the multilayer core substrate 100. The second stacked layer 120 is formed on a second surface 100S of the multilayer core substrate 100.

[0030] The first laminate 110 is formed by alternately forming an insulating layer 111 and a conductor layer 112 on a first surface 100F of the multilayer core substrate 100. The second laminate 120 is formed by alternately forming an insulating layer 121 and a conductor layer 122 on a second surface 100S of the multilayer core substrate 100. Figure 1 In the example, the first stacked layer 110 consists of two insulating layers 111 and two conductive layers 112, and the second stacked layer 120 consists of two insulating layers 121 and two conductive layers 122. Each insulating layer 111 has a via conductor 113 connecting the conductive layer on the insulating layer 111 to the conductive layer below it. Each insulating layer 121 has a via conductor 123 connecting the conductive layer on the insulating layer 121 to the conductive layer below it.

[0031] The multilayer core substrate 100 includes multiple insulating layers 90, through-hole conductors 91, surface conductor layers (first surface conductor layer 41 and second surface conductor layer 51), and connecting conductors (first connecting conductor 43 and second connecting conductor 53). Components (first component 70 and second component 80) are disposed within the multilayer core substrate 100. The multilayer insulating layer 90 includes a central insulating layer 10, a first resin substrate 20, a second resin substrate 30, a first outer insulating layer 40, and a second outer insulating layer 50. The first resin substrate 20 is formed on a first surface 10F of the central insulating layer 10. The second resin substrate 30 is formed on a second surface 10S of the central insulating layer 10. The central insulating layer 10 is sandwiched between the first resin substrate 20 and the second resin substrate 30.

[0032] A first internal conductor layer 21 is formed on a first surface of the first resin substrate 20, and a first internal conductor layer 22 is formed on a second surface of the first resin substrate 20. In other words, the first internal conductor layer 22 is formed on the side of the central insulating layer 10, and the first internal conductor layer 21 is formed on the opposite side of the central insulating layer 10. The first internal conductor layer 21 also includes a first cover conductor 23. The first internal conductor layer 22 also includes a first component placement conductor layer 24. A second internal conductor layer 31 is formed on a first surface of the second resin substrate 30, and a second internal conductor layer 32 is formed on a second surface of the second resin substrate 30. In other words, the second internal conductor layer 32 is formed on the side of the central insulating layer 10, and the second internal conductor layer 31 is formed on the opposite side of the central insulating layer 10. The second internal conductor layer 31 also includes a second cover conductor 33. The second internal conductor layer 32 also includes a second component placement conductor layer 34. Furthermore, the first internal conductor layer 22 and the second internal conductor layer 32 may be embedded in the central insulating layer 10, or they may not be embedded in the central insulating layer 10.

[0033] A first opening 25 is formed through the first resin substrate 20. The first opening 25 exposes the conductor layer 24 for first component placement. A first component 70 is housed within the first opening 25. The first component 70 is an electronic component. The first component 70 is, for example, a capacitor. The first component 70 can also be an inductor, IVR, etc. Furthermore, as another embodiment, multiple first components 70 can be housed within the first opening 25. The first component 70 has an electrode surface 71 and a first non-electrode surface 72 opposite to the first electrode surface 71. The first non-electrode surface 72 of the first component 70 is disposed on the conductor layer 24 for first component placement exposed from the first opening 25. That is, the first non-electrode surface 72 of the first component 70 is disposed on the first surface 10F of the central insulating layer 10 exposed from the first opening 25. The first electrode surface 71 of the first component 70 faces the first outer insulating layer 40. The first electrode surface 71 is connected to the first connecting conductor 43 of the first outer insulating layer 40. The gap between the inner surface of the first opening 25 and the first component 70 is filled by the first embedded resin 73. The first embedded resin 73 is, for example, a thermosetting resin. The first embedded resin 73 can also be a photocurable resin. The first embedded resin 73 is disposed separately from the first resin substrate 20 and the first outer insulating layer 40.

[0034] A second opening 35 is formed through the second resin substrate 30. The second opening 35 exposes the conductor layer 34 for mounting the second component. The second component 80 is housed within the second opening 35. The second component 80 is an electronic component. The second component 80 is identical to the first component 70. Alternatively, as another embodiment, multiple second components 80 may be housed within the second opening 35. The second component 80 has a second electrode surface 81 and a second non-electrode surface 82 opposite to the second electrode surface 81. The second non-electrode surface 82 of the second component 80 is disposed on the conductor layer 34 for mounting the second component exposed from the second opening 35. That is, the second non-electrode surface 82 of the second component 80 is disposed on the second surface 10S of the central insulating layer 10 exposed from the second opening 35. The second electrode surface 81 of the second component 80 faces the second outer insulating layer 50. The second electrode surface 81 is connected to the second connecting conductor 53 of the second outer insulating layer 50. The gap between the inner surface of the second opening 35 and the second component 80 is filled by the second embedded resin 83. The second embedded resin 83 is, for example, a thermosetting resin. The second embedded resin 83 can also be a photocurable resin. The second embedded resin 83 is separately disposed from the second resin substrate 30 and the second outer insulating layer 50.

[0035] In this embodiment, the second opening 35 and the second component 80 are disposed at a position that overlaps with the first opening 25 and the first component 70 in the thickness direction of the wiring substrate 1. Alternatively, as another embodiment, the second opening 35 and the second component 80 may also be disposed at a position that does not overlap with the first opening 25 and the first component 70 in the thickness direction of the wiring substrate 1.

[0036] A first outer insulating layer 40 is formed on the first resin substrate 20. A first surface conductor layer 41 is formed on the first surface of the first outer insulating layer 40. A first connecting conductor 43 is formed within the first outer insulating layer 40. The first connecting conductor 43 is formed within a hole 40b that penetrates the first outer insulating layer 40 and exposes the first electrode surface 71 of the first component 70. The first connecting conductor 43 connects the first surface conductor layer 41 to the first electrode surface 71 of the first component 70.

[0037] A second outer insulating layer 50 is formed on the second resin substrate 30. A second surface conductor layer 51 is formed on the second surface of the second outer insulating layer 50. A second connecting conductor 53 is formed within the second outer insulating layer 50. The second connecting conductor 53 is formed within a hole 50b that penetrates the second outer insulating layer 50 and exposes the second electrode surface 81 of the second component 80. The second connecting conductor 53 connects the second surface conductor layer 51 to the second electrode surface 81 of the second component 80.

[0038] In the wiring substrate 1, the first inner conductor layers 21 and 22, the first surface conductor layer 41, the second inner conductor layers 31 and 32, the second surface conductor layer 51, the conductor layer 112 in the first stacked layer 110, and the conductor layer 122 in the second stacked layer 120 can have arbitrary conductor patterns. These conductor layers in... Figure 1 For ease of observation, it is simplified to have a single-layer structure, but for details please refer to [reference needed]. Figure 2 As will be described later, it can also have a multi-layered structure with two or more layers.

[0039] Internal conductor layers, serving as the first internal conductor layer 21 and the second internal conductor layer 31, are formed in the through-holes 60 of the multilayer core substrate 100. By forming internal conductor layers in the through-holes 60, signal transmission through the multilayer core substrate 100 is stable. At this time, the size, thickness, and material of the internal conductor layers are not limited. The internal conductor layers can be formed from the first internal conductor layer 21 and the second internal conductor layer 31, or either the first internal conductor layer 21 or the second internal conductor layer 31. Forming internal conductor layers from the first internal conductor layer 21 and the second internal conductor layer 31 easily ensures stability during signal transmission. Furthermore, forming the first internal conductor layer 21 and the second internal conductor layer 31 ensures the strength of the multilayer core substrate 100.

[0040] Furthermore, in the description of the wiring substrate 1 in this embodiment, the side of the wiring substrate 1 that is away from the central insulating layer 10 in the thickness direction is also referred to as the "upper side" or "above," or simply "upper," and the side that is close to the central insulating layer 10 is also referred to as the "lower side" or "below," or simply "below." In each conductor layer and each insulating layer, the surface facing the side opposite to the central insulating layer 10 is also referred to as the "upper surface," and the surface facing the central insulating layer 10 is also referred to as the "lower surface." Therefore, for example, in the description of the first stacked layer 110 and the second stacked layer 120, the side away from the multilayer core substrate 100 is also referred to as the "upper side," "above," or simply "upper," and the side close to the multilayer core substrate 100 is also referred to as the "lower side," "below," or simply "below." In addition, in the description of the wiring substrate 1 in this embodiment, each conductor layer and each insulating layer is sometimes also referred to as the "first surface" or the "second surface." Here, the first surface is used as the upper surface only for ease of explanation; it can be either the upper surface or the lower surface.

[0041] The insulating layer and resin substrate constituting the multilayer insulating layer 90 of the present invention are formed by impregnating a core material, which serves as a reinforcing material, with an insulating resin and then curing it. As the insulating resin, epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin, etc., can be used. Reinforcing materials include glass fiber, aramid fiber, glass nonwoven fabric, aramid nonwoven fabric, etc. By including a core material in the insulating layer and resin substrate, a wiring substrate 1 with high rigidity and suppressed warping can be provided. On the other hand, the insulating layers 111 and 121 used as laminates are preferably formed of an insulating resin that does not contain a core material. This is because an insulating resin that does not contain a core material is suitable for via formation. Furthermore, each insulating layer may also contain inorganic fillers such as silica.

[0042] The through-hole conductor 91 is composed of a through-hole 60, a first through-hole conductor 42, and a second through-hole conductor 52. The through-hole conductor 91 connects the first surface conductor layer 41 and the second surface conductor layer 51.

[0043] The through-hole 60 is composed of an inner wall conductor layer 61 formed on the inner wall of the through-hole 60a and a filler 62 filling the through-hole 60a. The inner wall conductor layer 61 is formed on the inner wall of the through-hole 60a that penetrates the first resin substrate 20, the central insulating layer 10, and the second resin substrate 30. The filler 62 fills the through-hole 60a. A first cover conductor 23 connected to the inner wall conductor layer 61 is formed at the end of the through-hole 60 on the first resin substrate 20 side. The first cover conductor 23 covers the end of the filler 62 on the first resin substrate 20 side. A second cover conductor 33 connected to the inner wall conductor layer 61 is formed at the end of the through-hole 60 on the second resin substrate 30 side. The second cover conductor 33 covers the end of the filler 62 on the second resin substrate 30 side.

[0044] A first via conductor 42 is formed in a hole 40a that penetrates the first outer insulating layer 40 and exposes the first cover conductor 23. The first via conductor 42 connects the first surface conductor layer 41 and the first cover conductor 23. A second via conductor 52 is formed in a hole 50a that penetrates the second outer insulating layer 50 and exposes the second cover conductor 33. The second via conductor 52 connects the second surface conductor layer 51 and the second cover conductor 33.

[0045] A first stacked layer 110 and a second stacked layer 120 are formed on a multilayer core substrate 100 of the wiring substrate 1. The first stacked layer 110 is formed on a first surface 100F of the multilayer core substrate 100. The second stacked layer 120 is formed on a second surface 100S of the multilayer core substrate 100. In the illustrated example, both the first stacked layer 110 and the second stacked layer 120 include two conductor layers and two insulating layers, but they may also include three or more conductor layers and three or more insulating layers, or they may each include only one conductor layer and one insulating layer.

[0046] The surface-side conductor layer 112 in the first stacked layer 110, the outermost layer of the wiring substrate 1, and the surface-side conductor layer 122 in the second stacked layer 120, the outermost layer of the wiring substrate 1, include connecting pads 112a and 122a for mounting external electronic components, motherboards (not shown), etc. When mounting electronic components, bumps (not shown) made of any metal such as solder, copper, or tin are formed on the connecting pads 112a and 122a.

[0047] Reference Figure 2 The structure of the conductors contained in the wiring substrate 1 is described in detail. Figure 2 Show Figure 1 Enlarged view of Part II.

[0048] like Figure 2 As shown, the first internal conductor layer 22 is formed of a metal foil 22a formed on the lower surface (second surface) of the first resin substrate 20. A first component placement conductor layer 24 is formed on the first internal conductor layer 22. The second internal conductor layer 32 is formed of a metal foil 32a formed on the upper surface (first surface) of the second resin substrate 30. A second component placement conductor layer 34 is formed on the second internal conductor layer 32. The first internal conductor layer 22 and the second internal conductor layer 32 have a single-layer structure composed of metal foils 22a and 32a, but they can also be configured as a multi-layer structure with two or more layers. Furthermore, the type of metal in the metal foils 22a and 32a is not particularly limited, but a metal with copper as the main component is preferred.

[0049] Here, the conductor layer of the present invention is formed by any combination of a metal foil layer, a seed layer, and an electroplated layer. The metal foil layer is a conductor layer in which a pattern is formed starting from a metal foil formed on an insulating layer. Furthermore, the type of metal in the metal foil is not particularly limited, but a metal with copper as its main component is preferred. The seed layer is a conductor layer in which a seed film, such as a chemically plated film or a sputtered film, is formed on the entire surface of the substrate and a pattern is formed. Furthermore, the type of metal in the seed film is not particularly limited, but a metal with copper, nickel, or titanium as its main components is preferred. The electroplated layer is a conductor layer in which a pattern is formed using a resist based on the seed film formed on the substrate, and a pattern is formed using an electroplated film deposited on the non-formation areas of the resist. Furthermore, the type of metal in the electroplated film is not particularly limited, but a metal with copper as its main component is preferred.

[0050] On the other hand, the first internal conductor layer 21 is formed by a metal foil layer 21a, a seed layer 21b on the metal foil layer 21a, an electroplated layer 21c on the seed layer 21b, a seed layer 21d on the electroplated layer 21c, and an electroplated layer 21e on the seed layer 21d, all formed on the upper surface (first surface) of the first resin substrate 20. The first internal conductor layer 21 has a five-layer structure consisting of a metal foil layer 21a, a seed layer 21b, an electroplated layer 21c, a seed layer 21d, and an electroplated layer 21e. In addition, the first cover conductor 23 is formed by a seed layer 21d and an electroplated film 21e. Similarly, the second internal conductor layer 31 is formed by a metal foil layer 31a, a seed layer 31b on the metal foil layer 31a, an electroplated layer 31c on the seed layer 31b, a seed layer 31d on the electroplated layer 31c, and an electroplated layer 31e on the seed layer 31d, all formed on the upper surface (first surface) of the second resin substrate 30. The second inner conductor layer 31 has a five-layer structure consisting of a metal foil layer 31a, a seed layer 31b, an electroplated layer 31c, a seed layer 31d, and an electroplated layer 31e. Additionally, the second cover conductor 33 is formed from the seed layer 31d and the electroplated layer 31e.

[0051] The inner wall conductor layer 61 of the through-hole 60 is formed by a seed layer 61b and an electroplated film 61c formed on the inner wall surface of the through-hole 60a. The seed layer 61b is common to seed layers 21b and 31b and is formed simultaneously with them. The electroplated layer 61c is common to electroplated layers 21c and 31c and is formed simultaneously with them. The interior of the through-hole 60 is filled with a filler 62. The filler 62 is formed, for example, using an insulating material containing resins such as epoxy resin, acrylic resin, or phenolic resin. Alternatively, the filler 62 may be a cured conductive paste or conductive ink containing conductive particles such as silver particles. By filling the interior of the through-hole 60 with the filler 62, a via conductor can be formed directly above the through-hole 60. A first cap conductor 23 and a second cap conductor 33 are formed on the end face of the filler 62 in a manner that covers the end face of the filler 62.

[0052] The first surface conductor layer 41 is formed of a metal foil layer 41a, a seed layer 41b on the metal foil layer 41a, and an electroplated layer 41c on the seed layer 41b, all formed on the upper surface (first surface) of the first outer insulating layer 40. The first surface conductor layer 41 has a three-layer structure consisting of the metal foil layer 41a, the seed layer 41b, and the electroplated layer 41c. Similarly, the second surface conductor layer 51 is formed of a metal foil layer 51a, a seed layer 51b on the metal foil layer 51a, and an electroplated layer 51c on the seed layer 51b, all formed on the upper surface of the second outer insulating layer 50. The second surface conductor layer 51 has a three-layer structure consisting of the metal foil layer 51a, the seed layer 51b, and the electroplated layer 51c.

[0053] A first via conductor 42 is formed within a hole 40a that penetrates the first outer insulating layer 40 and exposes the first cover conductor 23. The first via conductor 42 is formed by a seed layer 41b formed on the inner wall surface of the hole 40a and the first cover conductor 23, and an electroplated layer 41c formed on the seed layer 41b and filling the hole 40a. The seed layer 41b and electroplated layer 41c forming the first via conductor 42 are common to the seed layer 41b and electroplated layer 41c forming the first surface conductor layer 41. The first surface conductor layer 41 and the first via conductor 42 are formed simultaneously. Similarly, a second via conductor 52 is formed within a hole 50a that penetrates the second outer insulating layer 50 and exposes the second cover conductor 33. The second via conductor 52 is formed by a seed layer 51b formed on the inner wall surface of the hole 50a and the second cover conductor 33, and an electroplated layer 51c formed on the seed layer 51b and filling the hole 50a. The seed layer 51b and electroplated layer 51c forming the second via conductor 52 are the same as the seed layer 51b and electroplated layer 51c forming the second surface conductor layer 51. The second surface conductor layer 51 and the second via conductor 52 are formed simultaneously.

[0054] The first connecting conductor 43 is formed within a hole 40b that penetrates the first outer insulating layer 40 and exposes the first electrode surface 71 of the first component 70. The first connecting conductor 43 is formed from a seed layer 41b formed on the inner wall surface of the hole 40b and the first electrode surface 71, and an electroplated layer 41c formed on the seed layer 41b and filling the hole 40b. The seed layer 41b and electroplated layer 41c forming the first connecting conductor 43 are common to the seed layer 41b and electroplated layer 41c forming the first surface conductor layer 41 and the first via conductor 42. The first surface conductor layer 41, the first via conductor 42, and the first connecting conductor 43 are formed simultaneously.

[0055] Similarly, the second connecting conductor 53 is formed within a hole 50b that penetrates the second outer insulating layer 50 and exposes the second electrode surface 81 of the second component 80. The second connecting conductor 53 is formed from a seed layer 51b formed on the inner wall surface of the hole 50b and the second electrode surface 81, and an electroplated layer 51c formed on the seed layer 51b and filling the hole 50b. The seed layer 51b and electroplated layer 51c forming the second connecting conductor 53 are common to the seed layer 51b and electroplated layer 51c forming the second surface conductor layer 51 and the second via conductor 52. The second surface conductor layer 51, the second via conductor 52, and the second connecting conductor 53 are formed simultaneously.

[0056] The conductor layers 112 and 122 in the first laminate 110 and the second laminate 120 are formed without using metal foil. The conductor layer 112 is formed by a seed layer 112b and an electroplated film 112c. Similarly, the conductor layer 122 is formed by a seed layer 122b and an electroplated layer 122c.

[0057] The via conductor 113 in the first stacked layer 110 is formed by a seed layer 112b and an electroplated layer 112c. The seed layer 112b and electroplated layer 112c of the via conductor 113 are common to the seed layer 112b and electroplated layer 112c of the conductor layer 112. Similarly, the via conductor 123 in the second stacked layer 120 is formed by a seed layer 122b and an electroplated layer 122c. The seed layer 122b and electroplated layer 122c of the via conductor 123 are common to the seed layer 122b and electroplated layer 122c of the conductor layer 122.

[0058] [Method for manufacturing wiring substrate 1 according to the embodiment]

[0059] Figures 3A to 3K A method for manufacturing the wiring substrate 1 according to an embodiment is shown. Figures 3A to 3K It is a sectional view. For example... Figure 3A As shown, a first resin substrate 20 is prepared to have a metal foil 21a formed on its upper surface (first surface) and a first internal conductor layer 22 formed on its lower surface (second surface). The first resin substrate 20 uses a double-sided copper-clad laminate with metal foils 21a and 22a formed on both sides of a resin substrate containing a core material as the starting material. For the metal foil 22a, a first internal conductor layer 22 with a desired conductor pattern is formed by a subtractive method such as etching using a mask depicting wiring. The first internal conductor layer 22 also includes a first component placement conductor layer 24. Similarly, a second resin substrate 30 is also prepared to have a metal foil 31a formed on its upper surface (first surface) and a second internal conductor layer 32 formed on its lower surface (second surface). The second internal conductor layer 32 also includes a second component placement conductor layer 34.

[0060] like Figure 3B As shown, a prepreg 10p and a second resin substrate 30 are configured to be cured with a first resin substrate 20 to form a central insulating layer 10. Specifically, the first resin substrate 20 is disposed on the first surface 10pF side of the prepreg 10p that forms the central insulating layer 10, and the second resin substrate 30 is disposed on the second surface 10pS side of the prepreg 10p. A first internal conductor layer 22 faces the first surface 10pF. A second internal conductor layer 32 faces the second surface 10pS.

[0061] The first resin substrate 20, the prepreg 10p, and the second resin substrate 30 are hot-pressed together. For example... Figure 3CAs shown, the prepreg 10p is cured to form a central insulating layer 10. A first internal conductor layer 22, after pressing, is embedded in the first surface 10F of the central insulating layer 10. A second internal conductor layer 32 is embedded in the second surface 10S of the central insulating layer 10. As a result, an intermediate substrate 2 comprising the central insulating layer 10, a first resin substrate 20, and a second resin substrate 30 is formed. During hot pressing, the pressure applied to the central portion in the pressing direction is concentrated in the prepreg 10p and absorbed, thereby ensuring good uniformity of its thickness. That is, the possibility of loss of parallelism between the first resin substrate 20 and the second resin substrate 30 is small, resulting in a multilayer core substrate 100 with good flatness.

[0062] For ease of explanation, the thickness of the first resin substrate 20 and the thickness of the second resin substrate 30 are the same, but the thicknesses of the first resin substrate 20 and the second resin substrate 30 can also be different. Specifically, the thickness of the first resin substrate 20 on which the first component 70 is disposed is less than the thickness of the second resin substrate 30 on which the second component 80 is disposed. This allows for the disposal of a thinner first component 70. Conversely, the thickness of the first resin substrate 20 on which the first component 70 is disposed is greater than the thickness of the second resin substrate 30 on which the second component 80 is disposed. This allows for the disposal of a thicker first component 70.

[0063] like Figure 3D As shown, a through-hole 60a is formed through the metal foil 21a, the first resin substrate 20, the first inner conductor layer 22, the central insulating layer 10, the second inner conductor layer 32, the second resin substrate 30, and the metal foil 31a. The through-hole 60a is formed, for example, by piercing with a cutting device such as a drill bit. The through-hole 60a can also be formed by laser irradiation.

[0064] like Figure 3E As shown, a seed layer 21b is formed on the metal foil layer 21a. A seed layer 61b is formed on the inner wall of the through hole 60a. A seed layer 31b is formed on the metal foil layer 31a. Seed layers 21b, 31b, and 61b are formed into seed films, for example, by chemical plating or sputtering. An electroplated film is formed using the seed film as a power supply layer. Electroplated films 21c, 31c, and 61c are formed on the seed film. Subsequently, an inner wall conductor layer 61 is formed by patterning, consisting of the seed layer 61b and the electroplated layer 61c.

[0065] The cavity of the through hole 60a is filled with a filler 62. For example, a resin such as epoxy resin, acrylic resin, or phenolic resin is injected from one or both ends of the through hole. The filler 62 can also be filled with a conductive paste containing conductive particles such as silver particles instead of an insulating resin such as epoxy resin to fill the through hole 60a. The insulating resin such as epoxy resin or the conductive paste used for the filler 62 is cured by heating or the like as needed to form the filler 62. The through hole 60 is formed in the through hole 60a by an inner wall conductive layer 61 and the filler 62. The end faces of the cured filler 62 can be ground as needed by any method such as chemical grinding or mechanical grinding. By this grinding, the two end faces of the filler 62 are preferably substantially flush with the surfaces of the electroplated layers 21c and 31c, respectively.

[0066] Furthermore, seed layers 21d, 31d, and electroplated layers 21e, 31e are sequentially formed on electroplated layers 21c, 31c and filler 62. Seed layers 21d, 31d and electroplated layers 21e, 31e are formed, for example, by the same method as seed layers 21b, 31b and electroplated layers 21c, 31c. A five-layer structure of metal foil layer 21a, seed layer 21b, electroplated layer 21c, seed layer 21d, and electroplated layer 21e is formed on the first resin substrate 20. A five-layer structure of metal foil layer 31a, seed layer 31b, electroplated layer 31c, seed layer 31d, and electroplated layer 31e is formed on the second resin substrate 30. Then, as... Figure 3F As shown, a first inner conductor layer 21 and a second inner conductor layer 31 with desired conductor patterns are formed by a subtractive method such as etching using a mask depicting wiring. Simultaneously, a first cap conductor 23, consisting of a seed layer 21d and an electroplated layer 21e, is formed on the end of the filler 62 on the first resin substrate 20 side. A second cap conductor 33, consisting of a seed layer 31d and an electroplated layer 31e, is formed on the end of the filler 62 on the second resin substrate 30 side.

[0067] like Figure 3G As shown, a first opening 25 is formed through the first resin substrate 20 within the area where the first component 70 is housed. The first opening 25 is formed, for example, by laser irradiation. The laser removes the resin from the first resin substrate 20 but does not remove the conductor layer 24 for mounting the first component. Therefore, the conductor layer 24 for mounting the first component is exposed on the bottom surface of the first opening 25. Similarly, a second opening 35 is formed through the second resin substrate 30 within the area where the second component 80 is housed. The conductor layer 34 for mounting the second component is exposed on the bottom surface of the second opening 35.

[0068] like Figure 3HAs shown, a first component 70 is disposed within the first opening 25. The first non-electrode surface 72 of the first component 70 is disposed on the first component placement conductor layer 24 exposed from the first opening 25. At this time, the first component 70 is fixed to the first component placement conductor layer 24 by providing an adhesive layer between the first non-electrode surface 72 of the first component 70 and the first component placement conductor layer 24. The first electrode surface 71 of the first component 70 is on the same plane as the upper surface of the first resin substrate 20. Alternatively, the first electrode surface 71 of the first component 70 may be lower than the upper surface of the first resin substrate 20. Similarly, a second component 80 is disposed within the second opening 35. The first non-electrode surface 82 of the second component 80 is disposed on the second component placement conductor layer 34 exposed from the second opening 35. The second component 80 is fixed to the second component placement conductor layer 34 by providing an adhesive layer between the second non-electrode surface 82 of the second component 80 and the second component placement conductor layer 34. The second electrode surface 81 of the second component 80 is on the same plane as the upper surface of the second resin substrate 30. In addition, the second electrode surface 81 of the second component 80 may be lower than the upper surface of the second resin substrate 30.

[0069] like Figure 3I As shown, a first embedding resin 73 is filled in the gap between the inner surface of the first opening 25 of the first resin substrate 20 and the first component 70. Similarly, a second embedding resin 83 is filled in the gap between the inner surface of the second opening 35 of the second resin substrate 30 and the second component 80. The first embedding resin 73 and the second embedding resin 83 are preferably thermosetting resins or photocurable resins. The first embedding resin 73 and the second embedding resin 83 are cured. The first component 70 is fixed in the first opening 25. The second component 80 is fixed in the second opening 35.

[0070] like Figure 3J As shown, a first outer insulating layer 40 composed of prepreg 40p is disposed on the first inner conductor layer 21. At this time, a metal foil 41a is disposed on the first outer insulating layer 40. A second outer insulating layer 50 composed of prepreg 50p is disposed on the second inner conductor layer 31. The metal foil 51a is disposed on the second outer insulating layer 50. The metal foil 41a, the first outer insulating layer 40, the intermediate substrate 2, the second outer insulating layer 50, and the metal foil 51a are hot-pressed together. The prepreg 40p is cured to form the first outer insulating layer 40. The prepreg 50p is cured to form the second outer insulating layer 50.

[0071] In the first outer insulating layer 40, an insulating layer penetrating the metal foil 41a and the first outer insulating layer 40 is formed, exposing the first cover conductor 23. Also, an insulating layer penetrating the metal foil 41a and the first outer insulating layer 40 is formed, exposing the first electrode surface 71 of the first component 70. In the second outer insulating layer 50, an insulating layer penetrating the second outer insulating layer 50 is formed, exposing the second cover conductor 33. Also, an insulating layer penetrating the metal foil 51a and the second outer insulating layer 50 is formed, exposing the second electrode surface 81 of the second component 80. The openings of the holes are formed, for example, by a laser using carbon dioxide. Seed films are formed on the inner surfaces of the metal foil 41a, the hole 40a, and the hole 40b by chemical plating or sputtering. Additionally, seed films are formed on the inner surfaces of the metal foil 51a, the hole 50a, and the hole 50b. An electroplated film is formed on the seed film, which serves as the power supply layer. The electroplated film fills the holes 40a, 40b, 50a, and 50b. Then, as... Figure 3K As shown, a first surface conductor layer 41 composed of a seed layer 41b and an electroplated layer 41c, and a second surface conductor layer 51 composed of a seed layer 51b and an electroplated layer 51c, having a desired conductor pattern, are formed by a subtractive method such as etching using a mask depicting wiring. Simultaneously, a first via conductor 42, a first connecting conductor 43, a second via conductor 52, and a second connecting conductor 53 are formed. Alternatively, the first surface conductor layer 41, the first via conductor 42, the first connecting conductor 43, the second surface conductor layer 51, the second via conductor 52, and the second connecting conductor 53 can also be formed using a semi-additive process (MSAP) with metal foils 41a and 51a. A multilayer insulating layer 90 is formed, comprising a central insulating layer 10, a first resin substrate 20, a second resin substrate 30, a first outer insulating layer 40, and a second outer insulating layer 50. A through-hole conductor 91 comprising the first via conductor 42, a via 60, and the second via conductor 52 is formed. A multilayer core substrate 100 is formed, comprising a multilayer insulating layer 90, a first surface conductor layer 41, a second surface conductor layer 51, and a through-hole conductor 91.

[0072] Insulating layers 111 and 121 and conductor layers 112 and 122 are alternately formed on both sides of the multilayer core substrate 100. A first laminate 110 is formed on the first surface 100F of the multilayer core substrate 100. A second laminate 120 is formed on the second surface 100S. For example, a film-like insulating resin (e.g., epoxy resin) without reinforcing material is thermo-pressed onto the first surface 100F and the second surface 100S to form an insulating layer 111 on the first surface 100F side and an insulating layer 121 on the second surface 100S side of the two insulating layers 111. Through-holes are formed at the formation sites of the via conductors 113 or 123 of the insulating layers 111 and 121, for example, using a carbon dioxide laser. Seed films made of conductors such as copper are formed on the inner walls of the through-holes and on the surfaces of the insulating layers 111 and 121 by chemical plating or sputtering. A seed film is used as the power supply layer, and a resist with openings for forming conductor layers is formed. Electroplating is then performed through these openings to form an electroplated film. Conductor layers 112 and 122, consisting of the seed layer and the electroplated layer, as well as via conductors 113 and 123, are formed through resist stripping and etching. Specifically, a conductor layer 112 on the first side 100F and a conductor layer 122 on the second side 100S of the two conductor layers 122 are formed using a semi-additive process (SAP) without the use of metal foil. A via conductor 113 penetrating the insulating layer 111 on the first side 100F and a via conductor 123 penetrating the insulating layer 121 on the second side 100S are formed together with these conductor layers 112 and 122.

[0073] Furthermore, the insulating layers 111 and 121 on the surface side are formed using the same method as the insulating layers 111 on the first surface 100F side and 121 on the second surface 100S side. Additionally, the conductor layers 112 and 122 on the surface side are formed using the same method as the conductor layers 112 on the first surface 100F side and 122 on the second surface 100S side. Furthermore, the via conductors 113 and 123 penetrating the insulating layers 111 and 121 on the surface side are formed using the same method as the via conductor 113 penetrating the insulating layer 111 on the first surface 100F side and the via conductor 123 penetrating the insulating layer 121 on the second surface 100S side. Thus, the first stacked layer 110 and the second stacked layer 120 are formed. As a result, the wiring substrate 1 of the embodiment is obtained. Figure 1 ).

[0074] In the wiring substrate 1 of this embodiment, a first opening 25 housing the first component 70 penetrates the first resin substrate 20. A second opening 35 housing the second component 80 penetrates the second resin substrate 30. The first opening 25 and the second opening 35 do not penetrate the multilayer core substrate 100. The number of first embedded resins 73 used to fill the gap between the inner surface of the first opening 25 and the first component 70, and the number of second embedded resins 83 used to fill the gap between the inner surface of the second opening 35 and the second component 80, can be reduced. Furthermore, in the wiring substrate 1 of this embodiment, a through-hole 60 penetrates the first resin substrate 20, the central insulating layer 10, and the second resin substrate 30. The length of the through-hole 60 is shorter than that of conventional wiring substrates. This ensures stability during signal transmission.

[0075] [Modified Example 1]

[0076] Figure 4 This is a cross-sectional view showing the wiring substrate 1 of the modified Example 1. Figure 4 As shown, in Modified Example 1, the gap between the inner surface of the first opening 25 and the first component 70 is filled by a portion of the first outer insulating layer 40. The embedding resin filling the gap between the inner surface of the first opening 25 and the first component 70 is a portion of the first outer insulating layer 40. Similarly, the gap between the inner surface of the second opening 35 and the second component 80 is filled by a portion of the second outer insulating layer 50. The embedding resin filling the gap between the inner surface of the second opening 35 and the second component 80 is a portion of the second outer insulating layer 50.

[0077] The manufacturing method of the wiring substrate 1 in Modified Example 1 is substantially the same as that in the embodiment. However, in Modified Example 1, as... Figure 3HAs shown, after the first component 70 is disposed in the first opening 25 and the second component 80 is disposed in the second opening 35, a prepreg 40p, which becomes the first outer insulating layer 40, is disposed on the first inner conductor layer 21. A metal foil 41a is disposed on the prepreg 40p. A prepreg 50p, which becomes the second outer insulating layer 50, is disposed on the second inner conductor layer 31. A metal foil 51a is disposed on the prepreg 50p. The metal foil 41a, the prepreg 40p, the intermediate substrate 2, the prepreg 50p, and the metal foil 51a are hot-pressed together. At this time, a portion of the prepreg 40p enters and fills the gap between the inner surface of the first opening 25 and the first component 70. A portion of the prepreg 50p enters and fills the gap between the inner surface of the second opening 35 and the second component 80. The prepreg 40p is cured to form the first outer insulating layer 40. The prepreg 50p is cured to form the second outer insulating layer 50. The gap between the inner surface of the first opening 25 and the first component 70 is filled by a portion of the first outer insulating layer 40. The first component 70 is fixed within the first opening 25. The gap between the inner surface of the second opening 35 and the second component 80 is filled by a portion of the second outer insulating layer 50. The second component 80 is fixed within the second opening 35. Then, the first surface conductor layer 41, the first via conductor 42, the first connecting conductor 43, the second surface conductor layer 51, the second via conductor 52, and the second connecting conductor 53 are formed using the same method as in the embodiment. The manufacturing process is then the same as in the embodiment. A multilayer insulating layer 90 is formed. A via conductor 91 including the first via conductor 42, the through-hole 60, and the second via conductor 52 is formed. A multilayer core substrate 100 including the multilayer insulating layer 90, the first surface conductor layer 41, the second surface conductor layer 51, and the through-hole conductor 91 is formed. A first stacked layer 110 and a second stacked layer 120 are formed. The wiring substrate 1 of Modified Example 1 is obtained. Figure 4 ).

[0078] [Modified Example 2]

[0079] The wiring substrate 1 in Modified Example 2 is the same as the wiring substrate 1 in Embodiment 1. In Modified Example 2, the manufacturing method of the wiring substrate 1 differs from that in Embodiment 1. In Modified Example 2, during manufacturing, substrate 2a (see...) Figure 5D Previously, the first component 70 and the second component 80 were configured. Regarding the change in Example 2, Figures 5A to 5D The manufacturing method of the wiring substrate 1 of the modified Example 2 is shown. Figures 5A to 5D It is a sectional view.

[0080] like Figure 5AAs shown, a first resin substrate 20 is prepared to have a metal foil 21a formed on its upper surface (first surface) and a first internal conductor layer 22 formed on its lower surface (second surface). Similarly, a second resin substrate 30 is also prepared to have a metal foil 31a formed on its upper surface (first surface) and a second internal conductor layer 32 formed on its lower surface (second surface).

[0081] like Figure 5B As shown, the metal foil 21a of the area housing the first component 70 on the first resin substrate 20 is removed by etching or the like. Similarly, the metal foil 31a of the area housing the second component 80 on the second resin substrate 30 is removed by etching or the like. A first opening 25 penetrating the first resin substrate 20 is formed within the area housing the first component 70 on the first resin substrate 20. The first opening 25 is formed, for example, by laser irradiation. The laser removes the resin from the first resin substrate 20, but does not remove the component placement conductor layer 24. Therefore, the bottom surface of the first opening 25 exposes the first component placement conductor layer 24. Similarly, a second opening 35 penetrating the second resin substrate 30 is formed within the area housing the second component 80 on the second resin substrate 30. The bottom surface of the second opening 35 exposes the second component placement conductor layer 34. The first component 70 is disposed within the first opening 25. The first non-electrode surface 72 of the first component 70 is disposed on the first component placement conductor layer 24 exposed from the first opening 25. At this time, the first component 70 is fixed to the first component placement conductor layer 24 by providing an adhesive layer between the first non-electrode surface 72 of the first component 70 and the first component placement conductor layer 24. The first electrode surface 71 of the first component 70 is on the same plane as the upper surface of the first resin substrate 20. Alternatively, the first electrode surface 71 of the first component 70 may be lower than the upper surface of the first resin substrate 20. Similarly, the second component 80 is disposed in the second opening 35. The first non-electrode surface 82 of the second component 80 is disposed on the second component placement conductor layer 34 exposed from the second opening 35. The second component 80 is fixed to the second component placement conductor layer 34 by providing an adhesive layer between the second non-electrode surface 82 of the second component 80 and the second component placement conductor layer 34. The second electrode surface 81 of the second component 80 is on the same plane as the upper surface of the second resin substrate 30. Alternatively, the second electrode surface 81 of the second component 80 may be lower than the upper surface of the second resin substrate 30.

[0082] Then, a first embedding resin 73 is filled into the gap between the first opening 25 of the first resin substrate 20 and the first component 70. Similarly, a second embedding resin 83 is filled into the gap between the second opening 35 of the second resin substrate 30 and the second component 80. The first embedding resin 73 and the second embedding resin 83 are preferably thermosetting resins or photocurable resins. The first embedding resin 73 and the second embedding resin 83 are cured. The first component 70 is fixed in the first opening 25. The second component 80 is fixed in the second opening 35.

[0083] like Figure 5C As shown, a prepreg 10p and a second resin substrate 30 are configured to be cured with a first resin substrate 20 to form a central insulating layer 10. Specifically, the first resin substrate 20, on the first surface 10pF side of the prepreg 10p that forms the central insulating layer 10, houses a first component 70, and the second resin substrate 30, on the second surface 10pS side of the prepreg 10p, houses a second component 80. A first internal conductor layer 22 faces the first surface 10pF. A second internal conductor layer 32 faces the second surface 10pS.

[0084] like Figure 5D As shown, a first resin substrate 20, a prepreg 10p, and a second resin substrate 30 are hot-pressed together. The prepreg 10p is cured to form a central insulating layer 10. A first internal conductor layer 22, after pressing, is embedded in the first surface 10F of the central insulating layer 10. A second internal conductor layer 32 is embedded in the second surface 10S of the central insulating layer 10. As a result, an intermediate substrate 2a comprising the central insulating layer 10, the first resin substrate 20, and the second resin substrate 30 is formed. During the hot-pressing process, the pressure applied to the central portion in the pressing direction is concentrated in the prepreg 10p and absorbed, thereby ensuring good uniformity of its thickness. That is, the possibility of loss of parallelism between the first resin substrate 20 and the second resin substrate 30 is small, and a multilayer core substrate 100 with good flatness can be obtained.

[0085] Subsequently, a through-hole 60 is formed in the intermediate substrate 2a using the same method as in the embodiment. A first inner conductor layer 21 and a second inner conductor layer 31 with desired conductor patterns are formed. A first cover conductor 23 and a second cover conductor 33 are formed (see reference). Figure 3I ).

[0086] Subsequently, a first outer insulating layer 40 and a second outer insulating layer 50 are formed in the same manner as in the embodiment (see reference). Figure 3J A first surface conductor layer 41, a first via conductor 42, a first connecting conductor 43, a second surface conductor layer 51, a second via conductor 52, and a second connecting conductor 53 are formed (see reference). Figure 3KA multilayer insulating layer 90 is formed, comprising a central insulating layer 10, a first resin substrate 20, a second resin substrate 30, a first outer insulating layer 40, and a second outer insulating layer 50. A through-hole conductor 91 is formed, comprising a first via conductor 42, a through-hole 60, and a second via conductor 52. A multilayer core substrate 100 is formed, comprising the multilayer insulating layer 90, a first surface conductor layer 41, a second surface conductor layer 51, and the through-hole conductor 91.

[0087] A first layer 110 is formed on a first surface 100F of a multilayer core substrate 100. A second layer 120 is formed on a second surface 100S. As a result, the wiring substrate 1 of the embodiment is obtained. Figure 1 ).

Claims

1. A wiring substrate having a multilayer core substrate and a laminate formed of an insulating layer and a conductor layer on the multilayer core substrate, wherein, The multilayer core substrate includes multiple insulating layers, through-hole conductors, a first surface conductor layer, a second surface conductor layer, a first connecting conductor, and a second connecting conductor. The multilayer core substrate is configured with components. The multilayer insulating layer consists of a central insulating layer, a first resin substrate, a second resin substrate, a first outer insulating layer, and a second outer insulating layer. The first resin substrate is formed on the first surface of the central insulating layer, the first outer insulating layer is formed on the first resin substrate, and the first surface conductor layer is formed on the first outer insulating layer. A second resin substrate is formed on the second side of the central insulating layer, a second outer insulating layer is formed on the second resin substrate, and a second surface conductor layer is formed on the second outer insulating layer. The via conductor is composed of a via, a first via conductor, and a second via conductor. The through-hole is a hole that passes through the first resin substrate, the central insulating layer, and the second resin substrate, and an inner wall conductor layer is formed on the inner wall of the hole. A first cover conductor is formed on the first resin substrate, and a second cover conductor is formed on the second resin substrate. The first via conductor is formed in a hole that penetrates the first outer insulating layer and exposes the first cover conductor, connecting the first surface conductor layer and the first cover conductor. The second via conductor is formed in a hole that penetrates the second outer insulating layer and exposes the second cover conductor, connecting the second surface conductor layer and the second cover conductor. The component includes a first component and a second component, wherein the first component is composed of a first electrode surface and a first non-electrode surface opposite to the first electrode surface. The second component is composed of a second electrode surface and a second non-electrode surface on the opposite side of the second electrode surface. A first opening penetrating the first resin substrate is formed, the first non-electrode surface of the first component is disposed on the first surface of the central insulating layer exposed from the first opening, and the first electrode surface is connected by the first connecting conductor of the first outer insulating layer. A second opening is formed through the second resin substrate, the second non-electrode surface of the second component is disposed on the second surface of the central insulating layer exposed from the second opening, and the second electrode surface is connected by the second connecting conductor of the second outer insulating layer.

2. The wiring substrate according to claim 1, wherein, The first electrode surface of the first component and the end of the through hole on the first resin substrate side are located on the same surface. The second electrode surface of the second component is located on the same surface as the end of the second resin substrate side of the through hole.

3. The wiring substrate according to claim 1, wherein, The gap between the inner surface of the first opening and the first component is filled with a first embedded resin. The gap between the inner surface of the second opening and the second component is filled with a second embedded resin.

4. The wiring substrate according to claim 3, wherein, The first embedded resin is part of the first outer insulating layer. The second embedded resin is part of the second outer insulating layer.

5. The wiring substrate according to claim 1, wherein, The interior of the through hole is filled with a resin-containing filler.

6. The wiring substrate according to claim 1, wherein, The central insulating layer, the first resin substrate, the second resin substrate, the first outer insulating layer, and the second outer insulating layer comprise a core material.

7. The wiring substrate according to claim 1, wherein, An internal conductor layer is formed in the through-hole of the multilayer core substrate.

8. The wiring substrate according to claim 7, wherein, The inner conductor layer is a first inner conductor layer and a second inner conductor layer. The first internal conductor layer is formed on the central insulating layer side of the first resin substrate and / or the second internal conductor layer is formed on the central insulating layer side of the second resin substrate.

9. The wiring substrate according to claim 8, wherein, The first inner conductor layer or the second inner conductor layer is embedded in the central insulating layer.

10. The wiring substrate according to claim 8, wherein, The first inner conductor layer has a first component configuration conductor layer corresponding to the range in which the first component is configured. The second inner conductor layer has a second component configuration conductor layer corresponding to the range in which the second component is configured.

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