Formation method of semiconductor structure and intermediate structure body
By controlling the etching depth through a step-by-step etching process, the problem of excessive etching of the floating gate layer during the etching process was solved, the active region was protected, and the quality of the semiconductor structure and the performance of the memory cell were improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-12
- Publication Date
- 2026-03-13
AI Technical Summary
In semiconductor manufacturing, the etching process can easily lead to over-etching of the floating gate layer, damaging the underlying active region and tunnel oxide layer, resulting in increased leakage current, decreased data retention capability, and device failure.
A two-stage etching process is employed. First, an anti-reflective layer is used as a mask to remove the initial floating gate layer in the uncovered area, forming a grid-like intermediate floating gate structure. Then, the anti-reflective layer between adjacent control gate structures is removed, precisely controlling the etching depth and avoiding the risk of over-etching.
It effectively protects the underlying active area from damage, ensures the integrity of the floating gate structure and good sidewall morphology, and improves product yield and memory cell performance stability.
Smart Images
Figure CN121665564A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure and an intermediate structure. Background Technology
[0002] In semiconductor manufacturing processes, floating-gate flash memory, as a mainstream non-volatile memory, is widely used in embedded systems, IoT devices, and memory chips due to its long lifespan, high reliability, and reprogrammable and erasable characteristics.
[0003] To improve the electric field control accuracy and charge retention capability of memory devices, the split-gate structure has emerged and gradually become the mainstream technology for high-capacity NOR Flash. By separating the control gate and the floating gate, split-gate optimizes the insulation characteristics between cells, significantly reduces crosstalk, and improves programming efficiency.
[0004] In the manufacturing process of multi-gate flash memory, deep trench etching is a crucial step in forming the isolation structure and floating gate, but its process stability directly affects the device's performance and yield. The current core problem is that the etching process can easily lead to over-etching of the floating gate layer, thereby damaging the underlying active region and tunnel oxide layer. This damage can cause increased leakage current, decreased data retention, and even device failure. Therefore, providing a technical solution to precisely control the etching depth and improve the quality of the semiconductor structure has become an urgent technical problem to be solved. Summary of the Invention
[0005] In view of this, embodiments of the present invention provide a method for forming a semiconductor structure and an intermediate structure, which can improve the quality of the semiconductor structure.
[0006] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: forming a substrate having mutually spaced and protruding control gate structures on the substrate, with recesses between adjacent control gate structures; forming a conformal-covered initial floating gate layer on the substrate; spin-coating an initial anti-reflective layer and an initial hard mask layer on the surface of the initial floating gate layer, wherein the initial anti-reflective layer has fluidity such that the thickness of the initial anti-reflective layer between adjacent control gate structures is greater than the thickness of the initial anti-reflective layer on the protruding control gate structures; and etching the initial anti-reflective layer at intervals along the extension direction of the control gate structures. A hard mask layer and an initial anti-reflective layer are used to obtain a mesh-like intermediate anti-reflective layer and a strip-like hard mask layer. The intermediate anti-reflective layer retains a portion of the initial anti-reflective layer located between adjacent control gate structures. Using the hard mask layer as a mask, a first floating gate etching process is used to remove the initial floating gate layer that does not cover the intermediate anti-reflective layer to obtain a mesh-like intermediate floating gate layer. The intermediate anti-reflective layer located between adjacent control gate structures is then removed. Using the remaining anti-reflective layer as a mask, a second floating gate etching process is used to remove the remaining intermediate floating gate layer that does not cover the anti-reflective layer to obtain a floating gate layer. Optionally, the step of forming the initial floating gate layer includes: providing a first active region and a second active region, wherein the first active region and the second active region are mutually perpendicular grid structures; and forming a conformal covering initial floating gate layer above the first active region and the second active region.
[0007] Optionally, the step of forming the initial anti-reflection layer further includes: forming a low-temperature oxide layer covering the initial anti-reflection layer as the initial hard mask layer; forming a photoresist layer covering the low-temperature oxide layer, and patterning the photoresist layer to expose the low-temperature oxide layer except above the first active region.
[0008] Optionally, the step of intermittently etching the initial anti-reflection layer includes: etching the low-temperature oxide layer and the initial anti-reflection layer, retaining the low-temperature oxide layer and the initial anti-reflection layer located above the first active region, and retaining a portion of the initial anti-reflection layer located above the second active region.
[0009] Optionally, one or more of the following conditions must be met: the material of the low-temperature oxide layer includes silicon dioxide; the low-temperature oxide layer is formed by chemical vapor deposition; the gas used to etch the anti-reflective layer includes chlorine and oxygen; the gas used to etch the initial floating gate layer includes hydrogen bromide and oxygen; and the gas used to etch the low-temperature oxide layer includes carbon tetrafluoride.
[0010] Optionally, the step of forming the control gate structure includes: forming an isolation layer to fill the mesh structure of the first active region and the second active region; forming an initial control gate, the initial control gate covering the first active region and the second active region, and the isolation layer; removing the initial control gate located above the second active region to expose the second active region and part of the isolation layer, thereby obtaining the control gate structure; forming a dielectric stack, the dielectric stack conformally covering the control gate structure, the second active region, and part of the isolation layer; wherein the dielectric stack is a structure of a double silicon oxide layer sandwiching a silicon nitride layer, and the silicon nitride layer covers the sidewall of the control gate.
[0011] Optionally, the material of the antireflective layer before spin coating is a liquid composition comprising: an organic solvent, serving as a dissolution carrier and providing flowability; a film-forming resin, dissolved in the organic solvent, for forming the main structure of the thin film; a light absorber, uniformly dispersed in the organic solvent, for achieving antireflective function at the target photolithography wavelength; and a crosslinking agent, for reacting with the film-forming resin to form a three-dimensional crosslinked network.
[0012] Optionally, after the initial hard mask layer and the initial anti-reflection layer are etched at intervals, the thickness of the anti-reflection layer located between adjacent control gate structures is selected from [20 nm, 50 nm].
[0013] Optionally, the surface of the initial floating gate layer is naturally oxidized to form a natural oxide layer; the step of removing the initial floating gate layer includes: removing the natural oxide layer and then removing the initial floating gate layer.
[0014] This invention also provides an intermediate structure for a semiconductor structure, comprising: a substrate having mutually spaced and raised control gate structures, with recesses between adjacent control gate structures; a grid-like intermediate floating gate layer, a portion of which is located between adjacent control gate structures, and another portion of which is perpendicular to the control gate structures; and a grid-like intermediate anti-reflective layer covering the intermediate floating gate layer.
[0015] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages: The semiconductor structure formation method and intermediate structure provided in this invention include: using a first floating gate etching process to remove the initial floating gate layer without an anti-reflection layer to obtain a grid-like intermediate floating gate layer; removing the anti-reflection layer located between adjacent control gate structures; and using a second floating gate etching process to remove the remaining intermediate floating gate layer without an anti-reflection layer to obtain the floating gate layer. The core of this solution is the use of a two-step etching process to obtain the floating gate layer. First, by decomposing the floating gate etching process into two independent steps, the risk of over-etching that may occur with a single etching step is effectively avoided, thereby protecting the underlying active region from damage. In the first floating gate etching process, the anti-reflection layer is used as a mask to remove only the uncovered area of the initial floating gate layer, forming a grid-like intermediate floating gate structure. This step effectively controls the etching depth, preventing the etching process from penetrating the floating gate layer and damaging the underlying critical functional layer. Subsequently, the anti-reflective layer between adjacent control gate structures is removed, creating conditions for the second floating gate etching process. At this point, because the height of the intermediate floating gate layer to be removed relative to the active region is nearly uniform, the second etching can more precisely control the etching endpoint, further reducing the possibility of over-etching. This step-by-step etching strategy, through the synergistic effect of the two etching processes, ensures both the integrity of the floating gate structure and maintains a good sidewall morphology, laying a solid foundation for subsequent process steps. Ultimately, it improves product yield and reliability while ensuring the performance stability of the memory cell. Therefore, adopting this approach can improve the quality of semiconductor structures. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of the invention in this specification, the drawings used in the description of the embodiments of the invention or the prior art in this specification will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure; Figure 2 This is a top view of a semiconductor structure; Figure 3 This is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present invention; Figure 4 This is a top view schematic diagram of a semiconductor structure according to an embodiment of the present invention; Figures 5 to 11 This is a schematic diagram of the device cross-sectional structure corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention; Figure 12 This is a top view schematic diagram of a semiconductor structure in an embodiment of the present invention. Detailed Implementation
[0018] The technical solutions of the present invention will be described in detail below with reference to specific embodiments and accompanying drawings. The embodiments described herein are specific implementations of the present invention, used to illustrate the concept of the present invention. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. These descriptions are illustrative and exemplary, and should not be construed as limiting the implementation of the present invention or the scope of protection of the present invention. In addition to the embodiments described herein, those skilled in the art can also adopt other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein.
[0019] It should be noted that the accompanying drawings in this embodiment are schematic diagrams used to illustrate the concept of the invention and to schematically show the shape and interrelationship of the various parts. It should be understood that, in order to clearly show the structure of the various components of the invention, the drawings are not drawn to the same scale, and the same reference numerals are used to indicate the same parts in the drawings.
[0020] In semiconductor manufacturing processes, floating-gate flash memory, as a mainstream non-volatile memory, is widely used in embedded systems, IoT devices, and memory chips due to its long lifespan, high reliability, and reprogrammable and erasable characteristics.
[0021] To improve the electric field control accuracy and charge retention capability of memory devices, the split-gate structure has emerged and gradually become the mainstream technology for high-capacity NOR Flash. By separating the control gate and the floating gate, split-gate optimizes the insulation characteristics between cells, significantly reduces crosstalk, and improves programming efficiency.
[0022] In the manufacturing process of multi-gate flash memory, deep trench etching is a crucial step in forming the isolation structure and floating gate, but its process stability directly affects the device's performance and yield. The current core problem is that the etching process can easily lead to over-etching of the floating gate layer, thereby damaging the underlying active region and tunnel oxide layer. This damage can cause increased leakage current, decreased data retention, and even device failure. Therefore, providing a technical solution to precisely control the etching depth and improve the quality of the semiconductor structure has become an urgent technical problem to be solved.
[0023] As described in the background art, a semiconductor structure suffers from low performance. The following section discusses... Figure 1 and Figure 2 The semiconductor structure is shown; analyze the reasons.
[0024] Reference Figure 1 and Figure 2 , Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure, specifically a cross-sectional schematic diagram of the process of forming a floating gate. Figure 2 This is a top view of a semiconductor structure. Figure 1 It can be Figure 2 A cross-sectional view along the Y direction.
[0025] The semiconductor structure includes: an active region 110, a control gate structure 120, and a dielectric stack 130.
[0026] like Figure 1 The semiconductor structure shown employs a single etching process to form the floating gate. Due to the need to ensure electrical isolation between adjacent floating gates, over-etching is easily caused during the etching process, damaging the underlying active region 110 and dielectric stack 130, resulting in damage at point W in the figure. This causes a sharp increase in off-state leakage current and a decrease in carrier mobility, leading to increased device power consumption and sluggish response. Furthermore, the damage induces threshold voltage drift and interface state charge fluctuations, causing a loss of device stability. For flash memory cells, this damage penetrates to the tunnel oxide layer, forming a fatal leakage path that allows floating gate charge to leak rapidly through the defect center, completely destroying the non-volatile memory foundation of data retention. The damaged area degrades more rapidly under electric field stress, significantly reducing device durability and lifespan.
[0027] To address the aforementioned technical problems, the semiconductor structure formation method and intermediate structure provided in this invention include: employing a first floating gate etching process to remove the initial floating gate layer without an anti-reflection layer to obtain a grid-like intermediate floating gate layer; removing the anti-reflection layer located between adjacent control gate structures; and employing a second floating gate etching process to remove the remaining intermediate floating gate layer without an anti-reflection layer to obtain the floating gate layer. The core of this solution is the use of a two-step etching process to obtain the floating gate layer. First, by decomposing the floating gate etching process into two independent steps, the risk of over-etching that might occur with a single etching step is effectively avoided, thereby protecting the underlying active region from damage. In the first floating gate etching process, the anti-reflection layer is used as a mask to remove only the uncovered area of the initial floating gate layer, forming a grid-like intermediate floating gate structure. This step effectively controls the etching depth, preventing the etching process from penetrating the floating gate layer and damaging the underlying critical functional layer. Subsequently, the anti-reflective layer between adjacent control gate structures is removed, creating conditions for the second floating gate etching process. At this point, because the height of the intermediate floating gate layer to be removed relative to the active region is nearly uniform, the second etching can more precisely control the etching endpoint, further reducing the possibility of over-etching. This step-by-step etching strategy, through the synergistic effect of the two etching processes, ensures both the integrity of the floating gate structure and maintains a good sidewall morphology, laying a solid foundation for subsequent process steps. Ultimately, it improves product yield and reliability while ensuring the performance stability of the memory cell. Therefore, adopting this approach can improve the quality of semiconductor structures.
[0028] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0029] See Figure 3 , Figure 3 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention. The method may perform the following steps S110 to S170.
[0030] In step S110, a substrate is formed having mutually spaced and raised control gate structures, with recesses between adjacent control gate structures.
[0031] In step S120, an initial floating grid layer with conformal coverage is formed on the substrate.
[0032] In step S130, an initial anti-reflective layer and an initial hard mask layer are spin-coated on the surface of the initial floating gate layer. The initial anti-reflective layer has fluidity such that the thickness of the initial anti-reflective layer between adjacent control gate structures is greater than the thickness of the initial anti-reflective layer on the raised control gate structure.
[0033] In step S140, along the extending direction of the control gate structure, the initial hard mask layer and the initial anti-reflection layer are etched at intervals to obtain a grid-shaped intermediate anti-reflection layer and a strip-shaped hard mask layer, and a part of the initial anti-reflection layer located between adjacent control gate structures is retained in the intermediate anti-reflection layer.
[0034] In step S150, using the hard mask layer as a mask, the initial floating gate layer that is not covered by the intermediate anti-reflection layer is removed by a first floating gate etching process to obtain a grid-shaped intermediate floating gate layer.
[0035] In step S160, the intermediate anti-reflection layer located between adjacent control gate structures is removed.
[0036] In step S170, using the remaining anti-reflection layer as a mask, the intermediate floating gate layer that remains uncovered by the anti-reflection layer is removed by a second floating gate etching process to obtain a floating gate layer.
[0037] The following Figures 4 to 12 is used to illustrate the above method.
[0038] Among them, Figures 4 to 11 is a partial step schematic diagram of a method for forming a semiconductor structure in an embodiment of the present invention.
[0039] Combined with reference to Figure 4 and Figure 5 , Figure 4 is a top view schematic diagram of a semiconductor structure in an embodiment of the present invention. Figure 5 is a cross-sectional schematic diagram of one step in a method for forming a semiconductor structure in an embodiment of the present invention.
[0040] It should be particularly noted that Figure 4 the filling color of the initial floating gate layer 240a in Figure 5 is different from that of the initial floating gate layer 240a in
[0041] but it does not mean that they are of different structures or different materials. Figure 4 As shown in
[0042] Figure 4 the grid-like structure similar to the character "丰" in Figure 5 is the active region 210, and the active region 210 includes: a first active region 211 and a second active region 212. Combining with the corresponding
[0043] It should be particularly noted that Figure 5 subfigure a in Figure 4 is a cross-sectional schematic diagram cut along Y1 in Figure 5 subfigure b in Figure 4 A schematic diagram of a cross-section cut along the Y2 axis.
[0044] Specifically, the step of forming the initial floating gate layer 240a may include: providing a first active region 211 and a second active region 212, wherein the first active region 211 and the second active region 212 are mutually perpendicular grid structures.
[0045] Specifically, the first active region 211 and Figure 4 Parallel in the Y direction, the second active region 212 and Figure 4 Parallel in the X direction. Figure 4 The Y-direction and X-direction are perpendicular to each other. Y1 is parallel to the Y-direction and is located above the first active region 211. A section along Y1 is used to obtain... Figure 5 Sub-figure a in the diagram. Y2 is parallel to the Y direction and is located above a portion of the second active region 212, obtained by cutting along Y2. Figure 5 Subgraph b in, thus Figure 5 Subgraph a and subgraph b show the first active region 211 and the second active region 212, respectively.
[0046] The first active region and the second active region are made of doped silicon.
[0047] See Figure 5 In sub-figure b, the shallow trench isolation layer 201 (STI) is located in the mesh of the mesh structure formed by the first active region 211 and the second active region 212. The shallow trench isolation layer 201 can be made of silicon oxide.
[0048] Then, a conformal covering initial floating gate layer 240a can be formed above the first active region 211 and the second active region 212.
[0049] Using a conformal deposition process, the initial floating gate layer 240a is conformally deposited above the first active region 211 and the second active region 212.
[0050] In this embodiment, the initial floating gate layer 240a is formed using a low-pressure chemical vapor deposition (LPCVD) process. LPCVD is a thin film deposition process that uses thermal energy to activate gaseous materials under low pressure (27-270 Pa). This technology is widely used in semiconductor manufacturing and photovoltaic fields, especially suitable for polycrystalline silicon layer deposition in TOPCon cells, offering advantages such as good film uniformity and high mass production yield. Its process temperature range is 425-900°C; by reducing pressure and increasing the gas diffusion rate, both film quality and step coverage are improved.
[0051] Specifically, the deposition process is carried out within a specific temperature range (400-650℃) and under precisely controlled pressure conditions. Through the thermal decomposition reaction of silane precursors, a uniformly thick and densely structured doped polycrystalline silicon thin film is formed in all exposed areas above the first active region 211 and the second active region 212. This conformal coverage characteristic ensures that the floating gate structure formed by the subsequent etching process maintains consistent physical dimensions across all spatial orientations. This lays the foundation for achieving a uniform distribution of the threshold voltage of the memory cell and provides a key material basis for constructing high-reliability floating gate flash memory cells.
[0052] like Figure 5 As shown, the steps of forming the control gate structure 220 may include: forming an isolation layer 201 and filling the mesh structure of the first active region 211 and the second active region 212.
[0053] The isolation layer 201 is a shallow trench isolation layer.
[0054] The top of the isolation layer 201 is coplanar with the tops of the first active region 211 and the second active region 212.
[0055] An initial control gate is formed, which covers the first active region 211 and the second active region 212, as well as the isolation layer 201.
[0056] The initial control gate is made of doped silicon.
[0057] Remove the initial control gate located above the second active region 212 to expose the second active region 212 and part of the isolation layer 201, thus obtaining the control gate structure 220.
[0058] It should be noted that an insulating layer is formed before the initial control gate is formed. The insulating layer covers the first active region 211 and the second active region 212 as well as the isolation layer 201 to achieve electrical isolation between the control gate structure 220 and the first active region 211 and the second active region 212.
[0059] A dielectric stack 230 is formed, which conformally covers the control gate structure 220, the second active region 212, and part of the isolation layer 201.
[0060] The dielectric stack 230 is a structure of a double silicon oxide layer sandwiching a silicon nitride layer (ONO), and the silicon nitride layer covers the sidewall of the control gate structure 220.
[0061] In step S110, a substrate is formed having mutually spaced and raised control gate structures 220, with recesses between adjacent control gate structures 220.
[0062] The substrate includes the first active region 211 and the second active region 212 as described above, as well as the isolation layer 201, the control gate structure 220, and the dielectric stack 230.
[0063] The recess between adjacent control gate structures 220 is formed to remove the initial control gate located above the second active region 212.
[0064] See Figure 6 , Figure 6 Continue Figure 5 The direction of the subgraph in the middle, i.e. Figure 6 Subgraph a in the middle is Figure 4 A cross-sectional view cut along line Y1. Figure 6 Subgraph b in the middle is Figure 4 A schematic diagram of a cross-section cut along the Y2 axis.
[0065] An initial antireflective layer 250a, an initial hard mask layer 251, and a photoresist layer 252 are spin-coated onto the surface of the initial floating gate layer.
[0066] It should be noted that the initial anti-reflective layer 250a has fluidity, such that the thickness of the initial anti-reflective layer 250a between adjacent control gate structures 220 is greater than the thickness of the initial anti-reflective layer 250a on the raised control gate structure 220.
[0067] The initial antireflective layer 250a, before spin coating, is a liquid composition comprising an organic solvent, which acts as a dissolving carrier and provides flowability to dissolve the solid polymer resin, forming a solution of suitable viscosity. During high-speed spin coating, centrifugal force enables the solution to have excellent flowability, allowing it to spread evenly and form a smooth liquid film.
[0068] A film-forming resin, dissolved in the organic solvent, is used to form the main structure of the film. The film-forming resin is the structural backbone of the BARC film, but before spin coating, it is dissolved in the solvent in the form of molecular chains. After the solvent evaporates, these polymer chains intertwine to form the basic framework of the film, providing mechanical strength, thermal stability, and etching resistance. The film-forming resin can be made of acrylate copolymers or aromatic polymers (such as "phenolic resin," which has a natural anti-reflective advantage in the deep ultraviolet region).
[0069] A light absorber, uniformly dispersed in an organic solvent, is used to achieve anti-reflection function at a target photolithography wavelength. The light absorber is dissolved in the solvent and uniformly dispersed between polymer resins. The molecular structure of the light absorber is designed to strongly absorb light of specific wavelengths (e.g., 365nm for i-line, 248nm for KrF, and 193nm for ArF). The light absorber can be made of anthraquinone or azo compounds.
[0070] A crosslinking agent is used to react with the film-forming resin to form a three-dimensional crosslinked network. Before spin coating, the crosslinking agent is an independent small molecule, freely dispersed in the solution. The crosslinking agent is the "key" to subsequent thermosetting; heating triggers a chemical reaction between the crosslinking agent and functional groups (such as hydroxyl groups -OH) on the matrix resin, forming a robust three-dimensional network structure. This step transforms the liquid BARC solution into a solid, insoluble, infusible, and stable film that can withstand subsequent photoresist solvent washing.
[0071] The step of forming the antireflective layer further includes: forming a low-temperature oxide layer 251 covering the initial antireflective layer 250a as the initial hard mask layer 251; and forming a photoresist layer 252 covering the low-temperature oxide layer 251.
[0072] Specifically, after spin coating and curing of the initial anti-reflective layer 250a, a low-temperature oxide layer 251 is formed on the surface of the initial anti-reflective layer 250a using a chemical vapor deposition process.
[0073] The material of the low-temperature oxide layer 251 may include silicon dioxide.
[0074] The thickness of the low-temperature oxide layer 251 is controlled in the range of 50-150 nanometers, and the deposition temperature is maintained below 400°C to avoid thermal damage to the underlying organic anti-reflective material. The low-temperature oxide layer 251 serves as the initial hard mask layer 251 to provide the required etching selectivity for subsequent patterning processes.
[0075] A photoresist layer 252 is spin-coated onto the surface of the low-temperature oxide layer 251. By adjusting the photoresist viscosity and spin-coating parameters, a uniformly thick cover layer is formed. The photoresist layer 252 will define the predetermined pattern in the subsequent exposure and development process, thereby establishing a composite pattern transfer stack structure comprising the photoresist layer 252, the low-temperature oxide layer 251, and the initial anti-reflective layer 250a. The construction of this multilayer mask system utilizes the optical control characteristics of the organic anti-reflective layer and enhances the mechanical stability and etching resistance of the overall mask structure through the inorganic low-temperature oxide layer.
[0076] See Figures 7 to 10 , Figures 7 to 10 for Figure 4 A schematic diagram of a cross-section cut along the Y2 axis.
[0077] See Figure 7 The photoresist layer 252 is patterned to expose the low-temperature oxide layer 251 except above the first active region 211.
[0078] Specifically, along the extension direction of the control gate structure 220 (i.e., the X direction, see...) Figure 4The initial hard mask layer 251 and the initial anti-reflective layer 250a are etched at intervals to obtain a mesh-like intermediate anti-reflective layer 250b and a strip-shaped hard mask layer 251. The intermediate anti-reflective layer 250b retains a portion of the initial anti-reflective layer 250a located between adjacent control gate structures 220. The gases used to etch the initial anti-reflective layer 250a include chlorine and oxygen, and the gas used to etch the low-temperature oxide layer 251 includes carbon tetrafluoride.
[0079] In other words, along the extension direction of the control gate structure 220 (i.e., the X direction, see...) Figure 4 The initial hard mask layer 251 and the initial anti-reflection layer 250a above the first active region 211 are not etched, while a portion of the initial anti-reflection layer 250a above the second active region 212 is retained, resulting in a mesh-like intermediate anti-reflection layer 250b. Only the portion of the initial hard mask layer 251 above the first active region 211 remains unetched, resulting in the strip-shaped hard mask layer 251.
[0080] After the initial hard mask layer 251 and the initial anti-reflection layer 250a are etched at intervals, the thickness of the anti-reflection layer (intermediate anti-reflection layer 250b) located between adjacent control gate structures 220 is selected from [20nm, 50nm].
[0081] It should be noted that the thickness of the portion of the initial anti-reflective layer 250a retained above the second active region 212 determines the height of the remaining initial floating gate layer 240a relative to the second active region 212 after the first floating gate etching process in subsequent processes.
[0082] See Figure 8 Using the hard mask layer 251 as a mask, the initial floating gate layer 240a that does not cover the intermediate anti-reflection layer 250b is removed by the first floating gate etching process to obtain the mesh-like intermediate floating gate layer 240b.
[0083] Specifically, the hard mask layer 251 is a patterned hard mask layer 251, specifically the strip-shaped hard mask layer 251. A first floating gate etching process is employed, using the portion of the initial anti-reflective layer 250a, i.e., the intermediate anti-reflective layer 250b, located above the second active region 212, as a mask. This etching process uses a mixture of hydrogen bromide and oxygen as the main etching medium. By adjusting the RF power and gas pressure parameters, selective removal of the unmasked area of the initial floating gate layer 240a is achieved. During this process, the intermediate anti-reflective layer 250b, due to its inherent organic polymer properties, achieves a superior etching selectivity with the underlying floating gate polysilicon material, ensuring the fidelity of the pattern transfer. After this process, the initial floating gate layer 240a is precisely etched to form a mesh-structured intermediate floating gate layer 240b, with the mesh openings located above the isolation layer 201.
[0084] The intermediate floating gate layer 240b lays a key foundation for the subsequent second floating gate etching process. The step-by-step etching strategy effectively avoids the risk of active layer damage caused by excessive etching in a single step.
[0085] See Figure 9 Remove the intermediate anti-reflective layer 250b located between adjacent control gate structures 220.
[0086] Specifically, an oxygen plasma ashing process is used to selectively remove the intermediate antireflective layer 250b located between adjacent control gate structures 220. This removal process achieves high selectivity etching of the organic antireflective material by adjusting the oxygen flow rate and radio frequency power, while preserving the integrity of the dielectric stack 230 and the control gate structure 220.
[0087] In some embodiments, the intermediate antireflective layer 250b is oxidized and decomposed into volatile gas products under plasma, thereby exposing the intermediate floating gate layer 240b. This step removes organic mask residue from the subsequent second floating gate etching process, ensuring the cleanliness of the etching interface and providing the necessary conditions for the subsequent etching of the intermediate floating gate layer 240b.
[0088] See also Figure 10 and Figure 11 , Figure 11 for Figure 4 A schematic diagram of a cross-section cut along line Y1.
[0089] Using the remaining anti-reflective layer as a mask, a second floating gate etching process is used to remove the remaining intermediate floating gate layer 240b that does not cover the anti-reflective layer, resulting in the floating gate layer 240.
[0090] The remaining anti-reflective layer is the anti-reflective layer located above the first active region 211.
[0091] In some embodiments, the strip-shaped hard mask layer 251 is also present above the remaining antireflective layer.
[0092] Using a second floating gate etching process, with the anti-reflection layer as a mask, the remaining intermediate floating gate layer 240b that does not cover the anti-reflection layer is removed. In other words, the intermediate floating gate layer 240b located between adjacent first active regions 211 is removed to obtain the floating gate layer 240.
[0093] See Figure 12 The floating gate layer 240 is spaced across the control gate structure 220 above it.
[0094] It should be noted that the structure between the control gate structure 220 and the floating gate layer 240 is omitted in this figure to facilitate the illustration of their positional relationship. The different pattern fills used for the control gate structure 220 and the floating gate layer 240 do not indicate that they are made of different materials; this is merely to highlight their positional relationship. Figure 12 The filling pattern of the floating grid layer 240 described in the text is consistent with... Figures 5 to 11 The different filling patterns do not mean that the floating grid layer 240 is made of a different material than the one in the previous figure.
[0095] It should be noted that, in this embodiment, the surface of the initial floating gate layer 240a and / or the surface of the intermediate floating gate layer 240b will naturally oxidize to form a natural oxide layer (not shown in the figure). The step of removing the initial floating gate layer 240a and / or the intermediate floating gate layer 240b further includes: removing the natural oxide layer.
[0096] Removing the natural oxide layer allows for precise control of the two etching processes on the floating gate layer. This helps avoid over-etching, which could damage the active region 210.
[0097] This invention also provides an intermediate structure for a semiconductor structure, comprising: a substrate having mutually spaced and raised control gate structures, with recesses between adjacent control gate structures; a grid-like intermediate floating gate layer, a portion of which is located between adjacent control gate structures, and another portion of which is perpendicular to the control gate structures; and a grid-like intermediate anti-reflective layer covering the intermediate floating gate layer.
[0098] See also Figure 4 , Figure 8 and Figure 12 , Figure 8 for Figure 4 or Figure 12 A schematic diagram of a cross-section cut along Y2. It should be noted that the cross-section obtained by cutting along Y2... Figure 8This is merely a description of the corresponding cutting positions and does not represent... Figure 8 The structure and Figure 12 or Figure 4 The structures in the text or the structures in the corresponding steps correspond one-to-one.
[0099] The substrate includes an active region 210, an isolation layer 201, a control gate structure 220, and a dielectric stack 230.
[0100] The substrate has mutually spaced and raised control gate structures 220, with recesses between adjacent control gate structures 220.
[0101] Figure 4 In the diagram, the active region 210 and the control gate structure 220 are identified by different dashed lines. The control gate structure 220 is located in the second active region 212 (see...). Figure 5 Above and to the sides of ).
[0102] A portion of the intermediate floating gate layer 240b is located between adjacent control gate structures 220, and another portion of the intermediate floating gate layer 240b is perpendicular to the control gate structure 220.
[0103] The intermediate floating grid layer 240b is located above the active region 210 and is in the form of a grid.
[0104] The intermediate anti-reflective layer 250b covers the intermediate floating grid layer 240b, so the intermediate anti-reflective layer 250b also has a grid-like structure.
[0105] The thickness of the intermediate anti-reflective layer 250b located between adjacent control gate structures 220 is selected from [20 nm, 50 nm].
[0106] The intermediate anti-reflective layer 250b can act as a mask during the formation of the intermediate floating gate layer 240b to limit the height of the intermediate floating gate layer 240b relative to the active region 210, making the height of the intermediate floating gate layer 240b relative to the active region 210 more consistent. This is for subsequent removal of the second active region 212 (see...). Figure 5 The intermediate floating gate layer 240b above the gate allows for more precise control of the etching endpoint, further reducing the possibility of over-etching. This intermediate structure provides the necessary conditions for ensuring the integrity of the floating gate structure and maintaining good sidewall morphology, and also lays a solid foundation for subsequent process steps. Ultimately, it improves product yield and reliability while ensuring the performance stability of the memory cell. Therefore, adopting the above solution can improve the quality of the semiconductor structure.
[0107] This invention also provides an electronic device, including any of the semiconductor devices described above.
[0108] The semiconductor device can be built into or externally connected to the electronic device, which includes, but is not limited to, mobile phones, computers, tablets, servers, cloud platforms, etc.
[0109] It is understood that the above describes multiple embodiments of semiconductor structure formation methods, i.e. intermediate structures and electronic devices. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed and made public by this invention.
[0110] It should be understood that "multiple" in the embodiments of this application refers to two or more.
[0111] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.
[0112] It should be noted that the sequence number of each step in this embodiment does not represent a limitation on the execution order of each step.
[0113] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is formed having mutually spaced and protruding control gate structures, with recesses between adjacent control gate structures; An initial floating grid layer with conformal coverage is formed on the substrate; An initial antireflective layer and an initial hard mask layer are spin-coated on the surface of the initial floating gate layer. The initial antireflective layer has fluidity such that the thickness of the initial antireflective layer between adjacent control gate structures is greater than the thickness of the initial antireflective layer on the raised control gate structure. Along the extension direction of the control gate structure, the initial hard mask layer and the initial anti-reflection layer are etched at intervals to obtain a mesh-like intermediate anti-reflection layer and a strip-like hard mask layer, wherein the intermediate anti-reflection layer retains a portion of the initial anti-reflection layer located between adjacent control gate structures; Using the hard mask layer as a mask, a first floating gate etching process is employed to remove the initial floating gate layer that does not cover the intermediate anti-reflection layer, in order to obtain a grid-like intermediate floating gate layer; Remove the intermediate anti-reflective layer located between adjacent control gate structures; Using the remaining anti-reflective layer as a mask, a second floating gate etching process is used to remove the remaining intermediate floating gate layer that does not cover the anti-reflective layer, thus obtaining the floating gate layer.
2. The method according to claim 1, characterized in that, The steps for forming the initial floating gate layer include: A first active region and a second active region are provided, wherein the first active region and the second active region are mutually perpendicular grid structures; An initial floating gate layer with conformal coverage is formed above the first active region and the second active region.
3. The method according to claim 2, characterized in that, The step of forming the initial anti-reflective layer further includes: A low-temperature oxide layer is formed covering the initial anti-reflection layer, serving as the initial hard mask layer; A photoresist layer is formed to cover the low-temperature oxide layer, and the photoresist layer is patterned to expose the low-temperature oxide layer except for the area above the first active region.
4. The method according to claim 3, characterized in that, The step of etching the initial antireflective layer at intervals includes: The low-temperature oxide layer and the initial anti-reflection layer are etched, retaining the low-temperature oxide layer and the initial anti-reflection layer located above the first active region, and retaining a portion of the initial anti-reflection layer located above the second active region.
5. The method according to claim 3, characterized in that, Meet one or more of the following: The material of the low-temperature oxide layer includes: silicon dioxide; The low-temperature oxide layer is formed using a chemical vapor deposition process; The gases used to etch the antireflective layer include chlorine and oxygen. The gases used to etch the initial floating gate layer include: hydrogen bromide and oxygen; The gas used to etch the low-temperature oxide layer includes carbon tetrafluoride.
6. The method according to claim 2, characterized in that, The steps for forming the control gate structure include: An isolation layer is formed, filling the first active region and the second active region with a grid-like structure; An initial control gate is formed, the initial control gate covering the first active region and the second active region, as well as the isolation layer; Remove the initial control gate located above the second active region to expose the second active region and part of the isolation layer, thus obtaining the control gate structure; A dielectric stack is formed, the dielectric stack conformally covering the control gate structure, the second active region, and a portion of the isolation layer; The dielectric stack is a structure in which a double silicon oxide layer encloses a silicon nitride layer, and the silicon nitride layer covers the sidewall of the control gate.
7. The method according to claim 1, characterized in that, The material of the antireflective layer before spin coating is a liquid composition including: Organic solvents serve as dissolution carriers and provide flowability; A film-forming resin, dissolved in the organic solvent, is used to form the main structure of the thin film; A light absorber, uniformly dispersed in an organic solvent, is used to achieve anti-reflection function at the target photolithography wavelength; A crosslinking agent is used to react with the film-forming resin to form a three-dimensional crosslinked network.
8. The method according to claim 1, characterized in that, After the initial hard mask layer and the initial anti-reflection layer are etched at intervals, the thickness of the anti-reflection layer located between adjacent control gate structures is selected from [20 nm, 50 nm].
9. The method according to claim 1, characterized in that, The surface of the initial floating gate layer is naturally oxidized to form a natural oxide layer; The step of removing the initial floating gate layer includes: After removing the natural oxide layer, remove the initial floating gate layer.
10. An intermediate structure of a semiconductor structure, characterized in that, include: A substrate having mutually spaced and raised control gate structures, with recesses between adjacent control gate structures; A grid-like intermediate floating gate layer, a portion of which is located between adjacent control gate structures, and another portion of which is perpendicular to the control gate structure; A mesh-like intermediate anti-reflective layer covers the intermediate floating grid layer.