Memory device and manufacturing method of the memory device

Abstract

A memory device and a method of manufacturing the memory device are provided. A memory device according to an embodiment of the present disclosure includes: a stacked structure including conductive layers spaced apart from each other in a first direction; a cell plug extending in a first direction in the stacked structure; and an air gap defined between the conductive layers, where the air gap extends across the conductive layers toward the cell plug.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to a memory device and a method of manufacturing the memory device, and more specifically, to a memory device comprising a memory block having a three-dimensional structure and a method of manufacturing the memory device. Background Technology

[0002] Memory devices can include non-volatile memory devices that retain stored data even without power. Based on the arrangement of memory cells, non-volatile memory devices can be classified as two-dimensional or three-dimensional memory devices. Memory cells of a two-dimensional non-volatile memory device can be arranged in a single layer on a substrate. Memory cells of a three-dimensional non-volatile memory device can be stacked in a direction perpendicular to the substrate. Because the integration density of three-dimensional non-volatile memory devices is greater than that of two-dimensional non-volatile memory devices, electronic devices incorporating three-dimensional non-volatile memory devices are continuously increasing. Summary of the Invention

[0003] According to one embodiment, a memory device may include: a stacked structure including conductive layers spaced apart from each other in a first direction; cell plugs extending in the stacked structure in the first direction; and an air gap defined between the conductive layers, wherein the air gap extends toward the cell plugs across the conductive layers.

[0004] According to one embodiment, a method of manufacturing a memory device may include: forming a stacked structure including a sacrificial layer and an interlayer insulating layer, wherein the sacrificial layer and the interlayer insulating layer are alternately stacked on each other in a first direction; forming an opening extending in the first direction in the stacked structure; forming a sacrificial pattern on a side surface of the interlayer insulating layer exposed through the opening; forming a cell plug in the opening in which the sacrificial pattern is formed; replacing the sacrificial layer with a conductive layer; and forming an air gap by removing the interlayer insulating layer and the sacrificial pattern. Attached Figure Description

[0005] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0006] Figure 2 This is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure;

[0007] Figure 3 This is a cross-sectional view showing the structure of a memory device according to an embodiment of the present disclosure;

[0008] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 4F This is a diagram illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure;

[0009] Figure 5A , Figure 5B and Figure 5C This is a diagram illustrating the structure of a memory device according to an embodiment of the present disclosure;

[0010] Figure 6 This is a diagram illustrating a memory card system employing a memory device according to an embodiment of the present disclosure; and

[0011] Figure 7 This is a diagram illustrating a solid-state drive (SSD) system for a memory device applied according to an embodiment of the present disclosure. Detailed Implementation

[0012] The specific structural or functional descriptions of examples of embodiments of the concept disclosed in this specification are shown only for the purpose of describing examples of embodiments of the concept, and examples of embodiments of the concept can be implemented in various forms, but the description is not limited to the examples of embodiments described in this specification.

[0013] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement the technical spirit of the present disclosure.

[0014] Various embodiments of this disclosure provide a memory device capable of improving operational performance by modifying the structure of the stacked structure, and a method for manufacturing the memory device.

[0015] Terms such as “first” and “second” are used to distinguish various elements without implying the size, order, priority, number, or importance of the elements. For example, in one example, a first element may be named a second element, while in another example, a second element may be named a first element. Terms such as “vertical,” “horizontal,” “above,” “side,” “lower,” “external,” and other terms that imply relative spatial relationships or orientations are used only for the purpose of description or reference to the accompanying drawings and are not restrictive. Crosshairs in all the drawings indicate corresponding or similar areas between the drawings, not indicating the material associated with these areas. It should be understood that when an element or layer is referred to as being “on,” “connected to,” or “linked to” another element or layer, the element or layer may be directly on, directly connected to, or linked to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element or layer is referred to as being “directly” on, “directly connected to,” or “directly linked to” another element or layer, there are no intermediate elements or layers. The same reference numerals always denote the same elements.

[0016] Figure 1 This is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0017] Reference Figure 1 The memory device 100 may include a memory cell array 110, peripheral circuitry 170, and control circuitry 180.

[0018] The memory cell array 110 may include first memory blocks BLK1 to j-th memory blocks BLKj. The first memory blocks BLK1 to j-th memory blocks BLKj may have a three-dimensional structure. The three-dimensional first memory blocks BLK1 to j-th memory blocks BLKj may include memory cells stacked in a direction perpendicular to the substrate.

[0019] Memory cells can store one or more bits of data depending on the programming method. For example, storing one bit of data in a single memory cell is called the single-level cell method, and storing two bits of data is called the multi-level cell method. Storing three bits of data in a single memory cell is called the three-level cell method, and storing four bits of data is called the four-level cell method.

[0020] The peripheral circuitry 170 may include programming operations for storing data in the memory cell array 110, reading operations for outputting data stored in the memory cell array 110, and erasing operations for erasing data stored in the memory cell array 110. For example, the peripheral circuitry 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and input / output circuitry 160.

[0021] Voltage generator 120 can generate various operating voltages Vop that are applied to perform programming, reading, or erasing operations in response to operation code OPCD. For example, voltage generator 120 can generate programming voltage, through voltage, turn-on voltage, turn-off voltage, ground voltage, negative voltage, source voltage, verification voltage, read voltage, erase voltage, and precharge voltage in response to operation code OPCD.

[0022] The programming voltage can be applied to a selected word line in the word line WL during a programming operation and can be used to increase the threshold voltage of the memory cell connected to the selected word line. The voltage can also be applied to an unselected word line in the word line WL during a programming or read operation and can be used to turn on the memory cell connected to the unselected word line.

[0023] A turn-on voltage can be applied to the drain-select line DSL or the source-select line SSL, and can be used to turn on the drain-select transistor or the source-select transistor. A turn-off voltage can be applied to the drain-select line DSL or the source-select line SSL, and can be used to turn off the drain-select transistor or the source-select transistor.

[0024] The ground voltage can be 0V. A negative voltage can be below 0V. The source voltage can be applied to the source line SL and can be negative, ground, or positive. The verification voltage can be used to determine the threshold voltage of a selected memory cell during programming or erasing operations and can be applied to a selected word line or all word lines connected to the selected memory block.

[0025] A read voltage can be applied to the selected word line during a read operation and is used to determine the data stored in the memory cell. An erase voltage can be applied to the source line SL during an erase operation and is used to lower the threshold voltage of the memory cell. A precharge voltage can be a positive voltage used to precharge the channel of an unselected string during a verification or read operation and can be provided to the source line SL.

[0026] The row decoder 130 can be connected to the voltage generator 120 via a global line, and to the first memory block BLK1 through the j-th memory block BLKj via the drain select line DSL, word line WL, source select line SSL, and source line SL. The row decoder 130 can be configured to apply an operating voltage Vop to the drain select line DSL, word line WL, source select line SSL, and source line SL connected to the selected memory block according to the row address RADD.

[0027] Page buffer group 140 may include page buffers (not shown) commonly connected to first memory blocks BLK1 through j-th memory blocks BLKj. For example, each of the page buffers (not shown) may be connected to first memory blocks BLK1 through j-th memory blocks BLKj via bit lines BL. The page buffers (not shown) may sense current or voltage in bit lines BL in response to a page buffer control signal PBSIG.

[0028] The column decoder 150 can transfer data between the page buffer group 140 and the input / output circuitry 160 in response to the column address CADD. For example, the column decoder 150 can be connected to the page buffer group 140 via the column line CL and to the input / output circuitry 160 via the data line DL.

[0029] Input / output circuit 160 can receive or output commands (CMD), addresses (ADD), and data via input / output line I / O. For example, input / output circuit 160 can transmit commands (CMD) and addresses (ADD) received from an external device via input / output line I / O to control circuit 180, and can transmit data received from an external controller via input / output line I / O to column decoder 150. Alternatively, input / output circuit 160 can output data transmitted from column decoder 150 to an external controller via input / output line I / O.

[0030] Control circuit 180 can output operation code OPCD, row address RADD, page buffer control signal PBSIG, and column address CADD in response to command CMD and address ADD. For example, when command CMD input to control circuit 180 corresponds to a programming operation, control circuit 180 can control peripheral circuit 170 to perform a programming operation on the memory block selected by address ADD. When command CMD input to control circuit 180 corresponds to a read operation, control circuit 180 can control peripheral circuit 170 to perform a read operation on the memory block selected by address ADD and output the read data. When command CMD input to control circuit 180 corresponds to an erase operation, control circuit 180 can control peripheral circuit 170 to perform an erase operation on the selected memory block.

[0031] Figure 2This is a circuit diagram showing the j-th storage block BLKj according to an embodiment of the present disclosure.

[0032] like Figure 1 The first storage block BLK1 to the j-th storage block BLKj shown can have the same configuration as each other. Figure 2 The j-th storage block BLKj is shown as an example from the first storage block BLK1 to the j-th storage block BLKj.

[0033] Reference Figure 2 The j-th storage block BLKj may include a string ST connecting the first bit line BL1 to the nth bit line BLn to the source line SL. The first bit lines BL1 to the nth bit lines BLn may extend in the Y direction and be spaced apart from each other in the X direction. Therefore, the string ST extending in the Z direction may be spaced apart from each other in both the X and Y directions.

[0034] The string ST, connected to the nth bit line BLn, is used as an example. String ST may include a source selection transistor SST, first memory cells MC1 to the i-th memory cells MCI, and a drain selection transistor DST. Provided as... Figure 2 The j-th memory block BLKj shown is used to schematically illustrate the connection configuration of the j-th memory block BLKj. Therefore, the number of source selection transistors SST, the number of first memory cells MC1 to the i-th memory cells MCI, and the number of drain selection transistors DST included in each of the strings ST can vary depending on the corresponding memory device. For example, the string ST may include two or more source selection transistors SST or two or more drain selection transistors DST.

[0035] The gates of the source-select transistors SST included in different cell strings ST can be connected to the source-select line SSL. The gates of the first memory cell MC1 to the i-th memory cell MCI can be connected to the first word line WL1 to the i-th word line WL1 to WLi. The gate of the drain-select transistor DST can be connected to the drain-select line DSL.

[0036] Memory cells formed on the same layer among the first memory cells MC1 to the i-th memory cell MCI can be connected to the same word line. For example, the first memory cells MC1 included in different strings ST can be jointly connected to the first word line WL1, and the i-th memory cells MCI included in different strings ST can be jointly connected to the i-th word line WLi. A group of memory cells included in different strings ST and connected to the same word line can constitute a page PG. Programming and reading operations can be performed on a page PG basis, and erasing operations can be performed on a memory block basis.

[0037] Figure 3This is a cross-sectional view showing the structure of a memory device according to an embodiment of the present disclosure.

[0038] Figure 3 The unit plug CPL shown can correspond to, for example, Figure 1 The portion of any string ST included in one of the first storage blocks BLK1 to the j-th storage block BLKj shown. For example, as referenced above. Figure 2 The source selection transistor SST, the first memory cell MC1 to the i-th memory cell MCI, and the drain selection transistor DST can be formed at the intersection between the cell plug CPL and the conductive layer CD.

[0039] Reference Figure 3 The memory device may include a stacked structure STK comprising conductive layers CD. The stacked structure STK may include conductive layers CD separated from each other in the Z direction. Each of the conductive layers CD may extend in both the X and Y directions. The conductive layers CD may correspond to the references above. Figure 1 and Figure 2 The drain select line DSL, word line WL, and source select line SSL are described. The conductive layer CD may include a conductive material. For example, the conductive layer CD may include at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polycrystalline silicon (poly-Si). However, as... Figure 3 The number of conductive layers CD shown is merely an example and is not limited to this. Figure 3 The quantity shown.

[0040] The memory device may include a cell plug CPL. The cell plug CPL may extend in the Z-direction within a stacked structure STK. The cell plug CPL may pass through a conductive layer CD. The cell plug CPL may include a recessed portion recessed inward toward its center. The side surfaces of the cell plug CPL may include a concave surface CS and a vertical surface VS. The concave surface CS and the vertical surface VS may be arranged alternately in the Z-direction. The conductive layer CD may contact the vertical surface VS of the cell plug CPL.

[0041] Air gaps AG can be inserted between conductive layers CD. That is, air gaps AG can be located between conductive layers CD. For example, each air gap AG can be defined by the upper surface US and the lower surface LS of the adjacent conductive layer CD. Air gaps AG can refer to the substantially empty space provided between conductive layers CD.

[0042] The air gap AG can extend in the X direction toward the cell plug CPL across the conductive layer CD. The air gap AG can protrude more than the side surface of the conductive layer CD in the horizontal direction. For example, the air gap AG can be defined by the concave surface CS of the cell plug CPL.

[0043] Each of the air gaps AG may include a first portion P1 located between the conductive layers CD. Each of the first portions P1 may be defined by the upper surface US and lower surface LS of the conductive layers CD that are adjacent to each other in the Z direction. Each of the first portions P1 may be surrounded by the upper surface US and lower surface LS of the adjacent conductive layers CD. The first portion P1 may overlap with the conductive layers CD in the Z direction. The first portion P1 may correspond to the space between the separated conductive layers CD. The first portion P1 may extend in the X and Y directions.

[0044] Each of the air gaps AG may include a second portion P2 extending from the first portion P1. Each of the second portions P2 may be defined by a side surface of the element plug CPL. For example, the second portion P2 may be defined by each of the concave surfaces CS of the element plug CPL. Each of the second portions P2 may overlap with the element plug CPL in the Z direction. The height of the second portion P2 (e.g., the length of the second portion P2 in the Z direction) may decrease toward the center of the element plug CPL. The side surface of each of the second portions P2 may have a circularly curved shape toward the center of the element plug CPL.

[0045] In this disclosure, a first portion P1 and a second portion P2, which are distinct from each other, are described based on the air gap AG. However, there may be no boundary between the first portion P1 and the second portion P2, or no boundary may be observed therebetween.

[0046] The cell plug CPL may include a barrier layer BX. The barrier layer BX may form the outer surface of the cell plug CPL. The barrier layer BX may contact the side surface of the conductive layer CD. The barrier layer BX may contact the air gap AG. The barrier layer BX may include an insulating material. Furthermore, the barrier layer BX may include an oxide layer. For example, the barrier layer BX may include a silicon oxide layer, a silicon oxynitride layer, or a corresponding oxide material. The barrier layer BX may include a high-k material.

[0047] The barrier layer BX may include vertical portions VP that contact the side surfaces of the conductive layer CD. The vertical portions VP may extend in the Z direction.

[0048] Furthermore, the barrier layer BX may include a recessed portion CP, which is recessed inward between the conductive layers CD toward the center of the cell plug CPL. The recessed portion CP may have a circular shape toward the center of the cell plug CPL. The outer and inner surfaces of each of the recessed portions CP may be curved surfaces. The recessed portion CP may contact the tunneling layer TX. The recessed portion CP may protrude further toward the center of the channel layer CH than the vertical portion VP. The second portion P2 of the air gap AG may be surrounded by the recessed portions CP of the barrier layer BX.

[0049] The vertical portion VP and the recessed portion CP of the barrier layer BX can be arranged alternately in the Z direction. The vertical portion VP and the recessed portion CP can extend to each other. The barrier layer BX can include a non-planar structure. The outer surface of the recessed portion CP of the barrier layer BX can be the concave surface CS of the element plug CPL. The outer surface of the vertical portion VP of the barrier layer BX can be the vertical surface VS of the element plug CPL. For ease of illustration, the vertical portion VP and the recessed portion CP are shown as distinct from each other in this disclosure. However, there may be no boundary between the vertical portion VP and the recessed portion CP, or no boundary may be observed therebetween.

[0050] The cell plug (CPL) may include data storage patterns (DS). The data storage patterns (DS) may be spaced apart in the Z-direction. The data storage patterns (DS) may be separated from each other by an air gap (AG). For example, the air gap (AG) and the barrier layer (BX) may be located between data storage patterns (DS) adjacent to each other in the Z-direction. Because the data storage patterns (DS) formed on different layers are not connected to each other and are separated, negative charges trapped in the data storage patterns (DS) during programming operations may not move vertically to other adjacent data storage patterns (DS). In one embodiment, the retention characteristics of the memory device can be improved by using data storage patterns (DS) separated from each other in the Z-direction, thereby improving the reliability of the memory device.

[0051] Each of the data storage patterns DS can be located in the X direction relative to each of the conductive layers CD. The data storage pattern DS can be at the same height as the conductive layers CD. Each data storage pattern DS can be surrounded by a conductive layer CD. In one embodiment, at least a portion of each of the data storage patterns DS is at the same height as the conductive layers CD. For example, as... Figure 3 As shown, at least a portion of each of the data storage patterns DS is located at the same height as the conductive layer CD.

[0052] The data storage pattern DS can be disposed between the recessed portions CP of the barrier layer BX. The data storage pattern DS can contact the vertical portions VP of the barrier layer BX respectively. The data storage pattern DS can fill the irregular portions formed in the barrier layer BX between the air gaps AG.

[0053] The data storage pattern DS may include a nitride layer. For example, the data storage pattern DS may include a silicon nitride layer.

[0054] The cell plug CPL may include a tunneling layer TX that contacts the data storage pattern DS and the barrier layer BX. The tunneling layer TX may contact the data storage pattern DS at a height corresponding to the conductive layer CD. Furthermore, the tunneling layer TX may contact the barrier layer BX at a height corresponding to the air gap AG. The tunneling layer TX may pass through the conductive layer CD. The tunneling layer TX may extend in the Z direction. The tunneling layer TX may include an insulating material. For example, the tunneling layer TX may include an oxide layer. The tunneling layer TX may include a silicon oxide layer or a corresponding oxide material.

[0055] The cell plug CPL may include a channel layer CH that contacts the inner surface of the tunneling layer TX. The channel layer CH may pass through the conductive layer CD. The channel layer CH may extend in the Z direction. The channel layer CH may be surrounded by the tunneling layer TX. The channel layer CH may include an undoped silicon layer or a doped silicon layer.

[0056] The cell plug CPL may include a core post CO that fills the interior of the channel layer CH. The core post CO may be surrounded by the channel layer CH. The core post CO may pass through the conductive layer CD. The core post CO may extend in the Z direction. The core post CO may include an insulating layer or a conductive layer.

[0057] Although not shown, the cell plug CPL may also include a capping layer formed on the die post CO. The capping layer may contact the channel layer CH on the die post CO. The capping layer may include an undoped silicon layer or a doped silicon layer.

[0058] According to one embodiment of this disclosure, an air gap AG can be formed between conductive layers CD, thereby reducing the parasitic capacitance between the conductive layers CD. In one embodiment of this disclosure, because the air gap AG extends toward the center of the cell plug CPL, the volume of the air gap AG can be increased further, thereby reducing the parasitic capacitance between the conductive layers CD. In one embodiment, the air gap AG extends across the conductive layers CD in the X direction toward the cell plug CPL, and can reduce the parasitic capacitance between the conductive layers CD and the channel layer CH.

[0059] According to one embodiment of this disclosure, the air gap AG may include a second portion P2 having a circular cross-section facing the center of the cell plug CPL. Furthermore, the barrier layer BX may include a recessed portion CP having a circular shape. The circular shape of the recessed portion CP of the barrier layer BX may result in increased control of the conductive layer CD over the channel layer CH or the memory cells (first memory cells MC1 to the i-th memory cells MCI).

[0060] Therefore, according to one embodiment of the present disclosure, the operational performance of a memory device can be enhanced by improving the structure of the stacked structure STK.

[0061] Figures 4A to 4FThis is a diagram illustrating a method for manufacturing a memory device according to an embodiment of the present disclosure.

[0062] Reference Figure 4A This can form a preliminary laminated structure pSTK, which includes a sacrificial layer SF and an interlayer insulating layer IL. The sacrificial layer SF and the interlayer insulating layer IL can be stacked alternately in the Z direction.

[0063] Each of the interlayer insulating layers IL may include an insulating material. For example, the interlayer insulating layer IL may include an oxide layer. The interlayer insulating layer IL may include a silicon oxide layer or a corresponding oxide material. The sacrificial layer SF may include a material that is selectively removed during subsequent processes. Therefore, the sacrificial layer SF may have a different etch selectivity than the interlayer insulating layer IL. The sacrificial layer SF may include a nitride material. For example, the sacrificial layer SF may include a silicon nitride layer.

[0064] Subsequently, an opening OP extending in the Z-direction can be formed in the initial laminated structure pSTK. The opening OP can penetrate the sacrificial layer SF and the interlayer insulating layer IL. The opening OP can be in the shape of a hole extending in the Z-direction. The side surfaces of the sacrificial layer SF and the interlayer insulating layer IL can be exposed through the side surfaces of the opening OP.

[0065] Reference Figure 4B The sacrificial pattern SP can be formed on the interlayer insulating layer IL exposed through the opening OP. The sacrificial pattern SP can be selectively deposited on the side surfaces of the interlayer insulating layer IL. For example, the sacrificial pattern SP can be grown from the surface of the interlayer insulating layer IL. The sacrificial pattern SP can include an insulating material. The sacrificial pattern SP can include the same type of material as the interlayer insulating layer IL. For example, the sacrificial pattern SP can include an oxide layer. The sacrificial pattern SP can include a silicon oxide layer or a corresponding oxide material.

[0066] The sacrificial pattern SP may project vertically from the side surface of the interlayer insulation layer IL in the horizontal direction. The inner surface of each of the sacrificial patterns SP may be a circular surface facing the center of the opening OP. Alternatively, the inner surface of each of the sacrificial patterns SP may be a convex surface facing the center of the opening OP. The height (e.g., length in the Z direction) of each of the sacrificial patterns SP may increase towards the interlayer insulation layer IL. The outer surface of the sacrificial pattern SP may contact the interlayer insulation layer IL. Furthermore, the outer surface of the sacrificial pattern SP may extend in the Z direction. Each of the sacrificial patterns SP may have an annular shape. The sacrificial patterns SP may be spaced apart from each other in the Z direction.

[0067] Reference Figure 4CThe barrier layer BX can be formed on the sacrificial layer SF and the sacrificial pattern SP. The barrier layer BX can extend on the sacrificial layer SF and the sacrificial pattern SP. The barrier layer BX can be conformally formed on the sacrificial layer SF and the sacrificial pattern SP. The barrier layer BX can include a high-k material.

[0068] Because the sacrificial pattern SP protrudes from the interlayer insulation layer IL, the barrier layer BX can have an uneven structure defined by the surfaces of the sacrificial pattern SP and the sacrificial layer SF. The barrier layer BX may include a vertical portion VP that contacts the sacrificial layer SF and a recessed portion CP that contacts the sacrificial pattern SP. The vertical portion VP may extend in the Z-direction. The recessed portion CP may surround the sacrificial pattern SP. The barrier layer BX may include a recess RC located between the sacrificial patterns SP arranged sequentially in the Z-direction.

[0069] Reference Figure 4D Data storage patterns DS can be formed in the opening OP. Data storage patterns DS can be spaced apart from each other in the Z direction. For example, data storage patterns DS can be formed between consecutive sacrificial patterns SP in the Z direction. Data storage patterns DS can be separated from each other in the Z direction by sacrificial patterns SP and barrier layers BX. Each of the data storage patterns DS can have an annular shape. Either the recessed portion CP of the barrier layer BX or the sacrificial pattern SP can be formed between adjacent data storage patterns DS in the Z direction.

[0070] Each of the data storage patterns DS can be positioned between the recessed portions CP of the barrier layer BX. The data storage pattern DS can contact the vertical portion VP of the barrier layer BX. The data storage pattern DS can be located in the horizontal direction of the sacrificial layer SF.

[0071] The recesses included in the barrier layer BX (e.g., Figure 4C The recesses (RC) in the data storage pattern (DS) can be filled with data storage material. For example, the data storage material can fill the barrier layer (BX) in the recesses (RC). Figure 4C The data storage material may include a nitride layer. The data storage material may cover the entire surface of the barrier layer BX. Subsequently, the data storage material can be removed from the lower part of the opening OP and the side surfaces of the barrier layer BX. A dry etching process can be performed to remove a portion of the data storage material. For example, anisotropic dry etching can be performed so that the data storage material remains within the barrier layer BX. Figure 4C In the recessed RC portion. In anisotropic dry etching, a source gas with higher etching selectivity for data storage materials compared to the barrier layer BX can be used. Retained in Figure 4C The data storage material in the recessed portion RC can be the data storage pattern DS.

[0072] Subsequently, the tunneling layer TX, the channel layer CH, and the core post CO can be sequentially formed in the opening OP. The tunneling layer TX can contact the data storage pattern DS and the barrier layer BX in the opening OP. The tunneling layer TX can contact at least a portion of each of the recessed portions CP of the barrier layer BX. The tunneling layer TX can be conformally formed on the side surfaces of the data storage pattern DS and the barrier layer BX. The channel layer CH can contact the inner surface of the tunneling layer TX. The channel layer CH can be conformally formed on the side surface of the tunneling layer TX. The core post CO can contact the inner surface of the channel layer CH and fill the opening OP. The barrier layer BX, the data storage pattern DS, the tunneling layer TX, the channel layer CH, and the core post CO can form a cell plug CPL. However, the structure and shape of the cell plug CPL are not limited to these parameters. Figure 4D The structure and shape are shown. For example, the capping layer can also be formed on the core post CO. Furthermore, the shape of the barrier layer BX can vary depending on the shape of the sacrificial pattern SP. The tunneling layer TX can include an oxide layer. The channel layer CH can include a doped silicon layer or an undoped silicon layer. The core post CO can include an insulating layer or a conductive layer.

[0073] Reference Figure 4E The sacrificial layer SF can be replaced by the conductive layer CD. For example, an etching process can be performed to remove the sacrificial layer SF. Because the sacrificial layer SF is formed between the interlayer insulating layers IL, isotropic dry etching or wet etching can be performed as the etching process. Because the sacrificial layer SF is removed, empty spaces are formed between the interlayer insulating layers IL. The conductive layer CD can be formed in these spaces. The conductive layer CD can include at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polysilicon (Poly-Si). In addition, various other conductive layers can be formed.

[0074] Reference Figure 4F The interlayer insulating layer IL and the sacrificial pattern SP can be removed to form an air gap AG. Isotropic wet etching can be performed to selectively etch the interlayer insulating layer IL and the sacrificial pattern SP. The space where the interlayer insulating layer IL has been removed can correspond to a first portion P1 of the air gap AG. The first portion P1 can be located between conductive layers CD. The space where the sacrificial pattern SP has been removed can correspond to a second portion P2 of the air gap AG. The second portion P2 can extend in the X direction from the first portion P1 toward the cell plug CPL across the conductive layer CD. A stacked structure STK can be formed by the conductive layers CD separated from each other by the air gap AG.

[0075] Figures 5A to 5C This is a diagram illustrating the structure of a memory device according to an embodiment of the present disclosure.

[0076] Figures 5A to 5C Showing the example of Figure 3Other embodiments with some changes to the configuration of the illustrated unit plug CP1. Combined with... Figures 5A to 5C The description will be brief or omitted. Figure 3 The description of the repeated portion of the configuration of the unit plug CPL shown.

[0077] Reference Figure 5A The unit plug CPL may include a first barrier layer BX1 that contacts the side surface of the conductive layer CD. The first barrier layer BX1 may correspond to, for example, Figure 3 The barrier layer BX is shown. The first barrier layer BX1 may include a vertical portion VP and a recessed portion CP. The second portion P2 of the air gap AG may be surrounded by the recessed portion CP of the first barrier layer BX1. The second portion P2 of the air gap AG may be defined by the outer surface of the first barrier layer BX1. The first portion P1 of the air gap AG may be defined by the lower surface and the upper surface of the conductive layer CD.

[0078] The unit plug CPL may include a second barrier layer BX2 that contacts at least a portion of the inner surface of the first barrier layer BX1. The second barrier layer BX2 may be formed on at least a portion of the inner surface of the first barrier layer BX1. For example, the second barrier layer BX2 may be formed on the inner surface of the vertical portion VP of the first barrier layer BX1. Furthermore, the second barrier layer BX2 may be formed on at least a portion of the inner surface of the recessed portion CP of the first barrier layer BX1. The second barrier layer BX2 may extend on the inner surface of the first barrier layer BX1 between air gaps AG. The second barrier layer BX2 may include a high-k material. The second barrier layer BX2 may be made of the same type of material as the first barrier layer BX1.

[0079] The second barrier layer BX2 may extend in the Z direction over the first barrier layer BX1. Alternatively, the second barrier layer BX2 may be separated from the first barrier layer BX1 in the Z direction. The inner surface of the first barrier layer BX1 may be completely covered by the second barrier layer BX2, or a portion of the inner surface of the first barrier layer BX1 may be exposed and in contact with the tunneling layer TX.

[0080] The cell plug CPL may include a data storage pattern DS surrounded by a second barrier layer BX2. The data storage pattern DS may contact the second barrier layer BX2. The data storage pattern DS may be separated from the first barrier layer BX1 through the second barrier layer BX2.

[0081] Because besides Figure 3 In addition to the implementation methods, Figure 5A The implementation also includes a second barrier layer BX2, which can improve the blocking performance of the unit plug CP1.

[0082] Reference Figure 5BThe unit plug CPL may include a first blocking pattern BP1. The first blocking patterns BP1 may be spaced apart from each other in the Z direction. The first blocking patterns BP1 may be separated from each other in the Z direction through an air gap AG. The first blocking pattern BP1 may contact a side surface of the conductive layer CD. The first blocking pattern BP1 may surround a second portion P2' of the air gap AG. The surface SSb1 of the first blocking pattern BP1 may be exposed through the second portion P2' of the air gap AG.

[0083] The unit plug CPL may include a second blocking pattern BP2. The second blocking patterns BP2 may be spaced apart from each other in the Z direction. The second blocking patterns BP2 may be separated from each other in the Z direction through an air gap AG. The second blocking patterns BP2 may contact the inner surface of the first blocking pattern BP1 respectively. The second blocking patterns BP2 may surround a second portion P2' of the air gap AG. The surface SSb2 of the second blocking pattern BP2 may be exposed through the second portion P2' of the air gap AG. However, with... Figure 5B Conversely, the second blocking pattern BP2 may not contact the second part P2'.

[0084] The first blocking pattern BP1 and the second blocking pattern BP2 may include a high-k material. The first blocking pattern BP1 and the second blocking pattern BP2 may include the same or similar materials.

[0085] The unit plug CPL may include data storage patterns DS separated from each other in the Z direction. The data storage patterns DS are separated from each other in the Z direction via an air gap AG. The data storage patterns DS may contact the inner surface of the second blocking pattern BP2. The data storage patterns DS may surround a second portion P2' of the air gap AG. The surface SSd of the data storage patterns DS may be exposed through the second portion P2' of the air gap AG.

[0086] However, besides Figure 3 and Figure 5A In addition to various implementation methods, the data storage pattern DS can be exposed via an air gap AG. For example... Figure 5B As shown, with Figure 5A Compared to other embodiments, a portion of the first barrier layer BX1 and a portion of the second barrier layer BX2 can be removed to form a first barrier pattern BP1 and a second barrier pattern BP2. The volume of each of the data storage patterns DS can be increased by an amount equal to the space from which the portion of the first barrier pattern BP1 and the portion of the second barrier pattern BP2 have been removed.

[0087] The tunneling layer TX can contact the inner surface of the data storage pattern DS. The tunneling layer TX can be separated from the first blocking pattern BP1 and the second blocking pattern BP2 through the data storage pattern DS. The tunneling layer TX can be surrounded by the second portion P2' of the air gap AG. The surface SSt of the tunneling layer TX can be exposed through the second portion P2' of the air gap AG.

[0088] Although not shown, but referenced Figure 4C and Figure 5B A first barrier layer can be formed on the sacrificial layer SF and the sacrificial pattern SP, and a portion of the first barrier layer on the sacrificial pattern SP can be removed to form a first barrier pattern BP1. Furthermore, a second barrier layer can be formed on the sacrificial pattern SP and the first barrier pattern BP1, and a portion of the second barrier layer on the sacrificial pattern SP can be removed to form a second barrier pattern BP2. Subsequently, a data storage pattern DS that contacts the second barrier pattern BP2 and is separated from each other by the sacrificial pattern SP can be formed. The sacrificial layer SF can be replaced by a conductive layer CD, and the interlayer insulating layer IL and the sacrificial pattern SP can be removed to form an air gap AG, each of which includes a first portion P1 and a second portion P2'.

[0089] Reference Figure 5C ,Apart from Figure 5B In addition to the above implementation, the unit plug CPL may also include a third blocking pattern BP3. Each of the third blocking patterns BP3 may be disposed between the first blocking patterns BP1. The third blocking patterns BP3 may connect with the first blocking patterns BP1 that are separated from each other. The third blocking patterns BP3 may contact the first blocking patterns BP1 arranged sequentially in the Z direction. According to one implementation, the third blocking pattern BP3 may contact the second blocking patterns BP2 arranged sequentially in the Z direction.

[0090] The third blocking pattern BP3 may surround the second portion P2” of the air gap AG. The second portion P2” may be defined by the third blocking pattern BP3. The first blocking pattern BP1 and the second blocking pattern BP2 may pass through the third blocking pattern BP3 without being exposed to the air gap AG. The third blocking pattern BP3 may be made of the same type of material as the first blocking pattern BP1 and the second blocking pattern BP2. The edge field of the conductive layer CD may be compensated by the third blocking pattern BP3.

[0091] The data storage pattern DS can contact the third barrier pattern BP3. The third barrier pattern BP3 prevents the data storage pattern DS from contacting the air gap AG. The air gap AG can be defined by the conductive layer CD and the third barrier pattern BP3.

[0092] Although not shown, but as referenced above Figure 5BFollowing the manufacturing process, a third barrier pattern BP3 can be formed in the air gap AG. For example, the third barrier pattern BP3 can cover the cell plug CPL exposed through the air gap AG.

[0093] Figure 6 This is a diagram illustrating a memory card system 3000 using a memory device according to an embodiment of the present disclosure.

[0094] Reference Figure 6 The memory card system 3000 may include a controller 3100, a memory device 3200, and a connector 3300.

[0095] Controller 3100 can be coupled to memory device 3200. Controller 3100 can be configured to access memory device 3200. For example, controller 3100 can control programming operations, read operations, erase operations, or background operations of memory device 3200. Controller 3100 can be configured to provide an interface between memory device 3200 and a host. Controller 3100 can be configured to drive firmware for controlling memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0096] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) according to a specific communication protocol. For example, controller 3100 can be configured to communicate with external devices via at least one of various communication protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 3300 can be defined by at least one of the aforementioned communication protocols.

[0097] Memory device 3200 may include multiple memory cells and can be connected with Figure 1 The memory device 100 shown is configured in the same manner.

[0098] The controller 3100 and memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and memory device 3200 can form a memory card such as a personal computer (PC) card (PCMCIA International Association) card, compact flash memory card (CF), smart media card (SM and SMC), memory stick, multimedia card (MMC, RS-MMC, MMCmicro or eMMC), SD card (SD, miniSD, microSD or SDHC) and universal flash memory (UFS).

[0099] Figure 7 This is a diagram illustrating a solid-state drive (SSD) system 4000 to which an embodiment of the memory device according to the present disclosure is applied.

[0100] Reference Figure 7 The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 can exchange signals with the host 4100 through a signal connector 4001 and can receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0101] The controller 4210 can control multiple memory devices 4221 to 422n in response to signals received from the host 4100. For example, the signals can be based on the interface between the host 4100 and the SSD 4200. For example, the signals can be defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0102] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n can be connected to... Figure 1 The memory devices 100 shown are configured in the same manner. Multiple memory devices 4221 to 422n can communicate with the controller 4210 via channels CH1 to CHn.

[0103] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can receive power from host 4100 and charge it. When the power supply from host 4100 is unstable, auxiliary power supply 4230 can provide power to SSD 4200. For example, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located on the motherboard and provide auxiliary power to SSD 4200.

[0104] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 can temporarily store data received from host 4100 or data received from multiple memory devices 4221 to 422n, or it can temporarily store metadata (e.g., mapping tables) of memory devices 4221 to 422n. Buffer memory 4240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM and PRAM.

[0105] According to various embodiments of this disclosure, the operating performance of a memory device can be improved by reducing the parasitic capacitance between conductive layers and the parasitic capacitance between the conductive layer and the channel layer.

[0106] It will be apparent to those skilled in the art that various modifications can be made to the above-described examples of the embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is intended to cover all such modifications, provided they fall within the scope of the appended claims and their equivalents.

[0107] Cross-reference to related applications

[0108] This application claims priority to Korean Patent Application No. 10-2024-0124650, filed on September 12, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: A stacked structure comprising conductive layers spaced apart from each other in a first direction; A unit plug, the unit plug being located in the stacked structure and extending in the first direction; as well as An air gap, defined by the unit plug and the conductive layer, is located between the conductive layers. The air gap extends toward the unit plug and across the conductive layer in a second direction that intersects with the first direction.

2. The memory device according to claim 1, wherein, Each of the air gaps includes: A first portion, the first portion being located between the conductive layers; and The second part extends from the first part toward the unit plug in the second direction.

3. The memory device according to claim 2, wherein, The first portion is defined by the upper and lower surfaces of the conductive layer, respectively.

4. The memory device according to claim 2, in, The side surface of the unit plug includes a concave surface, and The second part is defined by the concave surface of the unit plug.

5. The memory device according to claim 1, in, The unit plug includes a blocking layer. The barrier layer includes: Vertical portions, each contacting a side surface of the conductive layer; and The recessed portion bends inward toward the center of the unit plug, and Each of the recessed portions is located between the conductive layers.

6. The memory device according to claim 5, wherein, The air gaps are defined by the recessed portions of the barrier layer.

7. The memory device according to claim 1, wherein, The unit plug includes data storage patterns spaced apart from each other in the first direction via the air gap.

8. The memory device according to claim 7, wherein, At least a portion of each of the data storage patterns is located at the same height as the conductive layer.

9. The memory device according to claim 1, wherein, The unit plug includes: A channel layer that penetrates the conductive layer; Tunneling layer, the tunneling layer surrounding the trench layer; and A core post, which is surrounded by the channel layer.

10. The memory device according to claim 1, wherein, The unit plug includes: A first barrier layer, the first barrier layer contacting a side surface of the conductive layer; and A second barrier layer is in contact with at least a portion of the inner surface of the first barrier layer.

11. The memory device according to claim 10, wherein, The second barrier layer extends on the inner surface of the first barrier layer between the air gaps.

12. The memory device according to claim 10, wherein, The unit plug also includes a data storage pattern surrounded by the second barrier layer.

13. The memory device according to claim 1, wherein, The unit plug includes: A first blocking pattern, wherein the first blocking pattern respectively contacts the side surface of the conductive layer; A second blocking pattern, the second blocking pattern respectively contacting the inner surface of the first blocking pattern; and Data storage patterns, wherein the data storage patterns respectively contact the inner surface of the second blocking pattern.

14. The memory device according to claim 13, wherein, The first blocking pattern and the data storage pattern are exposed through the air gap.

15. The memory device according to claim 13, wherein, The first blocking patterns are separated from each other in the first direction through the air gap, and The second blocking patterns are separated from each other in the first direction through the air gap.

16. The memory device according to claim 13, wherein, The data storage patterns are separated from each other in the first direction through the air gap.

17. The memory device according to claim 13, wherein, The unit plug also includes a third blocking pattern disposed between the first blocking patterns.

18. The memory device according to claim 17, wherein, The air gaps are defined by the third blocking pattern.

19. The memory device according to claim 17, wherein, The third blocking pattern contacts both the first blocking pattern and the data storage pattern.

20. A method of manufacturing a memory device, the method comprising the steps of: A laminated structure comprising a sacrificial layer and an interlayer insulating layer is formed, wherein the sacrificial layer and the interlayer insulating layer are alternately laminated to each other in a first direction; An opening extending in the first direction is formed in the stacked structure; A sacrificial pattern is formed on the side surface of the interlayer insulation layer exposed through the opening; A unit plug is formed in the opening in which the sacrificial pattern is formed; Replace the sacrificial layer with a conductive layer; and An air gap is formed by removing the interlayer insulation layer and the sacrificial pattern.

21. The method according to claim 20, wherein, The step of forming the unit plug includes the following steps: forming a barrier layer extending on the sacrificial layer and the sacrificial pattern, and The barrier layer includes a vertical portion that contacts the sacrificial layer and a recessed portion that contacts the sacrificial pattern.

22. The method according to claim 21, wherein, The step of forming the unit plug further includes the step of forming a data storage pattern between the recessed portions of the barrier layer that contacts the vertical portion.

23. The method according to claim 22, wherein, The step of forming the unit plug further includes the following steps: A tunneling layer is formed that contacts the barrier layer and the data storage pattern; A channel layer is formed on the inner surface of the tunneling layer; and A core pillar is formed by the channel layer surrounding it.

24. The method of claim 20, wherein, In the step of forming the air gap, each of the air gaps includes a first portion located between the conductive layers and a second portion extending from the first portion toward the cell plug.

25. The method according to claim 20, wherein, The steps for forming the unit plug include the following: A first barrier layer extending on the sacrificial layer and the sacrificial pattern; and A second barrier layer is formed that contacts at least a portion of the inner surface of the first barrier layer.

26. The method of claim 20, wherein, The steps for forming the unit plug include the following: A first barrier layer is formed extending on the sacrificial layer and the sacrificial pattern; The first blocking pattern is formed by removing a portion of the first blocking layer located on the sacrificial pattern; A second barrier layer is formed on the sacrificial pattern and the first barrier pattern; and The second blocking pattern is formed by removing a portion of the second blocking layer located on the sacrificial pattern.

27. The method according to claim 26, wherein, The step of forming the unit plug includes the following steps: forming data storage patterns that respectively contact the second blocking pattern and are spaced apart from each other by the sacrificial pattern.

28. The method of claim 27, further comprising the step of: After the step of forming the air gap, a third blocking pattern is formed that contacts the first blocking pattern and the data storage pattern exposed through the air gap.

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