Memory and forming method thereof

Abstract

The invention discloses a memory and a forming method thereof, the memory comprises a first conductive layer and a second conductive layer, the first conductive layer comprises at least one first conductive structure, and the first conductive structure comprises a first end face facing the second conductive layer and a first cross section parallel to the first end face. The size of the first end face is smaller than that of the first section; the second conductive layer comprises a plurality of second conductive structures, each second conductive structure comprises a second end face facing the first conductive layer and a second cross section parallel to the second end face, and the size of the second end face is smaller than that of the second cross section; each first end face is at least partially coplanar with one second end face. According to the invention, even if the second conductive structure has a certain degree of alignment offset in the etching process, the safe interval is still kept between the second conductive structure and the adjacent first conductive structure, so that the electric leakage risk of the memory is reduced, and the reliability of the memory is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor-related technologies, and in particular to a memory and a method for forming the same. Background Technology

[0002] 3D memory, including 3D phase change memory (3D PCM) and 3D selective memory (3D SOM), expands storage cells vertically through a multi-layered stacked structure, significantly improving storage density and capacity. This technology combines non-volatility, high speed, and low power consumption, representing an important development direction for next-generation high-density memory devices.

[0003] During the manufacturing process of 3D memory, the numerous metal wires and contact structures between different layers, along with the complex interlayer relationships, make it highly susceptible to forming potential leakage paths. These potential leakage paths not only increase device power consumption but also affect data retention characteristics and overall reliability. Summary of the Invention

[0004] This application provides a memory and a method for forming the same, which aims to reduce the risk of leakage current in the memory and improve the reliability of the memory.

[0005] To achieve the above objectives, according to a first aspect of this application, a memory is provided, comprising: First conductive layer and second conductive layer The first conductive layer includes at least one first conductive structure, the first conductive structure including a first end face facing the second conductive layer and a first cross-section parallel to the first end face, the size of the first end face being smaller than the size of the first cross-section; The second conductive layer includes a plurality of second conductive structures, each of which includes a second end face facing the first conductive layer and a second cross-section parallel to the second end face, wherein the size of the second end face is smaller than the size of the second cross-section. Each of the first end faces is at least partially coplanar with one of the second end faces.

[0006] Optionally, the first end face is located within the second end face, or the second end face is located within the first end face, or the first end face and the second end face are partially offset from each other; the distance between the edge of the first end face and the edge of the adjacent second end face is less than or equal to 1 nm.

[0007] Optionally, the first conductive structure further includes a third cross section parallel to the first cross section and located on the side of the first cross section away from the first end face; the size of any of the third cross sections is greater than the size of the first cross section, or at least one of the third cross sections has a size smaller than the size of the first cross section.

[0008] Optionally, the second conductive structure further includes a fourth cross section parallel to the second cross section and located on the side of the second cross section away from the second end face; the size of any of the fourth cross sections is greater than the size of the second cross section, or at least one of the fourth cross sections has a size smaller than the size of the second cross section.

[0009] Optionally, the difference between the size of the first end face and the size of the first cross section is in the range of [1,2] nm, and the difference between the size of the second end face and the size of the second cross section is in the range of [1,2] nm.

[0010] Optionally, it also includes: Base; A first storage array, located on the substrate, includes a first storage cell arranged in an array; The second storage array is located on the side of the first storage array away from the substrate, and includes a second storage cell array. The first conductive layer and the second conductive layer are located between the first memory array and the second memory array, and the second conductive layer is located between the first conductive layer and the second memory array; the first conductive layer includes a plurality of first conductive structures that are parallel to each other and extend along a first direction, and the first conductive structures are connected to a plurality of first memory cells arranged along the first direction; the second conductive layer includes a plurality of second conductive structures that are parallel to each other and extend along the first direction, and the second conductive structures are connected to a plurality of second memory cells arranged along the first direction; the second conductive structures are connected to the first conductive structures one by one.

[0011] Optionally, it also includes: Base; A first storage array, located on the substrate, includes first storage cells arranged in an array within an array region, and a first conductive structure located in a peripheral region; The second conductive layer is located on the side of the first memory array away from the substrate, and includes a plurality of second conductive structures that are parallel to each other and extend along a first direction. The second conductive structures are connected to a plurality of first memory cells arranged along the first direction and connected to one of the first conductive structures.

[0012] Optionally, each of the first memory cells includes a first electrode layer, a bidirectional threshold switch layer, a second electrode layer, a phase change layer, and a third electrode layer sequentially stacked on the substrate; or, Each of the first memory cells includes a first electrode layer, a bidirectional threshold switch layer, and a second electrode layer, which are sequentially stacked on the substrate.

[0013] According to a second aspect of this application, a method for forming a memory is provided, comprising: A first conductive layer is formed, the first conductive layer including at least one first conductive structure; An initial second conductive layer is formed that is stacked and in contact with the first conductive layer; The initial second conductive layer is patterned to form a second conductive layer, which includes a plurality of second conductive structures; After the patterning process, the second conductive structure includes a second end face facing the first conductive layer and a second cross section parallel to the second end face, the size of the second end face being smaller than the size of the second cross section; the first conductive structure includes a first end face facing the second conductive layer and a first cross section parallel to the first end face, the size of the first end face being smaller than the size of the first cross section; each first end face and a second end face are at least partially coplanar.

[0014] Optionally, the patterning process of the initial second conductive layer includes: A mask layer is formed on the side of the initial second conductive layer that is opposite to the first conductive layer; Using the mask layer as a template, the initial second conductive layer and one end of the first conductive structure facing the second conductive layer are etched.

[0015] In the technical solution of this application, the second conductive structure is a higher layer structure than the first conductive structure. The initial second conductive layer is patterned to form a second conductive layer comprising multiple second conductive structures. After patterning, the second conductive structure includes a second end face facing the first conductive layer and a second cross-section parallel to the second end face, with the size of the second end face being smaller than the size of the second cross-section. The first conductive structure includes a first end face facing the second conductive layer and a first cross-section parallel to the first end face, with the size of the first end face being smaller than the size of the first cross-section. Each first end face and a second end face are at least partially coplanar. With this configuration, even if the second conductive structure experiences a certain degree of alignment misalignment during patterning, because the size of the first conductive structure near the second conductive structure is smaller, and the size of the second conductive structure near the first conductive structure is also smaller, the distance between the end of the first conductive structure facing the second conductive structure and the adjacent second conductive structure will correspondingly increase. Therefore, a safe distance can still be maintained between the second conductive structure and the adjacent first conductive structure, thereby reducing the risk of contact or short circuit between the second conductive structure and the adjacent first conductive structure, and improving the reliability of the memory.

[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0018] Figure 1 This is a schematic diagram of the structure of a memory disclosed in an embodiment of this application; Figure 2 yes Figure 1 A cross-sectional view of the memory shown along section line A-A1; Figure 3 yes Figure 2 Enlarged view of point C in the middle; Figure 4 This is a schematic diagram of the structure of a memory disclosed in another embodiment of this application; Figure 5 This is a schematic diagram of the structure of a memory disclosed in another embodiment of this application; Figure 6 yes Figure 5 A cross-sectional view of the memory shown along section line B-B1. Figures 7 to 8 This is a cross-sectional structural schematic diagram of the memory formation process according to an embodiment of this application; Figure 9 This is a cross-sectional structural schematic diagram of the memory formation process according to another embodiment of this application.

[0019] Explanation of reference numerals in the attached figures: 1. First conductive layer; 11. First conductive structure; 111. First end face; 112. First cross-section; 113. Third cross-section; 2. Second conductive layer; 21. Second conductive structure; 211. Second end face; 212. Second cross section; 213. Fourth cross section; 3. Substrate; 31. Array region; 32. Peripheral region; 4. First storage array; 41. First storage cell; 5. Second storage array; 51. Second storage unit; 61. First electrode layer; 62. Bidirectional threshold switch layer; 63. Second electrode layer; 64. Phase transition layer; 65. Third electrode layer; 7. Isolation layer; 8. Third conductive layer; 81. Third conductive structure; 9. Initial second conductive layer. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0021] As described in the background section, during the manufacturing process of 3D memory, the presence of numerous metal wires and contact structures between different layers, coupled with the complex interlayer relationships, makes it highly susceptible to the formation of potential leakage paths during the process. These potential leakage paths not only increase device power consumption but also affect data retention characteristics and overall reliability.

[0022] In the fabrication of 3D memory, a via interconnect layer is typically formed first to bring out the signals from the word lines (or bit lines). Subsequently, the word line layer (or bit line layer) is deposited and patterned to define the conductive lines. However, because the via interconnect layer and the word line layer (or bit line layer) are formed at different stages, and the via interconnect layer is fixed, if the photolithography alignment is insufficient or the etching morphology shifts during subsequent etching of the word line layer (or bit line layer), misalignment can easily occur between the word line (or bit line) and the via interconnect layer, resulting in non-target contact. This can lead to contact between the word line and adjacent word line via structures, causing localized leakage or short circuits, thus affecting the reliability of the device.

[0023] Similarly, in actual manufacturing processes, lower-level word lines (or lower-level bit lines) and upper-level word lines (or upper-level bit lines) are formed at different stages. After formation, the position of the lower-level word lines (or lower-level bit lines) is fixed. When the upper-level word lines (or upper-level bit lines) are patterned, if alignment or process control is inaccurate, upper-level word lines may contact adjacent lower-level word lines or upper-level bit lines may contact adjacent lower-level bit lines. These alignment deviations can create potential leakage paths in the multilayer stacked structure, thereby affecting the reliability of the device. Therefore, to reduce the leakage risk of the memory and improve its reliability, embodiments of this application provide a memory.

[0024] Reference Figure 1 and Figure 2 , Figure 2 yes Figure 1 The cross-sectional view of the memory shown is along the A-A1 section line. An embodiment of the memory in this application includes: First conductive layer 1 and second conductive layer 2 The first conductive layer 1 includes at least one first conductive structure 11, the first conductive structure 11 including a first end face 111 facing the second conductive layer 2 and a first cross section 112 parallel to the first end face 111, the size of the first end face 111 being smaller than the size of the first cross section 112; The second conductive layer 2 includes a plurality of second conductive structures 21. Each second conductive structure 21 includes a second end face 211 facing the first conductive layer 1 and a second cross section 212 parallel to the second end face 211. The size of the second end face 211 is smaller than the size of the second cross section 212. Each of the first end faces 111 and a second end face 211 is at least partially coplanar.

[0025] The following will be described in detail with reference to the accompanying drawings.

[0026] The memory includes a first direction, a second direction, and a third direction. The first and second directions are parallel to the surface of the substrate 3, the third direction is perpendicular to the surface of the substrate 3, and the first and second directions intersect.

[0027] In some embodiments, the memory further includes a substrate 3 and a third conductive layer 8.

[0028] Specifically, in some embodiments, the substrate 3 may include a substrate and a control circuit layer located on the substrate. The substrate may be a semiconductor substrate 3, such as silicon (Si), germanium (Ge), SiGe, silicon on insulator (SOI), or germanium on insulator (GOI). The control circuit layer may include complementary metal-oxide-semiconductor (CMOS).

[0029] The first storage array 4 is located on the substrate 3. The first storage array 4 includes a plurality of first storage cells 41 arranged in an array.

[0030] The third conductive layer 8 is located between the substrate 3 and the first memory array 4. The third conductive layer 8 includes a plurality of parallel third conductive structures 81 extending along a second direction. The third conductive structures 81 connect to a plurality of first memory cells 41 arranged along the second direction, and are electrically connected to the substrate 3 through conductive vias. The third conductive structures 81 can be word lines or bit lines. The material of the third conductive layer 8 can be tungsten.

[0031] In this embodiment, the first storage unit 41 is a phase change storage unit, and each first storage unit 41 includes a first electrode layer 61, a bidirectional threshold switch layer 62, a second electrode layer 63, a phase change layer 64 and a third electrode layer 65, which are sequentially stacked on the substrate 3.

[0032] In some other embodiments, the first storage unit 41 is a selectable storage unit, see reference. Figure 4 Each first storage cell 41 includes a first electrode layer 61, a bidirectional threshold switch layer 62, and a second electrode layer 63, which are sequentially stacked on the substrate 3.

[0033] The materials of the first electrode layer 61, the second electrode layer 63, and the third electrode layer 65 can be the same, and all can be carbon materials. The material of the bidirectional threshold switch layer 62 can include Znx Tey, Gex Tey, Nbx Oy, Six Asy, Asx Tey, etc. The material of the phase change layer 64 can include chalcogenide-based materials, which include any one of the four elements forming Group VIA of the periodic table: oxygen (O), sulfur (S), selenium (Se), and tellurium (Te).

[0034] The second conductive layer 2 is stacked with the first conductive layer 1 along a third direction, and the second conductive layer 2 is connected to the first conductive layer 1. Specifically, in this embodiment, the second conductive layer 2 is located on the side of the first memory array 4 away from the substrate 3. The second conductive layer 2 includes a plurality of parallel second conductive structures 21 extending along a first direction. In this embodiment, the plurality of second conductive structures 21 are spaced apart along a second direction. The second conductive structures 21 are connected to a plurality of first memory cells 41 arranged along the first direction. Each second conductive structure 21 is connected to a first conductive structure 11, and the end of the first conductive structure 11 facing away from the second conductive structure 21 is connected to the substrate 3.

[0035] In other words, in this embodiment, the second conductive structure 21 is a conductive layer formed on the side of the first memory array 4 away from the substrate 3, and is used as a word line or bit line; the first conductive layer 1 acts as a via connection layer, and is used to connect the second conductive structure 21 and the substrate 3 in the third direction, so as to bring out the signal of the second conductive structure 21.

[0036] Further, in this embodiment, the second conductive structure 21 includes a second end face 211 facing the first conductive layer 1 and a second cross section 212 parallel to the second end face 211, wherein the size of the second end face 211 is smaller than the size of the second cross section 212. In other words, the second conductive structure 21 is configured as a constricted end near the first conductive structure 11, giving it a smaller size in the second direction at the end near the first conductive structure 11. It should be noted that in Figure 2 In one specific embodiment shown, the second end face 211 and the second cross-section 212 are parallel to the first direction and the second direction, and perpendicular to the third direction. The second cross-section 212 is the cross-section indicated by the dashed line. In some other embodiments, the second cross-section 212 may also be any cross-section between the dashed line and the second end face 211. The dimension of the second end face 211 is the dimension of the second end face 211 in the second direction, and the dimension of the second cross-section 212 is the dimension of the second cross-section 212 in the second direction.

[0037] In this embodiment, the first conductive layer 1 includes at least one first conductive structure 11. First storage cells 41 arranged in an array are located in the array region 31, and the first conductive structure 11 is located in the peripheral region 32. An isolation layer 7 is provided between adjacent first storage cells 41 and in the peripheral region 32. The material of the isolation layer 7 includes, but is not limited to, insulating dielectric materials such as spin-on dielectric (SOD).

[0038] Furthermore, the first conductive structure 11 includes a first end face 111 facing the second conductive layer 2 and a first cross section 112 parallel to the first end face 111, wherein the size of the first end face 111 is smaller than the size of the first cross section 112.

[0039] Specifically, a first conductive structure 11 is formed in the peripheral region 32. The formation process of the first conductive structure 11 is typically as follows: first, a via penetrating the isolation layer 7 is formed in the isolation layer 7; then, conductive material is filled into the via to form the first conductive structure 11. During the etching of the isolation layer 7 along a third direction to form the through via, due to the influence of etching characteristics, the aperture of the via tends to decrease in the depth direction. (Refer to...) Figure 3 The first conductive structure 11 further includes a third section 113 parallel to the first section 112 and located on the side of the first section 112 away from the first end face 111, and at least one of the third sections 113 has a size smaller than the size of the first section 112. It should be noted that in... Figure 2 In one specific embodiment shown, the first end face 111, the first cross-section 112, and the third cross-section 113 are parallel to the first and second directions and perpendicular to the third direction. The first cross-section 112 and the third cross-section 113 are the cross-sections indicated by the corresponding dashed lines. In some other embodiments, the first cross-section 112 may also be any cross-section between the corresponding dashed line and the first end face 111. The third cross-section 113 may also be any cross-section of the first cross-section 112 away from the first end face 111. The dimension of the first end face 111 is the dimension of the first end face 111 in the second direction, the dimension of the first cross-section 112 is the dimension of the first cross-section 112 in the second direction, and the dimension of the third cross-section 113 is the dimension of the third cross-section 113 in the second direction.

[0040] It should be noted that, in the above embodiments, the spacing between adjacent first storage cells 41 is in the range of [19,21] nm; the difference between the size of the first end face 111 and the size of the first cross section 112 is in the range of [1,2] nm; and the difference between the size of the second end face 211 and the size of the second cross section 212 is in the range of [1,2] nm.

[0041] In this embodiment, the second conductive structure 21 is a higher layer structure than the first conductive structure 11. After the initial second conductive layer 9 is patterned, a second conductive layer 2 comprising multiple second conductive structures 21 is formed. After patterning, the second conductive structure 21 includes a second end face 211 facing the first conductive layer 1 and a second cross section 212 parallel to the second end face 211. The size of the second end face 211 is smaller than the size of the second cross section 212. Furthermore, during the patterning process of the second conductive structure 21, the end of the first conductive structure 11 facing the second conductive layer 2 can be simultaneously etched, so that the first conductive structure 11 includes a first end face 111 facing the second conductive layer 2 and a first cross section 112 parallel to the first end face 111. The size of the first end face 111 is smaller than the size of the first cross section 112. With this configuration, the second conductive structure 21 and the first conductive structure 11 both have contracted end morphologies in the areas where they are close to each other. Even if a certain degree of alignment misalignment occurs during the manufacturing process, sufficient spacing can still be maintained between the upper and lower conductive layers, thereby reducing the risk of electrical contact or short circuit between the conductive layers and improving the stability and reliability of the memory structure.

[0042] Meanwhile, in this embodiment, the above-mentioned structural features can be achieved simply by increasing the etching depth in the region of the second conductive layer 2 near the first conductive layer 1 when patterning the second conductive layer 2. This significantly improves the alignment tolerance (overlay window) of the process without introducing additional process steps. Compared with the solutions in other embodiments that reduce the overall size of the second conductive structure 21, the technical solution disclosed in this application only sets a smaller size at the end of the second conductive structure 21 facing the first conductive structure 11, which not only improves the reliability of the memory but also maintains the low resistance characteristics and current carrying capacity of the main conductive region.

[0043] exist Figure 2 In one specific embodiment shown, the first end face 111 and the second end face 211 are completely coplanar. In some other embodiments, the first end face 111 and the second end face 211 are partially coplanar. Specifically, in one embodiment, the first end face 111 is located within the second end face 211. In another embodiment, the second end face 211 is located within the first end face 111. In yet another embodiment, the first end face 111 and the second end face 211 are offset from each other and are partially planar. When the first end face 111 and the second end face 211 are partially coplanar, for the partially coplanar first end face 111 and the second end face 211, the distance between the edge of the first end face 111 and the edge of the adjacent second end face 211 is less than or equal to 1 nm; in other words, the distance between the edges of the first end face 111 and the second end face 211 on the same side is less than or equal to 1 nm.

[0044] Continue to refer to Figure 3In some embodiments, the second conductive structure 21 further includes a fourth section 213 parallel to the second cross-section 212 and located on the side of the second cross-section 212 away from the second end face 211. It should be noted that in... Figure 3 In one specific embodiment shown, the fourth section 213 is parallel to the first and second directions and perpendicular to the third direction. The fourth section 213 is the section indicated by the dashed line, and the dimensions of the fourth section 213 are all larger than the dimensions of the second section 212. In some other embodiments, the fourth section 213 can also be any section of the first section 112 away from the first end face 111. The dimensions of the fourth section 213 are the dimensions of the fourth section 213 in the second direction.

[0045] Furthermore, in some other embodiments, the end of the second conductive structure 21 that is away from the first memory array 4 also exhibits a contraction trend (i.e., the end that is away from the second end face 211), then there is at least one fourth cross section 213 with a size smaller than the size of the second cross section 212.

[0046] Reference Figure 5 and Figure 6 Another memory according to an embodiment of this application includes a second memory array 5 located on the side of the first memory array 4 away from the substrate 3, and includes second memory cells 51 arranged in an array.

[0047] Unlike the memory disclosed in the above embodiments, in this embodiment, the first conductive layer 1 and the second conductive layer 2 are located between the first memory array 4 and the second memory array 5, and the second conductive layer 2 is located between the first conductive layer 1 and the second memory array 5; the first conductive layer 1 includes a plurality of mutually parallel first conductive structures 11 extending along a first direction, and the first conductive structures 11 are connected to a plurality of first memory cells 41 arranged along the first direction; the second conductive layer 2 includes a plurality of mutually parallel second conductive structures 21 extending along the first direction, and the second conductive structures 21 are connected to a plurality of second memory cells 51 arranged along the first direction; the second conductive structures 21 are connected to the first conductive structures 11 in a one-to-one correspondence.

[0048] In other words, in this embodiment, the first conductive structure 11 is a conductive layer disposed on the side of the first memory array 4 away from the substrate 3, and is used as a lower word line or lower bit line between two adjacent memory arrays. The second conductive structure 21 is a conductive layer disposed on the side of the first conductive structure 11 away from the first memory array 4, and is used as an upper word line or upper bit line between two adjacent memory arrays.

[0049] Similar to the memory disclosed in the foregoing embodiments, in this embodiment, the second conductive structure 21 also includes a second end face 211 facing the first conductive layer 1 and a second cross section 212 parallel to the second end face 211, the size of the second end face 211 being smaller than the size of the second cross section 212. The first conductive structure 11 includes a first end face 111 facing the second conductive layer 2 and a first cross section 112 parallel to the first end face 111, the size of the first end face 111 being smaller than the size of the first cross section 112. In other words, the end of the first conductive structure 11 near the second conductive structure 21 is a contracted end, and the end of the second conductive structure 21 near the first conductive structure 11 is a contracted end. With this configuration, even if the first conductive structure 11 and the second conductive structure 21 experience a certain degree of alignment misalignment during the etching process, the second conductive structure 21 and the adjacent first conductive structure 11 can still maintain a safe distance, thereby reducing the risk of the second conductive structure 21 contacting or short-circuiting with the adjacent first conductive structure 11 and improving the reliability of the memory.

[0050] Continue to refer to Figure 6 ,exist Figure 6 In one specific embodiment shown, the third cross-section 113 is parallel to the first and second directions and perpendicular to the third direction. The third cross-section 113 is the cross-section indicated by the dashed line, and the size of the third cross-section 113 is larger than the size of the first cross-section 112. In some other embodiments, the third cross-section 113 can also be any cross-section of the first cross-section 112 away from the first end face 111. The size of the third cross-section 113 is the size of the third cross-section 113 in the second direction. Further, in some other embodiments, the end of the first conductive structure 11 facing the first memory array 4 also exhibits a contraction trend (i.e., the end away from the first end face 111), then at least one third cross-section 113 has a size smaller than the size of the first cross-section 112.

[0051] Furthermore, it should be noted that in this embodiment, each second storage unit 51 includes a first electrode layer 61, a bidirectional threshold switch layer 62, a second electrode layer 63, a phase change layer 64, and a third electrode layer 65, which are sequentially stacked on the second conductive layer 2 along the first direction. In some other embodiments, each second storage unit 51 includes a first electrode layer 61, a bidirectional threshold switch layer 62, and a second electrode layer 63, which are sequentially stacked on the second conductive layer 2 along the first direction.

[0052] It is worth mentioning that, compared with the solution that reduces the overall size of the second conductive structure 21, the technical solution disclosed in this embodiment only has a smaller size at the end of the second conductive structure 21 facing the first conductive structure 11. Through this local structural design, while effectively improving the contact or short-circuit problem of the conductive layer caused by alignment misalignment, the second conductive structure 21 can still maintain a large lateral size, thereby avoiding problems such as structural deformation, excessive current density, and decreased reliability that may occur when the overall linewidth is reduced.

[0053] It should be noted that, in this embodiment, the spacing between adjacent first storage cells 41 ranges from [19, 21] nm; the spacing between adjacent second storage cells 51 ranges from [19, 21] nm. The difference between the size of the first end face 111 and the size of the first cross-section 112 ranges from [1, 2] nm; the difference between the size of the second end face 211 and the size of the second cross-section 212 ranges from [1, 2] nm.

[0054] In some other embodiments, the memory structures disclosed in the foregoing embodiments and this embodiment of the present application can be applied simultaneously in the same memory structure. Specifically, the first conductive layer 1 and the second conductive layer 2 in the foregoing embodiments can respectively correspond to the via connection layer and the word line layer or bit line layer above it in the memory, while the first conductive layer 1 and the second conductive layer 2 in this embodiment can correspond to the lower word line layer (or lower bit line layer) and the upper word line layer (or upper bit line layer) in two adjacent memory arrays in the memory. In other words, in a multi-layer stacked three-dimensional memory, the conductive layers at different levels can adopt the end-shrinkage structure design of the foregoing embodiments or this embodiment according to their location and function. By alternating or combining the above two structural configurations between different layers, the alignment tolerance between each conductive structure can be optimized as a whole, reducing the risk of misalignment contact between conductive layers in the multi-layer stacked structure, thereby further improving the overall reliability and process consistency of the device.

[0055] Accordingly, embodiments of this application also provide a method for forming a memory. Please refer to... Figures 7 to 8 , Figures 7 to 8 yes Figure 1 and Figure 2 The diagram shows a cross-sectional structure illustrating the formation process of the memory.

[0056] Specifically, the method for forming the memory includes: A first conductive layer 1 is formed, the first conductive layer 1 including at least one first conductive structure 11; An initial second conductive layer 9 is formed that is stacked and in contact with the first conductive layer 1; The initial second conductive layer 9 is patterned to form a second conductive layer 2, which includes a plurality of second conductive structures 21. After patterning, the second conductive structure 21 includes a second end face 211 facing the first conductive layer 1 and a second cross section 212 parallel to the second end face 211, the size of the second end face 211 being smaller than the size of the second cross section 212; the first conductive structure 11 includes a first end face 111 facing the second conductive layer 2 and a first cross section 112 parallel to the first end face 111, the size of the first end face 111 being smaller than the size of the first cross section 112; each first end face 111 and a second end face 211 are at least partially coplanar.

[0057] In some embodiments, the first conductive layer 1 includes a first conductive structure 11 located in the peripheral region 32. Specifically, referring to... Figure 1 and Figure 2 The memory includes a substrate 3, a third conductive layer 8, and a first memory array 4. The first memory cell 41 in the first memory array 4 is located in the array region 31, and the first conductive structure 11 is located in the peripheral region 32. The structural and material characteristics of the substrate 3, the third conductive layer 8, and the first memory array 4 have been described in detail in the aforementioned memory embodiments and will not be repeated here.

[0058] Please refer to Figure 7 The first conductive layer 1 located in the peripheral area 32 includes at least one first conductive structure 11. The first conductive structure 11 acts as a via connection layer, used to connect the second conductive structure 21 and the substrate 3 in a third-direction upward direction after the subsequent formation of the second conductive structure 21, so as to enable the signal of the second conductive structure 21 to be led out. The material of the first conductive layer 1 can be tungsten metal.

[0059] Please refer to Figure 8 The initial second conductive layer 9 covers the surface of the first memory array 4 facing away from the substrate 3, and also covers the surface of the first conductive structure 11 facing away from the substrate 3. The initial second conductive layer 9 is made of tungsten. In some embodiments, after forming the initial second conductive layer 9, the initial second conductive layer 9 is planarized.

[0060] Please refer to Figure 1 and Figure 2After patterning the initial second conductive layer 9, the formed second conductive structure 21 includes a second end face 211 facing the first conductive layer 1 and a second cross section 212 parallel to the second end face 211, the size of the second end face 211 being smaller than the size of the second cross section 212; the formed first conductive structure 11 includes a first end face 111 facing the second conductive layer 2 and a first cross section 112 parallel to the first end face 111, the size of the first end face 111 being smaller than the size of the first cross section 112; each first end face 111 and a second end face 211 are at least partially coplanar. The structural and material characteristics of the first conductive structure 11 and the second conductive structure 21 have been described in detail in the foregoing memory embodiments, and will not be repeated here.

[0061] In some embodiments, the method of patterning the initial second conductive layer 9 to form the second conductive layer 2 includes: forming a mask layer on the side of the initial second conductive layer 9 away from the first conductive layer 1; and etching the initial second conductive layer 9 and the end of the first conductive structure 11 facing the second conductive layer 2 using the mask layer as a mask.

[0062] In the embodiments disclosed in this application, by appropriately extending the etching time or increasing the etching rate in the etching process, the etching depth of the end region of the second conductive layer 2 near the first conductive structure 11 is increased, thereby making the size of the first end face 111 smaller than the size of the first cross section 112, and the size of the second end face 211 smaller than the size of the second cross section 212.

[0063] Compared to other embodiments where the second conductive structure 21 is susceptible to changes in sidewall contours or local morphological shifts due to photolithographic overlay deviations and etching anisotropy differences, thus posing a risk of misalignment in the conductive layers, the technical solution disclosed in this application can appropriately reduce the dimensions of the first end face 111 and the second end face 211, thereby increasing the distance between the first end of the first conductive structure 11 and the second end of the adjacent second conductive structure 21. Therefore, even with certain overlay deviations, sufficient electrical isolation distance can still be maintained between the upper and lower conductive layers, effectively reducing the risk of short circuits and leakage, and improving the process tolerance and overall reliability of the device.

[0064] Specifically, in some embodiments, the first conductive layer 1 includes a first conductive structure 11 located on the side of the first memory array 4 facing away from the substrate 3. Please refer to... Figure 9 The first conductive layer 1 includes a plurality of parallel first conductive structures 11 extending along a first direction, and the first conductive structures 11 are connected to a plurality of first memory cells 41 arranged along the first direction. Please continue to refer to Figure 5 and 6The second conductive layer 2 includes a plurality of parallel second conductive structures 21 extending along a first direction. The second conductive structures 21 are connected to a plurality of second storage cells 51 arranged along the first direction. The second conductive structures 21 are connected to the first conductive structures 11 in a one-to-one correspondence.

[0065] In this embodiment, the first conductive structure 11 is a conductive layer formed on the side of the first memory array 4 away from the substrate 3, and is used as a lower word line or lower bit line between two adjacent memory arrays. The second conductive structure 21 is a conductive layer formed on the side of the first conductive structure 11 away from the first memory array 4, and is used as an upper word line or upper bit line between two adjacent memory arrays.

[0066] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0067] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0068] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0069] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A memory, characterized in that, include: First conductive layer (1) and second conductive layer (2). The first conductive layer (1) includes at least one first conductive structure (11), the first conductive structure (11) includes a first end face (111) facing the second conductive layer (2) and a first cross section (112) parallel to the first end face (111), the size of the first end face (111) is smaller than the size of the first cross section (112); The second conductive layer (2) includes a plurality of second conductive structures (21), each of which includes a second end face (211) facing the first conductive layer (1) and a second cross section (212) parallel to the second end face (211). The size of the second end face (211) is smaller than the size of the second cross section (212). Each of the first end faces (111) is at least partially coplanar with one of the second end faces (211).

2. The memory according to claim 1, characterized in that, The first end face (111) is located within the second end face (211), or the second end face (211) is located within the first end face (111), or the first end face (111) and the second end face (211) are partially offset from each other; the distance between the edge of the first end face (111) and the edge of the adjacent second end face (211) is less than or equal to 1 nm.

3. The memory according to claim 1, characterized in that, The first conductive structure (11) further includes a third section (113) parallel to the first section (112) and located on the side of the first section (112) away from the first end face (111); the size of any of the third sections (113) is larger than the size of the first section (112), or there is at least one third section (113) whose size is smaller than the size of the first section (112).

4. The memory according to claim 1, characterized in that, The second conductive structure (21) further includes a fourth section (213) parallel to the second section (212) and located on the side of the second section (212) away from the second end face (211); the size of any of the fourth sections (213) is greater than the size of the second section (212), or there is at least one fourth section (213) whose size is smaller than the size of the second section (212).

5. The memory according to claim 1, characterized in that, The difference between the size of the first end face (111) and the size of the first cross section (112) is in the range of [1,2] nm, and the difference between the size of the second end face (211) and the size of the second cross section (212) is in the range of [1,2] nm.

6. The memory according to claim 1, characterized in that, Also includes: Base (3); The first storage array (4) is located on the substrate (3) and includes the first storage cells (41) arranged in an array. The second storage array (5) is located on the side of the first storage array (4) away from the substrate (3) and includes a second storage cell (51) arranged in an array. The first conductive layer (1) and the second conductive layer (2) are located between the first memory array (4) and the second memory array (5), and the second conductive layer (2) is located between the first conductive layer (1) and the second memory array (5); the first conductive layer (1) includes a plurality of first conductive structures (11) that are parallel to each other and extend along a first direction, and the first conductive structures (11) are connected to a plurality of first memory cells (41) arranged along the first direction; the second conductive layer (2) includes a plurality of second conductive structures (21) that are parallel to each other and extend along the first direction, and the second conductive structures (21) are connected to a plurality of second memory cells (51) arranged along the first direction; the second conductive structures (21) are connected to the first conductive structures (11) one by one.

7. The memory according to claim 1, characterized in that, Also includes: Base (3); The first storage array (4) is located on the substrate (3) and includes a first storage cell (41) arranged in an array within the array region (31) and a first conductive structure (11) located in the peripheral region (32). The second conductive layer (2) is located on the side of the first memory array (4) away from the substrate (3), and includes a plurality of second conductive structures (21) that are parallel to each other and extend along a first direction. The second conductive structure (21) connects to a plurality of first memory cells (41) arranged along the first direction and is connected to a first conductive structure (11).

8. The memory according to claim 6 or 7, characterized in that, Each of the first memory cells (41) includes a first electrode layer (61), a bidirectional threshold switch layer (62), a second electrode layer (63), a phase change layer (64), and a third electrode layer (65) sequentially stacked on the substrate (3); or, Each of the first storage cells (41) includes a first electrode layer (61), a bidirectional threshold switch layer (62), and a second electrode layer (63) that are sequentially stacked on the substrate (3).

9. A method for forming a memory, characterized in that, include: A first conductive layer is formed, the first conductive layer including at least one first conductive structure; An initial second conductive layer is formed that is stacked and in contact with the first conductive layer; The initial second conductive layer is patterned to form a second conductive layer, which includes a plurality of second conductive structures; After the patterning process, the second conductive structure includes a second end face facing the first conductive layer and a second cross section parallel to the second end face, the size of the second end face being smaller than the size of the second cross section; the first conductive structure includes a first end face facing the second conductive layer and a first cross section parallel to the first end face, the size of the first end face being smaller than the size of the first cross section; each first end face and a second end face are at least partially coplanar.

10. The method for forming a memory according to claim 9, characterized in that, The patterning process for the initial second conductive layer includes: A mask layer is formed on the side of the initial second conductive layer that is opposite to the first conductive layer; Using the mask layer as a template, the initial second conductive layer and one end of the first conductive structure facing the second conductive layer are etched.

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