Lead-free GPP diode chip of flexible composite passivation layer

Abstract

The invention relates to a lead-free GPP diode chip with a flexible composite passivation layer, and belongs to the technical field of semiconductors, the lead-free GPP diode chip specifically comprises a monocrystalline silicon chip, glass layers, a polyimide film layer and a nickel-gold layer, the glass layers are passivated on the two sides of the monocrystalline silicon chip, the polyimide film layer is passivated on the glass layers, and the nickel-gold layer is passivated on the polyimide film layer. And the nickel-gold layer is respectively connected with the front surface and the back surface of the monocrystalline silicon chip. Zinc glass is adopted as a main passivation material, toxic lead elements are completely abandoned, the requirements of international environmental protection instructions such as RoHS are completely met, and the development trend of green electronic manufacturing is met.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, specifically relating to a lead-free GPP diode chip with a flexible composite passivation layer. Background Technology

[0002] GPP is an abbreviation for Glass Activated Passivation Parts or Parts of Anapparats, a general term for glass passivated devices. It refers to all active devices that incorporate or utilize junction film protection technology. GPP diode chips are key components in modern power electronic devices, widely used in rectification, voltage regulation, and protection circuits. Their core structure involves sintering a layer of leaded glass powder at the edge of a semiconductor silicon wafer, melting it at high temperature to form a dense glass layer. This glass layer effectively passivates the semiconductor surface, eliminates electric field concentration, and significantly improves the device's reverse withstand voltage, stability, and reliability.

[0003] Currently, the GPP diode chips commonly produced and used in the industry use lead-containing glass powder in their glass passivation layers, meaning the glass composition contains a high proportion of lead oxide (PbO). Lead oxide plays a crucial role in this system: firstly, it significantly lowers the melting temperature of the glass, allowing the glass powder to fully melt and flow at lower temperatures compatible with semiconductor processes (typically 600-850℃), achieving a good passivation effect and preventing damage to the semiconductor cell structure from high temperatures; secondly, lead oxide improves the coefficient of thermal expansion of the glass, better matching it with the coefficient of thermal expansion of silicon, reducing internal stress caused by thermal mismatch, and improving the mechanical strength and thermal cycling reliability of the device.

[0004] However, despite the maturity and stable performance of lead glass passivation technology, its inherent environmental and health hazards are becoming increasingly prominent, mainly due to the following drawbacks. Summary of the Invention

[0005] To solve the above problems, the technical solution adopted in this application is: The first aspect of this application provides a lead-free GPP diode chip with a flexible composite passivation layer, comprising: a monocrystalline silicon chip, a glass layer, a polyimide film layer, and a nickel-gold layer, wherein the glass layer is passivated on both sides of the monocrystalline silicon chip, the polyimide layer is passivated on the glass layer, and the nickel-gold layer is connected to the front and back sides of the monocrystalline silicon chip, respectively.

[0006] Furthermore, the front nickel-gold layer of the single-crystal silicon chip is passivated with a grid-shaped polyimide film strip, which divides the front nickel-gold layer into nine solder isolation areas.

[0007] Furthermore, the glass layer is zinc-based glass.

[0008] Furthermore, the thickness of the glass layer ranges from 5 μm to 70 μm.

[0009] Furthermore, the thickness of the polyimide film ranges from 2 μm to 30 μm.

[0010] Furthermore, the nickel-gold layer has a two-layer structure, wherein the inner structure is a nickel layer that is connected to the single-crystal silicon chip, and the outer structure is a gold layer that is connected to the nickel layer.

[0011] Furthermore, the thickness of the nickel layer ranges from 0.3 μm to 3 μm, and the thickness of the gold layer ranges from 50 nm to 200 nm.

[0012] Furthermore, the single-crystal silicon chip is P + N - N + Monocrystalline silicon chip.

[0013] The second aspect of this application provides a method for fabricating a lead-free GPP diode chip with a flexible composite passivation layer, comprising the following steps: Step S1: Provide a single-crystal silicon chip substrate with a P+N-N+ structure; Step S2, glass passivation layer formation: Zinc-based glass paste is coated or printed on both sides of the single-crystal silicon chip substrate, and then high-temperature sintering is performed to form a glass layer with a thickness of 5μm to 70μm. Step S3, formation of polyimide passivation layer: On the glass layer formed in step S2, polyimide liquid is coated or sprayed, and then imidization curing treatment is performed to form a polyimide film layer with a thickness of 2μm to 30μm. Step S4, Metallization electrode formation: Metallization treatment is performed on the front and back sides of the single crystal silicon chip. First, a nickel layer with a thickness of 0.3μm to 3μm is deposited by chemical plating or evaporation. Then, a gold layer with a thickness of 50nm to 200nm is deposited on the nickel layer to form a nickel-gold layer. Step S5, Patterned Polyimide Strip Formation: On the nickel-gold layer on the front side of the chip, a grid-shaped polyimide film strip is formed through photolithography and etching processes, dividing the front electrode into nine solder isolation areas.

[0014] A third aspect of this application provides an electronic device comprising a lead-free GPP diode chip with a flexible composite passivation layer as described in any one of claims 1-8.

[0015] Compared with the prior art, the beneficial effects of this application are as follows: 1. This application provides a lead-free GPP diode chip with a flexible composite passivation layer. This application uses zinc-based glass as the main passivation material, completely eliminating toxic lead elements, fully complying with international environmental protection directives such as RoHS, and meeting the development trend of green electronic manufacturing.

[0016] 2. This application provides a lead-free GPP diode chip with a flexible composite passivation layer. Through an innovative "glass layer + polyimide film layer" composite passivation structure, it combines the advantages of two materials. The inner glass layer provides dense and stable inorganic passivation protection, while the outer polyimide film layer has excellent flexibility, high adhesion and low internal stress. This composite structure can effectively absorb and buffer mechanical and thermal stress from the outside, significantly reducing the risk of cracking of the pure glass passivation layer due to brittleness, and greatly improving the durability and lifespan of the chip under harsh conditions.

[0017] 3. This application provides a lead-free GPP diode chip with a flexible composite passivation layer. The "grid-shaped polyimide film strip" designed on the front electrode effectively divides the pads into nine isolation areas. This structure can precisely limit the flow range of solder during subsequent packaging and soldering processes, preventing it from overflowing to the chip edge and damaging the passivation layer, thus ensuring the stability of the bonding process and the yield. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the single-crystal silicon chip in this application; Figure 2 This is a schematic diagram of the zinc-based glass after passivation in this application; Figure 3 This is a schematic diagram of the structure of the polyimide film after passivation in this application; Figure 4 This is a schematic diagram of the structure of the chip after the nickel-gold layers are formed on the front and back sides in this application; Figure 5 This is a top view of the structure of this application.

[0019] In the diagram: 1. Polycrystalline silicon chip, 2. Glass layer, 3. Polyimide film layer, 4. Nickel-gold layer, 5. Cross-shaped polyimide film strips. Detailed Implementation

[0020] The present application will be further described in detail below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present application. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present application.

[0021] Example 1 like Figures 1 to 5As shown, this application provides a lead-free GPP diode chip with a flexible composite passivation layer, comprising: a monocrystalline silicon chip 1, a glass layer 2, a polyimide film layer 3, and a nickel-gold layer 4. The glass layer 2 is passivated on both sides of the monocrystalline silicon chip 1, the polyimide layer 3 is passivated on the glass layer 2, and the nickel-gold layer 4 is connected to the front and back sides of the monocrystalline silicon chip 1, respectively. In this embodiment, the glass layer 2 is zinc-based glass.

[0022] The front nickel-gold layer 4 of the single-crystal silicon chip 1 is passivated with a grid-like polyimide film strip 5, which divides the front nickel-gold layer 4 into nine solder isolation areas. In this embodiment, a polyimide film 3 is passivated on the surface of the zinc-based glass, and simultaneously, grid-like polyimide film strips 5 are formed on the surface of the front nickel-gold layer 4 of the chip. This design serves three purposes: first, it compensates for insufficient breakdown voltage caused by insufficient thickness of the zinc-based glass. To reduce the stress mismatch between the zinc-based glass and silicon, the thickness of the zinc-based glass is reduced; however, when the thickness of the zinc-based glass is insufficient, air breakdown, i.e., arcing, will occur on the surface of the zinc-based glass when a high reverse voltage is applied to the diode, resulting in insufficient reverse breakdown voltage. After passivating the zinc-based glass surface with a polyimide film, the relatively thick composite passivation layer prevents air breakdown; secondly, the polyimide film prevents the zinc-based glass from absorbing moisture; and thirdly, during chip soldering, the grid-shaped polyimide film lines can isolate the solder into nine parts, thereby reducing the stress mismatch between the solder and the chip.

[0023] The thickness of the glass layer 2 ranges from 5 μm to 70 μm.

[0024] The thickness of the polyimide film 3 ranges from 2 μm to 30 μm.

[0025] The nickel-gold layer 4 has a two-layer structure, with an inner nickel layer connected to the single-crystal silicon chip 1, and an outer gold layer connected to the nickel layer. This application employs a composite metallization scheme of "nickel layer + gold layer." The nickel layer, acting as a barrier layer and ohmic contact layer, forms a good electrical connection with silicon and effectively prevents gold from diffusing into the silicon. The thin outer gold layer provides excellent solderability and oxidation resistance, ensuring that the electrode maintains low contact resistance and high stability during long-term use.

[0026] The thickness of the nickel layer ranges from 0.3 μm to 3 μm, and the thickness of the gold layer ranges from 50 nm to 200 nm.

[0027] The single-crystal silicon chip 1 is P + N - N + Single-crystal silicon chip; P + N - N +A single-crystal silicon chip is a semiconductor chip designed and manufactured using single-crystal silicon material and a special doping profile; its core is a lightly doped N-type silicon chip. - The drift region is used to achieve high voltage withstand and fast switching characteristics. Its most typical finished product is the fast recovery diode, an indispensable key component in modern power electronics and energy conversion systems. + N - N + Single-crystal silicon chips are formed through vertical doping using semiconductor processes, creating a three-layer "sandwich" structure. + This refers to a P-type semiconductor with a very high impurity concentration, N... - This refers to an N-type semiconductor with a very low impurity concentration. + This indicates a heavily doped N-type semiconductor.

[0028] Example 2 This application provides a method for fabricating a lead-free GPP diode chip with a flexible composite passivation layer, comprising the following steps: Step S1: Provide the chip substrate: Prepare a piece of P that has been formed by diffusion or epitaxy. + N - N + The structure consists of a single-crystal silicon wafer, which is then diced to obtain several independent single-crystal silicon chip substrates. This structure provides an ideal vertical doping distribution for the fabrication of high-voltage fast recovery diodes.

[0029] Step S2: Forming a glass passivation layer: S21. Prepare or purchase commercial lead-free zinc-based glass slurry, wherein the glass powder is mainly composed of oxides such as ZnO, B2O3, and SiO2.

[0030] S22. Using precision screen printing technology, the above-mentioned glass paste is uniformly coated on the front and back sides of the single crystal silicon chip 1 substrate, especially the PN junction area that needs to be passivated.

[0031] S23. The chip coated with the paste is transferred to a sintering furnace and sintered at high temperature under a nitrogen protective atmosphere. The peak sintering temperature is controlled between 600℃ and 750℃, and the temperature is maintained for a certain time to allow the glass powder to fully melt, flow, and wet the silicon wafer surface, forming a dense, smooth glass layer 2 that is tightly bonded to the silicon wafer. By controlling the paste viscosity and printing parameters, the final thickness of the sintered glass layer 2 is 5μm to 70μm.

[0032] Step S3: Forming a polyimide passivation layer: S31. On the chip with glass layer 2 already covered obtained in step S2, a layer of polyamic acid solution polyimide precursor with appropriate viscosity is uniformly coated by spin coating.

[0033] S32. Place the coated chip on a hot plate and perform a stepped-temperature imidization curing process. Specifically, pre-treat at 100°C to evaporate most of the solvent, then gradually increase the temperature to 250°C–350°C for high-temperature cyclization, completely converting the polyamic acid into polyimide. This ultimately forms a 2μm–30μm thick, firmly adhered, and uniformly colored polyimide film.

[0034] Step S4: Forming a metallized electrode: S41. First, clean and activate the front and back of the chip.

[0035] S42. A dense nickel layer with a thickness of 0.3μm to 3μm is selectively deposited on both sides of the chip using a chemical nickel plating process; this nickel layer forms a good ohmic contact with the single crystal silicon.

[0036] S43. Subsequently, a dense gold layer with a thickness of 50nm to 200nm is deposited on the nickel layer by chemical immersion gold or selective electroplating. This gold layer effectively prevents nickel from being oxidized and provides excellent solderability. The nickel layer and the gold layer together constitute the nickel-gold layer 4.

[0037] Step S5: Forming patterned polyimide strips: S51. On the nickel-gold layer 4 on the front side of the chip, a layer of photosensitive polyimide liquid is coated again by spraying.

[0038] S52. Use a pre-designed photomask with a grid pattern for ultraviolet exposure. After development, remove the polyimide outside the grid pattern area.

[0039] S53. Perform a curing process to completely solidify the remaining grid-shaped polyimide film strip 5. This grid-shaped polyimide film strip 5 clearly divides the nickel-gold layer 4 on the front electrode area into nine independent square solder isolation areas. At this point, the diode chip fabrication described in this application is complete. The fabrication method described in this application has clear steps, and the formation processes of each layer (such as coating, sintering, plating, chemical plating / evaporation, photolithography) are all mature semiconductor manufacturing technologies, easy to implement for industrial production, and have good economic benefits and promotional value.

[0040] Example 3 This embodiment provides an electronic device, which includes a lead-free GPP diode chip with a flexible composite passivation layer as described in Embodiment 1 above.

[0041] Of course, the above embodiments are not intended to limit this application, and this application is not limited to the examples given above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of this application should also fall within the protection scope of this application.

Claims

1. A lead-free GPP diode chip with a flexible composite passivation layer, characterized in that: include: The single-crystal silicon chip (1), glass layer (2), polyimide film layer (3) and nickel-gold layer (4) are provided. The glass layer (2) is passivated on both sides of the single-crystal silicon chip (1), the polyimide layer (3) is passivated on the glass layer (2), and the nickel-gold layer (4) is connected to the front and back sides of the single-crystal silicon chip (1) respectively.

2. The lead-free GPP diode chip with a flexible composite passivation layer according to claim 1, characterized in that: The front nickel-gold layer (4) of the single-crystal silicon chip (1) is passivated with a grid-shaped polyimide film strip (5), which divides the front nickel-gold layer (4) into nine solder isolation areas.

3. The lead-free GPP diode chip with a flexible composite passivation layer according to claim 1, characterized in that: The glass layer (2) is zinc-based glass.

4. The lead-free GPP diode chip with a flexible composite passivation layer according to claim 3, characterized in that: The thickness of the glass layer (2) ranges from 5 μm to 70 μm.

5. The lead-free GPP diode chip with a flexible composite passivation layer according to claim 1, characterized in that: The thickness of the polyimide film (3) ranges from 2 μm to 30 μm.

6. The lead-free GPP diode chip with a flexible composite passivation layer according to claim 1, characterized in that: The nickel-gold layer (4) has a two-layer structure, with the inner structure being a nickel layer connected to the single-crystal silicon chip (1) and the outer structure being a gold layer connected to the nickel layer.

7. A lead-free GPP diode chip with a flexible composite passivation layer according to claim 6, characterized in that: The thickness of the nickel layer ranges from 0.3 μm to 3 μm, and the thickness of the gold layer ranges from 50 nm to 200 nm.

8. The lead-free GPP diode chip with a flexible composite passivation layer according to claim 1, characterized in that: The single-crystal silicon chip (1) is P + N - N + Monocrystalline silicon chip.

9. A method for fabricating a lead-free GPP diode chip with a flexible composite passivation layer, characterized in that: Includes the following steps: Step S1: Provide a P+N-N+ structured monocrystalline silicon chip (1) substrate; Step S2, glass passivation layer formation: zinc-based glass paste is coated or printed on both sides of the single crystal silicon chip substrate, and then high-temperature sintering is performed to form a glass layer (2) with a thickness of 5μm to 70μm. Step S3, formation of polyimide passivation layer: On the glass layer formed in step S2, polyimide liquid is coated or sprayed, and then imidization curing treatment is performed to form a polyimide film layer with a thickness of 2μm to 30μm (3). Step S4, Metallization electrode formation: Metallization treatment is performed on the front and back sides of the single crystal silicon chip. First, a nickel layer with a thickness of 0.3μm to 3μm is deposited by chemical plating or evaporation. Then, a gold layer with a thickness of 50nm to 200nm is deposited on the nickel layer to form a nickel-gold layer (4). Step S5, Patterned polyimide strip formation: On the nickel-gold layer (4) on the front side of the chip, a grid-shaped polyimide film strip (5) is formed by photolithography and etching processes, dividing the front electrode into nine solder isolation areas.

10. An electronic device, characterized in that, A lead-free GPP diode chip including a flexible composite passivation layer as described in any one of claims 1-8.

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