Power semiconductor device, method of manufacturing a power semiconductor device, a single-chip half-bridge converter,

Abstract

The invention relates to a power semiconductor device, a method of manufacturing a power semiconductor device, a one-chip half-bridge converter, and a method of operating a power semiconductor device. The power semiconductor device includes: a semiconductor body including a substrate region having a first conductivity type or a second conductivity type, the semiconductor body having a front side; a first load terminal and a second load terminal at the front side, where the semiconductor body is configured to conduct both a forward load current in a forward direction between the first load terminal and the second load terminal and a reverse load current in a reverse direction between the first load terminal and the second load terminal. The forward direction and the reverse direction are opposite to each other. The power semiconductor device further includes: a first control terminal at the front side and adjacent to the first load terminal; and a second control terminal at the front side and adjacent to the second load terminal.

Description

Technical Field

[0001] This specification relates to embodiments of power semiconductor devices and embodiments of methods for manufacturing power semiconductor devices. The power semiconductor devices have a lateral configuration and are configured to conduct both forward load current and reverse load current. This specification also relates to embodiments of single-chip half-bridge converters and embodiments of methods for operating power semiconductor devices. Background Technology

[0002] Many functions of modern devices in automotive, consumer, and industrial applications—such as converting electrical energy and driving electric motors—rely on power semiconductor devices. For example, to name just a few, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes have been used in a wide range of applications, including but not limited to switches in power supplies and power converters.

[0003] A power semiconductor device includes a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is conducted via an active region of the power semiconductor device. The active region is surrounded by an edge-terminating region that is terminated by the edge of the chip.

[0004] In the case of controllable power semiconductor devices such as transistors, the load current path can be controlled by means of an insulating electrode (often referred to as the gate electrode). For example, upon receiving a corresponding control signal, such as from a driver unit and via the device's control terminal, the control electrode can set the power semiconductor device to either a forward-biased state or a forward-biased state.

[0005] In addition, some devices provide reverse load current capability; that is, the active region of the semiconductor body is also configured to conduct reverse load current along the reverse load current path between the two load terminals of the device. For example, the RC (reverse current) IGBT is a representative of such devices. In an RCIGBT, a single chip combines the IGBT structure and the diode structure. Summary of the Invention

[0006] The main aspects of the invention have been presented. Features of exemplary embodiments are defined in other aspects of the invention.

[0007] According to an embodiment, a power semiconductor device includes: a semiconductor body including a substrate region having a first conductivity type or a second conductivity type, wherein the semiconductor body has a front side; a first load terminal and a second load terminal at the front side, wherein the semiconductor body is configured to conduct both: a forward load current in a forward direction between the first load terminal and the second load terminal and a reverse load current in a reverse direction between the first load terminal and the second load terminal. The forward direction and the reverse direction are opposite to each other. The power semiconductor device further includes: a first control terminal at the front side and adjacent to the first load terminal, wherein the semiconductor body is configured to establish a first conductive channel based on a first control voltage applied between the first load terminal and the first control terminal; and a second control terminal at the front side and adjacent to the second load terminal, wherein the semiconductor body is configured to establish a second conductive channel based on a second control voltage applied between the second load terminal and the second control terminal.

[0008] According to another embodiment, a method of manufacturing a power semiconductor device includes forming: a semiconductor body including a substrate region having a first conductivity type or a second conductivity type, wherein the semiconductor body has a front side; a first load terminal and a second load terminal at the front side, wherein the semiconductor body is configured to conduct both: a forward load current in a forward direction between the first load terminal and the second load terminal and a reverse load current in a reverse direction between the first load terminal and the second load terminal. The forward direction and the reverse direction are opposite to each other. The method further includes: forming a first control terminal at the front side and adjacent to the first load terminal, wherein the semiconductor body is configured to establish a first conductive channel based on a first control voltage applied between the first load terminal and the first control terminal; and forming a second control terminal at the front side and adjacent to the second load terminal, wherein the semiconductor body is configured to establish a second conductive channel based on a second control voltage applied between the second load terminal and the second control terminal.

[0009] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0010] The components in the accompanying drawings are not necessarily drawn to scale; rather, the focus is on illustrating the principles of the invention. Furthermore, similar reference numerals designate corresponding components in the drawings. In the drawings:

[0011] Figures 1 to 5 Each schematically and exemplaryly illustrates a vertical cross-section of a power semiconductor device according to some embodiments;

[0012] Figure 6The horizontal projection of a single-chip half-bridge converter according to one or more embodiments is illustrated schematically and exemplary.

[0013] Figure 7 A circuit diagram of a single-chip half-bridge converter according to one or more embodiments is illustrated schematically and exemplaryly; and

[0014] Figures 8 to 9 The methods for operating power semiconductor devices according to some embodiments are illustrated schematically and exemplary. Detailed Implementation

[0015] In the following detailed description, reference is made to the accompanying drawings, which form part of the invention, and specific embodiments in which the invention may be practiced are illustrated by way of illustration.

[0016] In this regard, directional terms such as "top," "bottom," "below," "front," "rear," "rear part," "front," "back," "above," etc., can be used with reference to the orientation of the described drawings. Since the components of the embodiments can be positioned in multiple different orientations, the directional terms are for illustrative purposes and are by no means limiting. It should be understood that other embodiments can be utilized, and structural or logical changes can be made, without departing from the scope of the invention. Therefore, the following detailed description is not to be considered limiting, and the scope of the invention is defined by the appended claims.

[0017] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the accompanying drawings. Each example is provided by way of illustration and is not intended to limit the invention. For example, a feature shown or described as part of one embodiment may be used on or in combination with other embodiments to produce yet another embodiment. The invention is intended to include such modifications and variations. These examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same elements or manufacturing steps are designated by the same reference numerals in different drawings.

[0018] The term "horizontal" as used in this specification is intended to describe an orientation of a horizontal surface that is substantially parallel to a semiconductor substrate or semiconductor structure. This can be, for example, the surface of a semiconductor wafer, die, or chip. For example, the first lateral direction X and the second lateral direction Y mentioned below can both be horizontal directions, wherein the first lateral direction X and the second lateral direction Y can be perpendicular to each other.

[0019] The term "vertical" as used in this specification is intended to describe an orientation that is substantially perpendicular to a horizontal surface arrangement, i.e., parallel to the normal direction of the surface of a semiconductor wafer / chip / die. For example, the extension direction Z mentioned below can be an extension direction perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to herein as "vertical direction Z".

[0020] The first conductivity type is the opposite of the second conductivity type. In this specification, n-doping is referred to as the "first conductivity type," and p-doping is referred to as the "second conductivity type." Alternatively, the opposite doping relationship can be used, such that the first conductivity type can be p-doped, and the second conductivity type can be n-doped. The dopant dose can be defined as the integral of the dopant concentration of atoms with the corresponding conductivity type in the corresponding doped region in the vertical direction Z. The dopant dose can be the amount of dopant implanted in each region.

[0021] In the context of this specification, the terms "ohmic contact," "electrical contact," "ohmic connection," and "electrical connection" are intended to describe a low-ohmic electrical connection or low-ohmic current path between two regions, sections, zones, portions, or components of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode of a semiconductor device and a portion or component. "Low ohmic" may mean that the characteristics of the corresponding contact are substantially unaffected by ohmic resistance. Furthermore, in the context of this specification, the term "contact" is intended to describe a direct physical connection between two elements of a corresponding semiconductor device; for example, the transition between two contacting elements may not include additional intermediate elements.

[0022] Furthermore, in the context of this specification, unless otherwise stated, the term "electrically insulated" is used in its generally valid understanding and is therefore intended to describe two or more components positioned separately from each other and without an ohmic connection connecting these components. However, components that are electrically insulated from each other can still be coupled to each other, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled and / or electrostatically coupled (e.g., in the case of a junction). For example, the two electrodes of a capacitor can be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, for example, by means of an insulator (e.g., a dielectric).

[0023] The specific embodiments described in this specification pertain to, but are not limited to, power semiconductor devices that can be used in power converters or power supplies. Therefore, in these embodiments, such power semiconductor devices can be configured to carry load currents to be fed to a load and / or supplied by a power source. For example, a power semiconductor device may include one or more active power semiconductor unit cells, such as monolithically integrated diode units, derivatives of monolithically integrated diode units, monolithically integrated transistor units (e.g., monolithically integrated IGBT or MOSFET units), and / or derivatives thereof. Such diode / transistor units can be integrated within a single chip. Multiple such units can constitute a cell field arranged within the active region of the power semiconductor device.

[0024] The term "blocking state" in the context of power semiconductor devices can refer to the state in which the power semiconductor is configured to block the flow of load current when an external voltage is applied. More specifically, a power semiconductor device can be configured to block the forward load current flowing through it when a forward bias voltage is applied. In contrast, a power semiconductor device can be configured to conduct forward load current in its "forward conduction state" when a forward bias voltage is applied. The transition between the forward blocking state and the forward conduction state can be controlled by a control electrode, or more specifically, by the potential of the control electrode. Of course, these electrical characteristics are only applicable within a predetermined operating range of the external voltage and current density within the power semiconductor device. Therefore, the term "forward bias blocking state" can refer to the state in which the power semiconductor device is in a forward blocking state when a forward bias voltage is applied.

[0025] The term "power semiconductor device" as used in this specification is intended to describe a power semiconductor device on a single chip that has high voltage blocking and / or high current carrying capacity. In other words, such a power semiconductor device is intended for use with high current and / or high voltage, depending on the application, where the high current is typically in the range of several 100mA (e.g., up to several amperes or tens of amperes), and the high voltage is typically above 100V, more typically 300V and above (e.g., up to at least 600V or even higher (e.g., up to at least 1.2kV, or even up to 6kV or higher)).

[0026] For example, the term "power semiconductor device" as used in this specification does not refer to logic semiconductor devices used for, for example, storing data, computing data, and / or other types of semiconductor-based data processing.

[0027] For example, the power semiconductor device described below can be a single semiconductor chip and can be configured to be used as a power component in low, medium and / or high voltage applications.

[0028] Figure 1 A portion of a vertical cross-section of a power semiconductor device 1 according to one or more embodiments is illustrated schematically and exemplary.

[0029] The power semiconductor device 1 includes a semiconductor body 10, which includes a substrate region 100 having a first conductivity type or a second conductivity type, wherein the semiconductor body 10 has a front side 110.

[0030] At the front side 110, there are a first load terminal 11 and a second load terminal 12, wherein the semiconductor body 10 is configured to conduct both: a forward load current in the forward direction between the first load terminal 11 and the second load terminal 12, and a reverse load current in the reverse direction between the first load terminal 11 and the second load terminal 12. The forward direction and the reverse direction are opposite to each other.

[0031] The power semiconductor device 1 also includes a first control terminal 13 at the front side 110 and adjacent to the first load terminal 11, wherein the semiconductor body 10 is configured to establish a first conductive channel based on a first control voltage applied between the first load terminal 11 and the first control terminal 13.

[0032] Furthermore, at the front side 110 and adjacent to the second load terminal 12, there is a second control terminal 14, wherein the semiconductor body 10 is configured to establish a second conductive channel based on a second control voltage applied between the second load terminal 12 and the second control terminal 14.

[0033] For example, based on the second control terminal 14, the power semiconductor device 1 can operate as a lateral bidirectional power semiconductor transistor, for example, as a lateral bidirectional IGBT. Furthermore, a high unidirectional voltage blocking capability can be established (e.g., the second load terminal 12 (e.g., the collector terminal) is at a high voltage), wherein, additionally, according to some embodiments, a configuration with bidirectional blocking capability can be established.

[0034] Still refer to Figure 1 According to an embodiment, the power semiconductor device 1 includes a body region 1021 of a second conductivity type that is laterally overlapped with both the first load terminal 11 and the first control terminal 13 in the semiconductor body 10, wherein the body region 1021 is electrically connected to the first load terminal 11, and wherein the first conductive channel is formed in the body region 1021.

[0035] The power semiconductor device 1 may further include one or more source regions 1011 having a first conductivity type in the semiconductor body 10, wherein one or more source regions 1011 are electrically connected to the first load terminal 11 and are isolated from the substrate region 100 through the body region 1021.

[0036] For example, the first conductive channel is an inverted channel that extends into the body region 1021.

[0037] In addition, the body region 1021 may include a highly doped sub-region 10211 that is electrically connected to (e.g., in contact with) the first load terminal 11.

[0038] In one embodiment, a plurality of source regions 1011 are arranged to be spatially separated from each other adjacent to the first load terminal 11, wherein each of the plurality of source regions is isolated from the substrate region 100 by a body region 1021. Optionally, one or more (e.g., a corresponding number) highly doped sub-regions 10211 may be provided within the body region 1021. For example, a plurality of first conductive channels may be formed in the body region 1021, the plurality of first conductive channels corresponding to the number of source regions 1011 provided.

[0039] Both the first control terminal 13 and the second control terminal 14 can be isolated from the semiconductor body 10, for example, based on an insulating material (not shown) of a corresponding configuration. Furthermore, the first control terminal 13 is electrically insulated from the second control terminal 14. For example, the first control signal can therefore be independent of the second control signal. In other words, the first control signal can be different from the second control signal.

[0040] Corresponding to the configuration at the first load terminal 11 and the first control terminal 13, according to an embodiment, the power semiconductor device 1 includes a collector region 1022 of a second conductivity type that is in the semiconductor body 10 and laterally overlaps with both the second load terminal 12 and the second control terminal 14, wherein the collector region 1022 is electrically connected to the second load terminal 12, and wherein the second conductive channel is formed in the collector region 1022.

[0041] Similar to the body region 1021, the collector region 1022 may also include a highly doped subregion 10222 that is electrically connected to (e.g., in contact with) the second load terminal 12.

[0042] The power semiconductor device 1 may further include one or more short regions 1012 having a first conductivity type in the semiconductor body 10, wherein one or more short regions 1012 are electrically connected to the second load terminal 12 and isolated from the substrate region 100 through the collector region 1022.

[0043] In one embodiment, a plurality of short regions 1012 are arranged to be spatially separated from each other adjacent to the second load terminal 12, wherein each of the short regions is isolated from the substrate region 100 by a collector region 1022. Optionally, one or more (e.g., a corresponding number) highly doped sub-regions 10222 may be provided within the collector region 1022. For example, a plurality of second conductive channels may be formed in the collector region 1022, the plurality of second conductive channels corresponding to the number of short regions 1012 provided.

[0044] In one embodiment, the number of short regions 1012 corresponds to the number of source regions 1011. In another embodiment, the number of short regions 1012 is different from the number of source regions 1011.

[0045] According to another embodiment, and still referring to Figure 1 The power semiconductor device 1 includes a field stop region 107 having a first conductivity type, wherein the collector region 1022 is at least partially isolated from the substrate region 100 through the field stop region 107.

[0046] According to another embodiment, and still referring to Figure 1 The power semiconductor device 1 includes a reduced surface field RESURF region 108 having a first conductivity type or a second conductivity type, wherein the RESURF region 108 is disposed at a front side 110 and extends between a first load terminal 11 and a second load terminal 12. For example, the RESURF region 108 is adjacent to a body region 1021 on one side and to a field stop region 107 on the other side. For example, the RESURF region 108 extends from the front side along the vertical direction Z so as to perpendicularly overlap both the body region 1021 and the collector region 1022. The RESURF region 108 does not extend as far along the vertical direction Z as the body region 1021, for example. In another embodiment, the RESURF region 108 extends along the vertical direction Z as far as or further than the body region 1021.

[0047] like Figure 1 As shown, the power semiconductor device 1 may include an active region 1-2 and a terminal region 1-3 surrounding the active region 1-2.

[0048] The active regions 1-2 are configured for load current conduction (both the forward load current and the reverse load current), and therefore may include each of the above components, namely the four terminals 11, 12, 13 and 14 and the semiconductor regions 1011, 1021, 10211, 108, 107, 1022, 10222 and 1012.

[0049] Terminal regions 1-3 are not configured for load current conduction, but for other purposes, such as stabilizing the electric field and / or sealing the active regions 1-2 with the environment of the power semiconductor device 1.

[0050] Terminal regions 1-3 are based on, for example, oxides and terminated by edges 1-4 and bottom 1-5, for example, as Figure 1 As shown in the diagram. For example, edges 1-4 are chip edges and / or bottom 1-5 are chip bottoms. In another embodiment, edges 1-4 are transitions to additional chip regions that can accommodate additional semiconductor structures. For example, a single chip can accommodate two or more implementations of the power semiconductor device 1, for example, to form an integrated half-bridge converter (e.g., as further described below).

[0051] According to some embodiments, the semiconductor body 10 has a thickness ranging from 10 μm to 140 μm (e.g., 20 μm to 80 μm) along the vertical direction Z. Furthermore, the substrate region 100 has a thickness ranging from 10 μm to 140 μm (e.g., 20 μm to 80 μm) along the vertical direction Z.

[0052] according to Figure 1 In the embodiment shown, the substrate region 100 is of a second conductivity type, such that the power semiconductor device 1 can present an n-channel IGBT configuration having a p-doped substrate region 100. According to... Figure 2 In the embodiment shown, the substrate region 100 is of a first conductivity type, such that the power semiconductor device 1 can present an n-channel IGBT configuration having an n-doped substrate region 100. According to... Figure 3 In the embodiment shown, substrate region 100 is of the second conductivity type, i.e., p-doped, wherein the dopant type of each of the body region 1021, source region 1011, sub-region 10211, RESURF region 108, collector region 1022, sub-region 10222, and short region 1012 is the same as that of the substrate region 1021. Figure 1 The dopant types of the embodiments shown are complementary, so that the power semiconductor device 1 can present a p-channel IGBT configuration having a p-doped substrate region 100.

[0053] according to Figure 4 In the embodiment shown, the power semiconductor device 1 further includes an insulating trench 15 extending from the front side 110 to the back side 120 of the semiconductor body 10. The insulating trench 15 includes a trench dielectric 152 that also extends from the front side 110 to the back side 120 of the semiconductor body 10 to abut the insulating layers 1-30 there, and the trench dielectric 152, for example, insulates the trench electrode 151 of the insulating trench 15 from the semiconductor body. Figure 4As shown, trench electrode 151 may be electrically floated or connected to a defined potential, such as to a first load terminal 11. Trench electrode 151 may comprise doped or undoped polysilicon.

[0054] For example, the insulating trench 15 places the lateral semiconductor structure on its right side (which can be determined according to the above regarding...) Figures 1 to 3 (Configured in one or more of the described embodiments) and separated from other semiconductor structures that can be implemented within the chip. As described above, two or more implementations of the power semiconductor device 1 can be disposed within the same single chip, and insulating trenches 15 can be arranged between two or more implementations of the power semiconductor device 1.

[0055] Still refer to Figure 4 The power semiconductor device 1 may further include a field plate structure 1112 disposed above the front side 110 and extending between the first load terminal 11 and the second load terminal 12. The field plate structure 1112 may be electrically connected to the first load terminal 11 on one side and to the second load terminal 12 on the other side. A portion of the field plate structure 1112 between the first load terminal 11 and the second load terminal 12 may be electrically connected to the RESURF region 108, for example, via a highly doped region (not shown). Here, it should be understood that... Figure 4 The illustrations are merely illustrative, and, for example, the construction and / or number of portions of the field plate structure 1112 can be modified. For example, as... Figure 4 As shown, there may be more or fewer parts.

[0056] Still refer to Figure 4 The insulating layer 1-30 can be coupled to the semiconductor (e.g., silicon) substrate region 1-34 via the band 1-32.

[0057] As described above, insulating layers 1-30 may comprise or are respectively oxide layers. The oxide layers may have a thickness in the vertical direction ranging from 0.5 μm to 20 μm (e.g., between 2 μm and 20 μm). The oxide layers may be deposited on the back side 120. This approach allows for significant scalability of the voltage ratings of the power semiconductor device 1 because the thickness of the deposited oxide can be easily selected according to the desired breakdown voltage. According to embodiments, the combined thickness of the substrate region 100 and insulating layers 1-30 may range from 20.5 μm to 100 μm.

[0058] The semiconductor (e.g., silicon) substrate regions 1-34 can be attached directly (without the strips 1-32) or indirectly (e.g., with the strips 1-32). For example, one or more adhesion-promoting layers can be disposed between the insulating layer 1-30 and the semiconductor (e.g., silicon) substrate regions 1-34. One or more adhesion-promoting layers can include the strips 1-32, such as die-attach-foil (DAF) strips. For example, as an alternative to or supplement to one or more adhesion-promoting layers, one or more additional layers can be disposed between the insulating layer 1-30 and the semiconductor (e.g., silicon) substrate regions 1-34. One or more additional layers can include one or more dielectric layers and / or one or more metal layers.

[0059] Still refer to Figure 4 The power semiconductor device 1 can be arranged symmetrically with respect to the rotation axis R, thereby producing a columnar design. According to this columnar design, the second load terminal 12 and its associated semiconductor region are arranged in the central region of the columnar design, and the first load terminal 11 and its associated semiconductor region are arranged in the peripheral region of the columnar design (see also...). Figure 6 ).

[0060] Figure 5 The embodiments shown correspond to Figure 4 In this embodiment, two first control terminals 13 and two source regions 1011 are provided adjacent to the first load terminal 11. Additionally, a separate field stop region 109 can be provided to separate the body region 1021 from the substrate region 100. Similarly, two second control terminals 14 and two short regions 1012 are provided adjacent to the second load terminal 12. For example, with this design, the channel width can be increased, for example, doubled, at one or two load terminals because channels leading to the outside can also be formed in the corresponding body regions. This can reduce the voltage drop in each channel.

[0061] This article describes another implementation of the single-chip half-bridge converter 5 (see [link]). Figure 7 and Figure 8 The single-chip half-bridge converter 5 includes a first power semiconductor device 1-A according to the embodiment described above and a second power semiconductor device 1-B according to the embodiment described above, connected in series therewith. The two power semiconductor devices 1-A and 1-B may have the same configuration. The first power semiconductor device 1-A and the second power semiconductor device 1-B are integrated within the same single chip, and the insulating trench 15 may be arranged between the first power semiconductor device 1-A and the second power semiconductor device 1-B.

[0062] Figure 6 The horizontal projection of a single-chip half-bridge converter 5 according to one or more embodiments is illustrated schematically and exemplary. For example, a first power semiconductor device 1-A is arranged on the low side LS, and a second power semiconductor device 1-B is arranged on the high side HS. Figure 7 The proposed circuit diagrams of a single-chip half-bridge converter 5 according to one or more embodiments are illustrated schematically and exemplary. The second load terminal 12 of HS device 1-B is connected to the high-side voltage DC+. The first load terminal 11 of HS device 1-B is connected to the second load terminal 12 of LS device 1-A. The first load terminal 11 of LS device 1-A is connected to the low-side voltage DC-. Both the first load terminal 11 of HS device 1-B and the second load terminal 12 of LS device 1-A are connected to the load L.

[0063] In this implementation, the first power semiconductor device 1-A (e.g., an LS device) operates as both a first IGBT and a first freewheeling diode, and the second power semiconductor device 1-B (e.g., an HS device) also operates as both a second IGBT and a second freewheeling diode.

[0064] For example, controlling the first power semiconductor device 1-A (e.g., an LS device) may include applying a first control voltage VG between the first load terminal 11 and the first control terminal 13 (see...). Figure 8 ); and apply a second control voltage VCG between the second load terminal 12 and the second control terminal 14 of the first power semiconductor device 1-A.

[0065] Similarly, controlling the second power semiconductor device 1-B (e.g., an HS device) may include applying a first control voltage VG between the first load terminal 11 and the first control terminal 13 (see...). Figure 8 ); and apply a second control voltage VCG between the second load terminal 12 and the second control terminal 14 of the second power semiconductor device 1-B.

[0066] For example, in Figure 8 The two upper diagrams illustrate the first control signal VG and the second control signal VCG for the second power semiconductor device 1-B (HS device) in IGBT mode, and the two lower diagrams illustrate the first control signal VG and the second control signal VCG for the first power semiconductor device 1-A (LS device) in diode mode. For both devices, conventional IGBT operation is possible when the first control signal VG is on (e.g., positive) and the second control signal VCG is off (e.g., zero or negative).

[0067] The control scheme shown can provide one or more of the following effects:

[0068] Reverse guidance operation

[0069] When VG is off and VCG is on, device 1-A is reverse-biased and can be used as a freewheeling diode. This saves wafer space used for diodes.

[0070] IGBT desaturation

[0071] By switching the VCG to on before the IGBT (device 1-B) is turned off (see the duration t indicated in the diagram above). desat,IGBT This allows for reducing the plasma density in the IGBT before switching it on. This can significantly reduce IGBT turn-off losses. Furthermore, switching the VCG to on before IGBT turn-off allows for "fault-free" operation.

[0072] The small delay in the circuit is not critical.

[0073] Desaturation of freewheeling diode

[0074] By applying a VG pulse to the diode (device 1-A) before the IGBT (device 1-B) turns on (see the duration t indicated in the third figure), desat,diode This can desaturate a diode. This can be used to reduce diode turn-off losses.

[0075] The control scheme described above is for HS device 1-A in diode mode and LS device 1-B in IGBT mode (i.e., when...). Figure 8 When control schemes 1-A and 1-B are swapped, they work in the same way.

[0076] Figure 9 The four lower charts and Figure 8 The four charts shown are identical. The first / top chart shows an exemplary output of the microcontroller (μC output). (See also: Regarding...) Figure 8 The pulse used for IGBT desaturation (see the duration t indicated in the two upper diagrams) is explained. desat,IGBT This should occur before the actual switching command. However, causality may discourage the direct application of microcontroller signals to power semiconductor devices. In the implementation, the first control signal VG and the second control signal VCG are based on a delay time t relative to the input control signal. d1 and t d2 The signal is generated by delaying the microcontroller signal. Therefore, desaturation pulses (see time period t shown in the second figure) can be generated without violating causality and by maintaining the same on and off times as required by the microcontroller's control algorithm. off ).

[0077] The control scheme described above is applicable to devices with an n-channel configuration. In the case of a p-channel configuration, as is known to those skilled in the art, the voltages of the first control signal VG and the second control signal VCG need to be adjusted accordingly.

[0078] In one implementation, the drivers providing the first control signal VG and the second control signal VCG are monolithically integrated with the power semiconductor device 1. According to this implementation, in the event of a fault (e.g., a short circuit), the delay described above will be bypassed and a shutdown command will be sent immediately.

[0079] This article also introduces methods for manufacturing power semiconductor devices.

[0080] For example, a method of manufacturing a power semiconductor device includes forming: a semiconductor body including a substrate region having a first conductivity type or a second conductivity type, wherein the semiconductor body has a front side; a first load terminal and a second load terminal at the front side, wherein the semiconductor body is configured to conduct both: a forward load current in a forward direction between the first load terminal and the second load terminal and a reverse load current in a reverse direction between the first load terminal and the second load terminal. The forward direction and the reverse direction are opposite to each other. The method further includes: forming a first control terminal at the front side and adjacent to the first load terminal, wherein the semiconductor body is configured to establish a first conductive channel based on a first control voltage applied between the first load terminal and the first control terminal; and forming a second control terminal at the front side and adjacent to the second load terminal, wherein the semiconductor body is configured to establish a second conductive channel based on a second control voltage applied between the second load terminal and the second control terminal.

[0081] The implementation of the above method corresponds to the implementation of the power semiconductor device 1 described above. Therefore, these implementations of the method will not be described verbatim herein, but will be referred to above.

[0082] The above describes implementation methods related to power semiconductor devices and corresponding manufacturing methods.

[0083] For example, these power semiconductor devices are based on silicon (Si). Therefore, a single-crystal semiconductor region or layer, such as the semiconductor body and its regions / areas (e.g., regions, etc.), can be a single-crystal Si region or Si layer. In other embodiments, polycrystalline silicon or amorphous silicon can be used.

[0084] However, it should be understood that the semiconductor body and its regions / areas can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials include, but are not limited to: elemental semiconductor materials such as silicon (Si) or germanium (Ge); group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name just a few. The aforementioned semiconductor materials are also referred to as "homogeneous junction semiconductor materials." When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to: aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switching applications, Si, SiC, GaAs, and GaN materials are currently the primary materials used.

[0085] For ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" are used to describe the positioning of one element relative to a second element. These terms are intended to cover different orientations of the corresponding devices, except for orientations different from those depicted in the accompanying drawings. Furthermore, terms such as "first," "second," etc., are also used to describe various elements, regions, sections, etc., and are not intended to be limiting. Throughout the specification, similar terms may refer to similar elements.

Claims

1. A power semiconductor device (1), comprising: A semiconductor body (10) includes a substrate region (100) having a first conductivity type or a second conductivity type, wherein the semiconductor body has a front side (110); At the first load terminal (11) and the second load terminal (12) on the front side (110), the semiconductor body (10) is configured to conduct both of the following: The positive load current in the positive direction between the first load terminal (11) and the second load terminal (12), and A reverse load current in the opposite direction between the first load terminal (11) and the second load terminal (12), wherein the forward direction and the reverse direction are opposite to each other; A first control terminal (13) located on the front side (110) and adjacent to the first load terminal (11), wherein the semiconductor body (10) is configured to establish a first conductive channel based on a first control voltage (VG) applied between the first load terminal (11) and the first control terminal (13); and A second control terminal (14) located on the front side (110) and adjacent to the second load terminal (12), wherein the semiconductor body (10) is configured to establish a second conductive channel based on a second control voltage (VCG) applied between the second load terminal (12) and the second control terminal (14).

2. The power semiconductor device (1) according to claim 1 further comprises: A body region (1021) having the second conductivity type is located in the semiconductor body (10) and laterally overlaps with both the first load terminal (11) and the first control terminal (13), wherein the body region (1021) is electrically connected to the first load terminal (11), and wherein the first conductive channel is established in the body region (1021).

3. The power semiconductor device (1) according to claim 2 further includes: One or more source regions (1011) of the first conductivity type are present in the semiconductor body (10), wherein the one or more source regions (1011) are electrically connected to the first load terminal (11) and are isolated from the substrate region (100) through the body region (1021).

4. The power semiconductor device (1) according to claim 3, wherein, Based on the number of the one or more source regions (1011), a plurality of first conductive channels are established in the body region (1021).

5. The power semiconductor device (1) according to any one of the preceding claims further includes: A collector region (1022) having the second conductivity type is located in the semiconductor body (10) and laterally overlaps with both the second load terminal (12) and the second control terminal (14), wherein the collector region (1022) is electrically connected to the second load terminal (12), and wherein the second conductive channel is established in the collector region (1022).

6. The power semiconductor device (1) according to claim 5, further comprising: One or more short regions (1012) of the first conductivity type are present in the semiconductor body (10), wherein the one or more short regions (1012) are electrically connected to the second load terminal (12) and are isolated from the substrate region (100) through the collector region (1022).

7. The power semiconductor device (1) according to claim 6, wherein, Based on the number of the one or more short regions (1012), a plurality of second conductive channels are established in the collector region (1022).

8. The power semiconductor device (1) according to any one of claims 5 to 7 further comprises: The semiconductor body (10) has a field stop region (107) of the first conductivity type, wherein the collector region (1022) is at least partially isolated from the substrate region (100) by the field stop region (107).

9. The power semiconductor device (1) according to any one of the preceding claims further comprises: A reduced surface field RESURF region (108) having the first conductivity type or the second conductivity type in the semiconductor body (10), wherein the RESURF region (108) is disposed at the front side (110) and extends between the first load terminal (11) and the second load terminal (12).

10. The power semiconductor device (1) according to any one of the preceding claims, wherein, The first control terminal (13) is electrically insulated from the second control terminal (14).

11. The power semiconductor device (1) according to any one of the preceding claims, wherein, The first control signal (VG) is independent of the second control signal (VCG).

12. The power semiconductor device (1) according to any one of the preceding claims, wherein, The semiconductor body (10) and / or the substrate region (100) have a thickness in the range of 10 μm to 140 μm.

13. The power semiconductor device (1) according to any one of the preceding claims further includes an insulating layer (1-30) on the back side (120) of the semiconductor body (10).

14. The power semiconductor device (1) according to any one of the preceding claims further includes an insulating trench (15) extending from the front side (110) of the semiconductor body (10) to the back side (120), the insulating trench including a trench dielectric (152).

15. The power semiconductor device (1) according to any one of the preceding claims, wherein, The power semiconductor device (1) is arranged in a lateral IGBT configuration.

16. A single-chip half-bridge converter (5), wherein, The single-chip half-bridge converter includes: a first power semiconductor device (1-A), wherein the first power semiconductor device (1-A) is a power semiconductor device according to any one of the preceding claims; and a second power semiconductor device (1-B) connected in series with the first power semiconductor device (1-A), wherein the second power semiconductor device (1-B) is a power semiconductor device according to any one of the preceding claims.

17. The single-chip half-bridge converter (5) according to claim 16, wherein, The first power semiconductor device (1-A) and the second power semiconductor device (1-B) are integrated into the same single chip.

18. The single-chip half-bridge converter (5) according to claim 16 or 17, wherein, The first power semiconductor device (1-A) functions as both a first IGBT and a first freewheeling diode, and the second power semiconductor device (1-B) functions as both a second IGBT and a second freewheeling diode.

19. A method of operating a power semiconductor device (1) according to any one of claims 1 to 15, the method comprising: The first control voltage (VG) is applied between the first load terminal (11) and the first control terminal (13); as well as The second control voltage (VCG) is applied between the second load terminal (12) and the second control terminal (14).

20. A method of manufacturing a power semiconductor device (1), the method comprising forming the following components: The semiconductor body (10) includes a substrate region (100) having a first conductivity type or a second conductivity type, wherein, The semiconductor body has a front side (110); At the first load terminal (11) and the second load terminal (12) on the front side (110), the semiconductor body (10) is configured to conduct both of the following: The positive load current in the positive direction between the first load terminal (11) and the second load terminal (12), and A reverse load current in the opposite direction between the first load terminal (11) and the second load terminal (12), wherein the forward direction and the reverse direction are opposite to each other; A first control terminal (13) located on the front side (110) and adjacent to the first load terminal (11), wherein the semiconductor body (10) is configured to establish a first conductive channel based on a first control voltage (VG) applied between the first load terminal (11) and the first control terminal (13); and A second control terminal (14) located on the front side (110) and adjacent to the second load terminal (12), wherein the semiconductor body (10) is configured to establish a second conductive channel based on a second control voltage (VCG) applied between the second load terminal (12) and the second control terminal (14).

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