Metal oxide semiconductor transistor

Abstract

The invention relates to the field of semiconductors, and provides a metal oxide semiconductor transistor, which comprises a substrate layer; the channel layer is arranged at the top of the substrate layer; the source electrode layer is used for inputting current; the drain electrode layer is used for outputting current; the source electrode layer and the drain electrode layer are respectively arranged at two ends of the channel layer; the gate dielectric layer is arranged at the central position of the top of the channel layer; and the gate layer is arranged on one side of the central position of the top of the gate layer. The metal oxide semiconductor transistor is used for overcoming the defects that in the prior art, manufacturing difficulty is large, a storage function cannot be independently achieved, and thermal stability is poor, the metal oxide semiconductor transistor of a brand new structure is provided, and compared with a traditional structure, the metal oxide semiconductor transistor has the beneficial effect of non-volatility.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a metal-oxide-semiconductor transistor. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are field-effect transistors based on a metal-oxide-semiconductor structure and are widely used in analog and digital circuits.

[0003] Traditional MOSFETs have significant technical limitations, such as complex material structures, high manufacturing difficulty, and high cost: complex P / N doping processes (channel doping, LDD doping, S / D doping, HALO doping, etc.), thermal diffusion activation processes, etc.; they are volatile devices, requiring a voltage application greater than the threshold voltage to turn on, limiting their use to switching and logic device construction, and making them unsuitable for independent storage functions; their miniaturization is limited, as device sizes continue to shrink with advancements in process technology, but performance rapidly declines due to short-channel (DIBL) effects and leakage mechanisms such as GIDL / GIJL, necessitating the use of more complex and expensive GAA device structures; and they have poor thermal stability, as charge carriers are easily affected by temperature, resulting in poor thermal stability and significant differences in performance at high and low temperatures, making them unsuitable for special applications.

[0004] Therefore, there is an urgent need for a new metal-oxide-semiconductor field-effect transistor structure to improve the shortcomings of existing technologies. Summary of the Invention

[0005] This invention provides a metal-oxide-semiconductor transistor to address the shortcomings of related technologies, such as high manufacturing difficulty, inability to independently realize storage functions, and poor thermal stability. The solution of this application provides a metal-oxide-semiconductor transistor with a novel structure, which can bring the beneficial effect of non-volatility compared with the traditional structure.

[0006] This invention provides a metal-oxide-semiconductor transistor, comprising: Substrate layer; A channel layer is disposed on top of the substrate layer; The source layer is used for current input; Drain layer, used for current output; The source layer and the drain layer are respectively disposed at both ends of the channel layer; A gate dielectric layer is disposed at the center of the top of the channel layer; A gate layer is disposed on one side of the top center position of the gate layer.

[0007] According to the metal-oxide-semiconductor transistor provided by the present invention, the source layer and the drain layer are disposed on the top of the channel layer, and the bottom of the source layer and the drain layer are in contact with the channel layer.

[0008] According to the metal-oxide-semiconductor transistor provided by the present invention, the source layer and the drain layer are disposed on the side of the channel layer, and the side edges of the source layer and the drain layer are in contact with the side edges of the channel layer.

[0009] The metal-oxide-semiconductor transistor provided by the present invention further includes a back gate layer; The back gate layer is disposed between the channel layer and the substrate layer, and is used to adjust the electric field distribution of the channel layer; An insulating dielectric layer is provided between the back grid layer and the channel layer.

[0010] According to the metal oxide semiconductor transistor provided by the present invention, the channel layer is made of aluminum scandium nitride, or any one or more mixed materials selected from aluminum, gallium, indium, germanium, tin, zinc, silicon, nitrogen, phosphorus, arsenic, scandium, oxygen and yttrium.

[0011] According to the metal oxide semiconductor transistor provided by the present invention, the material of the gate dielectric layer includes, but is not limited to, any one or more of silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, hafnium oxide, zirconium oxide, hafnium nitride, and zirconium nitride.

[0012] According to the metal-oxide-semiconductor transistor provided by the present invention, the materials of the source layer and the drain layer include, but are not limited to, any one or more of titanium nitride, tungsten, tantalum, molybdenum, platinum, ruthenium, nickel and cobalt.

[0013] According to the metal-oxide-semiconductor transistor provided by the present invention, the material of the gate layer includes, but is not limited to, any one or more of polycrystalline silicon, titanium nitride, tungsten, tantalum, molybdenum, platinum, and aluminum.

[0014] According to the metal-oxide-semiconductor transistor provided by the present invention, during application, when a write voltage exceeding a threshold voltage is applied, the channel resistance changes, thereby realizing data writing. After the write voltage is removed, the written state remains unchanged, exhibiting non-volatility. Apply a readout voltage below the threshold voltage, determine whether the channel resistance is low or high based on the magnitude of the output current, and read out data 1 or 0.

[0015] In the metal-oxide-semiconductor transistor provided by the present invention, the threshold voltage is 0.1 to 1 volt.

[0016] The metal-oxide-semiconductor transistor provided by this invention has the characteristic of non-volatility compared with the traditional metal-oxide-semiconductor transistor structure. It can be directly used to make memory devices to realize 0 / 1 or even polystate storage. In addition, the fabrication process is compatible with the traditional semiconductor fabrication process, and it is easy to replace or upgrade it. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is one of the structural schematic diagrams of the metal-oxide-semiconductor transistor provided in the embodiments of the present invention; Figure 2 This is a second schematic diagram of the structure of a metal-oxide-semiconductor transistor provided in an embodiment of the present invention; Figure 3 This is the third schematic diagram of the structure of the metal-oxide-semiconductor transistor provided in the embodiments of the present invention; Figure 4 This is one of the performance evaluation diagrams provided in the embodiments of the present invention; Figure 5 This is the second performance evaluation diagram provided in the embodiments of the present invention.

[0019] in: 1-Substrate layer; 2-Channel layer; 3-Source layer; 4-Drain layer; 5-Gate dielectric layer; 6-Gate layer; 7-Back gate layer. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0021] Figure 1 This is one of the structural schematic diagrams of a metal-oxide-semiconductor transistor provided in an embodiment of the present invention.

[0022] Figure 2 This is the second schematic diagram of the structure of the metal-oxide-semiconductor transistor provided in the embodiment of the present invention.

[0023] like Figure 1 and Figure 2 As shown, this embodiment provides a metal-oxide-semiconductor transistor, including: Substrate 1; The channel layer 2 is disposed on top of the substrate layer; in practical applications, the material of the channel layer can be aluminum scandium nitride, or any one or more mixed materials selected from aluminum, gallium, indium, germanium, tin, zinc, silicon, nitrogen, phosphorus, arsenic, scandium, oxygen and yttrium. Source layer 3 is used for current input; Drain layer 4 is used for current output; The source layer and the drain layer are respectively disposed at both ends of the channel layer. The materials of the source layer and the drain layer can be any one or more of titanium nitride, tungsten, tantalum, molybdenum, platinum, ruthenium, nickel and cobalt. The gate dielectric layer 5 is disposed at the center of the top of the channel layer. The material of the gate dielectric layer may be any one or more of silicon suboxide, aluminum oxide, silicon nitride, aluminum nitride, hafnium oxide, zirconium oxide, hafnium nitride, and zirconium nitride. Gate layer 6 is disposed on one side of the top center position of the gate dielectric layer. The material of the gate layer may be any one or more of polysilicon, titanium nitride, tungsten, tantalum, molybdenum, platinum and aluminum, including but not limited to polysilicon, titanium nitride, tungsten, tantalum, molybdenum, platinum and aluminum.

[0024] In practical applications, the field-induced phase transition effect of AlScN (aluminum scandium nitride) can be utilized (a phase transition occurs when an electric field is applied, thereby changing the resistance state). Referring to the conventional metal-oxide-semiconductor transistor structure in the prior art, that is, referring to the MOSFET, an NV (non-volatile)-FET can be constructed, which is the metal-oxide-semiconductor transistor provided by the solution of this application. The core difference between the NV-FET provided by the solution of this application and the MOSFET in the related technology is that its channel material is different from that of traditional semiconductors. It is a non-volatile field-induced phase transition material. In addition, other thin film materials can be superimposed on the upper and lower surfaces of the channel material as needed to improve the interface characteristics.

[0025] in Figure 1 and Figure 2 Two implementations of the metal-oxide-semiconductor transistor provided for the solution of this application are as follows: Figure 1 As shown, the source layer and the drain layer can be disposed on the top of the channel layer, and the bottom of the source layer and the drain layer are in contact with the channel layer.

[0026] like Figure 2As shown, the source layer and the drain layer can also be disposed on the side of the channel layer, and the side edges of the source layer and the drain layer are in contact with the side edge of the channel layer. It also includes a back gate layer 7, which is disposed between the channel layer and the substrate layer and is used to adjust the electric field distribution of the channel layer. An insulating dielectric layer is provided between the back gate layer and the channel layer to separate the back gate layer and the channel layer to prevent leakage.

[0027] Figure 3 This is the third schematic diagram of the structure of a metal-oxide-semiconductor transistor provided in an embodiment of the present invention. Figure 3 This is a top view of a transistor. As can be seen from the top view angle, Figure 1 and Figure 2 The two corresponding implementations are identical.

[0028] The metal-oxide-semiconductor transistor provided in this application can also refer to the P / N type MOSFET in the prior art to construct various logic devices and memory devices. In principle, it can completely replace them and bring performance improvements such as non-volatility.

[0029] The metal-oxide-semiconductor transistor provided in this application can perform normal write and read operations during application. Specifically, during data writing, it can... In a write operation, if a write voltage exceeding the forward threshold voltage is applied, after successful programming, the NV-NFET exhibits a low-resistance state (high current), and the NV-PFET exhibits a high-resistance state (low current). After the voltage is removed, the written state remains unchanged, indicating non-volatility. Similarly, if a write voltage exceeding the reverse threshold voltage is applied, after successful programming, the NV-NFET exhibits a high-resistance state (low current), and the NV-PFET exhibits a low-resistance state (high current). After the voltage is removed, the written state remains unchanged, indicating non-volatility. Here, NV-NFET refers to an N-type NV-FET, and NV-PFET refers to a P-type NV-FET.

[0030] When performing data readout operations, NV-NFET and NV-PFET operate in the same way, and both can apply a readout voltage less than the threshold voltage. Preferably, it can be less than 50% of the threshold voltage. Furthermore, it can identify the high-resistance state (off, logic 0) and the low-resistance state (on, logic 1) based on the current magnitude. In practical applications, the threshold voltage can be 0.1 to 1 volt.

[0031] Figure 4 This is one of the performance evaluation diagrams provided in the embodiments of the present invention.

[0032] Figure 5 This is the second performance evaluation diagram provided in the embodiments of the present invention.

[0033] like Figure 4 and Figure 5 As shown, the performance of the metal-oxide-semiconductor transistor provided in this application can also be tested. In this embodiment, an ID-VG test was performed on the metal-oxide-semiconductor transistor. The ID-VG curve can show the variation of the drain-source current (ID) with the gate-source voltage (VGS) under a fixed drain-source voltage (VDS). Figure 4 The ID-VG curve obtained from the ID-VG experiment of NV-NFET. Figure 5 To obtain the ID-VG curve from the ID-VG test of the NV-PFET, from Figure 4 and Figure 5 As can be seen, the NV-FET provided in this embodiment can perform data writing and data reading operations normally.

[0034] In addition, the solution proposed in this application has the following beneficial effects: The principle of electric field-controlled phase transition means that the performance is only related to the electric field, and it has good consistency and temperature stability, making it suitable for special scenarios such as ultra-low temperature environments.

[0035] Its non-volatile nature allows it to be directly used to create storage devices, enabling 0 / 1 or even polymorphic storage.

[0036] The channel requires no doping, the process is simple and reliable, and the cost is low.

[0037] It facilitates process miniaturization and can replace traditional MOSFETs at advanced nodes.

[0038] It is compatible with traditional semiconductor processes and can be easily replaced or upgraded.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A metal-oxide-semiconductor transistor, characterized in that, include: Substrate layer; A channel layer is disposed on top of the substrate layer; The source layer is used for current input; Drain layer, used for current output; The source layer and the drain layer are respectively disposed at both ends of the channel layer; A gate dielectric layer is disposed at the center of the top of the channel layer; A gate layer is disposed on one side of the top center position of the gate layer.

2. The metal-oxide-semiconductor transistor according to claim 1, characterized in that, The source layer and the drain layer are disposed on top of the channel layer, and the bottom of the source layer and the drain layer are in contact with the channel layer.

3. The metal-oxide-semiconductor transistor according to claim 1, characterized in that, The source layer and the drain layer are disposed on the side of the channel layer, and the side edges of the source layer and the drain layer are in contact with the side edges of the channel layer.

4. The metal-oxide-semiconductor transistor according to claim 3, characterized in that, It also includes the back gate layer; The back gate layer is disposed between the channel layer and the substrate layer, and is used to adjust the electric field distribution of the channel layer; An insulating dielectric layer is provided between the back grid layer and the channel layer.

5. The metal-oxide-semiconductor transistor according to claim 1, characterized in that, The channel layer is made of aluminum scandium nitride, or a mixture of one or more of the elements aluminum, gallium, indium, germanium, tin, zinc, silicon, nitrogen, phosphorus, arsenic, scandium, oxygen, and yttrium.

6. The metal-oxide-semiconductor transistor according to claim 1, characterized in that, The material of the gate dielectric layer includes, but is not limited to, any one or more of silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, hafnium oxide, zirconium oxide, hafnium nitride, and zirconium nitride.

7. The metal-oxide-semiconductor transistor according to claim 1, characterized in that, The source layer and the drain layer are made of materials including, but not limited to, any one or more of titanium nitride, tungsten, tantalum, molybdenum, platinum, ruthenium, nickel, and cobalt.

8. The metal-oxide-semiconductor transistor according to claim 1, characterized in that, The material of the gate layer includes, but is not limited to, any one or more of polysilicon, titanium nitride, tungsten, tantalum, molybdenum, platinum, and aluminum.

9. The metal-oxide-semiconductor transistor according to claim 1, characterized in that, During application, when a write voltage exceeding the threshold voltage is applied, the channel resistance changes, thus enabling data writing. After the write voltage is removed, the written state remains unchanged, demonstrating non-volatility. Apply a readout voltage below the threshold voltage, determine whether the channel resistance is low or high based on the magnitude of the output current, and read out data 1 or 0.

10. The metal-oxide-semiconductor transistor according to claim 9, characterized in that, The threshold voltage is 0.1 to 1 volt.

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