Semiconductor structure and manufacturing method thereof
By placing a metal silicide layer on the outside of the functional layer in the semiconductor structure, increasing its distance from the channel region, the channel short-circuit problem caused by metal diffusion is solved, and the stability and performance of the device are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-05
- Publication Date
- 2026-03-13
AI Technical Summary
During semiconductor manufacturing, metal atoms in the metal silicide layer diffuse into the channel region, causing a short circuit in the channel and leading to device failure.
By forming a first gate on the functional layer, its projection area on the substrate is located inside the functional layer, and a metal silicide layer is disposed on the outside of the functional layer, thereby increasing the distance between the metal silicide layer and the channel region and blocking the diffusion of metal atoms.
It effectively prevents metal atoms from diffusing into the channel region, improves the short-channel effect, and enhances the operating stability and performance of the device.
Smart Images
Figure CN121665651A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Technology
[0002] In semiconductor manufacturing processes, a metal silicide layer is typically formed on the device surface to reduce the contact resistance between interconnect structures and other devices.
[0003] In the metal silicide layer, metal atoms diffuse. When metal atoms diffuse into the channel region, it is equivalent to forming a silicide layer in the channel region, which can easily lead to a short circuit in the channel and cause device failure. Summary of the Invention
[0004] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising:
[0005] Substrate, including a first region;
[0006] A functional layer is located on the substrate in the first region;
[0007] A first gate is located on the functional layer, and the projection area of the first gate on the substrate is located within the projection area of the functional layer on the substrate;
[0008] A metal silicide layer is located within the substrate and adjacent to the functional layer, wherein the projection area of the metal silicide layer on the substrate is located outside the projection area of the functional layer on the substrate.
[0009] In some embodiments, the functional layer includes:
[0010] A first functional layer is located between the gate and the substrate;
[0011] The second functional layer is located between the first functional layer and the metal silicide layer;
[0012] The thickness of the second functional layer is less than or equal to the thickness of the first functional layer.
[0013] In some embodiments, the thickness of the second sub-functional layer gradually decreases in the direction from the first sub-functional layer to the metal silicide layer.
[0014] In some embodiments, the width of the second functional layer is smaller than the width of the first functional layer in the horizontal direction.
[0015] In some embodiments, the width of the second functional layer is substantially equal to half the width of the first functional layer.
[0016] In some embodiments, the bandwidth of the functional layer is less than the bandwidth of the substrate.
[0017] In some embodiments, the diffusion distance of the metal silicide layer in the horizontal direction is less than the width of the second functional layer.
[0018] In some embodiments, the substrate further includes:
[0019] The second region is adjacent to the first region;
[0020] The second gate is located on the substrate within the second region.
[0021] In some embodiments, recesses are provided in the substrate located on both sides of the second gate in the second region;
[0022] The maximum depth of the recess is less than the thickness of the first functional layer.
[0023] In some embodiments, the width of the second functional layer is smaller than the width of the recess in the horizontal direction.
[0024] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:
[0025] A substrate is provided, the substrate including a first region;
[0026] A functional layer is formed on the substrate in the first region;
[0027] A first gate is formed on the functional layer, and the projection area of the first gate on the substrate is located within the projection area of the functional layer on the substrate;
[0028] A metal silicide layer is formed in the substrate of the first region, the metal silicide layer is adjacent to the functional layer, and the projection area of the metal silicide layer on the substrate is located outside the projection area of the functional layer on the substrate.
[0029] In some embodiments, after forming the first gate, the method further includes:
[0030] A barrier layer is formed on the substrate in the first region, the barrier layer covering the functional layer and the first gate;
[0031] Remove part of the barrier layer to form a barrier corner;
[0032] The blocking corner is located at the junction of the functional layer and the first gate.
[0033] In the horizontal direction, the width of the blocking corner covering the functional layer is smaller than the width of the first gate.
[0034] In some embodiments, prior to forming the metal silicide layer, the method further includes:
[0035] The blocking corner and the functional layer are etched to remove the blocking corner and part of the functional layer;
[0036] In the direction from the first gate to the metal silicide layer, the thickness of the functional layer gradually decreases.
[0037] In some embodiments, the substrate further includes a second region and a second gate on the substrate located in the second region;
[0038] The blocking corner also covers the junction between the second gate and the substrate.
[0039] In some embodiments, prior to forming the metal silicide layer in the second region, the method further includes:
[0040] The blocking corner and the substrate located in the second region are etched to remove the blocking corner and a portion of the substrate to form a recess in the substrate;
[0041] In the horizontal direction, the maximum depth of the recess is less than the thickness of the functional layer located below the first gate.
[0042] In some embodiments, the step of forming the metal silicide layer includes:
[0043] A metal layer is formed on the substrate located outside the functional layer;
[0044] An annealing step is performed to allow the metal layer to react with the substrate;
[0045] In summary, this disclosure provides a semiconductor structure and its manufacturing method. A first gate is formed on a functional layer, with its projection area on the substrate located inside the projection area of the functional layer on the substrate; that is, in the horizontal direction, the width of the first gate is smaller than the width of the functional layer. Simultaneously, the projection area of the metal silicide layer on the substrate is located outside the projection area of the functional layer, meaning there is no overlap between the projection areas of the metal silicide layer and the functional layer on the substrate. This increases the distance between the metal silicide layer and the first gate, effectively increasing the distance from the metal silicide layer to the channel region, thus hindering the diffusion of metal atoms. Therefore, metal ions in the metal silicide layer are less likely to diffuse into the channel region, thereby improving the short-channel effect. Attached Figure Description
[0046] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor structure according to an exemplary embodiment;
[0047] Figure 2 This is a schematic diagram of a substrate according to an exemplary embodiment;
[0048] Figure 3 This is a schematic diagram of a functional layer according to an exemplary embodiment;
[0049] Figure 4 This is a schematic diagram of a first gate and a second gate according to an exemplary embodiment;
[0050] Figure 5 This is a schematic diagram of a sidewall according to an exemplary embodiment;
[0051] Figure 6 This is illustrated according to an exemplary embodiment. Figure 5 Top view;
[0052] Figure 7 This is illustrated according to an exemplary embodiment. Figure 5 Another top view;
[0053] Figure 8 This is a schematic diagram of a barrier layer according to an exemplary embodiment;
[0054] Figure 9 This is a schematic diagram of a blocking corner according to an exemplary embodiment;
[0055] Figure 10 This is a schematic diagram of a recess according to an exemplary embodiment;
[0056] Figure 11 This is a schematic diagram of a metal silicide layer according to an exemplary embodiment;
[0057] Figure 12 This is an enlarged view of a functional layer according to an exemplary embodiment;
[0058] Figure 13 This is a top view illustrating a first gate, a functional layer, and a metal silicide layer according to an exemplary embodiment. Detailed Implementation
[0059] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.
[0060] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0061] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0062] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0063] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.
[0064] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.
[0065] Because metal silicides have advantages such as low resistance, low contact resistance with silicon, strong adhesion to silicon, and low stress at the contact interface with silicon, they have been widely used as contacts, electrodes, or wires in semiconductor devices. Moreover, the use of metal silicides in semiconductor devices can also shorten the RC delay time of semiconductor devices.
[0066] In some embodiments, nickel, cobalt, or titanium is used as the metal layer, which reacts with the substrate to form a metal silicide. NiSi has the advantages of low formation temperature, low silicon consumption during silicide formation, and lower contact resistance. However, Ni has a larger diffusion coefficient in silicon compared to Ti, Co, etc. When Ni diffuses into the channel region, it is equivalent to forming a silicide layer in the channel region, which can easily lead to a short circuit in the channel.
[0067] This embodiment of the invention extends the distance between the metal silicide layer and the channel region, thereby blocking the diffusion of Ni into the channel region, reducing the possibility of Ni diffusion into the channel region, improving the short-channel effect, and ensuring the operating stability of the device.
[0068] like Figure 1 As shown in the embodiments of this disclosure, a method for manufacturing a semiconductor structure is proposed, including:
[0069] S1: Provide a substrate, the substrate including a first region;
[0070] S2: A functional layer is formed on the substrate of the first region;
[0071] S3: A first gate is formed on the functional layer, and the projection area of the first gate on the substrate is located within the projection area of the functional layer on the substrate;
[0072] S4: A metal silicide layer is formed in the substrate of the first region. The metal silicide layer is adjacent to the functional layer, and the projection area of the metal silicide layer on the substrate is located outside the projection area of the functional layer on the substrate.
[0073] In this embodiment, a first gate is formed on the functional layer, and the projection area of the first gate on the substrate is located inside the projection area of the functional layer on the substrate, meaning the width of the functional layer is greater than the width of the first gate. Simultaneously, a metal silicide layer is adjacent to the functional layer, and the projection area of the metal silicide layer on the substrate is located outside the projection area of the functional layer on the substrate, meaning the metal silicide layer does not overlap with the functional layer. This increases the distance from the metal silicide layer to the first gate, which in turn increases the distance from the metal silicide layer to the channel region. This effectively blocks the diffusion of metal atoms into the channel region, thereby improving the short-channel effect.
[0074] like Figure 2 As shown, in step S1, a substrate 101 is provided in this embodiment of the disclosure. The substrate 101 may be a silicon substrate, such as a P-type or N-type substrate. The substrate 101 may also be a compound semiconductor, such as silicon carbide, indium arsenide, etc. The substrate 101 may include an isolation structure 102, which may be a shallow trench isolation structure. The isolation structure 102 can divide the substrate 101 into multiple regions. In this embodiment, a first region 103 and a second region 104 are shown. The first region 103 and the second region 104 can be used to form a PMOS region or an NMOS region. The first region 103 is used to form a PMOS region, and the second region 104 is used to form an NMOS region. Alternatively, the first region 103 is used to form an NMOS region, and the second region 104 is used to form a PMOS region. To form a PMOS region, it is necessary to dope with P-type impurities, such as boron, aluminum, or gallium. To form an NMOS region, it is necessary to dope with N-type impurities, such as phosphorus, arsenic, or antimony.
[0075] like Figure 3 As shown, in step S2, in this embodiment, a PMOS device is formed in the first region 103 and an NMOS device is formed in the second region 104, thereby forming a functional layer 105 on the substrate 101 of the first region 103. The functional layer 105 can be a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. In this embodiment, the bandwidth of the functional layer 105 can be smaller than the bandwidth of the substrate 101, thereby increasing the compressive stress in the channel region of the PMOS device and thus improving hole mobility to enhance device performance. The functional layer 105 can be silicon-germanium (SiGe). Of course, in some embodiments, if a PMOS device is formed in the second region 104, the functional layer 105 can be formed on the substrate 101 of the second region 104.
[0076] like Figure 3 As shown, in this embodiment of the present disclosure, silicon-germanium can be formed on the surface of the substrate 101 in the first region 103 using an epitaxial growth process, i.e., a functional layer 105 can be formed. This functional layer 105 is not formed on the isolation structure 102. The thickness of the functional layer 105 can be between 10-15 nm.
[0077] like Figure 4 As shown, in step S3, after forming the functional layer 105, a first gate 106 can be formed on the functional layer 105 in the first region 101, and a second gate 107 can be formed on the substrate 101 in the second region 104. The structures of the first gate 106 and the second gate 107 can be identical. The first gate 106 can be a polysilicon gate or a high-K metal gate. After forming the first gate 106 and the second gate 107, a protective layer 108 can be formed on the functional layer 105 and the first gate 106, and a protective layer 108 can be formed on the substrate 101 in the second region 104. That is, the protective layer 108 covers the functional layer 105 and the first gate 106, and the protective layer 108 also covers the second gate 107. The protective layer 108 can be silicon nitride or silicon oxide or a combination of both.
[0078] like Figure 5As shown, after forming the protective layer 108, it is also necessary to remove the protective layer 108 located on the top surface of the first gate 106 and the protective layer 108 located on the functional layer 105, thereby retaining the protective layer 108 located on the sidewalls of the first gate 106, that is, sidewalls 109 are formed on both sides of the first gate 106. Similarly, sidewalls 109 are formed on both sides of the second gate 107. In this embodiment, the protective layer 108 is removed, for example, by an etch-back method. The sidewalls 109 can prevent short circuits between the gate and subsequent conductive plugs, improving device performance. In some embodiments, the sidewalls 109 can also be used as part of the structure of the first gate 106 and the second gate 107, that is, the first gate 106 can be composed of a polysilicon gate and sidewalls 109, and the second gate 107 can also be composed of a polysilicon gate and sidewalls 109.
[0079] like Figures 5-6 As shown, Figure 6 The image shows a top view of the first gate 106 on functional layer 105. From Figure 6 As can be seen, the functional layer 105 forms a functional projection region 1051 on the substrate 101, the first gate 106 forms a gate projection region 1061 on the functional layer 105, and the sidewall 109 forms a sidewall projection region 1091 on the functional layer 105. The gate projection region 1061 is located inside the functional projection region 1051, that is, in the X direction (horizontal direction), the width of the first gate 106 is smaller than the width of the functional layer 105, and in the Y direction (vertical direction), the width of the first gate 106 is smaller than the width of the functional layer 105. Therefore, the first gate 106 is located above the functional layer 105, and the first gate 106 has a certain distance from the end of the functional layer 105 in the X or Y direction.
[0080] like Figure 5 and Figure 7As shown, in some embodiments, to facilitate the formation of conductive plugs on the first gate 106, the width of the first gate 106 can be extended in the Y direction, so that part of the structure of the gate projection region 1061 is located outside the functional projection region 1051, that is, the gate projection region 1061 is not completely located inside the functional projection region 1051. However, in the X direction, the width of the first gate 106 is still smaller than the width of the functional layer 105. That is, the horizontal width of the gate projection region 1061 is smaller than the horizontal width of the functional layer 1051. In subsequent processes, metal silicide layers will be formed on both sides of the functional layer 105 in the X direction, thus the width of the first gate 106 in the X direction is more important. Therefore, in the embodiments of this disclosure, the gate projection region 1061 being located inside the functional projection region 1051 can also be understood as: in the X direction, the horizontal width of the gate projection region 1061 is smaller than the horizontal width of the functional projection region 1051, and the gate projection region 1061 has a certain distance from the end of the functional projection region 1051 at least in the X direction. Therefore, it can be considered that... Figure 6 and Figure 7 The gate projection region 1061 is located inside the functional projection region 1051.
[0081] like Figures 6-7 As shown, the horizontal width of the gate projection region 1061 is smaller than the horizontal width of the functional projection region 1051, and there is a gap between the gate projection region 1061 and the end of the functional projection region 1051 in the horizontal direction. Simultaneously, the region below the gate projection region 1061 is the channel region, meaning there is also a distance between the channel region and the end of the functional projection region 1051 in the X direction. Since the channel region is located inside the functional layer projection region 1051 in the X direction, this indirectly increases the distance between the metal silicide layer and the channel region, indirectly preventing metal atoms in the metal silicide layer from diffusing into the channel region, thereby improving the short-channel effect and enhancing device performance.
[0082] like Figures 8-9As shown, after forming the sidewall 109, a barrier layer 110 is formed on the first region 103 and the second region 104. In the first region 103, the barrier layer 110 covers the functional layer 105 and the first gate 106. In the second region 104, the barrier layer 110 covers the substrate 101 and the second gate 107. This embodiment uses the formation of the barrier layer 110 in the first region 103 as an example. In this embodiment, a gas with a high C / F atom ratio, such as C4F8 / C4F6, is used to deposit the barrier layer 110. Simultaneously, during the deposition process, argon plasma is used to bombard the barrier layer 110. Due to the obstruction of the first gate 106 and the reflection of argon gas on the sidewall of the first gate 106, the barrier layer 110 at the junction of the first gate 106 and the functional layer 105 has a greater thickness. The material of the barrier layer 110 can be a polymer composed of C and F atoms. In this embodiment, the junction of the first gate 106 and the functional layer 105 can be understood as the angled region (e.g., a right angle) formed by the first gate 106 and the functional layer 105. The junction of the first gate 106 and the functional layer 105 can also be understood as the angled region formed by the sidewall 109 and the functional layer 105. The junction of the second gate 107 and the substrate 101 can be understood as the angled region (e.g., a right angle) formed by the second gate 107 and the substrate 101. The junction of the second gate 107 and the substrate 101 can also be understood as the angled region formed by the sidewall 109 and the substrate 101.
[0083] like Figure 9As shown, after the barrier layer 110 is formed, it is then etched. In this embodiment, a gas with a relatively small C / F atomic ratio, such as CF4 / CHF3, is used to etch the barrier layer 110. Simultaneously, under an appropriate bias voltage, the etching gas is kept vertically downward, thus reaching the barrier layer 110 on the surface of the removed functional layer 105 and the barrier layer 110 on the sidewall of the first gate 106. Since the barrier layer 110 at the junction of the first gate 106 and the functional layer 105 is thicker, while the barrier layer 110 on the surface of the functional layer 105 is thinner, after etching, a portion of the barrier layer 110 remains at the junction, forming a barrier corner 111. Similarly, a barrier corner 111 is formed at the junction of the second gate 107 and the substrate 101. This embodiment uses the barrier corner 111 in the first region 103 as an example. This barrier corner 111 is located in the angled region formed by the first gate 106 and the functional layer 105. The blocking corner 111 also covers a portion of the functional layer 105. Since the functional layer 105 needs to be etched in subsequent processes to form source / drain regions in the substrate 101, the blocking corner 111 can protect the functional layer 105 below it during the etching process, thus leaving a portion of the blocking layer 105, i.e., retaining the portion of the functional layer 105 below the blocking corner 111. Horizontally, the width of the functional layer 105 covered by the blocking corner 111 is smaller than the width of the first gate 106. Because the blocking corner 111 has a small horizontal width, meaning the horizontal width of the retained functional layer 105 is also relatively small, the spacing between the source / drain regions can be reduced when forming the source / drain regions on the outside of the functional layer 105. This reduces the conduction time for carrier flow across the channel, lowers the gate voltage required for channel turn-on, facilitates easier conduction, reduces switching losses, and simultaneously reduces channel on-resistance, thus reducing conduction losses.
[0084] like Figure 10As shown, after forming the blocking corner 111, the functional layer 105 needs to be etched to expose the surface of the substrate 101 in the first region 103. In this embodiment, the functional layer 105 is silicon-germanium. If the functional layer 105 is not removed to expose the surface of the substrate 101, a metal silicide layer cannot be formed on the surface of the substrate 101. During the etching process of the functional layer 105, due to the blocking effect of the blocking corner 111, a portion of the functional layer 105 below the blocking corner 111 is retained, that is, a portion of the functional layer 105 exists on both sides of the first gate 106. The thickness of the functional layer 105 below the first gate 106 is greater than the thickness of the functional layers 105 on both sides of the first gate 106. In the horizontal direction, towards the second gate 107 from the first gate 106, the thickness of the functional layer 105 located outside the first gate 106 gradually decreases, and the functional layer 105 is recessed towards the substrate. Because the functional layer 105 is recessed, it is beneficial to form an interlayer dielectric layer structure on the functional layer 105. Simultaneously, during the etching of the functional layer 105, the substrate 101 in the second region 104 is also etched, thereby forming recesses 112 on both sides of the second gate 107. It should be noted that the maximum depth of these recesses 112 is less than the thickness of the functional layer 105 located below the first gate 106; that is, the recesses 112 are relatively shallow. If the recesses 112 were deeper, meaning more of the substrate 101 is etched, the distance from the source / drain region to the channel surface would increase, potentially leading to a short-channel effect.
[0085] like Figure 11As shown, in step S4, before forming the metal silicide layer 114, the substrate 101 needs to be doped to form source / drain regions 113 in the substrate 101. In the first region 103, the source / drain regions 113 are located outside the functional layer 105 and do not extend below the functional layer 105. In the second region 104, the source / drain regions 113 are located in the recess 112 and have a certain distance from the second gate 107. After forming the source / drain regions 113, a metal layer is formed on the source / drain regions 113, and then annealing is performed to allow the metal layer 113 to react with the substrate 101, thereby forming the metal silicide layer 114. In this embodiment, nickel metal is used to react with the substrate to form NiSi. NiSi has the advantages of low formation temperature, low silicon consumption during silicide formation, and lower contact resistance. Meanwhile, since the metal silicide layer 114 is located outside the functional layer 105, that is, the projection area of the metal silicide layer 114 on the substrate 101 is outside the projection area of the functional layer 105 on the substrate 101, the metal silicide layer 114 does not extend below the functional layer 105. Because the metal silicide layer 114 is far from the channel region, metal atoms in the metal silicide layer 114 are difficult to diffuse into the channel region. In this embodiment, metal atoms diffuse from high concentration to low concentration, and the diffusion distance decreases as the concentration decreases. The functional layer 105 located on both sides of the first gate 106 has a certain width, and the diffusion distance of metal atoms will be less than the horizontal width of the functional layer 105. Therefore, it is even more difficult for metal atoms to diffuse into the channel region, and thus metal silicide will not form in the channel region, thereby improving the short-channel effect.
[0086] like Figure 11 As shown, by increasing the distance between the metal silicide layer 114 and the channel region, this embodiment of the present disclosure increases the difficulty of metal atoms diffusing into the channel region, thereby reducing the diffusion of metal atoms into the channel region and reducing the formation of metal silicides in the channel region, thus reducing the short-channel effect.
[0087] like Figure 11As shown, this disclosure provides a semiconductor structure, the manufacturing method of which can be referred to the above description. The semiconductor structure may include a substrate 101, with an isolation structure 102 dividing the substrate 101 into a first region 103 and a second region 104. The first region 103 can serve as a PMOS region, and the second region 104 can serve as an NMOS region. A functional layer 105 is located on the substrate 101 in the first region 103, with a first gate 106 and sidewalls 109 on its sidewalls. A source / drain region 113 is located on the substrate 101 in the first region 103, with a metal silicide layer 114 in the source / drain region 113. In this embodiment, a PMOS device is formed on the first region 103, and the bandwidth of the functional layer 105 is less than the bandwidth of the substrate 101. The material of functional layer 105 can be a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor, such as silicon germanium. The material of substrate 101 can be a silicon substrate. Functional layer 105 can increase the compressive stress in the channel region of the PMOS device, thereby increasing hole mobility and improving device performance.
[0088] like Figures 12-13 As shown, the functional layer 105 may include a first functional layer 105a and a second functional layer 105b. The first functional layer 105a may be in contact with the substrate 101 and the first gate 106. The second functional layer 105b is located on both sides of the first functional layer 105a. The second functional layer 105b is in contact with the substrate 101. The thickness of the first functional layer 105a is greater than the thickness of the second functional layer 105b. Since the first gate 106 is located on the first functional layer 105a, a channel region is formed directly below the first functional layer 105a. Because the first functional layer 105a has a greater thickness, the hole mobility can be improved, thereby improving the performance of the PMOS device. The thickness of the second functional layer 105b gradually decreases, that is, from the first gate 106 to the metal silicide layer 114, the thickness of the second functional layer 105b gradually decreases, and the second functional layer 105b is recessed towards the substrate 101. Since an interlayer dielectric layer needs to be deposited on the substrate 101 later, the recessed nature of the second functional layer 105b facilitates the deposition process of the interlayer dielectric layer.
[0089] like Figures 12-13As shown, in the top view direction, the first gate 106 has a gate projection region 1061 on the functional layer 105, and the functional layer 105 has a functional projection region 1051 on the substrate 101. The gate projection region 1061 is located within the functional projection region 1051. The metal silicide layer 1141 has a silicide projection region 1141 on the substrate 101. The silicide projection region 1141 is located outside the functional projection region 1051, that is, the silicide projection region 1141 does not overlap with the functional projection region 1051, meaning that the metal silicide layer 114 does not extend below the functional layer 105. Since the metal silicide layer 114 does not extend below the functional layer 105, the distance from the metal silicide layer 114 to the channel region is equivalent to the width d2 of the second functional layer 105b. Because the diffusion distance of metal atoms in the metal silicide layer 114 is less than the width d2 of the second functional layer 105b, metal atoms are less likely to diffuse into the channel region, thus preventing the formation of metal silicide in the channel region and improving device performance. Simultaneously, in the horizontal direction, the width d1 of the first functional layer 105b is greater than the width d2 of the second functional layer 105b. Below the metal silicide layer 114 are source / drain regions 113. Since the width d2 of the second functional layer 105b is smaller, the spacing between the source / drain regions 113 in the first region 103 can be reduced, thereby decreasing the conduction time for carrier flow across the channel, lowering the gate voltage required for channel turn-on, making conduction easier, reducing switching losses, and simultaneously reducing channel on-resistance, thus reducing conduction losses. Furthermore, since the diffusion distance of metal atoms in the metal silicide layer 114 is related to the concentration of metal atoms, the higher the metal atom concentration, the greater the diffusion distance. Since the diffusion distance of metal atoms is less than the width d2 of the second functional layer 105b, and the spacing between the source / drain regions 113 also needs to be ensured, the width of the second functional layer 105b is set to be approximately half the width d1 of the first functional layer 105b in this embodiment. This ensures that metal atoms in the metal silicide layer 114 will not enter the channel region, and also reduces the conduction time of charge carriers crossing the channel.
[0090] like Figures 11-12As shown, the substrate 101 contains a second region 104. The second region 104 is used to form an NMOS device. A second gate 107 is located in the second region 104, i.e., the second gate 107 is situated on the substrate 101 of the second region 104. The first gate 106 and the second gate 107 can have the same structure, for example, both being polysilicon gates. Recesses 112 are located on both sides of the second gate 107 in the substrate 101. Source / drain regions 113 are located in the recesses 112, and metal silicide layers 114 are present in the source / drain regions 113. The maximum depth of the recesses 112 is less than the thickness of the first functional layer 105a. The recesses 112 are obtained by etching the substrate 101; if the substrate 101 is etched too deeply, it will cause problems. Simultaneously, in the horizontal direction, the width of the second functional layer 105b is less than the width of the recesses 112. That is, the recesses 112 have a shallow depth and a large width. If the recess 112 is deep, the distance between the source / drain region 113 and the surface of the channel region increases, which can easily lead to a short-channel effect. If the recess 112 is wide in the horizontal direction, it can maintain a certain distance between the source / drain region 113 and the second gate 107, reducing gate-induced leakage current in the source / drain region 113.
[0091] Of course, in subsequent processes, conductive plugs need to be formed on the first gate 106, the second gate 107, and the metal silicide layer 114 to transmit electrical signals.
[0092] In summary, this disclosure provides a semiconductor structure and its manufacturing method. During the manufacturing process, a blocking corner is formed at the junction of the first gate and the functional layer. During the etching of the functional layer, the blocking corner acts as a barrier, allowing a portion of the functional layer below the blocking corner to be retained, thus forming a second functional layer. During the formation of the metal silicide layer, the metal silicide layer is located outside the functional layer, increasing the distance between the metal silicide layer and the channel region. This makes it difficult for metal atoms in the metal silicide layer to diffuse into the channel region, thereby improving device performance.
[0093] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A semiconductor structure, characterized in that, include: Substrate, including a first region; A functional layer is located on the substrate in the first region; A first gate is located on the functional layer, and the projection area of the first gate on the substrate is located within the projection area of the functional layer on the substrate; A metal silicide layer is located within the substrate and adjacent to the functional layer, wherein the projection area of the metal silicide layer on the substrate is located outside the projection area of the functional layer on the substrate.
2. The semiconductor structure according to claim 1, characterized in that, The functional layer includes: A first functional layer is located between the gate and the substrate; The second functional layer is located between the first functional layer and the metal silicide layer; The thickness of the second functional layer is less than the thickness of the first functional layer.
3. The semiconductor structure according to claim 2, characterized in that, The thickness of the second sub-functional layer gradually decreases in the direction from the first sub-functional layer to the metal silicide layer.
4. The semiconductor structure according to claim 2 or 3, characterized in that, In the horizontal direction, the width of the second functional layer is smaller than the width of the first functional layer.
5. The semiconductor structure according to claim 4, characterized in that, The width of the second functional layer is approximately half the width of the first functional layer.
6. The semiconductor structure according to any one of claims 1-3, characterized in that, The bandwidth of the functional layer is less than the bandwidth of the substrate.
7. The semiconductor structure according to claim 2 or 3, characterized in that, In the horizontal direction, the diffusion distance of the metal silicide layer is less than the width of the second functional layer.
8. The semiconductor structure according to claim 2 or 3, characterized in that, The substrate further includes: The second region is adjacent to the first region; The second gate is located on the substrate within the second region.
9. The semiconductor structure according to claim 8, characterized in that, In the second region, recesses are provided in the substrate located on both sides of the second gate; The maximum depth of the recess is less than the thickness of the first functional layer.
10. The semiconductor structure according to claim 9, characterized in that, In the horizontal direction, the width of the second functional layer is smaller than the width of the recess.
11. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region; A functional layer is formed on the substrate in the first region; A first gate is formed on the functional layer, and the projection area of the first gate on the substrate is located within the projection area of the functional layer on the substrate; A metal silicide layer is formed in the substrate of the first region, the metal silicide layer is adjacent to the functional layer, and the projection area of the metal silicide layer on the substrate is located outside the projection area of the functional layer on the substrate.
12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, After forming the first gate, the method further includes: A barrier layer is formed on the substrate in the first region, the barrier layer covering the functional layer and the first gate; Remove part of the barrier layer to form a barrier corner; The blocking corner is located at the junction of the functional layer and the first gate. In the horizontal direction, the width of the blocking corner covering the functional layer is smaller than the width of the first gate.
13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that, Prior to the formation of the metal silicide layer, the method further includes: The blocking corner and the functional layer are etched to remove the blocking corner and part of the functional layer; In the direction from the first gate to the metal silicide layer, the thickness of the functional layer gradually decreases.
14. The method for manufacturing a semiconductor structure according to claim 12 or 13, characterized in that, The substrate further includes a second region, and a second gate on the substrate located in the second region; The blocking corner also covers the junction between the second gate and the substrate.
15. The method for manufacturing a semiconductor structure according to claim 14, characterized in that, Before forming the metal silicide layer in the second region, the method further includes: The blocking corner and the substrate located in the second region are etched to remove the blocking corner and a portion of the substrate to form a recess in the substrate; In the horizontal direction, the maximum depth of the recess is less than the thickness of the functional layer located below the first gate.
16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that, The steps for forming the metal silicide layer include: A metal layer is formed on the substrate located outside the functional layer; An annealing step is performed to allow the metal layer to react with the substrate; In the horizontal direction, the diffusion distance of the metal silicide layer is less than the width of the functional layers located on both sides of the first gate.