Transistor structure and manufacturing method thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-18
- Publication Date
- 2026-03-13
Smart Images
Figure CN121665652A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor structure, and more particularly to a transistor structure. Background Technology
[0002] In integrated circuits, transistors are one of the main components. A transistor includes a gate and source and drain regions located in the substrate on either side of the gate. In some transistors, the gate can be a metal gate. Metal gates can be formed using a replacement gate process. In this process, a polysilicon layer is removed, and a metal layer is filled into the recess formed by the removal of the polysilicon layer. Then, a chemical mechanical polishing (CMP) process is performed to remove the metal layer outside the recess, forming a metal gate within the recess.
[0003] However, when the metal gate is large, dishing occurs on the top surface of the metal layer in the groove after the aforementioned chemical mechanical polishing process, thus affecting the performance of the formed transistor. Furthermore, to avoid dishing, multiple transistors with smaller metal gates are formed. This increases the chip size, which is detrimental to the development of microdevices. Summary of the Invention
[0004] The present invention provides a transistor structure and a method for manufacturing the same, wherein the gate includes a metal portion and a polycrystalline silicon portion located within the metal portion.
[0005] The transistor structure of the present invention includes a gate, a doped region, and a gate dielectric structure. The gate is disposed on a substrate and includes a first portion and a second portion, wherein the second portion surrounds the first portion, and the material of the first portion is different from the material of the second portion. The doped region is disposed in the substrate on both sides of the gate. The gate dielectric structure is disposed between the gate and the substrate.
[0006] In one embodiment of the transistor structure of the present invention, the material of the first portion includes polycrystalline silicon, and the material of the second portion includes metal.
[0007] In one embodiment of the transistor structure of the present invention, the gate dielectric structure includes a high dielectric constant layer.
[0008] In one embodiment of the transistor structure of the present invention, the gate dielectric structure further includes an interface layer disposed between the high dielectric constant layer and the substrate.
[0009] In one embodiment of the transistor structure of the present invention, a cover layer is further included, which is disposed between the gate dielectric structure and the gate.
[0010] In one embodiment of the transistor structure of the present invention, the top surface of the first portion and the top surface of the second portion are coplanar.
[0011] In one embodiment of the transistor structure of the present invention, the first portion is in contact with the second portion.
[0012] In one embodiment of the transistor structure of the present invention, the first portion includes a plurality of patterned portions.
[0013] In one embodiment of the transistor structure of the present invention, the plurality of patterned portions are arranged in an array on the substrate.
[0014] The method for manufacturing the transistor structure of the present invention includes the following steps: forming a gate on a substrate, wherein the gate includes a first portion and a second portion, the second portion surrounding the first portion, and the material of the first portion being different from the material of the second portion; forming a gate dielectric structure between the gate and the substrate; and forming doped regions in the substrate on both sides of the gate.
[0015] In one embodiment of the method for manufacturing the transistor structure of the present invention, the material of the first part includes polycrystalline silicon, and the material of the second part includes metal.
[0016] In one embodiment of the method for manufacturing the transistor structure of the present invention, the gate dielectric structure includes a high dielectric constant layer.
[0017] In one embodiment of the method for manufacturing the transistor structure of the present invention, the gate dielectric structure further includes an interface layer formed between the high dielectric constant layer and the substrate.
[0018] In one embodiment of the method for manufacturing a transistor structure according to the present invention, the method for forming the gate and the gate dielectric structure includes the following steps: forming a gate dielectric material layer on the substrate; forming a first gate material layer on the gate dielectric material layer; patterning the gate dielectric material layer and the first gate material layer to form the gate dielectric structure and an initial gate; removing a portion of the initial gate to form a first portion on the gate dielectric structure; and forming a second portion on the gate dielectric structure to form the gate.
[0019] In one embodiment of the method for manufacturing the transistor structure of the present invention, the method for forming the second portion includes the following steps: forming a second gate material layer on the gate dielectric structure to cover the first portion; removing the portion of the second gate material layer until the top surface of the first portion is exposed.
[0020] In one embodiment of the method for manufacturing the transistor structure of the present invention, the doped region is formed after the gate dielectric material layer and the gate material layer are patterned.
[0021] In one embodiment of the manufacturing method of the transistor structure of the present invention, the top surface of the first portion and the top surface of the second portion are coplanar.
[0022] In one embodiment of the method for manufacturing the transistor structure of the present invention, the first portion is in contact with the second portion.
[0023] In one embodiment of the method for manufacturing the transistor structure of the present invention, the first part includes a plurality of patterned portions.
[0024] In one embodiment of the method for manufacturing the transistor structure of the present invention, the plurality of patterned portions are arranged in an array on the substrate.
[0025] Based on the above, in the transistor structure of the present invention, the gate includes a metal portion and a polycrystalline silicon portion located in the metal portion. Therefore, during the replacement of the gate, the top surface of the gate can be effectively prevented from being recessed due to chemical mechanical polishing. Attached Figure Description
[0026] Figures 1A to 1E This is a schematic cross-sectional view of the manufacturing process of the transistor structure according to an embodiment of the present invention;
[0027] Figure 2 This is a top view of the gate of a transistor structure according to an embodiment of the present invention;
[0028] Figure 3 This is a top view of the gate of a transistor structure according to another embodiment of the present invention.
[0029] Symbol Explanation
[0030] 10: Transistor Structure
[0031] 100: Base
[0032] 102: Isolation Structure
[0033] 104: Interface Material Layer
[0034] 104a: Interface Layer
[0035] 106: Gate dielectric material layer
[0036] 106a: Gate dielectric layer
[0037] 108: Covering material layer
[0038] 108a: Overlay
[0039] 110: First gate material layer
[0040] 110a: Initial gate
[0041] 112: Hard mask material layer
[0042] 112a: Hard mask layer
[0043] 114: Spacer wall
[0044] 116: Doped region
[0045] 118: Metal silicide layer
[0046] 120: Dielectric layer
[0047] 122: Contact etching stop layer
[0048] 124: Second gate material layer
[0049] G: Gate
[0050] GS: Initial gate structure
[0051] P1: Part 1
[0052] P2: Part Two
[0053] R: Groove Detailed Implementation
[0054] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same elements will be designated with the same symbols in the following description.
[0055] The terms "includes," "including," and "has" used in the text are all open-ended, meaning they "include but are not limited to."
[0056] When terms such as "first" and "second" are used to describe elements, they are only used to distinguish these elements from each other and do not limit the order or importance of these elements. Therefore, in some cases, a first element may also be called a second element, and a second element may also be called a first element, without departing from the scope of the present invention.
[0057] Furthermore, directional terms used in this document, such as "upper" and "lower," are merely for reference to the directions in the accompanying drawings and are not intended to limit the invention. Therefore, it should be understood that "upper" and "lower" can be used interchangeably, and when a layer or film is placed "on" another element, the element can be placed directly on the other element, or there may be an intermediate element. Conversely, when an element is said to be placed "directly" on another element, there is no intermediate element between them.
[0058] Figures 1A to 1E This is a cross-sectional schematic diagram of the manufacturing process of a transistor structure according to an embodiment of the present invention.
[0059] First, please refer to Figure 1A A substrate 100 is provided. In this embodiment, the substrate 100 is a silicon substrate, but the invention is not limited thereto. Next, an isolation structure 102 is formed in the substrate 100 to define an active area. The isolation structure 102 may be a shallow trench isolation (STI) structure, and its material may be silicon oxide. Furthermore, in some embodiments, after forming the isolation structure 102, an ion implantation process may be performed on the substrate 100 in the active area to form a well region in the substrate 100.
[0060] Then, an interface material layer 104, a gate dielectric material layer 106, a capping material layer 108, a first gate material layer 110, and a hard mask material layer 112 are formed on the substrate 100. The interface material layer 104 may be made of silicon oxide. The gate dielectric material layer 106 may be made of a high-k dielectric material. High-k dielectric materials generally refer to dielectric materials with a dielectric constant greater than 4 in this technical field. Examples of high-k dielectric materials include alumina (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), and lanthanum oxide (La2O3), but this invention is not limited to these. The capping material layer 108 may be made of titanium nitride. The first gate material layer 110 may be made of polysilicon. The hard mask layer 112 may be made of silicon nitride.
[0061] Next, please refer to Figure 1BA patterning process is performed on the interface material layer 104, the gate dielectric material layer 106, the cover material layer 108, the first gate material layer 110, and the hard mask material layer 112 to form an initial gate structure GS composed of an interface layer (IL) 104a, a gate dielectric layer 106a, a cover layer 108a, an initial gate 110a, and a hard mask layer 112a. In this embodiment, the interface layer 104a and the gate dielectric layer 106a constitute a gate dielectric structure located between the gate and the substrate 100, while the initial gate 110a is a polysilicon gate.
[0062] After forming the initial gate structure GS, spacers 114 are formed on the sidewalls of the initial gate structure GS. The material of the spacers 114 may be silicon nitride. The method for forming the spacers 114 may include the following steps: First, a spacer material layer is conformally formed on the substrate 100. Then, an anisotropic etching process is performed on the spacer material layer until the surface of the substrate 100 and the top surface of the hard mask layer 112a are exposed.
[0063] After the spacer wall 114 is formed, an ion implantation process is performed using the spacer wall 114 and the initial gate structure GS as a mask to form doped regions 116 in the substrate 100 on both sides of the initial gate structure GS. The doped regions 116 can serve as the source and drain of the transistor structure in this embodiment. Next, a metal silicide layer 118 can be formed on the surface of the doped regions 116. The metal silicide layer 118 can be formed, for example, by performing a self-aligned silicide (salicide) fabrication process. In this embodiment, since the hard mask layer 112a covers the initial gate 110a, the metal silicide layer 118 is not formed on the top surface of the initial gate 110a.
[0064] Then, please refer to Figure 1C The hard mask layer 112a and a portion of the spacer wall 114 are removed to expose the top surface of the initial gate 110a. The method for removing the hard mask layer 112a and a portion of the spacer wall 114 is, for example, an etching-back fabrication process. Then, a dielectric layer 120 is formed on the substrate 100. The dielectric layer 120 covers the initial gate 110a. The dielectric layer 120 serves as an inter-layer dielectric (ILD) layer. The material of the dielectric layer 120 can be silicon oxide. Furthermore, before forming the dielectric layer 120, a contact etch stop layer can be conformally formed on the substrate 100. 122. The material of the contact etching stop layer 122 may be silicon nitride.
[0065] Next, please refer to Figure 1D A portion of the dielectric layer 120 and a portion of the contact etch stop layer 122 are removed to expose the top surface of the initial gate 110a. The method for removing a portion of the dielectric layer 120 and a portion of the contact etch stop layer 122 is, for example, a chemical mechanical polishing process.
[0066] Then, a portion of the initial gate 110a is removed, such that the remaining initial gate 110a forms the first portion P1 of the gate of the transistor structure of this embodiment on the capping layer 108a, and forms a groove R. Specifically, in this embodiment, after removing a portion of the initial gate 110a, the initial gate 110a remaining on the capping layer 108a forms a plurality of patterned portions that are spaced apart from each other, and these patterned portions can serve as part of the gate (first portion P1) of the transistor structure of this embodiment.
[0067] Furthermore, in this embodiment, these patterned portions (first portion P1) are arranged in an array on the cover layer 108a, but the invention is not limited thereto. In other embodiments, these patterned portions can be arranged in any form on the cover layer 108a. Alternatively, in one embodiment, after removing a portion of the initial gate 110a, a patterned portion can be retained as the first portion P1 of the gate of the transistor structure of this embodiment. Additionally, in this embodiment, the first portion P1 may have the required number, outline, and size, depending on the actual situation, and the invention does not limit this.
[0068] Next, please refer to Figure 1E A second gate material layer 124 is formed in the groove R. The material of the second gate material layer 124 may be metal. The second gate material layer 124 fills the groove to surround the first portion P1. The second gate material layer 124 serves as the second portion P2 of the gate of the transistor structure of this embodiment. The method of forming the second gate material layer 124 may include the following steps. First, a gate material layer is formed on the substrate 100 to cover the dielectric layer 120 and the first portion P1, and to fill the groove R. Then, a chemical mechanical polishing process is performed to remove the gate material layer outside the groove R until the top surface of the first portion P1 is exposed. Therefore, in the groove R, the second portion P2 surrounds the first portion P1, the first portion P1 and the second portion P2 are in contact, and the top surface of the first portion P1 and the top surface of the second portion P2 are coplanar. In this way, the transistor structure 10 of this embodiment is formed, wherein the first portion P1 and the second portion P2 form the gate G of the transistor structure 10.
[0069] Figure 2 This is a top view of the gate G of a transistor structure. Figure 2 In this drawing, for clarity and ease of explanation, only the gate G, the substrate 100, and the isolation structure 102 are shown. Figure 2 As shown, in this embodiment, the gate G includes a plurality of first portions P1 and second portions P2 surrounding these first portions P1. Furthermore, viewed from above the substrate 100, these first portions P1 are arranged in a 5×3 array, but the invention is not limited thereto. In other embodiments, such as... Figure 3 As shown, these first portions P1 can be arranged in other types of arrays. Furthermore, viewed from above the base 100, the first portions P1 have a rectangular outline, but the invention is not limited thereto. In other embodiments, the first portions P1 may have other shapes, such as circular, elliptical, or square outlines.
[0070] In this embodiment, the gate G is composed of a first portion P1 made of polysilicon and a second portion P2 made of metal, thus the gate G is a hybrid gate. Furthermore, during the chemical mechanical polishing process for forming the second portion P2, since the first portion P1 has already been formed in the groove R, the formation of a depression on the top surface of the formed gate G can be effectively avoided.
[0071] Furthermore, in this embodiment, since the gate G, formed by the first portion P1 and the second portion P2 of different materials, fills the groove R, the threshold voltage (Vt) of the transistor structure 10 can be effectively prevented from dropping excessively. In this embodiment, viewed from above the substrate 100, the area of the first portion P1 can be between 10% and 50% of the area of the gate G located directly above the gate dielectric layer 106a. In this way, in addition to avoiding the formation of a depression on the surface of the gate G after the chemical mechanical polishing process, it is also possible to avoid the threshold voltage of the transistor structure 10 dropping excessively due to an excessively high proportion of the first portion P1.
[0072] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.
Claims
1. A transistor structure, comprising: A gate is disposed on a substrate and includes a first portion and a second portion, wherein the second portion surrounds the first portion and the material of the first portion is different from the material of the second portion; Doped regions are disposed in the substrate on both sides of the gate; as well as A gate dielectric structure is disposed between the gate and the substrate.
2. The transistor structure of claim 1, wherein the material of the first portion comprises polycrystalline silicon, and the material of the second portion comprises metal.
3. The transistor structure of claim 2, wherein the gate dielectric structure comprises a high dielectric constant layer.
4. The transistor structure of claim 3, wherein the gate dielectric structure further comprises an interface layer disposed between the high dielectric constant layer and the substrate.
5. The transistor structure of claim 1 further includes a cover layer disposed between the gate dielectric structure and the gate.
6. The transistor structure of claim 1, wherein the top surface of the first portion and the top surface of the second portion are coplanar.
7. The transistor structure of claim 1, wherein the first portion is in contact with the second portion.
8. The transistor structure of claim 1, wherein the first portion comprises a plurality of patterned portions.
9. The transistor structure of claim 8, wherein the plurality of patterned portions are arranged in an array on the substrate.
10. A method for manufacturing a transistor structure, comprising: A gate is formed on a substrate, wherein the gate includes a first portion and a second portion, the second portion surrounding the first portion, and the material of the first portion is different from the material of the second portion; A gate dielectric structure is formed between the gate and the substrate; as well as Doped regions are formed in the substrate on both sides of the gate.
11. The method of manufacturing a transistor structure as claimed in claim 10, wherein the material of the first portion comprises polycrystalline silicon, and the material of the second portion comprises metal.
12. The method of manufacturing a transistor structure as claimed in claim 10, wherein the gate dielectric structure comprises a high dielectric constant layer.
13. The method of manufacturing a transistor structure as claimed in claim 12, wherein the gate dielectric structure further comprises an interface layer formed between the high dielectric constant layer and the substrate.
14. The method for manufacturing a transistor structure as claimed in claim 10, wherein the method for forming the gate and the gate dielectric structure comprises: A gate dielectric material layer is formed on the substrate; A first gate material layer is formed on the gate dielectric material layer; The gate dielectric material layer and the first gate material layer are patterned to form the gate dielectric structure and the initial gate; A portion of the initial gate is removed to form the first portion on the gate dielectric structure; as well as The second portion is formed on the gate dielectric structure to form the gate.
15. The method of manufacturing a transistor structure as claimed in claim 14, wherein the method of forming the second portion comprises: A second gate material layer is formed on the gate dielectric structure to cover the first portion; as well as Remove a portion of the second gate material layer until the top surface of the first portion is exposed.
16. The method of manufacturing a transistor structure as claimed in claim 14, wherein the doped region is formed after patterning the gate dielectric material layer and the gate material layer.
17. The method of manufacturing a transistor structure as claimed in claim 10, wherein the top surface of the first portion and the top surface of the second portion are coplanar.
18. The method of manufacturing a transistor structure as claimed in claim 10, wherein the first portion is in contact with the second portion.
19. The method of manufacturing a transistor structure as claimed in claim 10, wherein the first part comprises a plurality of patterned portions.
20. The method of manufacturing a transistor structure as claimed in claim 19, wherein the plurality of patterned portions are arranged in an array on the substrate.