Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the steps that a substrate is provided and comprises a gate region used for forming a gate structure, a first region located on one side of the gate region and a second region located on the other side of the gate region; an auxiliary layer covering the second region and a gate structure located on the side wall of the auxiliary layer and covering the gate region are formed on the substrate, and the first region is exposed out of the auxiliary layer and the gate structure; forming a first side wall on the side wall of the gate structure exposed out of the auxiliary layer; forming a first source-drain region in the first region exposed by the gate structure, the auxiliary layer and the first side wall; removing the auxiliary layer to expose the second region; forming a second side wall on the side wall of one side, adjacent to the second region, of the gate structure, wherein the thickness of the second side wall is different from that of the first side wall; and forming a second source-drain region in the second region exposed by the second side wall, wherein the doping type of the second source-drain region is different from that of the first source-drain region. The embodiment of the invention improves the performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] Traditional CMOS (Complementary Metal Oxide Semiconductor) devices are subject to Boltzmann limitation, resulting in a minimum subthreshold swing at room temperature. Therefore, as CMOS device sizes continue to shrink, static power consumption increases exponentially with decreasing operating voltage. Consequently, CMOS is generally used in high-performance computing, where dynamic power consumption is dominant.

[0003] Unlike conventional CMOS, TFET (Tunneling Field-effect Transistor) has different doping types in its source and drain regions. TFET replaces the source-channel-drain structure with a PIN structure and uses band-to-band tunneling as the conduction mechanism. This can overcome the subthreshold swing limitation and achieve extremely low static leakage current and lower operating voltage, thereby reducing static power consumption.

[0004] Therefore, TFET devices with excellent subthreshold characteristics can be hybridized with traditional CMOS devices to reduce the overall power consumption of the circuit. The high-frequency part of the circuit is completed by conventional CMOS devices, and the low-frequency part is completed by TFET devices. This hybrid integration method has wide applications in the Internet of Things.

[0005] However, the performance of TFET devices still needs to be improved. Summary of the Invention

[0006] The problem addressed by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the performance of TFET devices.

[0007] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a gate region for forming a gate structure, a first region located on one side of the gate region, and a second region located on the other side of the gate region; forming an auxiliary layer covering the second region and a gate structure located on the sidewall of the auxiliary layer and covering the gate region on the substrate, the auxiliary layer and the gate structure exposing the first region; forming a first sidewall on the sidewall of the gate structure exposed by the auxiliary layer; forming a first source / drain region in the first region exposed by the gate structure, the auxiliary layer, and the first sidewall; removing the auxiliary layer to expose the second region; forming a second sidewall on the sidewall of the gate structure adjacent to the second region, the thickness of the second sidewall being different from the thickness of the first sidewall; and forming a second source / drain region in the second region exposed by the second sidewall, the second source / drain region having a different doping type than the first source / drain region.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure formation method provided by the embodiments of the present invention, an auxiliary layer covering the second region and a gate structure located on the sidewall of the auxiliary layer and covering the gate region are formed on the substrate. A first sidewall is formed on the sidewall of the gate structure exposed by the auxiliary layer. After forming the first source / drain region, the auxiliary layer is removed to expose the second region. After removing the auxiliary layer, a second sidewall is formed on the sidewall of the gate structure adjacent to the second region. Thus, the embodiments of the present invention can, with the aid of the auxiliary layer, form first and second sidewalls of different thicknesses on the sidewalls of the gate structure at different steps, so as to achieve gate... Asymmetrical sidewall structures are formed on both sides of the gate structure. Compared with the approach of first forming a sidewall of uniform thickness on the sidewall of the gate structure and then removing a portion of the sidewall near the first region, the present invention omits the step of removing a portion of the sidewall near the first region. This not only improves the thickness uniformity of the first sidewall by omitting the removal process, but also avoids damage to the sidewall on the second region side caused by alignment misalignment during the removal process. Consequently, the structural integrity and thickness uniformity of the second sidewall are improved, thereby optimizing the performance of the semiconductor structure.

[0010] Furthermore, in this embodiment of the invention, after forming a first sidewall on the sidewall of the gate structure exposed by the auxiliary layer, and then forming a first source / drain region in the first region exposed by the gate structure, the auxiliary layer, and the first sidewall, compared to the scheme of forming the first source / drain region in the first region after removing a portion of the thickness of the sidewall near the first region, this embodiment of the invention eliminates the step of removing a portion of the thickness of the sidewall near the first region, improves the thickness uniformity of the first sidewall, and correspondingly also helps to improve the uniformity of the doping position and doping concentration of the first source / drain region, thereby optimizing the performance of the semiconductor structure. Attached Figure Description

[0011] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figures 7 to 33 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0013] Figures 34 to 35 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0014] As the background technology shows, the performance of TFET devices currently needs improvement. This paper analyzes the reasons why the performance of TFET devices needs further improvement, using a semiconductor structure formation method as an example.

[0015] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0016] refer to Figure 1 A substrate 10 is provided; a gate structure 20 is formed on the substrate 10, wherein the substrate 10 on one side of the gate structure 20 is used as a first region 10a and the substrate 10 on the other side is used as a second region 10b; a sidewall 25 is also formed on the sidewall of the gate structure 20, the sidewall 25 including a first sub-sidewall 21 located on the sidewall of the gate structure 20 and a second sub-sidewall 22 located on the sidewall of the first sub-sidewall 21.

[0017] refer to Figure 2 A leak region 11 is formed within the substrate 10 of the second region 10b.

[0018] refer to Figures 3 to 5The step of removing the second sub-sidewall 22 located on the sidewall adjacent to the first region 10a of the gate structure 20 includes: forming a mask layer 15 on the substrate 10 covering the drain region 11, the mask layer 15 exposing the first region 10a and the top of the sidewall 25 adjacent to the first region 10a; removing the second sub-sidewall 22 exposed by the mask layer 15; and removing the mask layer 15.

[0019] refer to Figure 6 After removing the second sub-sidewall 22 located on the sidewall adjacent to the first region 10a of the gate structure 20, a source region 12 is formed in the first region 10a. The ion doping type of the source region 12 is different from that of the drain region 11.

[0020] In the formation method, removing the second sub-sidewall 22 located on the sidewall adjacent to the first region 10a of the gate structure 20 includes the step of forming a mask layer 15 covering the drain region 12 on the substrate 10. The step of forming the mask layer 15 typically includes a photolithography process. During the photolithography process, there is a risk of alignment misalignment. When the alignment misalignment is large, the mask layer 15 may expose the sidewall 25 adjacent to the drain region 11. Consequently, in the subsequent step of removing the second sub-sidewall 22 exposed by the mask layer 15, the probability of damaging the sidewall 25 near the drain region 11 is increased, which may lead to poor performance of the formed semiconductor structure.

[0021] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure. The method involves forming an auxiliary layer covering a second region on a substrate, and a gate structure located on the sidewall of the auxiliary layer and covering the gate region. A first sidewall is formed on the sidewall of the gate structure exposed by the auxiliary layer. After forming a first source / drain region, the auxiliary layer is removed to expose the second region. After removing the auxiliary layer, a second sidewall is formed on the sidewall of the gate structure adjacent to the second region. Thus, embodiments of the present invention, with the aid of the auxiliary layer, can form first and second sidewalls of different thicknesses on the sidewalls of the gate structure at different steps. The present invention eliminates the step of removing the sidewall near the first region compared to the previous method of first forming a sidewall of uniform thickness on the sidewall of the gate structure and then removing a portion of the sidewall near the first region. This not only improves the thickness uniformity of the first sidewall by eliminating the removal process, but also avoids damage to the sidewall on the second region side caused by alignment misalignment during the removal process. Consequently, the structural integrity and thickness uniformity of the second sidewall are improved, thereby optimizing the performance of the semiconductor structure.

[0022] Furthermore, in this embodiment of the invention, after forming a first sidewall on the sidewall of the gate structure exposed by the auxiliary layer, and then forming a first source / drain region in the first region exposed by the gate structure, the auxiliary layer, and the first sidewall, compared to the scheme of forming the first source / drain region in the first region after removing a portion of the thickness of the sidewall near the first region, this embodiment of the invention eliminates the step of removing a portion of the thickness of the sidewall near the first region, improves the thickness uniformity of the first sidewall, and correspondingly also helps to improve the uniformity of the doping position and doping concentration of the first source / drain region, thereby optimizing the performance of the semiconductor structure.

[0023] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figures 7 to 33 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0024] refer to Figures 7 to 8 , Figure 7 This is a top view. Figure 8 for Figure 7 A cross-sectional view along the 1-1 direction shows a substrate 100, the substrate 100 including a gate region G for forming a gate structure, a first region A located on one side of the gate region G, and a second region B located on the other side of the gate region G.

[0025] The substrate 100 is used to provide a process platform for subsequent process manufacturing.

[0026] In this embodiment, taking the substrate 100 as an example for forming a planar field-effect transistor, the substrate 100 is a planar substrate. In other embodiments, depending on the type of transistor actually formed, the substrate may also be a three-dimensional substrate.

[0027] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0028] In this embodiment, the substrate 100 is used to form a tunneling field-effect transistor (TFET).

[0029] Specifically, in this embodiment, in the step of providing the substrate 100, the substrate 100 includes a plurality of device regions 100T and an isolation region 100I located between the device regions 100T; each device region 100T includes a gate region G, a first region A located on one side of the gate region G and a second region B located on the other side of the gate region G.

[0030] The device region 100T is used to form the tunneling field-effect transistor. Specifically, a plurality of device regions 100T are arranged along a first direction (e.g., Figure 7 (as shown in the X direction) and the second direction (as shown in the X direction) Figure 7 Arranged in the Y direction (as shown), with the first direction perpendicular to the second direction.

[0031] In other embodiments, the substrate can also be used to form a metal-oxide-semiconductor field-effect transistor (MOSFET). Accordingly, the substrate includes a first device region for forming a tunneling field-effect transistor and a second device region for forming a MOSFET, the first device region and the second device region being isolated from each other.

[0032] The isolation region 100I is used to achieve isolation between device regions 100T.

[0033] Therefore, in this embodiment, an isolation structure 110 is also formed within the substrate 100 of the isolation region 100I, and the isolation structure 110 is used to achieve isolation between 100T.

[0034] In this embodiment, the material of the isolation structure 110 is an insulating material. As an example, the isolation structure 110 is a shallow trench isolation structure (STI), and the material of the isolation structure 110 is silicon oxide. In other embodiments, the isolation structure may also be one or more of silicon nitride, silicon oxynitride, and silicon oxide.

[0035] Specifically, in this embodiment, a groove (not shown) is formed in the base 100 of the isolation zone 100I, and the isolation structure 110 is formed in the groove.

[0036] The gate region G is used to subsequently form a gate structure. The subsequently formed gate structure is a strip structure with an extending direction. Accordingly, in this embodiment, the gate region G also has an extending direction. In this embodiment, the gate region G extends along the second direction.

[0037] In this embodiment, in each device region 100T, the first region A and the second region B are respectively located on both sides of the gate region G. Specifically, in each device region 100T, the first region A and the second region B are distributed along a first direction on both sides of the gate region G.

[0038] Wherein, the first region A is used to form the first source-drain region, and the second region B is used to form the second source-drain region.

[0039] As an example, in each device region 100T, there are multiple first regions A, and the multiple first regions A are arranged sequentially at intervals along the second direction; in each device region 100T, there are multiple first regions A, and the multiple first regions A are arranged sequentially at intervals along the second direction.

[0040] Accordingly, in this embodiment, the isolation structure 110 is formed not only between adjacent device regions 100T, but also between adjacent first regions A and adjacent second regions B.

[0041] refer to Figures 9 to 14 An auxiliary layer 120 covering the second region B and a gate structure 115 located on the sidewall of the auxiliary layer 120 and covering the gate region G are formed on the substrate 100, wherein the auxiliary layer 120 and the gate structure 115 expose the first region A.

[0042] The auxiliary layer 120 is used to cover the second region B so that in the subsequent step of forming the first sidewall, the first sidewall can be formed on the sidewall of the gate structure 115 adjacent to the first region A; and after the first source-drain region is subsequently formed, the auxiliary layer 120 is removed to expose the sidewall of the gate structure 115 adjacent to the second region B, thereby enabling the formation of a first sidewall and a second sidewall of different thicknesses in different steps.

[0043] In this embodiment, in the step of forming the auxiliary layer 120, the auxiliary layer 120 is made of a material that has etching selectivity between the gate structure 115 and the substrate 100, thereby reducing the difficulty of subsequent removal of the auxiliary layer 120 and reducing the probability of accidental damage to the gate structure 115 and the substrate 100 in the subsequent removal of the auxiliary layer 120.

[0044] In this embodiment, the auxiliary layer 120 is made of one or more of germanium (Ge) and silicon germanide (SiGe). As an example, the auxiliary layer 120 is made of germanium. Germanium is a commonly used semiconductor material in semiconductor processes, which helps reduce process costs. Furthermore, germanium has high etching selectivity with the material of the substrate 100 in this embodiment, facilitating the subsequent removal of the auxiliary layer 120.

[0045] When the device is in operation, the gate structure 115 is used to control the opening and closing of the conductive channel.

[0046] In a specific embodiment, the gate structure 115 includes a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0047] The gate dielectric layer is used to isolate the gate layer from the conductive channel. In this embodiment, the gate dielectric layer includes a gate oxide layer, and the material of the gate oxide layer includes silicon oxide or nitrogen-doped silicon oxide. In other embodiments, the gate dielectric layer may also be a high-k dielectric material.

[0048] Specifically, during device operation, the gate layer is used to control the opening or closing of the conductive channel. In this embodiment, the material of the gate layer includes polycrystalline silicon or amorphous silicon.

[0049] In this embodiment, the steps of forming an auxiliary layer 120 covering the second region B on the substrate 100, and a gate structure 115 located on the sidewall of the auxiliary layer 120 and covering the gate region G, include:

[0050] like Figures 9 to 11 As shown, an auxiliary layer 120 covering the second region B is formed on the substrate 100, and the auxiliary layer 120 exposes the first region A and the gate region G.

[0051] In this embodiment, an auxiliary layer 120 is formed before the gate structure 115 is formed, so that the auxiliary layer 120 can provide support for the formation of the gate structure 115, and the gate structure 115 can be formed in a self-aligned manner, which is beneficial to simplifying the process.

[0052] In this embodiment, the auxiliary layer 120 is also located on a portion of the isolation region 100I.

[0053] Specifically, as an example, two adjacent device regions 100T along the first direction are designated as unit regions (not shown). In the unit region, the auxiliary layer 120 covers the second region between the gate regions 100G and the isolation structure 110, so that in the subsequent step of forming a gate structure on the sidewall of the auxiliary layer 120, the gate structure can be formed only on the gate region G within the device region 100T, thereby avoiding the formation of a gate structure on the isolation region between adjacent device regions 100T within the unit region.

[0054] As an example, in the step of forming the auxiliary layer 120, the auxiliary layer 120 further extends along the second direction to cover the isolation area 100I.

[0055] Specifically, in this embodiment, the step of forming the auxiliary layer 120 includes: as follows Figure 9 As shown, an auxiliary material layer 125 is formed covering the substrate 100; as Figures 10 to 11 As shown, Figure 10 This is a top view. Figure 11 for Figure 10 A cross-sectional view along the 1-1 direction is used to pattern the auxiliary material layer 125. The auxiliary material layer 125 located in the gate region G and the first region A is removed, and the remaining auxiliary material layer 125 located in the second region B is used as the auxiliary layer 120.

[0056] In this embodiment, a deposition process is used to form an auxiliary material layer 125 covering the substrate 100. Specifically, the deposition process can be a chemical vapor deposition process.

[0057] In this embodiment, an anisotropic dry etching process is used to pattern the auxiliary material layer 125, removing the auxiliary material layer 125 located in the gate region G and the first region A, which helps to improve the quality of pattern transfer.

[0058] like Figures 12 to 14 As shown, a gate structure 115 covering the gate region G is formed on the sidewall of the auxiliary layer 120, and the gate structure 115 exposes the first region A.

[0059] In this embodiment, the step of forming a gate structure 115 covering the gate region G on the sidewall of the auxiliary layer 120 includes: as follows Figure 12 As shown, a gate material layer 116 is formed on the top and sidewalls of the auxiliary layer 120, and on the exposed top surface of the substrate 100 of the auxiliary layer 120; as Figures 13 to 14 As shown, Figure 13 This is a top view. Figure 14 for Figure 13 A cross-sectional view along direction 1-1 shows that the gate material layer 116 located on the top of the auxiliary layer 120 and on the exposed top surface of the substrate 100 of the auxiliary layer 120 has been removed, and the remaining gate material layer 116 on the sidewall of the auxiliary layer 120 is used as the gate structure 115.

[0060] In this embodiment, a conformal deposition process is used to form the gate material layer 116, which helps to improve the thickness uniformity of the gate material layer 116. As an example, the conformal deposition process can be a chemical vapor deposition process.

[0061] In this embodiment, an anisotropic etching process is used to remove the gate material layer 116 located on the top of the auxiliary layer 120 and on the exposed top surface of the substrate 100. The anisotropic etching process has the characteristics of anisotropic etching; the etching rate along the direction perpendicular to the surface of the substrate 100 is much greater than the etching rate along the direction parallel to the surface of the substrate 100. This allows for the removal of the gate material layer 116 located on the top of the auxiliary layer 120 and on the exposed top surface of the substrate 100, while simultaneously ensuring that the remaining gate material layer 116 on the sidewalls of the auxiliary layer 120 is retained for use as the gate structure 115.

[0062] Specifically, the anisotropic etching process can be anisotropic dry etching process.

[0063] refer to Figures 15 to 17 A first sidewall 130 is formed on the sidewall of the gate structure 115 exposed in the auxiliary layer 120.

[0064] In this embodiment, with the help of the auxiliary layer 120, the first sidewall 130 can be formed only on the sidewall of the gate structure 115 adjacent to the first region A. This facilitates the formation of the first sidewall 130 and the second sidewall of different thicknesses in different steps, thereby eliminating the step of removing the part of the thickness sidewall near the first region A and improving the thickness consistency of the first sidewall 130.

[0065] The first sidewall 130 is used to cover the sidewall of the gate structure 115 adjacent to the first region A, thereby protecting the sidewall of the gate structure 115 adjacent to the first region A; the first sidewall 130 is also used to define the formation location of the first source and drain regions of the TFET device.

[0066] In this embodiment, the material of the first sidewall 130 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbonate, and silicon carbonitride. As an example, the material of the first sidewall 130 is silicon nitride.

[0067] In this embodiment, the step of forming the first sidewall 130 includes: as follows Figure 15 As shown, the first sidewall material layer 135 is located on top of the auxiliary layer 120 and the gate structure 115, on the sidewall of the gate structure 115 exposed by the auxiliary layer 120, and on the top surface of the substrate 100 exposed by the auxiliary layer 120 and the gate structure 115; as Figures 16 to 17 As shown, Figure 16 This is a top view. Figure 17 for Figure 16 A cross-sectional view along the 1-1 direction shows that the first sidewall material layer 135 located on the top of the auxiliary layer 120 and the gate structure 115, and on the top surface of the substrate 100 exposed by the auxiliary layer 120 and the gate structure 115, is removed. The remaining first sidewall material layer 135 on the sidewall of the gate structure 115 is used as the first sidewall 130.

[0068] In this embodiment, a conformal deposition process is used to form the first sidewall material layer 135. As an example, using atomic layer deposition to form the first sidewall material layer 135 is beneficial for improving the thickness uniformity of the first sidewall material layer 135.

[0069] In this embodiment, an anisotropic etching process is employed to remove the first sidewall material layer 135 located on top of the auxiliary layer 120 and the gate structure 115, and on the exposed top surface of the substrate 100 where the auxiliary layer 120 and the gate structure 115 are exposed. The anisotropic etching process has the characteristics of anisotropic etching; the etching rate along the direction perpendicular to the surface of the substrate 100 is much greater than the etching rate along the direction parallel to the surface of the substrate 100. This allows for the removal of the first sidewall material layer 135 located on top of the auxiliary layer 120 and the gate structure 115, and on the exposed top surface of the substrate 100 where the auxiliary layer 120 and the gate structure 115 are exposed, while simultaneously ensuring that the remaining first sidewall material layer 135 on the sidewall of the gate structure 115 is retained and used as the first sidewall 130.

[0070] Specifically, the anisotropic etching process can be anisotropic dry etching process.

[0071] refer to Figures 18 to 19 , Figure 18 This is a top view. Figure 19 for Figure 18 A cross-sectional view along the 1-1 direction shows that a first source / drain region 210 is formed in the first region A exposed by the gate structure 115, the auxiliary layer 120, and the first sidewall 130.

[0072] In this embodiment, the first sidewall 130 is used to define the formation location of the first source / drain region 210. This embodiment omits the step of removing a portion of the thickness of the sidewall near the first region A, thereby improving the thickness uniformity of the first sidewall 130 and correspondingly improving the uniformity of the doping location and doping concentration of the first source / drain region 210, thus optimizing the performance of the semiconductor structure.

[0073] The first source-drain region 210 is used as the source or drain region of a tunneling field-effect transistor. In this embodiment, the first source-drain region 210 is used as the source region of a tunneling field-effect transistor for illustration.

[0074] As an example, the TFET device is a P-type TFET device, and the dopant ions in the source region are N-type ions. In other embodiments, when forming an N-type TFET device, the dopant ions in the source region are P-type ions.

[0075] In this embodiment, the step of forming the first source / drain region 210 includes: performing ion doping treatment on the substrate exposed by the auxiliary layer 120, the gate structure 115, and the first sidewall 130 to form the first source / drain region 210 in the first region A. Specifically, the ion doping treatment process is an ion implantation process.

[0076] In other embodiments, the step of forming the first source / drain region 210 may further include: forming a first groove in the substrate exposed by the auxiliary layer 120, the gate structure 115, and the first sidewall 130; forming a first epitaxial layer in the first groove; and performing in-situ doping in the step of forming the first epitaxial layer to form a first epitaxial layer doped with ions, which serves as the first source / drain region 210.

[0077] refer to Figures 20 to 24 Remove the auxiliary layer 120 to expose the second region B.

[0078] The auxiliary layer 120 is removed to expose the second region B, which facilitates the subsequent formation of the second source / drain region within the second region B. It also exposes the sidewall of the gate structure 115 adjacent to the second region B, so that a second sidewall can be formed on the sidewall of the gate structure 115 adjacent to the second region B.

[0079] In this embodiment, during the step of removing the auxiliary layer 120, the sidewall of the gate structure 115 and the substrate 100 of the second region B form an opening 200, and the sidewall of the opening 200 provides support for the subsequent formation of the second sidewall. Specifically, in this embodiment, the sidewall of the gate structure 115 adjacent to the second region B and the substrate of the second region B form the opening 200.

[0080] Specifically, in this embodiment, the step of removing the auxiliary layer 120 includes: as follows Figures 20 to 22 As shown, a capping layer 230 is formed on the substrate 100 on the side of the auxiliary layer 120, the gate structure 115, and the first sidewall 130, and the capping layer 230 covers the first source / drain region 210; as Figures 23 to 24 As shown, the auxiliary layer 120 is removed.

[0081] The cover layer 230 is used to cover the first source / drain region 210, thereby reducing the process impact on the first source / drain region 210 during the step of removing the auxiliary layer 120.

[0082] As an example, the material of the capping layer 230 is an insulating dielectric material, so that the capping layer 230 can be retained in the semiconductor structure, thereby eliminating the step of removing the capping layer 230 and simplifying the process flow; in addition, the capping layer 230 can also be used as part of the interlayer dielectric layer, which is conducive to integrating the capping layer 230 with the process of forming the interlayer dielectric layer.

[0083] Furthermore, the cover layer 230 is located on the substrate 100 on the side of the auxiliary layer 120, the gate structure 115, and the first sidewall 130. After the auxiliary layer 120 is removed, the cover layer 230 covers the sidewall of the first sidewall 130, preventing the sidewall of the first sidewall 130 from being exposed. Thus, in the subsequent step of forming the second sidewall, the second sidewall can be formed only on the sidewall of the gate structure 115 adjacent to the second region B, so as to prevent the step of forming the second sidewall from affecting the thickness of the first sidewall 130. Accordingly, it is convenient to form the first sidewall 130 and the second sidewall with different thicknesses in different steps.

[0084] As an example, the material of the capping layer 230 is silicon oxide. In other embodiments, the material of the capping layer 230 may also be other types of insulating dielectric materials, such as one or more of silicon nitride, silicon oxynitride, and silicon oxide.

[0085] In this embodiment, the step of forming the cover layer 230 includes: as follows Figure 20As shown, an initial cover layer 235 is applied to the substrate, covering the auxiliary layer 120, the gate structure 115, the first sidewall 130, and the top surface of the substrate; as Figures 21 to 22 As shown, Figure 21 This is a top view. Figure 22 for Figure 21 A cross-sectional view along the 1-1 direction shows that the initial cover layer 235 above the top surface of the auxiliary layer 120 is removed, and the remaining initial cover layer 235 is used as the cover layer 230.

[0086] As an example, the initial capping layer 235 is formed using a chemical vapor deposition (CVD) process. CVD offers good coverage, strong gap-filling capability, low cost, and high process maturity.

[0087] As an example, a planarization process is employed to remove the initial cover layer 235 that extends above the top surface of the auxiliary layer 120. The planarization process can stop at the top surface of the auxiliary layer 120, thereby reducing the difficulty of removing the initial cover layer 235 that extends above the top surface of the auxiliary layer 120, and the planarization process helps improve the flatness and height consistency of the top surface of the cover layer 230. Specifically, the planarization process can be a chemical mechanical planarization process.

[0088] In this embodiment, during the step of removing the auxiliary layer 120, the auxiliary layer 120, the gate structure 115, the capping layer 230, the first sidewall 130, and the substrate have a high etching selectivity, thereby reducing the process difficulty of removing the auxiliary layer 120 and reducing the probability of damage to the gate structure 115, the capping layer 230, the first sidewall 130, and the substrate caused by the process of removing the auxiliary layer 120.

[0089] As an example, the process for removing the auxiliary layer 120 includes an isotropic etching process. The isotropic etching process has the characteristics of isotropic etching, which helps to completely remove the auxiliary layer 120 and reduce the residue of the auxiliary layer 120.

[0090] More specifically, in this embodiment, isotropic and anisotropic dry etching processes are used to remove the auxiliary layer 120. This not only helps reduce the residue of the auxiliary layer 120, but the anisotropic dry etching process also helps improve the removal efficiency of the auxiliary layer 120. In this embodiment, the etching gas in the dry etching process includes HCl, HBr, and F2.

[0091] In other embodiments, the isotropic etching process can also be a wet etching process. Wet etching processes can easily achieve a high etching selectivity, thereby reducing the chance of damage to other film structures.

[0092] refer to Figure 25 and Figure 26 , Figure 25 This is a top view. Figure 26 for Figure 25 In a cross-sectional view along the 1-1 direction, a second sidewall 140 is formed on the sidewall of the gate structure 115 adjacent to the second region B, and the thickness of the second sidewall 140 is different from the thickness of the first sidewall 130.

[0093] In this embodiment, the thickness of the second sidewall 140 is different from the thickness of the first sidewall 130, thereby enabling the formation of asymmetrical sidewall structures on both sides of the gate structure 115, which improves process flexibility.

[0094] In this embodiment, an auxiliary layer 120 covering the second region B and a gate structure 115 located on the sidewall of the auxiliary layer 120 and covering the gate region G are formed on the substrate 100. A first sidewall 130 is formed on the sidewall of the gate structure 115 exposed by the auxiliary layer 120. After forming the first source / drain region 210, the auxiliary layer 120 is removed to expose the second region B. After removing the auxiliary layer 120, a second sidewall 140 is formed on the sidewall of the gate structure 115 adjacent to the second region B. Thus, this embodiment of the invention can, with the aid of the auxiliary layer 120, form first sidewalls 130 and 140 of different thicknesses on the sidewalls of the gate structure 115 in different steps. The second sidewall 140 is configured to form an asymmetrical sidewall structure on both sides of the gate structure 115. Compared to the approach of first forming a sidewall of uniform thickness on the sidewall of the gate structure 115 and then removing a portion of the sidewall near the first region A, this embodiment eliminates the step of removing a portion of the sidewall near the first region A. This not only improves the thickness uniformity of the first sidewall 130 by eliminating the removal process, but also avoids damage to the sidewall on the second region B side caused by alignment misalignment during the removal process. Consequently, the structural integrity and thickness uniformity of the second sidewall 140 are improved, thereby optimizing the performance of the semiconductor structure.

[0095] In this embodiment, the second sidewall 140 is used to protect the sidewall of the gate structure 115, and the second sidewall 140 is also used to define the formation location of the subsequent second source / drain region.

[0096] In this embodiment, the substrate 100 is used to form a tunneling field-effect transistor; after the second sidewall 140 is formed, the thickness of the second sidewall 140 is greater than the thickness of the first sidewall 130 along the direction perpendicular to the sidewall of the gate structure 115; the subsequent steps also include: forming a second source / drain region in the second region B exposed by the second sidewall 140, wherein the doping type of the second source / drain region is different from that of the first source / drain region 210.

[0097] In this embodiment, the first source-drain region 210 is used as the source region, and the second source-drain region subsequently formed in the second region B is used as the drain region. That is, the sidewall thickness of the gate structure 115 near the drain region is greater than the sidewall thickness of the gate structure 115 near the source region. This makes it easier to make the boundary of the source region closer to the channel below the gate structure 115, while the drain region is relatively farther away from the channel. This helps to improve the bipolar effect of the TFET device, improve the switching capability of the TFET device, and reduce the leakage current when the device is turned off.

[0098] The bipolar effect refers to the phenomenon where tunneling occurs at the drain junction of a TFET device due to the opposite doping types of the source and drain, thereby increasing the subthreshold leakage current and degrading the transistor's performance.

[0099] In this embodiment, the material of the second sidewall 140 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbonate, and silicon carbonitride. The structure of the second sidewall 140 can be a single-layer structure or a multilayer structure.

[0100] As an example, the second sidewall 140 is a stacked structure, and the second sidewall 140 includes a first sub-sidewall 41 located on the sidewall adjacent to the gate structure 115 and the second region B, and a second sub-sidewall 42 located on the sidewall of the first sub-sidewall 41.

[0101] As an example, the material of the first sub-sidewall 41 is silicon oxide. In other embodiments, the material of the first sidewall 130 may also be an insulating dielectric material such as silicon nitride or a low-k dielectric material.

[0102] As an example, the material of the second sub-sidewall 42 is silicon oxide. In other embodiments, the material of the second sidewall 140 may also be an insulating dielectric material such as silicon nitride or a low-k dielectric material.

[0103] In this embodiment, during the step of removing the auxiliary layer 120, the sidewall of the gate structure 115 and the substrate 100 of the second region B form an opening 200; the step of forming the second sidewall 140 includes: forming the second sidewall 140 on the sidewall of the opening 200, so that the second sidewall 140 is formed only on the sidewall adjacent to the gate structure 115 and the second region B, which facilitates the formation of a second sidewall 140 with a different thickness than the first sidewall 130; moreover, the second sidewall 140 can be formed by maskless etching, that is, the second sidewall 140 can be self-aligned and formed on the sidewall adjacent to the gate structure 115 and the second region B, which also helps to improve the thickness uniformity of the second sidewall 140.

[0104] As an example, the step of forming the second sidewall 140 on the sidewall of the opening 200 includes: forming a first sub-sidewall 41 on the sidewall of the opening 200; forming a second sub-sidewall 42 located on the sidewall of the first sub-sidewall 41, wherein the second sub-sidewall 42 and the first sub-sidewall 42 are used to constitute the second sidewall 140.

[0105] As an example, the step of forming a first sub-sidewall 41 on the sidewall of the opening 200 includes: forming a first sub-sidewall material layer (not shown) on the top of the gate structure 115, the first sidewall 130, and the cover layer 230, and on the bottom and sidewall of the opening 200; removing the first sub-sidewall material layer located on the top of the gate structure 115, the first sidewall 130, and the cover layer 230, and on the bottom of the opening 200, and the remaining first sub-sidewall material layer on the sidewall of the opening 200 is used as the first sub-sidewall 41.

[0106] In this embodiment, a conformal deposition process is used to form the first sub-sidewall material layer. As an example, using atomic layer deposition to form the first sub-sidewall material layer is beneficial for improving the thickness uniformity of the first sub-sidewall material layer.

[0107] In this embodiment, an anisotropic etching process is used to remove the first sub-sidewall material layer located on the top of the gate structure 115, the first sidewall 130, and the capping layer 230, and at the bottom of the opening 200. The anisotropic etching process has the characteristics of anisotropic etching, with an etching rate much greater along the direction perpendicular to the surface of the substrate 100 than the etching rate along the direction parallel to the surface of the substrate 100. This allows for the removal of the first sub-sidewall material layer located on the top of the gate structure 115, the first sidewall 130, and the capping layer 230, and at the bottom of the opening 200, while simultaneously ensuring that the remaining first sub-sidewall material layer on the sidewall of the opening 200 is retained as the first sub-sidewall 41.

[0108] Specifically, the anisotropic etching process can be anisotropic dry etching process.

[0109] Similarly, the specific steps for forming the second sub-sidewall 42 can be found in the detailed description of the steps for forming the first sub-sidewall 41 described above, and will not be repeated here in this embodiment.

[0110] refer to Figures 27 to 28 In this embodiment, the method for forming the semiconductor structure further includes: after forming the second sidewall 140, removing the gate structure 115, the first sidewall 130 and the second sidewall 140 located in the isolation region 100i.

[0111] The gate structure 115, the first sidewall 130, and the second sidewall 140 located in the isolation region 100i are removed to define the pattern of the device region in order to achieve isolation between adjacent device regions.

[0112] Specifically, after the second sidewall 140 is formed and before the second source / drain region 220 is formed, the gate structure 115, the first sidewall 130, and the second sidewall 140 located in the isolation region 100i are removed.

[0113] As an example, the step of removing the gate structure 115, the first sidewall 130, and the second sidewall 140 located in the isolation region 100I includes: as follows Figure 27 As shown, a shielding layer 2402 is formed covering the device region 100T, and the shielding layer 240 exposes the isolation region 100I; as Figure 28 The shielding layer 240 is used as a mask to remove the gate structure 115, the first sidewall 130 and the second sidewall 140 located in the isolation region 100I; the shielding layer 240 is removed.

[0114] refer to Figure 29 and Figure 30 , Figure 29 This is a top view. Figure 30 for Figure 29 A cross-sectional view along the 1-1 direction shows that a second source / drain region 220 is formed in the second region B exposed by the second sidewall 140. The doping type of the second source / drain region 220 is different from that of the first source / drain region 210.

[0115] In this embodiment, after forming a first sidewall 130 on the sidewall of the gate structure 115 exposed by the auxiliary layer 120, and then forming a first source / drain region 210 in the first region A exposed by the gate structure 115, the auxiliary layer 120, and the first sidewall 130, compared with the scheme of forming the first source / drain region 210 in the first region A after removing a portion of the thickness of the sidewall near the first region A, this embodiment omits the step of removing a portion of the thickness of the sidewall near the first region A, improves the thickness uniformity of the first sidewall 130, and correspondingly also helps to improve the uniformity of the doping position and doping concentration of the first source / drain region 210, thereby optimizing the performance of the semiconductor structure.

[0116] In this embodiment, one of the first source / drain region 210 and the second source / drain region 220 is used as the source region and the other is used as the drain region, and the doping types of the drain region and the source region are different.

[0117] In this embodiment, the drain region and the source region are used as the drain and source of the TFET device, respectively, and the doping types of the drain region and the source region are different, thereby forming a PIN (P-Intrinsic-N) structure, and then using band tunneling as the conduction mechanism.

[0118] In this embodiment, the first source / drain region 210 is used as the source region; the second source / drain region 220 is used as the drain region. As an example, the TFET device is a P-type TFET device, and the dopant ions in the second source / drain region 220 are P-type ions. In other embodiments, when forming an N-type TFET device, the dopant ions in the second source / drain region 220 are N-type ions.

[0119] In this embodiment, the first source-drain region 210 is used as the source region, and the second source-drain region 220 is used as the drain region. That is, the sidewall thickness of the gate structure 115 near the drain region is greater than the sidewall thickness of the gate structure 115 near the source region. This makes it easier to make the boundary of the source region closer to the channel below the gate structure 115, while the drain region is relatively farther away from the channel. This helps to improve the bipolar effect of the TFET device, improve the switching capability of the TFET device, and reduce the leakage current when the device is turned off.

[0120] In this embodiment, the step of forming the second source / drain region 220 includes: performing ion doping treatment on the substrate exposed by the second sidewall 140 to form the second source / drain region 220 within the second region B. Specifically, the ion doping treatment process is an ion implantation process.

[0121] In other embodiments, the step of forming the second source / drain region 220 may further include: forming a second groove in the substrate exposed by the second sidewall 140; forming a second epitaxial layer in the second groove; and performing in-situ doping in the step of forming the second epitaxial layer to form a second epitaxial layer doped with ions, which serves as the second source / drain region 220.

[0122] refer to Figures 31 to 33 In this embodiment, the material of the cover layer 230 is an insulating dielectric material; the method for forming the semiconductor structure further includes: after forming the second source / drain region 220, forming a dielectric layer 250 covering the second source / drain region 220, the dielectric layer 250 also covering the cover layer 230, the gate structure 115, the first sidewall 130, and the second sidewall 140. The dielectric layer 250 also covers the isolation structure 110.

[0123] The dielectric layer 250, together with the capping layer 230, forms an interlayer dielectric (ILD) to achieve isolation between devices and between gate structures 115.

[0124] In this embodiment, the material of the cover layer 230 is an insulating dielectric material, so that the cover layer 230 can be retained in the semiconductor structure, so that the cover layer 230 can also be used as part of the interlayer dielectric layer, which is beneficial to integrating the cover layer 230 with the process of forming the interlayer dielectric layer.

[0125] The dielectric layer 250 is made of an insulating dielectric material. As an example, the dielectric layer 250 is made of silicon oxide.

[0126] As an example, the steps for forming the dielectric layer 250 include: Figure 31 As shown, a dielectric material layer 240 is formed to fill the opening 200 and cover the gate structure 115, the first sidewall 130, the second sidewall 140, and the top of the cover layer 230; as Figure 32 and Figure 33 As shown, Figure 32 This is a top view. Figure 33 for Figure 32 In the cross-sectional view along the 1-1 direction, the top of the dielectric material layer 240 is planarized, and the remaining dielectric material layer 240 is used as the dielectric layer 250.

[0127] In this embodiment, a deposition process is used to form the dielectric material layer 240. As an example, the process for forming the dielectric material layer 240 includes chemical vapor deposition.

[0128] In this embodiment, planarizing the top of the dielectric material layer 240 is beneficial for improving the flatness and height consistency of the top surface of the dielectric layer 250. As an example, a chemical mechanical planarization process is used to planarize the top surface of the dielectric material layer 240.

[0129] Figures 34 to 35 This is a schematic diagram of the structure corresponding to each step in another embodiment of the semiconductor structure formation method of the present invention. The similarities between this embodiment and the foregoing embodiments will not be repeated here. The differences between this embodiment and the foregoing embodiments are as follows:

[0130] In this embodiment, the method for forming the semiconductor structure further includes: after forming the first sub-sidewall 31 and before forming the second sub-sidewall, forming a lightly doped region 300 in the second region B exposed by the first sub-sidewall 31.

[0131] Accordingly, in this embodiment, the first sub-sidewall 31 is also used to define the formation location of the lightly doped region 300.

[0132] The lightly doped region 300 has the same doping type as the second source / drain region, and the doping depth of the lightly doped region 300 is less than the doping depth of the second source / drain region.

[0133] In this embodiment, an ion implantation process is used to form a lightly doped region 300 within the second region B exposed by the first sub-sidewall 31. Specifically, the process for forming the lightly doped region 300 within the second region B exposed by the first sub-sidewall 31 is a lightly doped drain (LDD) implantation process.

[0134] Accordingly, refer to Figure 35 In this embodiment, after forming the second sub-sidewall 32 and the second source / drain region 320, the doping depth of the second source / drain region 320 is greater than the doping depth of the lightly doped region 300.

[0135] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a gate region for forming a gate structure, a first region located on one side of the gate region, and a second region located on the other side of the gate region; An auxiliary layer covering the second region and a gate structure located on the sidewall of the auxiliary layer and covering the gate region are formed on the substrate, wherein the auxiliary layer and the gate structure expose the first region; A first sidewall is formed on the sidewall of the gate structure exposed by the auxiliary layer; A first source / drain region is formed in the first region exposed by the gate structure, the auxiliary layer, and the first sidewall; Remove the auxiliary layer to expose the second region; A second sidewall is formed on the sidewall of the gate structure adjacent to the second region, and the thickness of the second sidewall is different from the thickness of the first sidewall. A second source / drain region is formed in the second region exposed by the second sidewall, and the doping type of the second source / drain region is different from that of the first source / drain region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming an auxiliary layer covering the second region on the substrate, and a gate structure located on the sidewall of the auxiliary layer and covering the gate region, includes: forming an auxiliary layer covering the second region on the substrate, the auxiliary layer exposing the first region and the gate region; A gate structure covering the gate region is formed on the sidewall of the auxiliary layer, and the gate structure exposes the first region.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The step of forming a gate structure covering the gate region on the sidewall of the auxiliary layer includes: forming a gate material layer on the top and sidewall of the auxiliary layer, and on the exposed top surface of the substrate of the auxiliary layer; Remove the gate material layer located on top of the auxiliary layer and on the exposed substrate top surface of the auxiliary layer, and the remaining gate material layer located on the sidewall of the auxiliary layer is used as the gate structure.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate is used to form a tunneling field-effect transistor; After the second sidewall is formed, the thickness of the second sidewall is greater than the thickness of the first sidewall in a direction perpendicular to the sidewall of the gate structure. The first source-drain region is used as a source region; the second source-drain region is used as a drain region.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of removing the auxiliary layer includes: forming a capping layer on the substrate of the auxiliary layer, the gate structure, and the first sidewall side, the capping layer covering the first source / drain region; and removing the auxiliary layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The material of the covering layer is an insulating dielectric material; The method for forming the semiconductor structure further includes: after forming the second source / drain region, forming a dielectric layer covering the second source / drain region, wherein the dielectric layer also covers the cover layer, the gate structure, the first sidewall, and the second sidewall.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the capping layer includes: covering the substrate with an initial capping layer, the initial capping layer covering the auxiliary layer, the gate structure, the first sidewall, and the top surface of the substrate; removing the portion of the initial capping layer above the top surface of the auxiliary layer, and using the remaining initial capping layer as the capping layer.

8. The method for forming a semiconductor structure as described in claim 1 or 5, characterized in that, In the step of removing the auxiliary layer, the sidewall of the gate structure and the substrate of the second region form an opening; The step of forming the second sidewall includes: forming the second sidewall on the sidewall of the opening.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of forming the second sidewall on the sidewall of the opening includes: forming a first sub-sidewall on the sidewall of the opening; forming a second sub-sidewall located on the sidewall of the first sub-sidewall, wherein the second sub-sidewall and the first sub-sidewall are used to constitute the second sidewall.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the semiconductor structure further includes: forming a lightly doped region in a second region exposed by the first sub-sidewall after forming the first sub-sidewall and before forming the second sub-sidewall.

11. The method for forming a semiconductor structure as described in claim 2, characterized in that, The step of forming the auxiliary layer includes: forming an auxiliary material layer covering the substrate; patterning the auxiliary material layer, removing the auxiliary material layer located in the gate region and the first region, and using the remaining auxiliary material layer located in the second region as the auxiliary layer.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the auxiliary layer, the material of the auxiliary layer includes one or more of germanium and silicon germanide.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the auxiliary layer includes an isotropic etching process.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing a substrate, the substrate includes a plurality of device regions and an isolation region located between the device regions; each device region includes a gate region, a first region located on one side of the gate region and a second region located on the other side of the gate region; The method for forming the semiconductor structure further includes: after forming the second sidewall and before forming the second source / drain region, removing the gate structure, the first sidewall, and the second sidewall located in the isolation region.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, After forming the second source / drain region, the gate structure, the first sidewall, and the second sidewall located in the isolation region are removed.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the first sidewall includes: a first sidewall material layer on top of the auxiliary layer and the gate structure, on the sidewall of the gate structure exposed by the auxiliary layer, and on the top surface of the substrate exposed by the auxiliary layer and the gate structure; The first sidewall material layer located on the top of the auxiliary layer and the gate structure, as well as on the exposed top surface of the substrate of the auxiliary layer and the gate structure, is removed, and the remaining first sidewall material layer on the sidewall of the gate structure is used as the first sidewall.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first sidewall includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbonate, and silicon carbonitride; The material of the second sidewall includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbonate, and silicon carbonitride.

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