Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate with a first conductive type; the epitaxial layer is positioned on the substrate and has a first conductive type; a first doped region extending from the top surface of the epitaxial layer into the epitaxial layer, the first doped region having a first conductivity type; the first element is located in the first doped region, and the substrate serves as a drain electrode of the first element; a second doped region extending from the top surface of the epitaxial layer into the epitaxial layer, the second doped region having a second conductivity type, the second doped region being located at one side of the first doped region, and a portion of the epitaxial layer extending between the first doped region and the second doped region to separate the first doped region from the second doped region; and a second element located in the second doped region.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods of forming them, and particularly to semiconductor structures and methods of forming them that integrate multiple different types of elements on the same substrate. Background Technology

[0002] The semiconductor industry continues to improve the integration density of various electronic components by continuously reducing the minimum component size, allowing more components to be integrated within a given area. It also explores integrating different types of components on the same substrate. However, as the requirements for the electrical performance of semiconductor devices continue to increase, the complexity of semiconductor device integration and its fabrication methods also increases.

[0003] Taking laterally diffused metal-oxide-semiconductor (LDMOS) devices as an example, they can meet the requirements of high output power and gate-source breakdown voltage greater than 60 volts, and are mainly used in high-end amplifiers and radio power amplifiers for wireless cellular networks. The drive current of LDMOS devices is planar. Vertical metal-oxide-semiconductor (VDMOS) devices, on the other hand, have high voltage resistance and are widely used in power switch devices. The drive current of VDMOS devices flows vertically. Currently, integrating LDMOS and VDMOS devices with different drive current directions on a substrate increases the complexity of the fabrication method, and the electrical performance of each device is easily affected by other different types of devices, making it unable to meet application requirements. Therefore, although existing semiconductor devices, individually, are usually appropriate and sufficient to meet their intended purpose, their integrated fabrication is not entirely satisfactory. Summary of the Invention

[0004] Some embodiments disclosed herein provide a semiconductor structure including a substrate having a first conductivity type; an epitaxial layer located on the substrate, and the epitaxial layer having the first conductivity type; a first doped region extending from the top surface of the epitaxial layer into the epitaxial layer, and the first doped region having the first conductivity type; a first element located in the first doped region, wherein the substrate serves as a drain of the first element; a second doped region extending from the top surface of the epitaxial layer into the epitaxial layer, and the second doped region having a second conductivity type, the second doped region being located on one side of the first doped region, wherein a portion of the epitaxial layer extends between the first doped region and the second doped region to separate the first doped region and the second doped region; and a second element formed in the second doped region.

[0005] Some embodiments disclosed herein also provide a method for forming a semiconductor structure, including providing a substrate having a first conductivity type; forming an epitaxial layer having the first conductivity type on the substrate; forming a first doped region in the epitaxial layer, wherein the first doped region extends from the top surface of the epitaxial layer toward the substrate, and the first doped region has the first conductivity type; forming a first element in the first doped region, wherein the substrate serves as a drain of the first element; forming a second doped region in the epitaxial layer, wherein the second doped region extends from the top surface of the epitaxial layer toward the substrate, and the second doped region has a second conductivity type, wherein the second doped region is located on one side of the first doped region, wherein a portion of the epitaxial layer extends between the first doped region and the second doped region to separate the first doped region and the second doped region; and forming a second element in the second doped region. Attached Figure Description

[0006] Figure 1 This is a simplified cross-sectional view of a semiconductor structure at an intermediate manufacturing stage, according to some embodiments of this disclosure.

[0007] Figure 2A , Figure 2B , Figure 2C , Figure 2D This is a schematic cross-sectional view of a semiconductor structure at multiple intermediate manufacturing stages, according to some embodiments of this disclosure.

[0008] Figure 3 This is a schematic cross-sectional view of a semiconductor structure at an intermediate manufacturing stage, according to some embodiments of this disclosure.

[0009] Figure 4 This is a schematic cross-sectional view of a semiconductor structure at an intermediate manufacturing stage, according to some embodiments of this disclosure.

[0010] Figure 5 This is a schematic cross-sectional view of a semiconductor structure at an intermediate manufacturing stage, according to some embodiments of this disclosure.

[0011] Symbol Explanation

[0012] 1, 2, 3, 4, 5: Semiconductor Structure

[0013] 100: Base

[0014] 102: Epitaxial layer

[0015] 1021: First extensional part

[0016] 1022: Second extensional part

[0017] 100a, 102a: Top surface

[0018] 11: First Component

[0019] 110: First doped region

[0020] 1101: First deep well section

[0021] 1102: Second deep well section

[0022] R D Drift Zone

[0023] 110b, 118b, 210b: Bottom surface

[0024] 118: Trench structure

[0025] 1181: Insulation layer

[0026] 1182: Conductive part

[0027] 119: End ring

[0028] 120, 320: matrix area

[0029] 122, 124, 212, 213, 214, 222, 223, 224, 312, 313, 314, 412, 413, 414: Heavily doped regions

[0030] 126, 216, 226, 316: Gate structures

[0031] 21: Second Component

[0032] 21N: NMOS device

[0033] 21P: PMOS device

[0034] 210: Second doped region

[0035] 210B, 310B, 410B: Buried layer

[0036] 210W, 301, 310W, 410W: Trap

[0037] 211, 311: Grooved isolation components

[0038] 211L: Lower part

[0039] 2111: Insulation layer

[0040] 2112: Conductive part

[0041] 31: Third Component

[0042] 310: Third doped region

[0043] 500: Insulation layer

[0044] 502, 503, 508, 512, 513, 514, 515, 518, 522, 523, 524, 525, 528, 532, 533, 534, 542, 543, 544: Contact elements

[0045] PW: P-type well

[0046] NW: N-type well

[0047] 41: Fourth Component

[0048] d1: First distance

[0049] d2: Second distance

[0050] d3: Third distance

[0051] D1: First Direction

[0052] D2: Second Direction

[0053] D3: Third direction Detailed Implementation

[0054] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided semiconductor device. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in different examples of embodiments of the invention. Such repetition is for brevity and clarity and is not intended to indicate a relationship between the different embodiments discussed.

[0055] Furthermore, spatially related terms such as "below," "under," "below," "above," "above," and other similar expressions may be used in the following description to simplify the statement of the relationship between an element or component and other elements or components as shown in the figure. These spatially related terms include not only the direction depicted in the figure but also the different orientations of the device during use or operation. The device may be positioned in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptions used herein may be interpreted accordingly.

[0056] The following describes some variations of the embodiments. In embodiments with different figures and descriptions, similar element symbols are used to identify similar elements. It is understood that additional steps may be provided before, during, or after the method, and some described steps may be replaced or omitted for other embodiments of the method.

[0057] This disclosure provides a semiconductor structure and its formation method, which includes various types of metal-oxide-semiconductor (MOS) devices. Furthermore, by appropriately configuring isolation regions and / or components according to the application requirements, each MOS device can exhibit good electrical performance. Moreover, the semiconductor device formation method proposed in the embodiments is simple in process and does not require expensive manufacturing costs, enabling the integration of different types of MOS devices on the same substrate (e.g., a wafer).

[0058] The embodiments described herein can be applied to integrating multiple MOS devices on a substrate, such as complementary metal-oxide-semiconductor (CMOS), lateral-diffused metal-oxide-semiconductor (LDMOS), double-diffused metal-oxide-semiconductor (DMOS), vertical-diffused metal-oxide-semiconductor (VDMOS), or other MOS devices. For example, bipolar transistors, CMOS, DMOS, and VDMOS transistors can be integrated on the same substrate. However, this disclosure is not limited thereto.

[0059] Figure 1 This is a simplified cross-sectional view of a semiconductor structure at an intermediate manufacturing stage, according to some embodiments of this disclosure. This example proposes integrating multiple elements on a substrate 100, such as fabricating a first element 11, a second element 21, and a third element 31, to form a semiconductor structure 1. The first element 11 is a vertical metal-oxide-semiconductor (MOS) element, such as a VDMOS element. The second element 21 and the third element 31 are non-vertical MOS elements, such as a CMOS element and an LDMOS element, respectively.

[0060] In this example, the substrate 100 is, for example, a silicon wafer doped with a first conductivity type. An epitaxial layer 102, suitable plurality of wells and heavily doped regions, a gate structure, an insulating layer, and contacts are formed on the substrate 100 to form the first element 11, the second element 21, and the third element 31. In applications where a vertical metal-oxide-semiconductor device is used as the first element 11, the substrate 100 having the first conductivity type can serve as the drain region of the first element 11. In one example, the first conductivity type is n-type, but this disclosure is not limited to this. In some other examples, the first conductivity type can also be p-type, the opposite conductivity type.

[0061] Furthermore, in some embodiments, the epitaxial layer 102 has the same conductivity type as the substrate 100. In one example, the epitaxial layer 102 has a first conductivity type, such as (but not limited to) n-type. Also, according to some embodiments of this disclosure, the doping concentration of the substrate 100 is greater than the doping concentration of the epitaxial layer 102.

[0062] In this example, the semiconductor structure 1 further includes a first doped region 110 extending from the top surface 102a of the epitaxial layer 102 into the epitaxial layer 102, and the first element 11 is located in the first doped region 110. The first doped region 110 has the same conductivity type as the substrate 100. In one example, the first doped region 110 has a first conductivity type, such as (but not limited to) n-type. Furthermore, according to some embodiments of this disclosure, the doping concentration of the first doped region 110 is greater than the doping concentration of the epitaxial layer 102.

[0063] Furthermore, in applications where non-vertical metal-oxide-semiconductor elements are used as the second element 21 and the third element 31, the second element 21 and the third element 31 are formed in regions with a different conductivity type than the substrate 100, in order to reduce the influence of the substrate 100 of the first conductivity type on the operation of the second element 21 and the third element 31.

[0064] In one embodiment, the substrate 100 and the epitaxial layer 102 have a first conductivity type, such as n-type; while the second element 21 and the third element 31 are formed in a second doped region 210 having a second conductivity type, such as a p-type region. The second doped region 210 extends from the top surface 102a of the epitaxial layer 102 toward the substrate 100. Furthermore, the second doped region 210 and the first doped region 110 are separated by a distance. For example... Figure 1As shown, a portion of the epitaxial layer 102 extends between the first doped region 110 and the second doped region 210, separating the first doped region 110 and the second doped region 210 to further reduce interference between operating the first element 11 and operating the second element 21 and / or the third element 31. In one embodiment, the substrate 100 and the epitaxial layer 102 are P-type, the first doped region 110 is P-type, and the second doped region 210 is N-type.

[0065] Furthermore, in some embodiments, the first doped region 110 may extend deeper into the epitaxial layer 102 and be closer to the substrate 100 than the second doped region 210. In the example where the first element 11 is a VDMOS element, the closer the first doped region 110 is to the substrate 100, which serves as the drain, the better the electrical performance of the VDMOS element.

[0066] Although, in some embodiments, such as Figure 1 As shown, a second element 21 and a third element 31 are formed in a corresponding second doped region 210, but this disclosure is not limited thereto. In some other embodiments, the second element 21 and the third element 31 may be formed in two different regions respectively; for example, the second element 21 is formed in the second doped region 210, and the third element 31 is formed in the third doped region (not shown in the second doped region 210). Figure 1 (as shown in the figure) a third element 31 is formed, wherein the second doped region 210 and the third doped region have a second conductivity type, such as p-type.

[0067] Refer to Figure 1 In some embodiments, one or more first elements 11 may be disposed in the first doped region 110. In an example where a VDMOS element is used as the first element 11, the first element 11 includes adjacent heavily doped portions 122 and 124, which serve as the source region and base region of the first element 11, respectively. The heavily doped portion 122 and the first doped region 110 have the same conductivity type, while the heavily doped portion 124 and the heavily doped portion 122 have different conductivity types. In one example, the heavily doped portion 122 and the first doped region 110 have a first conductivity type, such as (but not limited to) n-type; the heavily doped portion 124 has a second conductivity type, such as (but not limited to) p-type.

[0068] In some embodiments, the first element 11 includes a planar gate structure. For example... Figure 1 As shown, the first element 11 includes a gate structure 126 located on the epitaxial layer 102, and spanning the heavily doped portion 122 and a portion of the first doped region 110 (which is the drift region R of the first element 11). D Above the gate structure 126, for example, a gate dielectric layer (not shown) and a gate electrode located above the gate dielectric layer.

[0069] In some embodiments where the VDMOS element is the first element 11, the first element 11 further includes a trench structure 118. The trench structure 118 contains a conductive material and extends from the top surface 102a of the epitaxial layer 102 toward the substrate 100 in the first doped region 110.

[0070] In some embodiments where the CMOS element is the second element 21, the second element 21 includes an NMOS element 21N and a PMOS element 21P disposed adjacently. In one example, the NMOS element 21N is disposed in a P-type well (P well; PW) and includes heavily doped portions 212, 213, and 214, wherein the heavily doped portions 212 and 214 are disposed adjacently and are the source and base regions of the NMOS element 21N, respectively. The heavily doped portion 213 is the drain region of the NMOS element 21N. The heavily doped portions 212 and 213 have the same conductivity type, such as (but not limited to) n-type. The heavily doped portion 214 and the heavily doped portion 212 have different conductivity types, such as (but not limited to) p-type.

[0071] Furthermore, in some embodiments, the NMOS element 21N includes a planar gate structure, such as a gate structure 216 located on the epitaxial layer 102 and between the heavily doped portion 212 (source region) and the heavily doped portion 213 (drain region). The gate structure 216 includes, for example, a gate dielectric layer and a gate electrode located above the gate dielectric layer.

[0072] In one example, the PMOS element 21P is disposed in an N-type well (N-well; NW) and includes heavily doped regions 222, 223, and 224. Heavily doped regions 223 and 224 are disposed adjacently and serve as the source and base regions of the PMOS element 21P, respectively. Heavily doped region 222 is the drain region of the PMOS element 21P. Heavily doped regions 222 and 223 have the same conductivity type, such as (but not limited to) p-type. Heavily doped regions 224 and 222 have different conductivity types, with heavily doped region 224 being, for example, (but not limited to) n-type.

[0073] Furthermore, in some embodiments, the PMOS element 21P includes a planar gate structure, such as a gate structure 226 located on the epitaxial layer 102 and between the heavily doped region 222 (source region) and the heavily doped region 223 (drain region). The gate structure 226 includes, for example, a gate dielectric layer and a gate electrode located above the gate dielectric layer.

[0074] In some embodiments where the LDMOS element is the third element 31, the third element 31 also includes multiple heavily doped portions and a gate structure. Taking LDNMOS as an example, the third element 31 is disposed in an N-type well (NW) and includes heavily doped portions 312, 313, and 314, wherein the heavily doped portions 312 and 314 are disposed adjacently in a P-type well (PW) and serve as the source and base regions of the LDNMOS element, respectively. The heavily doped portion 313 is the drain region of the LDNMOS element. The heavily doped portions 312 and 313 have the same conductivity type, such as (but not limited to) n-type. The heavily doped portions 314 and 312 have different conductivity types, such as (but not limited to) p-type.

[0075] Furthermore, in some embodiments, the third element 31 (e.g., an LDNMOS element) also includes a planar gate structure, such as a gate structure 316 located on the epitaxial layer 102 and between the heavily doped portion 312 (source region) and the heavily doped portion 313 (drain region). The gate structure 316 includes, for example, a gate dielectric layer and a gate electrode located above the gate dielectric layer.

[0076] According to some embodiments disclosed herein, when the first element 11, the second element 21, and the third element 31 are integrated on the same substrate 100, similar components of each element can be fabricated in the same process to save fabrication time and cost. For example, heavily doped portions of each element having the same conductivity type can be fabricated in the same process. Heavily doped portions 122, 212, 213, 222, 223, 312, and 313 having the first conductivity type (n-type) described above can be fabricated in the same process. Heavily doped portions 124, 214, 224, and 314 having the second conductivity type (p-type) described above can be fabricated in the same process. The gate structures of each element (e.g., gate structures 126, 216, 226, and 316) can be fabricated in the same process.

[0077] Although Figure 1 The semiconductor structure shown is illustrated using the integration of CMOS, LDMOS, and VDMOS elements on substrate 100 as an example. However, in practical applications, the configurations of these MOS elements are not limited to this; rather, the configurations of the elements to be integrated are selected according to the application requirements. Furthermore, the following are illustrated with reference to the figures, demonstrating a method for integrating VDMOS and CMOS elements on a substrate according to some embodiments of this disclosure. Note that the details in the following related content are for illustrative purposes only and are not intended to limit this disclosure.

[0078] Figures 2A to 2D This is a schematic cross-sectional view of a semiconductor structure at multiple intermediate manufacturing stages, according to some embodiments of this disclosure. Figures 2A to 2D Zhongyu Figure 1 Identical or similar parts use the same or similar reference numbers.

[0079] Reference Figure 2A According to some embodiments, a substrate 100 having a first conductivity type is provided. In some embodiments, the substrate 100 may be a block-shaped semiconductor substrate, such as a semiconductor wafer. For example, the substrate 100 is a silicon wafer. In some embodiments, the substrate 100 may be made of silicon or other semiconductor materials, or the substrate 100 may contain other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the substrate 100 may include compound semiconductors, such as silicon carbide or gallium nitride. In some embodiments, the substrate 100 may include alloy semiconductors, such as silicon-germanium, silicon-germanium carbide, or other suitable substrates. In some embodiments, the substrate 100 may consist of a multilayer material, such as silicon / silicon-germanium or silicon / silicon carbide.

[0080] In this example, substrate 100 is, for example, a silicon wafer doped with a first conductivity type. Please refer to... Figure 1 and Figure 2A In an application where a vertical metal-oxide-semiconductor device (MOSS) element is used as the first element 11, a substrate 100 having a first conductivity type serves as the drain region of the first element 11. In this example, the first conductivity type is n-type. Furthermore, in this example, the substrate 100 extends in a first direction D1 (e.g., the X direction) and a second direction D2 (e.g., the Y direction), and has a thickness in a third direction D3 (e.g., the Z direction).

[0081] In some embodiments, an epitaxial growth process is performed to form an epitaxial layer 102 on a substrate 100. The epitaxial growth process is performed, for example, in a third direction D3 (e.g., the Z direction) to form the epitaxial layer 102. In some embodiments, the epitaxial layer 102 has the same conductivity type as the substrate 100. In one example, the epitaxial layer 102 has a first conductivity type, such as n-type. Furthermore, according to some embodiments disclosed herein, the doping concentration of the substrate 100 is greater than the doping concentration of the epitaxial layer 102. For example, the doping concentration of the substrate 100 is approximately 1E18 atoms / cm². 3 Up to approximately 1E21 atoms / cm 3 The doping concentration of epitaxial layer 102 is within the range of approximately 1E14 atoms / cm². 3 Up to approximately 1E16 atoms / cm 3 Between the ranges.

[0082] In some embodiments, the epitaxial layer 102 further includes a plurality of suitable doped regions, for example Figure 2AThe first doped region 110 and the second doped region 210 are shown. The first doped region 110 and the second doped region 210 are separated by a gap in the lateral direction (e.g., the first direction D1).

[0083] In one example, the first doped region 110 has a first conductivity type, such as (but not limited to) n-type, and the doping concentration of the first doped region 110 is greater than the doping concentration of the epitaxial layer 102. According to some embodiments of this disclosure, the first doped region 110 is a deep well, such as an n-type deep well (DNW), and extends from the top surface 102a of the epitaxial layer 102 toward the substrate 100. In some embodiments, the doping concentration of the first doped region 110 is approximately 1E16 atoms / cm². 3 Up to approximately 1E21 atoms / cm 3 Between the ranges. According to some embodiments, the surface of the first doped region 110 can serve as a channel region for the subsequently formed first element 11.

[0084] In this example, the second doped region 210 further includes a buried layer 210B and a well 210W above the buried layer 210B. Unlike the first conductivity type of the substrate 100, the buried layer 210B and the well 210W have a second conductivity type, such as (but not limited to) p-type. The well 210W extends from the top surface 102 of the epitaxial layer 102 to the buried layer 210B. A second element 21 is subsequently formed in the well 210W. That is, the second element 21 is further separated from the substrate 100 by the buried layer 210B below it. Furthermore, the buried layer 210B and the well 210W have different doping concentrations. In this example, the doping concentration of the well 210W is greater than the doping concentration of the buried layer 210B.

[0085] Furthermore, the epitaxial layer 102 can be formed through a multi-stage epitaxial growth method, so as to form a first doped region 110 and a second doped region 210 inside the epitaxial layer 102.

[0086] Reference Figure 2A In some embodiments, an epitaxial growth process may be performed on the top surface 100a of the substrate 100 to form a first epitaxial portion 1021 of the epitaxial layer 102. Subsequently, implantation is performed in the first epitaxial portion 1021 to form a first deep well portion 1101 and a buried layer 210B.

[0087] For example, in one embodiment, a patterned mask (not shown) corresponding to the ion implantation region of the first deep well portion 1101 may be provided above the first epitaxial portion 1021, and ions of a first conductivity type (e.g., n-type) may be implanted into the ion implantation region of the first deep well portion 1101 through this patterned mask to form the first deep well portion 1101. The formation of the first deep well portion 1101 at an appropriate depth in the epitaxial layer 102 can be controlled by adjusting the implantation energy or other suitable methods. In some embodiments, the first deep well portion 1101 has a uniform ion doping concentration. In some other embodiments, the first deep well portion 1101 has a gradually varying ion doping concentration.

[0088] For example, in one embodiment, a patterned mask (not shown) corresponding to the buried layer 210B may be provided above the first epitaxial portion 1021, and ions of a second conductivity type (e.g., p-type) (e.g., boron) may be implanted into the ion implantation region of the buried layer 210B through this patterned mask. Subsequently, a high-temperature process, such as a high-temperature furnace tube process, is performed to diffuse the implanted ions, thereby forming the buried layer 210B. The formation of the buried layer 210B at an appropriate depth in the epitaxial layer 102 can be controlled by adjusting the implantation energy or other suitable methods. In some embodiments, the buried layer 210B has a uniform ion doping concentration. In some other embodiments, the buried layer 210B has a gradually varying ion doping concentration.

[0089] Furthermore, in some embodiments, the doping concentration of the first deep well portion 1101 is approximately 1E18 atoms / cm². 3 Up to approximately 1E21 atoms / cm 3 The doping concentration of the buried layer 210B is within the range of approximately 1E15 atoms / cm². According to some embodiments, the doping concentration of the buried layer 210B is approximately 1E15 atoms / cm². 3 Up to approximately 1E18 atoms / cm 3 Between the ranges.

[0090] Then, refer to Figure 2A According to some embodiments, a second epitaxial portion 1022 is formed by continuing epitaxial growth in a third direction D3 (e.g., the Z direction) on the top surface of the first epitaxial portion 1021. The second epitaxial portion 1022 also has a first conductivity type, such as n-type. In this example, the first epitaxial portion 1021 and the second epitaxial portion 1022 together constitute an epitaxial layer 102.

[0091] In some embodiments, the epitaxial growth process described above can be performed using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable processes, or combinations thereof, including forming an epitaxial layer 102 by forming a first epitaxial portion 1021 and a second epitaxial portion 1022. In applications where a vertical metal-oxide-semiconductor device is subsequently formed as the first element 11, the second epitaxial portion 1022 can serve as a drift region of the first element 11.

[0092] The doping concentration of the second epitaxial portion 1022 may be less than or approximately equal to the doping concentration of the first epitaxial portion 1021. In some embodiments, the doping concentration of the first epitaxial portion 1021 is approximately 1E15 atoms / cm². 3 Up to approximately 1E16 atoms / cm 3 The doping concentration of the second epitaxial portion 1022 is within the range of approximately 1E14 atoms / cm². In some embodiments, the doping concentration of the second epitaxial portion 1022 is approximately 1E14 atoms / cm². 3 Up to approximately 1E16 atoms / cm 3 Between the ranges.

[0093] After forming the second epitaxial portion 1022, an ion implantation process is performed to form a second deep well portion 1102 and a well 210W within the second epitaxial portion 1022. The second deep well portion 1102 is located on and connected to the first deep well portion 1101. The second deep well portion 1102 has a first conductivity type, such as n-type. The well 210W is located on and connected to the buried layer 210B. The well 210W has a second conductivity type, such as p-type. The methods for forming the second deep well portion 1102 and the well 210W can be referred to the aforementioned descriptions of the first deep well portion 1101 and the buried layer 210B, and will not be repeated here.

[0094] like Figure 2AAs shown, the first deep well portion 1101 and the second deep well portion 1102 constitute a deep well to serve as the first doped region 110 of the subsequently formed first element 11. The well 210W and the buried layer 210B constitute the second doped region 210 of the subsequently formed first element 11. According to some embodiments, the horizontal position of the buried layer 210B corresponds to the area between the bottom surface 110b of the first doped region 110 and the well 210W.

[0095] The doping concentration of the second deep well portion 1102 may be greater than or approximately equal to the doping concentration of the first deep well portion 1101. In some embodiments, the doping concentration of the second deep well portion 1102 is approximately 1E15 atoms / cm². 3 Up to approximately 1E18 atoms / cm 3 Between the ranges.

[0096] According to some embodiments disclosed herein, the doping concentration of the epitaxial layer 102 is less than the doping concentration of the substrate 100. For example, in one example, the average doping concentration of the first epitaxial portion 1021 and the second epitaxial portion 1022 is less than the doping concentration of the substrate 100.

[0097] Furthermore, according to some embodiments disclosed herein, the doping concentration of the first doped region 110 is greater than the doping concentration of the epitaxial layer 102. For example, in one example, the average doping concentration of the first deep well portion 1101 and the second deep well portion 1102 is greater than the average doping concentration of the first epitaxial portion 1021 and the second epitaxial portion 1022. The high doping concentration of the first doped region 110 can reduce the on-resistance of the subsequently formed first element 11 (e.g., a VDMOS element), thereby improving the electrical performance of the formed first element 11.

[0098] Furthermore, according to some embodiments disclosed herein, the doping concentration of the well 210W of the second doped region 210 is greater than the doping concentration of the epitaxial layer 102 and less than the doping concentration of the substrate 100. According to some embodiments, the buried layer 210B of the second doped region 210 is less than the doping concentration of the epitaxial layer 102 and less than the doping concentration of the substrate 100.

[0099] Furthermore, according to some embodiments disclosed herein, the first doped region 110 is closer to the substrate 100 than the second doped region 210. For example... Figure 2A As shown, the bottom surface 110b of the first doped region 110 and the top surface 100a of the substrate 100 are separated by a first distance d1 along the third direction D3, and the bottom surface 210b of the second doped region 210 (i.e. the bottom surface of the buried layer 210B) and the top surface 100a of the substrate 100 are separated by a second distance d2 along the third direction D3, and the second distance d2 is greater than the first distance d1.

[0100] In some embodiments where a VDMOS device is used as the first element 11, the closer the bottom surface 110b of the first doped region 110 is to the substrate 100 with a dopant of a first conductivity type (e.g., n-type) serving as the drain, the better the electrical performance of the VDMOS device. Furthermore, in some embodiments where a CMOS or LDMOS device is used as the second / third element, in addition to achieving good electrical isolation between the device disposed therein and other elements through the second doped region 210, the farther the bottom surface 210b of the second doped region 210 is from the substrate 100, the less the influence of the substrate 100 with a first conductivity type (e.g., n-type) on the second / third element at the second doped region 210.

[0101] According to some embodiments disclosed herein, in applications where a VDMOS element is subsequently formed as the first element 11, a trench structure 118 may also be formed in the first doped region 110. The trench structure 118 extends from the top surface 102a of the epitaxial layer 102 toward the substrate 100 within the first doped region 110. The bottom of the trench structure 118 does not extend beyond the first doped region 110. That is, the sidewalls and bottom of each trench structure 118 are surrounded and covered by the first doped region 110.

[0102] In some examples where the bottom surface 110b of the first doped region 110 is close to the substrate 100, a vertical distance (e.g., a first distance d1) between the bottom surface 110b of the first doped region 110 and the top surface 100a of the substrate 100 may be smaller than a vertical distance (e.g., a third distance d3) between the bottom surface 118b of the trench structure 118 and the bottom surface 110b of the first doped region 110.

[0103] Furthermore, in some embodiments where the bottom surface 210b of the second doped region 210 is far from the substrate 100, the bottommost point of the trench structure 118 may be on approximately the same horizontal plane as the bottom surface 210b of the second doped region 210. Alternatively, in some embodiments, the trench structure 118 may extend downwards to a point where its bottommost point is below the bottom surface 210b of the second doped region 210. That is, the trench structure 118 is closer to the substrate 100 than the second doped region 210. The depth of the trench structure 118 can adjust the longitudinal current of the VDMOS.

[0104] According to some embodiments, each trench structure 118 includes an insulating layer 1181 and a conductive portion 1182, wherein the insulating layer 1181 covers the sidewalls and bottom of the conductive portion 1182. In some embodiments, viewed from above the substrate 100, a first doped region 110 and a second doped region 210 are spaced apart in a first direction D1 (e.g., the X direction), and trench structures 118 extend in the first doped region 110 along a second direction D2 (e.g., the Y direction), and these trench structures 118 are spaced apart from each other in the first direction D1 (e.g., the X direction). The second direction D2 is different from the first direction D1, for example, the second direction D2 is perpendicular to the first direction D1.

[0105] The interaction between the trench structure 118 and other subsequently formed components, as proposed in the embodiments, can improve the electrical performance of the formed first element. For example, if the conductive portion 1182 of the trench structure 118 is subsequently electrically connected to the gate, the on-resistance can be significantly reduced; or if the conductive portion 1182 of the trench structure 118 is subsequently electrically connected to the source, it can effectively reduce the on-resistance while also possessing good dynamic characteristics, such as shortening the switching time between on and off and significantly reducing switching energy loss. In one embodiment, the conductive portion 1182 in the trench structure 118 can be a field plate.

[0106] According to some embodiments of this disclosure, the location of the trench structure 118 can be defined by a suitable photolithography patterning process. In some examples, a mask (not shown) is formed over the epitaxial layer 102, and this mask has a plurality of openings to expose the top surface 102a of the first doped region 110. In some embodiments, this mask is a patterned photoresist formed of a photoresist material. In some other embodiments, the material of this mask may be a hard mask (HM) composed of an oxide layer and a nitride layer. In some examples where a patterned photoresist is used as the mask, the above-described photolithography patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or combinations of the foregoing processes, to form these openings.

[0107] Subsequently, portions of the first doped region 110 can be removed through openings in the mask, for example, by performing one or more etching processes to form grooves (not shown) in the first doped region 110. In some embodiments, the positions of these grooves correspond to... Figure 2AThe location of the trench structure 118 shown. The depth of these grooves in the first doped region 110 (e.g., along the third direction D3) is equal to the depth of the subsequently formed trench structure 118 in the first doped region 110 (e.g., along the third direction D3).

[0108] Furthermore, in some embodiments, the etching process described above includes a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the foregoing processes. Additionally, it is understood that the dimensions, shape, and position of the grooves and the trench structures 118 formed therein are for illustrative purposes only and are not intended to limit the embodiments of the present invention.

[0109] According to some embodiments, after the grooves are formed, the mask can be removed by an ashing process, a wet etching process (e.g., acid etching), or other acceptable processes. After mask removal, a cleaning process can be selectively performed to remove residues.

[0110] In some embodiments, after the trench is formed, an insulating material (not shown) can be conformally deposited on the top surface 102a of the epitaxial layer 102, and this insulating material is deposited on the sidewalls and bottom surface of the trench as a liner layer. The trench structure 118 proposed in the embodiments can be electrically coupled to the source or the gate, so the insulating material can be appropriately selected according to the coupling situation of the trench structure 118 in the actual application.

[0111] In some embodiments where the trench structure 118 is electrically coupled to the source, the insulating material may be silicon oxide, germanium oxide, other suitable semiconductor oxide materials, or combinations thereof. In some examples, an oxidation process can be used to isotropically form the insulating material on the sidewalls and bottom surfaces of the trench and on the top surface 102a of the epitaxial layer 102. In some embodiments, the oxidation process may be thermal oxidation, radical oxidation, or other suitable processes. In some embodiments, a thermal process may also be selectively applied to the insulating material to increase its density. In some embodiments, the aforementioned thermal process may be a rapid thermal annealing (RTA) process.

[0112] In some embodiments where the trench structure 118 is electrically coupled to the gate, i.e., the trench structure 118 serves as a trench gate structure, the insulating material can be silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, alumina-hafnium alloy, silicon-hafnium dioxide, silicon-oxygen-hafnium, tantalum-hafnium oxide, titanium-hafnium oxide, zirconium-hafnium oxide, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the insulating material can be formed on the sidewalls and bottom surfaces of the trench and on the top surface 102a of the epitaxial layer 102 by a deposition process, such as an isotropic deposition process, and can be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, other suitable deposition processes, or combinations thereof.

[0113] Subsequently, according to some embodiments, a conductive material (not shown) can be deposited on top of the insulating material using a deposition process, with the conductive material filling the space in the groove excluding the insulating material. A thermal process, such as an annealing process, can be selectively applied to the conductive material. In some embodiments, the conductive material can be a single-layer or multi-layer structure, formed of amorphous silicon, polycrystalline silicon, or a combination of the aforementioned materials. The deposition process can be physical vapor deposition (PVD), chemical vapor deposition (CVD), other suitable deposition processes, or a combination of the aforementioned processes. In some examples, the conductive material comprises polycrystalline silicon.

[0114] Next, excess insulating material and excess conductive material are removed, for example, portions of insulating material and conductive material extending beyond the top surface 102a of the epitaxial layer 102 are removed to form a layer as shown in the image. Figure 2A The groove structure 118 shown.

[0115] In some examples, the steps of removing portions of insulating material and conductive material described above may (but are not limited to) include: removing excess portions of conductive material and excess portions of insulating material located above the top surface 102a of the epitaxial layer 102 using a planarization process to expose the top surface 102a of the epitaxial layer 102. The planarization process described above is, for example, a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination of the foregoing processes.

[0116] After the above removal steps, the remaining portion of the insulating material becomes the insulating layer 1181, and the remaining portion of the conductive material becomes the conductive portion 1182. The conductive portion 1182 is separated from the material layer of the first doped region 110 by the insulating layer 1181. In some examples, after the planarization process, the conductive portion 1182 is located on the insulating layer 1181, and the top surface of the conductive portion 1182 and the top surface of the insulating layer 1181 are substantially coplanar with the top surface 102a of the epitaxial layer 102.

[0117] In some embodiments, the conductive portion 1182 may optionally include a dopant of a first conductivity type. In this example, the first conductivity type is n-type. In some embodiments, the dopant of the conductive portion 1182 may be phosphorus or other suitable dopant. According to some embodiments, if the trench structure 118 is subsequently electrically connected to a gate, the conductive portion 1182 of the trench structure 118, in addition to reducing on-resistance, may further enhance the effect of reducing the surface field (RESURF) by having a conductive portion 1182 of the first conductivity type.

[0118] Additionally, in some embodiments, one or more termination rings 119 may be formed in the first doped region 110. These termination rings 119 are located outside and surround the subsequently formed first element 11. During operation of the first element 11, the termination rings 119 can be used to adjust the electric field distribution at the edges. It is worth noting that, although in Figure 2A In the cross-sectional view, the end ring 119 and the groove structure 118 have similar elongated cross-sections, but if viewed from above the base 100 (not shown), the end ring 119 appears to be closedly surrounding the periphery of the subsequently formed first element 11.

[0119] Furthermore, according to some embodiments, a trench isolation 211 may be formed in the second doped region 210. The trench isolation 211 extends from the top surface of the second doped region 210 of the epitaxial layer 102 toward the substrate 100, for example, extending along a third direction D3. In some examples, the bottom of the trench isolation 211 does not extend beyond the bottom of the second doped region 210. Furthermore, the bottom of the trench isolation 211 in the second doped region 210 may be on approximately the same horizontal plane as the bottom of the trench structure 118 in the first doped region 110, or it may be on a different horizontal plane. This disclosure does not impose many limitations on this, and appropriate design and adjustment can be made according to the actual process.

[0120] According to some embodiments, although Figure 2AThe cross-sectional view shows two elongated trench separators 211 formed in the second doped region 210, but if viewed from above the substrate 100 (not shown), the trench separators 211 are, for example, enclosedly surrounding the periphery of the subsequently formed second element 21.

[0121] Furthermore, the trench spacer 211 can extend through the well 210W into the embedded layer 210B. According to some embodiments, a portion of the trench spacer 211 extends into the embedded layer 210B. Therefore, the lower portion 211L of the trench spacer 211 is located within the embedded layer 210B. In other words, the bottom surface of the trench spacer 211 is lower than the bottom surface of the well 210W, such as... Figure 2A As shown.

[0122] According to some embodiments, the trench isolation member 211 can form an isolation structure with the buried layer 210B, so that the second element 21 subsequently formed in the second doped region 210 can achieve good electrical isolation from the elements formed outside the second doped region 210 (e.g., the first element 11). In particular, in some examples where the first element 11 is a VDMOS element, the substrate 100, which serves as the drain of the first element 11, is connected to a drain operating voltage, which can easily cause electrical instability of other integrated elements on the substrate 100 (e.g., the second element 21 in the second doped region). Through the buried layer 210B, or the isolation structure formed by the buried layer 210B and the trench isolation member 211, the second element 21 in the second doped region 210 can achieve good electrical isolation from the first element 11 in the first doped region 110.

[0123] Furthermore, in some embodiments, the isolation effect between the buried layer 210B and the epitaxial layer 102 (e.g., the first epitaxial portion 1021) can be improved by adjusting the doping concentration of the second conductivity type dopant in the buried layer 210B. In some examples, the buried layer 210B and the substrate 100 have opposite conductivity types, and the doping concentration of the second conductivity type dopant in the buried layer 210B is less than the doping concentration of the second conductivity type dopant in the well 210W and less than the doping concentration of the first conductivity type dopant in the substrate 100.

[0124] In some embodiments, the trench isolation member 211 includes an insulating layer 2111 and a conductive portion 2112, wherein the insulating layer 2111 covers the sidewalls and bottom of the conductive portion 2112. In some embodiments, the insulating layer 2111 includes silicon oxide, germanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, alumina-hafnium alloy, silicon dioxide hafnium, silicon oxynitride hafnium, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, other suitable materials, or combinations thereof. In some embodiments, the conductive portion 2112 includes amorphous silicon, polycrystalline silicon, other suitable materials, or combinations thereof. In some examples, the conductive portion 2112 includes polycrystalline silicon.

[0125] Furthermore, the formation of the grooved isolation element 211 can be made by referring to the manufacturing method of the grooved structure 118 described above or other suitable methods, and will not be repeated here.

[0126] According to some embodiments, the trench structure 118 in the first doped region 110 and the trench separator 211 in the second doped region 210 may have similar configurations and can be fabricated in the same process to simplify the process and reduce manufacturing costs. For example, the insulating layer 1181 of the trench structure 118 and the insulating layer 2111 of the trench separator 211 contain the same material and are fabricated in the same process; the conductive portion 1182 of the trench structure 118 and the conductive portion 2112 of the trench separator 211 contain the same material and are fabricated in the same process. In some examples, these trench structures 118 and trench separators 211 may have substantially the same profile, such as the same width and depth.

[0127] After forming the trench structure 118 (or the trench structure 118 and the trench separator 211), refer to Figure 2B Wells required for subsequent device fabrication are formed in the first doped region 110 and the second doped region 210. According to some embodiments, a first element 11, such as a VDMOS element, is formed in the first doped region 110; and a second element 21, such as a CMOS element, is formed in the second doped region 210.

[0128] like Figure 2B As shown, in some embodiments where a VDMOS device is used as the first element 11, a body region 120 is formed in the first doped region 110. The body region 120 has a different conductivity type than the first doped region 110, for example, a second conductivity type. In this example, the body region 120 is, for example, p-type, and may also be called a p-body region. Furthermore, in some embodiments, one side of the formed body region 120 is in contact with the trench structure 118, while the other side and bottom of the body region 120 are covered by the doped portion of the first doped region 110. According to some embodiments, the body region 120 can serve as the channel region of the VDMOS device.

[0129] In subsequent processes, a source region (e.g., heavily doped portion 122) and a base region (e.g., heavily doped portion 124) of the first element 11 can be formed in the substrate region 120. In some embodiments, the doping concentration of the substrate region 120 is less than the doping concentration of the source and base regions. In some embodiments, the doping concentration of the substrate region 120 is, for example (but not limited to), about 1E16 atoms / cm². 3 Up to approximately 1E18 atoms / cm 3 Between the ranges.

[0130] According to some embodiments, doping can be performed on the top surface 102a of the epitaxial layer 102 using deposition, photolithography, etching, and implantation processes to form a doped region 110. Figure 2B The substrate region 120 is shown. Therefore, the substrate region 120 is doped downwards from the top surface 102a of the doped epitaxial layer 102 in the first doped region 110 to a specific depth.

[0131] In one example, an oxide hard mask material layer (not shown) may be deposited over the doped epitaxial layer 102 of the first doped region 110. Then, a patterned photoresist corresponding to the location of the substrate region 120 is formed on this oxide hard mask material layer. The oxide hard mask material layer is etched according to this patterned photoresist to form an oxide hard mask. The patterned photoresist is then removed, and the first doped region 110 is doped according to the formed oxide hard mask to form the substrate region 120 in the first doped region 110. The oxide hard mask is then removed.

[0132] In some embodiments where a CMOS element is used as the second element 21, the subsequently formed CMOS element includes an adjacent NMOS element 21N and a PMOS element 21P. A P-type well PW and an N-type well NW are formed in the well 210W of the second doped region 210, wherein the P-type well PW is adjacent to the N-type well NW. The subsequently formed NMOS element 21N corresponds to the P-type well PW, and the PMOS element 21P corresponds to the N-type well NW. In this example, the P-type well PW and the N-type well NW are spaced laterally (e.g., in the first direction D1) from the trench isolation member 211 by an appropriate distance. Details of the fabrication of the P-type well PW and the N-type well NW can be found in the description of the fabrication of the substrate region 120 described above, and will not be repeated here.

[0133] Furthermore, in some embodiments, the P-type well PW in the second doped region 210 can be formed in the same process as the substrate region 120 of the same conductivity type in the first doped region 110 to simplify the process. For example, a patterned mask (e.g., a hard oxide mask) is provided above the epitaxial layer 102, and dopants of the second conductivity type are implanted at the positions of the P-type well PW and the substrate region 120 according to the patterned mask to form the P-type well PW and the substrate region 120. The patterned mask is then removed.

[0134] Then, refer to Figure 2CThis forms heavily doped portions of the components to be integrated. For example, in some embodiments where a VDMOS element is used as the first element 11, adjacent heavily doped portions 122 and 124 are formed in the substrate region 120 of the first doped region 110 to serve as the source region and base region of the first element 11, respectively. The heavily doped portions 124 and 122 have different conductivity types. In this example, the heavily doped portion 122 and the first doped region 110 have the same first conductivity type, such as n-type; the heavily doped portion 124 has a second conductivity type, such as p-type.

[0135] According to some embodiments, for example, doping is performed from the top surface 102a of the epitaxial layer 102 in the substrate region 120 of the first doped region 110 to form heavily doped portions 122 and 124 in the substrate region 120. For example, doping can be performed from the top surface 102a of the epitaxial layer 102 by deposition, photolithography, etching, and implantation processes to form the heavily doped portions 122 and 124. In some embodiments, the doping concentrations of the heavily doped portions 122 and 124 are approximately 1E18 atoms / cm², respectively. 3 Up to approximately 1E21 atoms / cm 3 Between the ranges.

[0136] In some embodiments, the formation of the heavily doped portion 124 may allow the contact 503 subsequently formed above the heavily doped portion 122 to be made easier to form. Figure 2D It has good ohmic contact with the substrate region 120. In this example, one side of the heavily doped portion 124 is in contact with the adjacent trench structure 118, for example, the heavily doped portion 124 directly contacts the insulating layer 1181 of the trench structure 118.

[0137] In some embodiments where a CMOS element (including an NMOS element 21N and a PMOS element 21P) is used as the second element 21, heavily doped portions 212, 213, and 214 may be formed in the P-type well PW, and these heavily doped portions 212, 213, and 214 may be spaced appropriately apart from each other. Heavily doped portions 212 and 213 may respectively be the source and drain regions of the subsequently formed NMOS element 21N. Heavily doped portion 214 is the base region of the NMOS element 21N. Furthermore, in this example, heavily doped portions 212 and 213 have the same conductivity type, for example (but not limited to) n-type. Heavily doped portions 214 and 212 have different conductivity types, with heavily doped portion 214 being, for example (but not limited to) p-type.

[0138] Furthermore, in some embodiments where a CMOS element is used as the second element 21, heavily doped portions 222, 223, and 224 can be formed in the N-type well NW, and these heavily doped portions 222, 223, and 224 can be spaced appropriately apart from each other. Heavily doped portions 222 and 223 can be the drain and source regions of the subsequently formed PMOS element 21P, respectively. Heavily doped portion 224 is the base region of the PMOS element 21P. Furthermore, in this example, heavily doped portions 222 and 223 have the same conductivity type, for example (but not limited to) p-type. Heavily doped portions 224 and 222 have different conductivity types; heavily doped portion 224 is, for example (but not limited to) n-type.

[0139] Furthermore, in some embodiments, heavily doped portions of the same conductivity type in the second doped region 210 and the first doped region 110 can be formed in the same process to simplify the process. For example, heavily doped portions 122, 212, 213, and 224, which also have a first conductivity type (e.g., n-type), can be formed by implanting dopants of the first conductivity type at the locations of these heavily doped portions using a patterned mask (e.g., an oxide hard mask) provided above the epitaxial layer 102; the patterned mask is then removed. Similarly, heavily doped portions 124, 214, 222, and 223, which also have a second conductivity type (e.g., n-type), can be formed by implanting dopants of the second conductivity type at the locations of these heavily doped portions using another patterned mask; the patterned mask is then removed.

[0140] Then, refer to Figure 2D Gate structures and contacts for each element are formed above the epitaxial layer 102. According to some embodiments, the first element 11 and the second element 21 include planar gate structures and have similar configurations and arrangements to facilitate fabrication together in the same process.

[0141] In some embodiments, a gate structure 126 is formed at a location corresponding to the first doped region 110. The gate structure 126 includes, for example, a gate dielectric layer (not shown) and a gate electrode located above the gate dielectric layer, wherein the gate structure 126 is located on the surface of the epitaxial layer 102. Furthermore, the gate structure 126 is adjacent to the heavily doped portion 122 (which is the source region of the first element 11), for example, spanning the heavily doped portion 122 and a portion of the first doped region 110 (which is the drift region R of the first element 11). D Above. In this example, a trench structure 118, which can be a source or field plate, a substrate region 120, a heavily doped region 122, a heavily doped region 124, and a gate structure 126 can constitute a VDMOS device, with the substrate 100 as the drain region. Several VDMOS devices can be formed in the first doped region 110.

[0142] In some embodiments, a gate structure 216 is formed on the P-type well PW corresponding to the second doped region 210 to serve as the gate structure of the NMOS element 21N. The gate structure 216 is located on the epitaxial layer 102 and between the heavily doped region 212 (source region) and the heavily doped region 213 (drain region). The gate structure 216 includes, for example, a gate dielectric layer (not shown) and a gate electrode located above the gate dielectric layer.

[0143] Furthermore, in some embodiments, a gate structure 226 is formed on the N-type well NW corresponding to the second doped region 210 to serve as the gate structure of the PMOS element 21P. The gate structure 226 is located on the epitaxial layer 102 and between the heavily doped region 222 (drain region) and the heavily doped region 223 (source region). The gate structure 226 includes, for example, a gate dielectric layer (not shown) and a gate electrode located above the gate dielectric layer.

[0144] In some embodiments, the gate structures 126, 216 and 226 described above are located on the surface of the epitaxial layer 102 and can be formed in the same process to simplify the process.

[0145] According to an embodiment, after forming gate structures 126, 216, and 226, an insulating layer 500 is formed over the epitaxial layer 102, and this insulating layer 500 covers the gate structures 126, 216, and 226. Next, a plurality of contact holes (not shown) are formed in the insulating layer 500, and these contact holes expose the top surfaces of the gate structure, source region, drain region, and base region of each element. In some embodiments, contact holes are also formed in the insulating layer 500 that expose the top surface of the trench structure 118 in the first doped region 110 and the top surface of the trench separator 211 in the second doped region 210. Then, conductive material is filled into these contact holes to form contacts.

[0146] In some embodiments, the insulating layer 500 may be silicon oxide, other suitable dielectric materials, or combinations thereof. In some embodiments, the material of the insulating layer 500 is different from the material of the gate dielectric layer of the gate structures 126, 216, and 226. In some other embodiments, the material of the insulating layer 500 may be the same as the material of the gate dielectric layer of the gate structures 126, 216, and 226.

[0147] According to some embodiments, an insulating layer 500 having multiple contact holes can be formed by a deposition process, a photolithography patterning process, and an etching process. In one example, an insulating layer 500 is first deposited on a surface including multiple heavily doped portions and a gate structure using a deposition process. Next, a photolithography patterning process is performed to remove portions of the insulating material, thereby forming multiple contact holes. Furthermore, conductive material is filled into these contact holes to form multiple contacts.

[0148] According to some embodiments, such as Figure 2D As shown, the formed contact 502 directly contacts the gate structure 126, while the contact 503 directly contacts the heavily doped portion 122 (e.g., the source region of the first element 11) and the heavily doped portion 124. Since the heavily doped portion 124, having a second conductivity type (e.g., p-type), directly contacts the substrate region 120, the formed contact 503 can achieve good ohmic contact with the substrate region 120 through the heavily doped portion 124. Additionally, in some examples, the contact 508 directly contacts the trench structure 118, and the trench structure 118 can be electrically connected to the gate structure 126 or the heavily doped portion 122 serving as the source region of the first element, depending on the application design.

[0149] Furthermore, according to some embodiments, such as Figure 2D As shown, in the NMOS element 21N, the formed contact 512 directly contacts the gate structure 216, while contacts 513 and 514 directly contact the heavily doped portion 212 (source region) and the heavily doped portion 213 (drain region), respectively. Contact 515 directly contacts the heavily doped portion 214 (base region).

[0150] like Figure 2D As shown, in the PMOS element 21P, the formed contact 522 directly contacts the gate structure 226, while contacts 523 and 524 directly contact the heavily doped portion 222 (drain region) and the heavily doped portion 223 (source region), respectively. Contact 525 directly contacts the heavily doped portion 224 (base region).

[0151] Furthermore, in some embodiments, contacts 518 and 528 directly contact the trench isolator 211 to prevent charge accumulation in the trench isolator 211. In other embodiments, contacts 518 and 528 are not provided, and the trench isolator 211 is treated as floating.

[0152] Each of the aforementioned contacts may comprise one or more material layers. In some examples, a barrier material (not shown) may be formed on the insulating layer 500 by a deposition process, and the barrier material may be conformally deposited in the contact hole; then, a conductive material (not shown) may be deposited on top of the barrier material layer, and the conductive material may fill the remaining space in the contact hole. Next, excess portions of the conductive and barrier materials above the insulating layer 500 are removed (e.g., etched) to form a contact barrier layer and a contact conductive layer in the contact hole, thereby forming the contact.

[0153] In some embodiments, the material of the aforementioned contact barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), other suitable barrier materials, or combinations thereof. In some embodiments, the contact barrier layer may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable processes, or combinations thereof.

[0154] In some embodiments, the aforementioned conductive contact layer may be a single layer or multiple layers, and its conductive material may include tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), other suitable metals, or combinations of the foregoing materials. Furthermore, in some embodiments, this conductive material may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, other suitable processes, or combinations of the foregoing processes.

[0155] Figure 3 This is a schematic cross-sectional view of a semiconductor structure 3 at an intermediate manufacturing stage, according to some embodiments of the present disclosure. Figure 3 and Figure 1 , Figures 2A to 2D Identical or similar components are referred to by the same or similar reference numbers, and the details of these components in the above embodiments can be found therein, and will not be repeated in this example.

[0156] Compared to Figure 2D Semiconductor structure 2, Figure 3 In addition to the first element 11 and the second element 21, the semiconductor structure 3 further integrates a third element 31. The components included in the first element 11 and the second element 21 are described in the exemplary embodiment above. Similarly... Figure 2A The second doped region 210 shown includes a buried layer 210B and a well 210W, and a third element 31 is formed within the third doped region 310. In this example, the third element 31 is, for example, a laterally diffused N-type metal-oxide-semiconductor (LDNMOS) element. The third doped region 310 includes, for example, a buried layer 310B, wells 301 and 310W of different conductivity types.

[0157] In some embodiments, well 301 is located above and continues the buried layer 310B. Well 301 has the same first conductivity type as the epitaxial layer 102, such as n-type. If the third element 31 is a high-voltage LDNMOS device (e.g., operating at 40V or other high voltages), well 301 may also be referred to as a high-voltage N-type well (HVNW). In some embodiments, the doping concentration of well 301 is greater than the doping concentration of the epitaxial layer 102. In some embodiments, the doping concentration of well 301 is approximately equal to the doping concentration of the first doped region 110.

[0158] In some embodiments, the well 310W is outside the well 301, and the well 310W and the buried layer 310B have a second conductivity type, such as p-type. In some embodiments, the bottom of the well 310W extends further into the buried layer 310B to provide better electrical isolation between the third element 31 and other elements on the substrate.

[0159] Furthermore, in this example, similar to the trench spacer 211 in the second doped region 210, a trench spacer 311 is also formed in the third doped region 310. The trench spacer 311 can extend through the well 310W to the buried layer 310B; for example, the lower part of the trench spacer 311 is located in the buried layer 310B. In other words, the bottom surface of the trench spacer 311 is lower than the bottom surface of the well 310W. Figure 3 As shown.

[0160] According to some embodiments, the trench isolation element 311 can form an isolation structure with the buried layer 310B, so that the third element 31 subsequently formed in the third doped region 310 can achieve good electrical isolation from the elements formed outside the second doped region 310 (e.g., the first element 11 and the second element 21). In particular, in some examples where the first element 11 is a VDMOS element, the substrate 100, which serves as the drain of the first element 11, is connected to a drain operating voltage, which can easily cause electrical instability in other integrated elements on the substrate 100 (e.g., the second element 21 in the second doped region 210 and the third element 31 in the third doped region 310). The isolation structure formed by the buried layer 310B and the trench isolation element 311 can solve the above problem.

[0161] In some embodiments where an LDNMOS element is used as the third element 31, such as Figure 3 As shown, the third element 31 includes a heavily doped region 312 (source region), a heavily doped region 313 (drain region), and a heavily doped region 314 (base region). In this example, the heavily doped regions 312 and 313 have the same first conductivity type, such as n-type. The heavily doped region 314 has a second conductivity type, such as p-type. Furthermore, the heavily doped regions 312 and 314 may be formed in a substrate region 320 having the second conductivity type.

[0162] In this example, the third element 31 also includes a gate structure 316 located between the heavily doped portion 312 (source region) and the heavily doped portion 313 (drain region). The gate structure 316 includes, for example, a gate dielectric layer (not shown) and a gate electrode located above the gate dielectric layer. Details of its fabrication and materials can be found in the description of the gate structures 126, 216, 226, etc., described above.

[0163] This example also includes forming a plurality of contacts in the insulating layer 500 to electrically connect the third element 31. Examples include contact 532 which directly contacts the gate structure 316, contact 533 which directly contacts the heavily doped portion 313 (drain region), and contact 534 which directly contacts the heavily doped portion 312 (source region) and the heavily doped portion 314 (base region). Details regarding the fabrication method and materials of contacts 532, 533, and 534 can be found in the descriptions of contacts 502, 503, 512, 513, 514, 515, 522, 523, 524, and 525 described above.

[0164] Furthermore, similar doped regions in the first doped region 110, the second doped region 210, and the third doped region 310 can be fabricated together in the same process to save steps. For example, the buried layer 310B of the third doped region 310 can be fabricated in the same process as the buried layer 210B of the second doped region 210, and the well 310W of the third doped region 310 can be fabricated in the same process as the well 210W of the second doped region 210. Similar components in the first element 11, the second element 21, and the third element 31 can be fabricated together in the same process to save steps. For example, the first element 11, the second element 21, and the third element 31 include gate structures of the same or similar configuration and are fabricated in the same process. For example, multiple related contacts of the first element 11, the second element 21, and the third element 31 can be fabricated in the same process. Accordingly, the semiconductor structure proposed according to the embodiment, which includes the integration of different types of MOS elements on the same substrate, can be completed without increasing manufacturing costs.

[0165] Furthermore, according to some embodiments, the contacts formed after component integration have top surfaces of approximately the same height, for example, flush with the top surface of the insulating layer 500, so that the resulting semiconductor structure has a flat top surface, which is beneficial for fabricating subsequent components above the insulating layer.

[0166] Figure 4 This is a schematic cross-sectional view of a semiconductor structure 4 at an intermediate manufacturing stage, according to some embodiments of this disclosure. Figure 4 and Figure 1 , Figures 2A to 2D , Figure 3Identical or similar components are referred to by the same or similar reference numbers, and the details of these components in the above embodiments can be found therein, and will not be repeated in this example.

[0167] Compared to Figure 2D Semiconductor structure 2, Figure 4 In addition to the first element 11 and the second element 21, the semiconductor structure 4 further integrates another element, referred to herein as the fourth element 41 for ease of explanation. The fourth element 41 is formed in the fourth region 410. In this example, the fourth element 41 is, for example, a laterally diffused p-type metal-oxide-semiconductor (LDPMOS) element. The fourth region 410 includes, for example, a buried layer 410B and a well 410W located above the buried layer 410B. The well 410W and the buried layer 410B have the same second conductivity type, for example, p-type. If the fourth element 41 is a high-voltage LDPMOS element (e.g., operating at 40V or other high voltages), the well 410W may also be referred to as a high-voltage p-type well (HVPW). In some embodiments, the doping concentration of the well 410W is greater than the doping concentration of the buried layer 410B.

[0168] In some embodiments, the fourth element 41 further includes a heavily doped region 412 (source region), a heavily doped region 413 (drain region), a heavily doped region 414 (base region), and a gate structure 416. In this example, the heavily doped regions 412 and 413 have the same second conductivity type, such as p-type. The heavily doped region 414 has a first conductivity type, such as n-type. Furthermore, the heavily doped regions 412 and 414 may be formed in a well 420 having the first conductivity type.

[0169] In this example, a plurality of contacts are formed in the insulating layer 500 to electrically connect the fourth element 41. For example, contacts 542 that directly contact the gate structure 416, contacts 543 that directly contact the heavily doped portion 413 (drain region), and contacts 544 that directly contact the heavily doped portion 412 (source region) and the heavily doped portion 414 (base region).

[0170] The configuration, materials, and manufacturing methods of the components of the fourth element 41 can be referred to the descriptions of the first element 11, the second element 21, and / or the third element 31, and will not be repeated here. Furthermore, similar doped regions in the first element 11, the second element 21, and the fourth element 41 can be fabricated together in the same process, and components with the same or similar configurations in each element (e.g., heavily doped portions, gate structures, and contacts of the same conductivity type) can be fabricated in the same process to save steps.

[0171] Figure 5 This is a schematic cross-sectional view of a semiconductor structure 5 at an intermediate manufacturing stage, according to some embodiments of this disclosure. Figure 5Zhongyu Figure 1 , Figures 2A to 2D , Figure 3 , Figure 4 Identical or similar components are referred to by the same or similar reference numbers, and the details of these components in the above embodiments can be found therein, and will not be repeated in this example. Figure 5 The semiconductor structure 5 integrates a first element 11, a second element 21, a third element 31, and a fourth element 41. The configuration, materials, and manufacturing methods of the various components of these elements can be found in the description of these components in the above embodiments.

[0172] In summary, based on the semiconductor structures and formation methods disclosed in some embodiments of this disclosure, semiconductor structures comprising various types of MOS elements can be fabricated, wherein each MOS element can operate in its respective doped region and exhibits good electrical performance. According to some embodiments, the semiconductor structure integrating multiple MOS elements includes vertical MOS elements and non-vertical MOS elements (e.g., lateral MOS elements), wherein the substrate of the semiconductor structure contains a highly doped dopant, which can serve as a drain region for the vertical MOS element. According to some embodiments, the non-vertical MOS element, through the provision of a buried layer (e.g., buried layer 210B), can reduce the influence of the substrate on the electrical performance of the non-vertical MOS element, wherein the buried layer has a conductivity type opposite to that of the substrate and the epitaxial layer on the substrate, avoiding the generation of an undesirable vertical electric field at the corresponding non-vertical MOS element by the highly doped substrate. In some examples, the substrate of the semiconductor structure has a first conductivity type (e.g., n-type), and the buried layer has a second conductivity type (e.g., p-type). Furthermore, in some embodiments, a highly doped region (such as the first doped region 110) can be formed in the epitaxial layer at the location corresponding to the vertical MOS element, and this region is adjacent to the substrate, thereby further improving the electrical performance of the vertical MOS element. Furthermore, according to some embodiments of this disclosure, different types of MOS elements (e.g., non-vertical and vertical MOS elements) can be freely selected and combined in a semiconductor structure by the arrangement of the doped region, and these MOS elements are electrically isolated from each other, achieving good electrical performance. For example, according to embodiments, BCD (including bipolar elements, CMOS elements, and DMOS elements) and VDMOS elements can be integrated on the same wafer to comprehensively solve the design challenges of complex, high-power applications. In addition, the formation method proposed in some embodiments of this disclosure allows for the fabrication of semiconductor devices containing different types of MOS elements through simplified processes compatible with existing fabrication methods. Therefore, the processes of these embodiments are simple and do not significantly increase additional manufacturing costs.

[0173] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any person skilled in the art can understand, from the disclosure of some embodiments of this disclosure, current or future developed processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claims and embodiments.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a first type of conductivity; An epitaxial layer is located on the substrate, and the epitaxial layer has the first conductivity type; A first doped region extends from the top surface of the epitaxial layer into the epitaxial layer, and the first doped region has the first conductivity type; A first element is located in the first doped region, wherein the substrate serves as a drain of the first element; A second doped region extends from the top surface of the epitaxial layer into the epitaxial layer, and the second doped region has a second conductivity type. The second doped region is located on one side of the first doped region, wherein a portion of the epitaxial layer extends between the first doped region and the second doped region to separate the first doped region and the second doped region; and A second element is formed in the second doped region.

2. The semiconductor structure as described in claim 1, characterized in that, The doping concentration of the first doped region is greater than the doping concentration of the epitaxial layer.

3. The semiconductor structure as described in claim 1, characterized in that, The doping concentration of the substrate is greater than that of the first doped region.

4. The semiconductor structure as described in claim 1, characterized in that, The bottom surface of the first doped region has a first distance to the top surface of the substrate, and the bottom surface of the second doped region has a second distance to the top surface of the substrate, the second distance being greater than the first distance.

5. The semiconductor structure as described in claim 1, characterized in that, Including: A trench structure is located in the first doped region, and the trench structure extends from the top surface of the epitaxial layer toward the substrate in the first doped region.

6. The semiconductor structure as described in claim 5, characterized in that, The vertical distance from the bottom surface of the first doped region to the top surface of the substrate is less than the vertical distance from the bottom surface of the trench structure to the bottom surface of the first doped region.

7. The semiconductor structure as described in claim 5, characterized in that, The second doped region and the first doped region are separated in a first direction, and the trench structure extends in a second direction, which is different from the first direction.

8. The semiconductor structure as described in claim 1, characterized in that, It also includes a trench separator extending from the top surface of the epitaxial layer toward the substrate in the second doped region, wherein, viewed from above the substrate, the trench separator surrounds the periphery of the second element.

9. The semiconductor structure as described in claim 1, characterized in that, The second doped region includes: An embedded layer having the second conductivity type; and A well, having the second conductivity type, extending from the top surface of the epitaxial layer to the buried layer, wherein the second element is formed in the well. The doping concentration of the buried layer is different from the doping concentration of the well.

10. The semiconductor structure as described in claim 9, characterized in that, The doping concentration of the well is greater than the doping concentration of the buried layer.

11. The semiconductor structure as described in claim 9, characterized in that, The horizontal position of the buried layer is between the bottom surface of the first doped region and the well.

12. The semiconductor structure as claimed in claim 9, characterized in that, Including: A trench structure is located in the first doped region, the trench structure extending from the top surface of the epitaxial layer toward the substrate within the first doped region. The bottom surface of the trench structure is closer to the top surface of the substrate than the bottom surface of the well in the second doped region.

13. The semiconductor structure as described in claim 9, characterized in that, Including: A trench isolator is located in the second doped region, and the trench isolator extends from the top surface of the epitaxial layer toward the substrate to the buried layer.

14. The semiconductor structure as described in claim 13, characterized in that, The lower part of the trench isolation element is located in the embedded layer.

15. The semiconductor structure as claimed in claim 1, characterized in that, The first element and the second element each include a planar gate structure on the top surface of the epitaxial layer.

16. The semiconductor structure as claimed in claim 1, characterized in that, Including: A base region is formed in the first doped region, and the base region extends from the top surface of the epitaxial layer into the epitaxial layer, and the base region has the second conductivity type; A first heavily doped region is formed in the substrate region and extends downward from the top surface of the epitaxial layer, the first heavily doped region having the first conductivity type, wherein the first heavily doped region is a source region of the first element; and A first gate structure is located on the top surface of the epitaxial layer and corresponds to the first doped region, and the first gate structure spans over the substrate region and the first heavily doped portion.

17. The semiconductor structure as claimed in claim 16, characterized in that, Including: A second doped region and a third doped region are formed in the second doped region and extend from the top surface of the epitaxial layer into the epitaxial layer, serving as a source region and a drain region of the second element, respectively; and A second gate structure is located on the top surface of the epitaxial layer and corresponds to the second doped region, wherein the second gate structure is located between the second heavily doped region and the third heavily doped region.

18. The semiconductor structure as claimed in claim 1, characterized in that, Including: A third element is formed in the second doped region or in another region having the second conductivity type, wherein the third element is located on one side of the second element.

19. The semiconductor structure as claimed in claim 1, characterized in that, Including: A third doped region extends from the top surface of the epitaxial layer into the epitaxial layer, and the third doped region has the second conductivity type. The third doped region is located between the first doped region and the second doped region, wherein the third doped region is separated from the first doped region and the second doped region by a portion of the epitaxial layer; and A third element is formed in the third doped region.

20. The semiconductor structure as claimed in claim 1, characterized in that, The first element is a vertically diffused metal-oxide-semiconductor element.

21. A method for forming a semiconductor structure, characterized in that, include: A substrate having a first conductivity type is provided; An epitaxial layer is formed on the substrate, the epitaxial layer having the first conductivity type; A first doped region is formed in the epitaxial layer, and the first doped region extends from the top surface of the epitaxial layer toward the substrate, and the first doped region has the first conductivity type; A first element is formed in the first doped region, wherein the substrate serves as a drain of the first element; A second doped region is formed in the epitaxial layer, the second doped region extending from the top surface of the epitaxial layer toward the substrate, and the second doped region having a second conductivity type. The second doped region is located on one side of the first doped region, wherein a portion of the epitaxial layer extends between the first doped region and the second doped region to separate the first doped region and the second doped region. as well as A second element is formed in the second doped region.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, Including: A trench structure is formed in the first doped region, the trench structure extending from the top surface of the epitaxial layer toward the substrate in the first doped region.

23. The method for forming a semiconductor structure as described in claim 22, characterized in that, Including: A trench isolator is formed in the second doped region, the trench isolator extending from the top surface of the epitaxial layer toward the substrate in the second doped region, wherein the trench isolator surrounds the periphery of the second element.

24. The method for forming a semiconductor structure as described in claim 23, characterized in that, The trench structure and the trench isolation element are manufactured in the same process.

25. The method for forming a semiconductor structure as described in claim 21, characterized in that, Including: A first gate structure is formed on the top surface of the epitaxial layer, and the first gate structure corresponds to the first doped region; as well as A second gate structure is formed on the top surface of the epitaxial layer, and the second gate structure corresponds to the second doped region. The first gate structure and the second gate structure are fabricated in the same process.

26. The method for forming a semiconductor structure as described in claim 25, characterized in that, Including: A base region is formed in the first doped region, the base region having the second conductivity type and extending from the top surface of the epitaxial layer into the epitaxial layer; A first heavily doped region is formed in the substrate region and extends downward from the top surface of the epitaxial layer. The first heavily doped region has the first conductivity type and serves as a source region of the first element. A second doped region and a third doped region are formed in the second doped region and extend downward from the top surface of the epitaxial layer to serve as a source region and a drain region of the second element, respectively.

27. The method for forming a semiconductor structure as described in claim 26, characterized in that, Including: An insulating layer is formed on the epitaxial layer, and the insulating layer covers the first gate structure and the second gate structure; A first gate contact is formed in the insulating layer to connect to the first gate structure, a second gate contact to connect to the second gate structure, a first source contact to connect to the first heavily doped portion, a second source contact to connect to the second heavily doped portion, and a drain contact to connect to the third heavily doped portion. The first gate contact, the second gate contact, the first source contact, the second source contact, and the drain contact are all fabricated in the same process.

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