Monolithic three-dimensional integrated photoelectric detector and preparation method thereof

Abstract

The invention provides a monolithic three-dimensional integrated photoelectric detector and a preparation method thereof. The preparation method comprises the following steps: forming an isolation passivation layer on a readout integrated circuit serving as a substrate of the photoelectric detector; forming a source conductive through hole, a drain conductive through hole and a bottom gate contact hole in the isolation passivation layer; a conductive material is deposited and planarized, the source electrode conductive through hole, the drain electrode conductive through hole and the bottom gate contact hole are filled with the conductive material, the conductive material in the source electrode conductive through hole forms a source electrode conductive channel, the conductive material in the drain electrode conductive through hole forms a drain electrode conductive channel, and the conductive material in the bottom gate contact hole forms a bottom gate electrode layer; forming a bottom gate dielectric layer on the planarized surface, and forming a channel layer on the bottom gate dielectric layer; forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are electrically connected with the connecting port of the read-out integrated circuit through a source electrode conductive channel and a drain electrode conductive channel respectively; and forming a top gate structure which comprises a top gate dielectric layer and a photosensitive layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a monolithic three-dimensional integrated photodetector and its fabrication method. Background Technology

[0002] Photoelectric detection technology enables efficient conversion between optical and electrical signals, and its applications cover numerous key fields. However, with the continuous increase in requirements for the resolution, sensitivity, integration, and reliability of detection systems, existing photoelectric detection systems can no longer meet the actual needs of high-end applications.

[0003] Existing photoelectric detection systems employ separate fabrication of the detector array and the readout integrated circuit (ROIC), followed by flip-flop interconnection to connect them. During this flip-flop interconnection process, In (indium) / Cu (copper) pillar flip-flop technology is used to achieve the electrical connection between the detector array and the readout integrated circuit. For example… Figure 1 As shown. However, the solder joints produced by the inverted soldering process suffer from poor stability and insufficient reliability. Due to material properties and process limitations, the solder joints inherently carry the risk of slippage, for example... Figure 2 As shown in the circle. This will lead to problems such as poor solder joint contact, easy detachment, and impact on electrical performance. Furthermore, the solder joint size and alignment accuracy of the flip-flop process directly limit the minimum pixel size. Currently, the pixel size of mainstream technologies both domestically and internationally can only reach 5μm, making further reduction difficult. Otherwise, it would lead to problems such as decreased interconnect strength, increased contact resistance, and increased alignment difficulty. Due to the limitation on the minimum pixel size, it is impossible to meet the demand for smaller pixels in high-resolution imaging.

[0004] As application demands shift towards larger arrays and higher densities, the shortcomings of flip-flop soldering technology are further amplified. Large-scale arrays require the arrangement of massive numbers of solder joints, significantly increasing the probability of problems such as solder joint slippage and poor contact, leading to a substantial drop in yield. At the same time, the alignment and interconnection processes for these massive numbers of solder joints are extremely complex, with manufacturing difficulties and costs increasing exponentially, making it difficult to achieve large-scale production of large-scale array detectors. Summary of the Invention

[0005] This disclosure provides a method for fabricating a monolithic three-dimensional integrated photodetector and the monolithic three-dimensional integrated photodetector fabricated by this method. The fabrication method of this disclosure solves the problems existing in the flip-flop process and makes the mass production of large-area array detectors a reality. Furthermore, it can further reduce the size of pixels.

[0006] According to one aspect of this disclosure, a method for fabricating a monolithic three-dimensional integrated photodetector is provided, comprising: depositing an electrically isolated passivation material on a readout integrated circuit serving as a substrate of the photodetector to form an isolation passivation layer; forming source conductive vias, drain conductive vias, and bottom gate contact vias in the isolation passivation layer; depositing a conductive material and performing planarization, wherein the conductive material at least fills the source conductive vias, drain conductive vias, and bottom gate contact vias, the conductive material filling the source conductive vias forming source conductive channels, the conductive material filling the drain conductive vias forming drain conductive channels, and the conductive material filling the bottom gate contact vias forming a bottom gate electrode layer; forming a bottom gate dielectric layer on the planarized surface, and forming a channel layer on the bottom gate dielectric layer; forming a source and a drain, wherein the source and the drain are electrically connected to the connection ports of the readout integrated circuit through the source conductive channels and the drain conductive channels, respectively; and forming a top gate structure, wherein the top gate structure includes a top gate dielectric layer and a photosensitive layer.

[0007] According to one aspect of the technical solution disclosed herein, a readout integrated circuit is used as a substrate to deposit an isolation passivation layer and form source and drain conductive vias and bottom gate contact holes. Through-hole interconnects replace the traditional In / Cu pillar flip-flop process, completely solving problems such as solder joint slippage, poor contact, and insufficient reliability associated with flip-flops, significantly improving the long-term operational stability of the device. The through-hole interconnect design offers higher alignment accuracy, breaking the existing 5μm pixel size limitation and allowing for further reduction in pixel size to meet high-resolution imaging requirements. Furthermore, a monolithic three-dimensional integrated architecture is adopted to achieve integrated fabrication of the detector and readout integrated circuit, eliminating the need for separate manufacturing and interconnection. This simplifies the process flow, reduces processing complexity and cost, and avoids the yield degradation caused by massive solder joints in large-scale arrays. This enables the mass production of large-area, high-density detectors.

[0008] According to at least one embodiment of the present disclosure, in the process of depositing conductive material in the conductive vias and bottom gate contact holes, the same conductive material is deposited using the same process to fill the source conductive vias, drain conductive vias and bottom gate contact holes.

[0009] According to the technical solution of this embodiment, by using the same process and the same conductive material to simultaneously fill three types of hole structures, the process flow is simplified and the electrical parameters of the source / drain conductive channels and the bottom gate electrode layer are unified.

[0010] According to a method for fabricating a monolithic three-dimensional integrated photodetector according to at least one embodiment of the present disclosure, after forming the channel layer, a barrier layer is deposited on the channel layer, and the barrier layer, channel layer, and bottom gate dielectric layer outside the active region are etched away.

[0011] According to the technical solution of this embodiment, by depositing a barrier layer on the channel layer and precisely etching away the barrier layer, channel layer and bottom gate dielectric layer outside the active region, the barrier layer can effectively protect the active region channel layer from contamination and damage by subsequent processes, and can also accurately define the active region of the device.

[0012] According to at least one embodiment of the method for fabricating a monolithic three-dimensional integrated photodetector, after etching away the barrier layer, channel layer, and bottom gate dielectric layer outside the active region, the method further includes: depositing a protective layer, wherein the protective layer covers the barrier layer, the isolation passivation layer, the source conductive channel, and the drain conductive channel; etching the protective layer to form a source contact hole and a drain contact hole, wherein the source contact hole terminates at the source conductive channel, and the drain contact hole terminates at the drain conductive channel.

[0013] According to the technical solution of this embodiment, by depositing a protective layer to fully cover the barrier layer, the isolation passivation layer and the source-drain conductive channel, the contamination and structural damage caused by subsequent processes are effectively avoided, ensuring the integrity of the structure. At the same time, the contact holes terminating at the source-drain conductive channel are precisely etched to ensure reliable electrical connection between the source, drain and conductive channel, which is compatible with the process collaboration requirements of monolithic three-dimensional integration.

[0014] According to the fabrication method of a monolithic three-dimensional integrated photodetector according to at least one embodiment of the present disclosure, during the formation of the source and drain electrodes, a source contact layer and a source electrode layer are sequentially deposited in the source contact hole, and a drain contact layer and a drain electrode layer are sequentially deposited in the drain contact hole, wherein the source contact layer directly contacts the channel layer and the source conductive channel, and the drain contact layer directly contacts the channel layer and the drain conductive channel.

[0015] According to the technical solution of this embodiment, the contact layer and electrode layer are deposited in layers. The contact layer directly contacts the channel layer and the source / drain conductive channels, ensuring reliable electrical connection between the source / drain and the channel / conductive channels, and effectively reducing contact resistance and carrier transport barrier. The contact layer adapts to the interface characteristics of different channel materials, and the electrode layer ensures high conductivity, achieving optimization of interface compatibility and transport efficiency, further improving the stability of device electrical performance and detection response speed, and meeting the process and performance requirements of monolithic 3D integration.

[0016] According to at least one embodiment of the present disclosure, the method for fabricating a monolithic three-dimensional integrated photodetector further includes, after forming the source electrode layer and the drain electrode layer, depositing an insulating layer on the surface; etching the insulating layer and the barrier layer in the top gate region, stopping at the channel layer, to form a top gate contact hole.

[0017] According to the technical solution of this embodiment, the existing source, drain and other structures are protected from contamination and damage by the deposition of an insulating layer. At the same time, the insulating layer and barrier layer of the top gate region are precisely etched and terminated at the channel layer, providing a precisely positioned contact hole for the top gate structure, which meets the process requirements of monolithic three-dimensional integration and the electrical performance of the device.

[0018] According to at least one embodiment of the present disclosure, a method for fabricating a monolithic three-dimensional integrated photodetector includes a barrier layer comprising a silicon nitride layer and an aluminum oxide layer located between the silicon nitride layer and the channel layer. During the etching process of the barrier layer, the silicon nitride layer is removed by dry etching, and the aluminum oxide layer is removed by wet etching.

[0019] According to the technical solution of this embodiment, by using a composite barrier layer design of silicon nitride layer and aluminum oxide layer, combined with a layered etching method of dry etching of silicon nitride and wet etching of aluminum oxide, the silicon nitride layer can be removed efficiently and accurately by means of dry etching, while the underlying channel layer can be avoided by means of wet etching. This meets the process requirements of monolithic 3D integration and can also ensure the stability and yield of device performance.

[0020] According to at least one embodiment of the present disclosure, the method for fabricating a monolithic three-dimensional integrated photodetector includes the following steps in forming the top grid structure: depositing a top grid dielectric layer at least in the top grid contact holes; and depositing a photosensitive layer at least on top of the top grid dielectric layer.

[0021] According to another aspect of this disclosure, a monolithic three-dimensional integrated photodetector is provided, a readout integrated circuit serving as a substrate, and a plurality of detection units, each detection unit comprising a source and a drain, the source and drain being electrically connected to a connection port of the readout integrated circuit via source conductive channels and drain conductive channels, respectively, wherein the source conductive channels and drain conductive channels are formed of conductive material deposited in conductive vias, and further wherein an isolation passivation material layer is deposited on the surface of the readout integrated circuit and the isolation passivation material is etched. The system comprises: a conductive via layer; a channel layer serving as a carrier transport channel between the source and drain; a bottom gate structure formed beneath the channel layer and including a bottom gate dielectric layer and a bottom gate electrode layer, wherein the bottom gate dielectric layer is located between the channel layer and the bottom gate electrode layer, and the bottom gate electrode layer is formed by etching the isolation passivation material layer and depositing a bottom gate electrode material; and a top gate structure formed above the channel layer and including a top gate dielectric layer and a photosensitive layer, wherein the top gate dielectric layer is located between the channel layer and the photosensitive layer.

[0022] According to another aspect of the technical solution disclosed herein, a monolithic three-dimensional integrated photodetector achieves integrated integration using a readout integrated circuit as a substrate. By replacing traditional flip-flop interconnects with source / drain conductive channels formed by etching an isolation passivation layer and depositing conductive materials, and with a bottom gate electrode layer, it completely solves problems such as solder joint slippage and insufficient reliability, breaking through pixel size limitations to meet high-resolution requirements. This enables the mass production of large-area, high-density detectors.

[0023] According to at least one embodiment of the present disclosure, a monolithic three-dimensional integrated photodetector has an insulating layer, a top gate dielectric layer and a portion of a photosensitive layer sequentially disposed on the drain electrode, and an insulating layer, a top gate dielectric layer and a portion of a photosensitive layer sequentially disposed on the source electrode.

[0024] According to the technical solution of this embodiment, by sequentially forming an insulating layer, a top-gate dielectric layer, and a partial photosensitive layer on the source and drain electrodes, the insulating layer protects the source and drain electrodes from subsequent process contamination and damage, and can also serve as an interlayer dielectric layer after the structure is formed. Simultaneously, a larger area photosensitive layer is formed, improving the detection sensitivity. Attached Figure Description

[0025] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0026] Figure 1 A schematic diagram of a prior art detector array and readout integrated circuit connected by a flip-soldering process is shown.

[0027] Figure 2 A schematic diagram is shown illustrating problems such as solder joint slippage in the existing reverse soldering process.

[0028] Figure 3 A flowchart illustrating a method for fabricating a monolithic three-dimensional integrated photodetector according to an embodiment of the present disclosure is shown.

[0029] Figures 4 to 25 The various steps of a method for fabricating a monolithic three-dimensional integrated photodetector are illustrated in the form of an exemplary device structure.

[0030] Figure 26 A top view schematic diagram of a monolithic three-dimensional integrated photodetector according to an embodiment of the present disclosure is shown. Detailed Implementation

[0031] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0032] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0033] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0034] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, the specific process sequence may be performed in a manner different from that described.

[0035] This disclosed technical solution addresses the problems of solder joint slippage and insufficient reliability in existing photoelectric detection technologies, such as In / Cu pillar flip-flop processes, pixel size limitations of 5μm that cannot meet high-resolution requirements, low yield, and increased cost and complexity in large-area array integration. It constructs a monolithic three-dimensional integrated photoelectric detector architecture using a readout integrated circuit (ROIC) as a substrate, solving interconnect defects, overcoming pixel size limitations, and enabling large-area, high-density detector mass production. Specifically, the various processes in the fabrication method make large-scale production a reality, reducing process difficulty and improving device integration, reliability, and photoelectric conversion efficiency.

[0036] According to embodiments of this disclosure, a method for fabricating a monolithic three-dimensional integrated photodetector is provided. Figure 1 A flowchart of a method for fabricating a monolithic three-dimensional integrated photodetector is shown, including steps S110 to S160.

[0037] In step S110, an electrically isolated passivation material is deposited on the readout integrated circuit, which serves as the substrate of the photodetector, to form an isolation passivation layer. In this application, the readout integrated circuit is used as the substrate, serving as the carrier of the photodetector. The electrically isolated passivation material can be selected from suitable materials so that the formed isolation passivation layer can achieve electrical isolation between the readout integrated circuit and the subsequently formed detector structure, and that the readout integrated circuit is not subject to physical and chemical damage from subsequent processes, maintaining its original electrical performance. The formed isolation passivation layer has good surface flatness.

[0038] In step S120, source conductive vias, drain conductive vias, and bottom gate contact vias are formed in the isolation passivation layer. Through photolithography and etching processes, these vias are formed in the isolation passivation layer, and all of them terminate on the surface of the readout integrated circuit. During the process, the photolithography process ensures that these vias are aligned with the corresponding parts of the readout integrated circuit, guaranteeing the alignment accuracy of the interconnection.

[0039] In step S130, conductive material is deposited and planarized. The conductive material fills at least the source conductive vias, drain conductive vias, and bottom gate contact vias. The conductive material filling the source conductive vias forms source conductive channels, the conductive material filling the drain conductive vias forms drain conductive channels, and the conductive material filling the bottom gate contact vias forms the bottom gate electrode layer. The same conductive material can be deposited in the source conductive vias, drain conductive vias, and bottom gate contact vias. A single deposition process is used to simultaneously fill the source conductive vias, drain conductive vias, and bottom gate contact vias, followed by chemical mechanical polishing (CMP) planarization. The planarization process uses an isolation passivation layer as a stop layer to precisely control the final thickness of the conductive material and remove excess conductive material from the surface, ensuring the flatness of the device surface. The final source conductive channels, drain conductive channels, and bottom gate electrode layer are all directly electrically connected to the readout integrated circuit, completely replacing traditional In / Cu pillar soldering and improving interconnect reliability and alignment accuracy.

[0040] In step S140, a bottom gate dielectric layer is formed on the planarized surface, and a channel layer is formed on the bottom gate dielectric layer. After the channel layer is formed, a barrier layer is deposited on the channel layer, and the barrier layer, channel layer, and bottom gate dielectric layer outside the active region are etched away, leaving the barrier layer, channel layer, and bottom gate dielectric layer in the active region.

[0041] In step S150, a source and a drain are formed, wherein the source and drain are electrically connected to the connection port of the readout integrated circuit through source conductive channels and drain conductive channels, respectively. After step S140, a protective layer can be deposited, wherein the protective layer covers the barrier layer, the isolation passivation layer, the source conductive channel, and the drain conductive channel. The protective layer is etched to form source contact holes and drain contact holes, wherein the source contact holes terminate at the source conductive channel, and the drain contact holes terminate at the drain conductive channel. Simultaneously, contact layer material is deposited in the source contact holes and drain contact holes, thus forming the source contact layer and drain contact layer concurrently. Then, electrode layer material is simultaneously deposited in the hollow space between the source contact layer and the drain contact layer, thus simultaneously forming the source electrode layer and the drain electrode layer, thereby forming the source and drain. The source contact layer directly contacts the channel layer and the source conductive channel, and the drain contact layer directly contacts the channel layer and the drain conductive channel.

[0042] In addition, after forming the source electrode layer and drain electrode layer, an insulating layer can be deposited on the surface of the device. Then, the insulating layer and barrier layer in the top gate region are etched, stopping at the channel layer to form a top gate contact hole. Then, in step S160, a top gate structure is formed. The top gate structure includes a top gate dielectric layer and a photosensitive layer, wherein the photosensitive layer is a pn junction structure or a pin junction structure. Specifically, the top gate dielectric layer is deposited at least in the top gate contact hole; and the photosensitive layer is deposited at least on top of the top gate dielectric layer. The specific structure of the photosensitive layer can be designed according to actual needs.

[0043] The following will refer to the appendix. Figures 4 to 25 This invention discloses a method for fabricating a monolithic three-dimensional integrated photodetector according to an embodiment of the present invention, illustrating the device structure.

[0044] like Figure 4 As shown, an electrically isolated passivation material is deposited on the surface of the readout integrated circuit (ROIC) 100, forming an isolation passivation layer 200. The surface of the readout integrated circuit has wiring, etc. The electrically isolated passivation material can be a material with electrical isolation passivation effect, such as silicon dioxide (SiO2), silicon nitride (SiN), or a combination thereof. Specifically, a certain thickness of electrically isolated passivation material can be deposited using processes such as PECVD (plasma-enhanced chemical vapor deposition) and HDPCVD (high-density plasma chemical vapor deposition). The readout integrated circuit can be, for example, a fabricated readout integrated circuit wafer, such as an integrated array fabricated using an 8-inch platform. The readout integrated circuit can include readout wiring (metal interconnect layer), connection ports (such as conductive via interfaces, also called pads, which connect to subsequent bottom gate electrodes, source electrodes, and drain electrodes), etc.

[0045] In this application, the traditional mode of separately processing and assembling the detector array and the readout integrated circuit is broken, and the integrated array of the readout circuit becomes the carrier substrate of the detector unit, realizing the integrated processing of detection and readout, that is, changing the two separate assembly to a single three-dimensional integration.

[0046] like Figure 5 As shown, photolithography and etching processes are performed to form conductive vias 210 and bottom gate contact holes 220 in the isolation passivation layer 200.

[0047] As an example, photoresist is spin-coated onto the surface of the isolation passivation layer 200, followed by mask alignment, exposure, and development steps to form patterns of conductive vias 210 and bottom gate contact holes 220 on the surface of the passivation layer. It is ensured that the patterns of the conductive vias 210 and bottom gate contact holes 220 are aligned with the corresponding connection ports of the readout integrated circuit 100. The isolation passivation layer 200 is then etched, stopping at the surface of the readout integrated circuit 100. For example, PE (Plasma Etching) or RIE (Reactive Ion Etching) processes can be used to etch the isolation passivation layer 200. Finally, the conductive vias 210 and bottom gate contact holes 220 are formed. The photoresist is then removed, and the conductive vias 210 and bottom gate contact holes 220 are cleaned.

[0048] like Figure 6 As shown, conductive material 300 is deposited. The conductive material can be one or more functional materials such as tungsten (W), titanium (Ti), titanium nitride (TiN), and palladium (Pd). The deposition process can be PVD (physical vapor deposition) or PECVD. The conductive material needs to fill the conductive vias 210 and the bottom gate contact vias 220, and its height is higher than the isolation passivation layer 200. The conductive material filling the conductive vias 210 electrically connects the source and drain electrodes to the connection ports of the readout integrated circuit. The conductive material filling the bottom gate contact vias 220 serves as the bottom gate electrode layer and can be electrically connected to the connection ports of the readout integrated circuit.

[0049] like Figure 7 As shown, the surface of the conductive material 300 is planarized using CMP (chemical mechanical polishing). The height of the conductive material 300 is polished to at least the height of the isolation passivation layer 200, thus forming the bottom gate electrode layer 310, the source conductive channel 320, and the drain conductive channel 330.

[0050] like Figure 6 and Figure 7As shown in the steps, conductive materials can be deposited using the same process to form the bottom gate electrode layer 310, the source conductive channel 320, and the drain conductive channel 330, respectively. The formation of these parts is integrated into a single deposition process, avoiding the cumbersome steps of multiple depositions and reducing the number of process steps.

[0051] like Figure 8 As shown, a bottom gate dielectric layer 400 is formed on the surface of the conductive material 300 and the isolation passivation layer 200 after CMP planarization. The bottom gate dielectric layer 400 can be a high-k dielectric material, such as one or more of hafnium dioxide (HfO2), aluminum oxide (Al2O3), and yttrium oxide (Y2O3). The bottom gate dielectric layer 400 of a predetermined thickness can be formed on the surface of the conductive material 300 and the isolation passivation layer 200 by ALD (atomic layer deposition) or CVD (chemical vapor deposition) processes.

[0052] like Figure 9 As shown, a channel layer 500 is formed on the bottom gate dielectric layer 400. The material of the channel layer can be selected from carbon nanotubes or two-dimensional materials, wherein the two-dimensional materials can be selected from molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), boron nitride (BN), tungsten diselenide (WSe2), graphene, or black phosphorus. The preferred material of the channel layer is carbon nanotubes, wherein a carbon nanotube film is prepared on the surface of the bottom gate dielectric layer 400 by static deposition or dip-coating, and annealing can be performed after deposition.

[0053] like Figure 10 As shown, a barrier layer 600 is formed on the channel layer 500. The barrier layer 600 can be deposited on the surface of the channel layer 500. Its purpose is to prevent impurities, physical damage or chemical erosion from affecting the channel carrier transport performance and gate dielectric insulation characteristics of the channel layer 500 and the underlying bottom gate dielectric layer 400 in the channel region, thereby ensuring the stability of the device's electrical function.

[0054] The barrier layer 600 can be composed of an alumina (Al2O3) film or a combination of an alumina (Al2O3) film and a silicon nitride (SiN) film. The alumina film can be deposited using atomic layer deposition (ALD) to coat the channel layer 500, while the silicon nitride film can be prepared using plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0055] Then, the active region is defined on the surface of the barrier layer 600 through photolithography and development processes. A layered dry etching process is then performed to etch away portions of the barrier layer 600, channel layer 500, and bottom gate dielectric layer 400. For example, ICP (Inductively Coupled Plasma) can be used to implement layered etching. For instance, etching gases suitable for the barrier layer material can be selected to etch the barrier layer; etching gases suitable for the channel layer material can be selected to etch the channel layer; and etching gases suitable for the bottom gate dielectric layer material can be selected to etch the bottom gate dielectric layer. The etching process finally stops at the isolation passivation layer 200. Afterwards, residual photoresist is removed and the device surface is cleaned. At this point, a structure resembling... Figure 11 The structure shown.

[0056] A protective layer 700 is deposited, which can cover the surface of the barrier layer 600, the exposed isolation passivation layer 200, the exposed source conductive channel, and the exposed drain conductive channel. The material of the protective layer 700 can be silicon dioxide or silicon nitride, etc. At this time, a structure is formed... Figure 12 The structure shown.

[0057] CMP planarization is performed, which removes the upper protective layer and a portion of the barrier layer 600. This forms a structure as shown... Figure 13 The structure is shown. In one example, the barrier layer 600 is formed of an aluminum oxide layer and a silicon nitride layer located on top of the aluminum oxide layer, in which case planarization can be performed up to the middle of the silicon nitride layer.

[0058] Then, the source and drain regions (source and drain contact holes) are defined through photolithography and development processes. Next, the protective layer is etched using an ICP process with a suitable etching gas for the protective layer material, employing a dry etching process, stopping at the isolation passivation layer 200. As an example, in the case where the barrier layer 600 is formed of an aluminum oxide layer and a silicon nitride layer above the aluminum oxide layer, the channel layer is protected. For example, an ICP process can be used, selecting a gas suitable for etching silicon nitride to etch the silicon nitride layer of the barrier layer 600, where the etching stops at the aluminum oxide layer. This forms a structure as shown below. Figure 14 The structure is shown. The aluminum oxide layer of the barrier layer 600 is then removed by wet etching. During the wet etching process, for example, a TMAH (tetramethylammonium hydroxide) solution is selected to remove the aluminum oxide. This continues until a portion of the channel layer 500 is exposed. This forms a structure as shown. Figure 15 The structure shown is followed by etching, cleaning, and drying.

[0059] A functional layer 810 of predetermined thickness is deposited. The functional layer 810 is formed on... Figure 15The top and side surfaces of the structure are shown. The work function of the material of functional layer 810 needs to be compatible with that of the channel layer to form a low-resistance ohmic contact. When the channel layer 500 is made of carbon nanotubes, palladium (Pd) can be chosen as the material for functional layer 810 for P-type devices, and scandium (Sc) can be chosen for N-type devices. When palladium is used as the functional layer material, PVD deposition can be employed; when scandium is used as the functional layer material, PVD deposition can also be employed. This results in a structure as shown... Figure 16 The structure shown.

[0060] A conductive material is deposited, wherein the height of the conductive material 820 is greater than the height of the functional layer 810, and the conductive material fills the source and drain contact holes. This forms a structure as follows: Figure 17 The structure shown. For Figure 17 The structure undergoes CMP planarization, with the planarization stopping at the 600mm barrier layer or partially submerging the barrier layer. This results in a structure like... Figure 18 The structure shown. In Figure 18 In the structure shown, the functional layer 810 in the source contact hole serves as the source contact layer 811, and the conductive material 820 in the source contact hole serves as the source electrode layer 821; the functional layer 810 in the drain contact hole serves as the drain contact layer 812, and the conductive material 820 in the drain contact hole serves as the drain electrode layer 822. The source contact layer 811 is electrically connected to the source conductive channel 320 and is in direct contact with the channel layer 500. The source contact layer 811 has a hollow space, which is filled with the conductive material serving as the source electrode layer 821. The drain contact layer 812 has a hollow space, which is filled with the conductive material serving as the drain electrode layer 822.

[0061] exist Figure 18 An insulating layer 710 is deposited on the surface of the structure shown. The material of the insulating layer 710 can be the same as the material of the protective layer 700 mentioned earlier. The insulating layer 710 can be deposited using processes such as PECVD to form insulation protection for the source and drain electrodes, preventing electrical short circuits, etc. At this time, an insulating layer 710 is formed as shown. Figure 19 The structure shown.

[0062] The top gate region is positioned on the insulating layer 710 using photolithography and development processes. Then, the insulating layer 710 and the barrier layer 600 are etched using dry etching. During the etching process, a layered etching method is employed. First, an etching gas suitable for the insulating layer material is selected for etching, stopping at the silicon nitride layer of the barrier layer; then, an etching gas suitable for silicon nitride is selected for etching the silicon nitride layer, stopping at the aluminum oxide layer of the barrier layer. This forms a layer as shown in the image. Figure 20The structure shown is followed by photoresist removal and cleaning. Then, the aluminum oxide layer of the barrier layer 600 is removed by wet etching. During the wet etching process, for example, a TMAH (tetramethylammonium hydroxide) solution is selected to remove the aluminum oxide. This continues until the channel layer 500 of the top gate region is exposed. At this point, a structure like the one shown is formed. Figure 21 The structure shown.

[0063] Then Figure 21 The structure shown has a top gate dielectric layer 910 deposited on its surface. The material of the top gate dielectric layer 910 can be a high-k dielectric material, such as alumina or hafnium dioxide. The deposition process can be an ALD process. This forms a structure as shown... Figure 22 The structure shown.

[0064] A photosensitive layer will now be formed on the top gate dielectric layer 910. The photosensitive layer described below can be a pn junction structure or a pin junction structure. For example, in the case of a pin junction structure, it can include the carrier transport layer (n-type layer) and quantum dot layers (i-type layer and p-type layer) described below. Alternatively, other photosensitive layer structures can also be used.

[0065] Photolithography and development are performed, and a carrier transport layer 920 is deposited. PVD (Photopolymerization) can be used to deposit the carrier transport layer 920, with a photoresist mask serving as a shadow mask for the PVD process. The material of the carrier transport layer can be selected based on the specific material of the photovoltaic pn junction, for example, zinc oxide (ZnO) or tin dioxide (SnO2) (n-type layer). At this point, a structure is formed... Figure 23 The structure shown.

[0066] The carrier transport layer 920 is peeled off using a lift-off process, which preserves the carrier transport layer 920 above the channel layer in the top gate region, forming a structure as follows: Figure 24 The structure shown.

[0067] After that Figure 24 A quantum dot layer 930 is prepared on the surface of the structure shown, forming a structure as follows: Figure 25 As shown. As an example, a lead sulfide (PdS) ​​quantum dot layer and an ethylenedithiol-modified lead sulfide (PdS-edt) quantum dot layer are used as the i-type and p-type layers of a pin junction, respectively. Of course, those skilled in the art will understand that the quantum dot layer can be selected based on the specific materials of the heterojunction structure of the photovoltaic effect.

[0068] In addition, Figure 26 The diagram shows a top view of a monolithic three-dimensional integrated photodetector according to this disclosure. Figure 26As shown, multiple detection units 1000 are formed in the readout integrated circuit 100. The detection units 1000 can detect light. Taking infrared light as an example, when the photosensitive material of the quantum dot layer absorbs photon energy, it excites the generation of charge carriers (electron-hole pairs), thereby realizing the conversion of light signals into charge carrier signals. The quantum dot layer and the charge carrier transport layer form a pn junction structure. The top and bottom gate electric fields work together to separate electron-hole pairs and accelerate the transport of charge carriers to the source and drain electrodes, thus forming a weak current signal. This current signal is transmitted to the readout integrated circuit below, which amplifies, filters, and digitizes the current signal, outputting a detection signal, thereby completing the detection of infrared light.

[0069] According to further embodiments of this disclosure, a monolithic three-dimensional integrated photodetector is also provided. Reference will be made below. Figure 25 A detailed explanation follows. The readout integrated circuit 100 serves as the substrate for the entire integrated photodetector. The detection units mentioned below are fabricated on top of the readout integrated circuit 100. The photodetector can include multiple detection units, for example, forming a 32×32 detection array. Figure 25 In the image, only one detection unit is shown; the remaining detection units also use the same structure.

[0070] The detection unit includes a source and a drain. The source includes a source contact layer 811 and a source electrode layer 821, which form a stacked structure. The source contact layer 811 has a hollow space, and the source electrode layer 821 is formed in the hollow space. The source contact layer 811 is in direct contact with the underlying source conductive channel 320, and also in contact with the channel layer 500. The source contact layer 811 can cover the upper and side surfaces of one end of the channel, forming a stepped structure. The source conductive channel 320 is formed by conductive material in a source conductive via formed in the isolation passivation layer 200. The source conductive channel 320 realizes the electrical connection between the source and the readout integrated circuit. The drain includes a drain contact layer 812 and a drain electrode layer 822, which form a stacked structure. The drain contact layer 812 has a hollow space, and the drain electrode layer 822 is formed in this hollow space. The drain contact layer 812 is in direct contact with the drain conductive channel 330 below, and the drain contact layer 812 is also in contact with the channel layer 500. The drain contact layer 812 can cover the upper surface and side surface of one end of the channel, forming a stepped structure. The drain conductive channel 330 is formed of conductive material in the drain conductive via formed in the isolation passivation layer 200. The drain conductive channel 330 realizes the electrical connection between the drain and the readout integrated circuit.

[0071] The detection unit also includes a channel layer 500, which serves as a carrier transport channel between the source and drain. A bottom gate structure is formed beneath the channel layer. The bottom gate structure includes a bottom gate dielectric layer 400 and a bottom gate electrode layer 310. The bottom gate dielectric layer 400 contacts the channel layer 500 and is located between the channel layer 500 and the bottom gate electrode layer 310. The bottom gate electrode layer 310 is formed of conductive material in a bottom gate contact hole formed in the isolation passivation layer 200, wherein the conductive material can be the same as the conductive material of the source conductive channel 320 and the drain conductive channel 330. The bottom gate electrode layer 310 can be electrically connected to a readout integrated circuit. In this application, the bottom gate electrode layer 310, the source conductive channel 320, and the drain conductive channel 330 are separated by the material of the isolation passivation layer 200, thereby achieving electrical insulation.

[0072] The detection unit also includes a top gate structure. The top gate structure includes a top gate dielectric layer 910 and a photosensitive layer. The photosensitive layer may include the aforementioned carrier transport layer 920 and quantum dot layer 930. The photosensitive layer can be selected with appropriate structures or materials depending on the actual application, and is not limited in this application. For example, the materials of the aforementioned carrier transport layer 920 and quantum dot layer 930 can be used for infrared detection. The top gate dielectric layer 910 is located above the channel layer 500, and the photosensitive layer is located above the top gate dielectric layer 910. In this application, the photosensitive layer is not only formed in the top gate contact hole, but can also extend to the upper surface region of the detection unit, thus increasing the detection area, such as... Figure 25 As shown. When the photosensitive layer extends to the upper surface of the detection unit, an insulating layer 710 may also be included. The insulating layer 710 covers the source and drain. Furthermore, during the formation of the top-gate dielectric layer 910, the top-gate dielectric layer 910 is also deposited on the insulating layer 710; that is, the top-gate dielectric layer 910 is not only deposited on the top and sidewalls of the top-gate contact hole, but also deposited and retained on the insulating layer 710. In other words, an insulating layer, a top-gate dielectric layer, and a portion of the photosensitive layer are sequentially disposed on the drain, and an insulating layer, a top-gate dielectric layer, and a portion of the photosensitive layer are sequentially disposed on the source.

[0073] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0074] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0075] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A method for fabricating a monolithic three-dimensional integrated photodetector, characterized in that, include: An electrically isolated passivation material is deposited on the readout integrated circuit, which serves as the substrate of the photodetector, to form an isolation passivation layer; Source conductive vias, drain conductive vias, and bottom gate contact vias are formed in the isolation passivation layer; A conductive material is deposited and planarized, wherein the conductive material is filled in the source conductive via, the drain conductive via, and the bottom gate contact via. The conductive material filled in the source conductive via forms a source conductive channel, the conductive material filled in the drain conductive via forms a drain conductive channel, and the conductive material filled in the bottom gate contact via forms a bottom gate electrode layer. A bottom gate dielectric layer is formed on the planarized surface, and a channel layer is formed on the bottom gate dielectric layer; A source and a drain are formed, wherein the source and the drain are electrically connected to the connection port of the readout integrated circuit through the source conductive channel and the drain conductive channel, respectively; and A top gate structure is formed, wherein the top gate structure includes a top gate dielectric layer and a photosensitive layer.

2. The method as described in claim 1, characterized in that, During the deposition of conductive material in the conductive vias and bottom gate contact holes, the same conductive material is deposited simultaneously in the source conductive vias, drain conductive vias, and bottom gate contact holes.

3. The method as described in claim 1, characterized in that, After the channel layer is formed, a barrier layer is deposited on the channel layer, and the barrier layer, channel layer and bottom gate dielectric layer outside the active region are etched away.

4. The method as described in claim 3, characterized in that, After etching away the barrier layer, channel layer, and bottom gate dielectric layer outside the active region, the process also includes: A protective layer is deposited, wherein the protective layer covers the barrier layer, the isolation passivation layer, the source conductive channel, and the drain conductive channel; The protective layer is etched to form source contact holes and drain contact holes, wherein the source contact holes terminate at the source conductive channel and the drain contact holes terminate at the drain conductive channel.

5. The method as described in claim 4, characterized in that, During the formation of the source and drain electrodes, contact layer material is deposited simultaneously in the source contact hole and the drain contact hole to form the source contact layer and the drain contact layer. Then, electrode layer material is deposited simultaneously to form the source electrode layer and the drain electrode layer. The source contact layer directly contacts the channel layer and the source conductive channel, and the drain contact layer directly contacts the channel layer and the drain conductive channel.

6. The method as described in claim 5, characterized in that, After forming the source electrode layer and the drain electrode layer, the process also includes: An insulating layer is deposited on the surface; The insulating layer and barrier layer of the top gate region are etched, stopping at the channel layer to form a top gate contact hole.

7. The method as described in claim 6, characterized in that, The barrier layer includes a silicon nitride layer and an aluminum oxide layer located between the silicon nitride layer and the channel layer. During the etching process of the barrier layer, the silicon nitride layer is removed by dry etching and the aluminum oxide layer is removed by wet etching.

8. The method as described in claim 6, characterized in that, The process of forming the top grid structure includes: At least a top gate dielectric layer is deposited in the top gate contact hole; and A photosensitive layer is deposited at least on top of the top gate dielectric layer.

9. A monolithic three-dimensional integrated photodetector, characterized in that, A readout integrated circuit, which serves as a substrate; as well as Detection units, wherein there are multiple detection units. Each detection unit includes: The source and drain are electrically connected to the connection port of the readout integrated circuit through source conductive channels and drain conductive channels, respectively. The source conductive channels and drain conductive channels are formed by conductive material deposited in conductive vias. The conductive vias are formed by depositing an isolation passivation material layer on the surface of the readout integrated circuit and etching the isolation passivation material layer. The channel layer serves as a carrier transport channel between the source and drain. A bottom gate structure is formed beneath the channel layer and includes a bottom gate dielectric layer and a bottom gate electrode layer, wherein the bottom gate dielectric layer is located between the channel layer and the bottom gate electrode layer, and the bottom gate electrode layer is formed by etching the isolation passivation material layer and depositing a bottom gate electrode material; A top-gate structure is formed on the channel layer and includes a top-gate dielectric layer and a photosensitive layer, wherein the top-gate dielectric layer is located between the channel layer and the photosensitive layer.

10. The monolithic three-dimensional integrated photodetector as described in claim 9, characterized in that, An insulating layer, a top gate dielectric layer, and a portion of a photosensitive layer are sequentially disposed on the drain electrode, and an insulating layer, a top gate dielectric layer, and a portion of a photosensitive layer are sequentially disposed on the source electrode.

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