Passivation method of TOPCon battery

Abstract

The invention relates to the technical field of solar cells, and provides a passivation method of a TOPCon cell. The invention discloses a passivation method of a TOPCon battery. The passivation method comprises the following steps: S1, depositing a tunneling oxide layer on a silicon wafer of which the back surface is polished; s2, forming a first poly layer on the tunneling oxide layer; s3, forming a first oxide layer on the first poly layer; s4, forming a second poly layer on the first oxide layer; s5, forming a second oxide layer on the second poly layer; s6, forming a third poly layer on the second oxide layer; wherein the treatment time of the first poly layer ranges from 80 s to 100 s, and the flow rate of phosphorane ranges from 300 sccm / s to 320 sccm / s. The passivation method has the effect that the tunneling oxide layer is not easily damaged by the silver paste in the metallization process.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more specifically, to a passivation method for TOPCon cells. Background Technology

[0002] TOPCon cells (Tunnel Oxide Passivating Contacts), especially N-type TOPCon cells, have a lower boron content in phosphorus-doped N-type crystalline silicon compared to P-type PERC cells (Passivated Emitter Rear Cells), resulting in better passivation.

[0003] Currently, the doped polycrystalline silicon layer for TOPCon solar cells mainly uses LPCVD (Low-Pressure Chemical Vapor Deposition) technology. This involves combining LPCVD to prepare a polycrystalline silicon film with a traditional full diffusion process. LPCVD deposits a polycrystalline silicon thin film, followed by phosphorus diffusion. LPCVD primarily grows i-polySi by high-temperature decomposition of silane, followed by a polycrystalline silicon doping step. PECVD, on the other hand, can achieve integrated processing of silicon oxide, amorphous silicon, and doping. Specifically, it uses LPCVD thermal oxidation to deposit a tunneling oxide layer, followed by PECVD in-situ doping to prepare a Poly-Si layer, forming the back passivation layer.

[0004] Thin poly passivation is a key direction for improving the efficiency of Topcon solar cells. Compared to thick poly layers, thin poly layers have lower parasitic absorption and better optical response, which is beneficial for increasing the current of Topcon solar cells and thus improving conversion efficiency. The industry has begun to reduce the thickness of the poly layer to reduce its parasitic absorption and improve its conversion efficiency. Currently, most Topcon solar cells use PECVD / LPCVD methods to deposit the poly layer on the back side, and achieve good passivation through annealing / phosphorus diffusion. Combined with silver paste, it can also form a very beneficial ohmic contact. With the increasing maturity of Topcon technology, it is possible to thin the poly layer on the back side. Thinning the poly layer can greatly shorten the time required for cell production and significantly reduce the cost of production materials.

[0005] However, when using thin poly technology, the silver paste can easily damage the tunneling oxide layer during the metallization process, affecting the passivation performance and resulting in a higher saturation current density (J0). Therefore, a passivation technology suitable for thin poly is needed to compensate for this defect. Summary of the Invention

[0006] The purpose of this invention is to provide a passivation method for TOPCon batteries, which has the effect that the silver paste does not easily damage the tunnel oxide layer during the metallization process.

[0007] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0008] This invention provides a passivation method for TOPCon batteries, comprising the following steps:

[0009] S1. Deposit a tunnel oxide layer on the back-side polished silicon wafer;

[0010] S2. Then, the first poly layer is formed on the tunneling oxide layer;

[0011] S3. A first oxide layer is formed on the first poly layer;

[0012] S4. A second poly layer is formed on the first oxide layer;

[0013] S5. A second oxide layer is formed on the second poly layer;

[0014] S6. A third poly layer is formed on the second oxide layer;

[0015] The processing time for the first poly layer is 80s-100s, and the phosphine flow rate is 300sccm / s-320sccm / s.

[0016] In some embodiments of the present invention, the thickness of the tunneling oxide layer is 1-2 nm, the thickness of the first poly layer is 9 nm-11 nm, the thickness of the first oxide layer is 0.3 nm-0.5 nm, the thickness of the second poly layer is 25 nm-35 nm, the thickness of the second oxide layer is 0.5 nm-0.7 nm, and the thickness of the third poly layer is 40 nm-60 nm.

[0017] In some embodiments of the present invention, the tunneling oxide layer treatment time is 70-80s, the tunneling oxide layer deposition temperature is 425℃-435℃, the deposition pressure is 1800mtorr-2000mtorr, the deposition power is 14000w-15000w, and the duty cycle is 20 / 2000.

[0018] In some embodiments of the present invention, the deposition temperature of the first poly layer is 425-435℃, the deposition pressure is 3200mtorr-3400mtorr, the power supply is 14500w-15000w, the duty cycle is 60 / 600, silane, phosphine and hydrogen are introduced during deposition, and the deposition time is 80s-100s.

[0019] In some embodiments of the present invention, the processing time of the first oxide layer is 18s-23s, the deposition temperature is 425℃-435℃, the deposition pressure is 1800mtorr-2000mtorr, the power supply is 14500w-15000w, and the duty cycle is 20 / 2000.

[0020] In some embodiments of the present invention, the deposition temperature of the second poly layer is 425℃-435℃, the deposition pressure is 3200mtorr-3400mtorr, silane, phosphine and hydrogen are introduced during deposition, the power supply is 14500w-15000w, the duty cycle is 40 / 450, and the deposition time is 180s-200s.

[0021] In some embodiments of the present invention, the deposition temperature of the second oxide layer is 425-435℃, the deposition pressure is 1800mtorr-2000mtorr, the power supply is 14500w-15000w, the duty cycle is 20 / 2000, and the deposition time is 28s-33s.

[0022] In some embodiments of the present invention, the deposition temperature of the third poly layer is 425-435°C, the deposition pressure is 3200-3400 mtorr, silane, phosphine and hydrogen are introduced during deposition, the power supply is 14500w-15000w, the duty cycle is 40 / 400, and the deposition time is 280s-320s.

[0023] In some embodiments of the present invention, the above also includes step S7, annealing the silicon wafer after depositing the third oxide layer.

[0024] In some embodiments of the present invention, the annealing temperature is 910℃-925℃, the pressure is 800Pa-900Pa, nitrogen gas is introduced at 3000sccm / s-4500sccm / s during annealing, and the annealing time is 1800s-2000s.

[0025] Compared with the prior art, the present invention has at least the following advantages or beneficial effects:

[0026] This invention, by adding an oxide layer between poly layers, effectively controls the silver paste etching rate while reducing the total thickness of the poly layers. Based on the original thin poly layer, the silver paste etching rate can be better controlled, avoiding damage to the tunneling oxide layer by the silver paste, preserving better passivation performance, reducing fill factor loss, and significantly improving conversion efficiency. Furthermore, passivation data shows that this invention has excellent passivation effect, achieving a high minority carrier lifetime, low saturation current density, and a high fill factor. With the increase or decrease of poly layers, other passivation data show a deterioration trend, indicating that the three-layer poly + multi-layer oxide structure can achieve good passivation performance. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0028] In the picture:

[0029] Figure 1 This is a diagram of the silicon wafer layer structure after passivation treatment in Embodiment 1 of the present invention;

[0030] Figure 2 This is a diagram of the silicon wafer layer structure after passivation treatment in Comparative Example 1 of the present invention;

[0031] Figure 3 This is a comparison chart of minority carrier lifetimes for Embodiment 2 and Comparative Examples 1-3 of the present invention;

[0032] Figure 4 This is a comparison diagram of the open-circuit voltage of Embodiment 2 and Comparative Examples 1-3 of the present invention;

[0033] Figure 5 This is a comparison diagram of the saturation current density of Embodiment 2 and Comparative Examples 1-3 of the present invention;

[0034] Figure 6 This is a comparison chart of the fill factor of Embodiment 2 and Comparative Examples 1-3 of the present invention;

[0035] Figure 7 This is a product diagram of Comparative Example 4 of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to specific embodiments.

[0038] This invention provides a passivation method for TOPCon batteries, comprising the following steps:

[0039] S1. Deposit a tunnel oxide layer on the back-side polished silicon wafer;

[0040] S2. Then, the first poly layer is formed on the tunneling oxide layer;

[0041] S3. A first oxide layer is formed on the first poly layer;

[0042] S4. A second poly layer is formed on the first oxide layer;

[0043] S5. A second oxide layer is formed on the second poly layer;

[0044] S6. A third poly layer is formed on the second oxide layer;

[0045] The processing time for the first poly layer is 80s-100s, and the phosphine flow rate is 300sccm / s-320sccm / s.

[0046] This invention adds an oxide layer between poly layers, which reduces the total thickness of the poly layer while effectively controlling the silver paste etching rate. Based on the original thin poly layer, the silver paste etching rate can be better controlled, avoiding damage to the tunneling oxide layer by the silver paste, preserving better passivation performance, reducing the loss of filler factor, and greatly improving conversion efficiency.

[0047] In some embodiments of the present invention, the thickness of the tunneling oxide layer is 1nm-2nm, the thickness of the first poly layer is 9nm-11nm, the thickness of the first oxide layer is 0.3nm-0.5nm, the thickness of the second poly layer is 25nm-35nm, the thickness of the second oxide layer is 0.5nm-0.7nm, and the thickness of the third poly layer is 40nm-60nm.

[0048] Based on the aforementioned thickness, the total thickness of the poly layer is between 74-106 nm, preferably 100 nm. This invention improves poly transmittance by reducing the poly layer thickness, resulting in better optical response, lower parasitic absorption, and higher short-circuit current, thus achieving high conversion efficiency. Furthermore, the inventors' research has revealed that when the poly layer thickness is below 70 nm, the thinner poly layer cannot provide sufficient doping atoms, thereby increasing contact resistivity. This leads to greater resistance for charge carriers passing through the poly layer, affecting the battery's current transport efficiency and overall battery efficiency. Conversely, when the poly layer thickness exceeds 130 nm, the poly layer exhibits poor transmittance, poor optical response, and even worse parasitic absorption and short-circuit current.

[0049] Controlling the oxide layer thickness can effectively reduce the slurry etching rate. Experimental results show that an excessively thick oxide layer can lead to a weakening or even failure of the tunneling effect, resulting in severe EL defects and seriously affecting the conversion efficiency.

[0050] In some embodiments of the present invention, the tunneling oxide layer treatment time is 70-80s, the tunneling oxide layer deposition temperature is 425℃-435℃, the deposition pressure is 1800mtorr-2000mtorr, the deposition power is 14000w-15000w, and the duty cycle is 20 / 2000.

[0051] Preferably, nitrous oxide is introduced during the deposition of the tunnel oxide layer, with a nitrous oxide flow rate of 10000 sccm / s-12000 sccm / s.

[0052] In some embodiments of the present invention, the deposition temperature of the first poly layer is 425℃-435℃, the deposition pressure is 3200mtorr-3400mtorr, the power supply is 14500w-15000w, the duty cycle is 60 / 600, silane, phosphine and hydrogen are introduced during deposition, and the deposition time is 80s-100s.

[0053] Preferably, the flow rate of silane during the deposition of the first poly layer is 3000 sccm / s-3300 sccm / s, the flow rate of phosphine is 300 sccm / s-320 sccm / s, and the flow rate of hydrogen is 10000 sccm / s-12000 sccm / s.

[0054] In some embodiments of the present invention, the processing time of the first oxide layer is 18s-23s, the deposition temperature is 425℃-435℃, the deposition pressure is 1800mtorr-2000mtorr, the power supply is 14500-15000w, and the duty cycle is 20 / 2000.

[0055] Preferably, nitrous oxide is introduced during the first oxide layer treatment, with a flow rate of 10000 sccm / s to 12000 sccm / s.

[0056] In some embodiments of the present invention, the deposition temperature of the second poly layer is 425℃-435℃, the deposition pressure is 3200mtorr-3400mtorr, silane, phosphine and hydrogen are introduced during deposition, the power supply is 14500w-15000w, the duty cycle is 40 / 450, and the deposition time is 180s-200s.

[0057] Preferably, during the deposition of the second poly layer, the silane flow rate is 3000 sccm / s-3300 sccm / s, the phosphine flow rate is 630 sccm / s-670 sccm / s, and the hydrogen flow rate is 10000 sccm / s-12000 sccm / s.

[0058] In some embodiments of the present invention, the deposition temperature of the second oxide layer is 425-435℃, the deposition pressure is 1800mtorr-2000mtorr, the power supply is 14500w-15000w, the duty cycle is 20 / 2000, and the deposition time is 28s-33s.

[0059] Preferably, the nitric oxide flow rate during the deposition of the second oxide layer is 10,000-12,000 sccm / s.

[0060] In some embodiments of the present invention, the deposition temperature of the third poly layer is 425-435°C, the deposition pressure is 3200 mtorr-3400 mtorr, silane, phosphine and hydrogen are introduced during deposition, the power supply is 14500w-15000w, the duty cycle is 40 / 400, and the deposition time is 280s-320s.

[0061] Preferably, during the deposition of the third poly layer, the silane flow rate is 3000 sccm / s-3300 sccm / s, the phosphine flow rate is 820 sccm / s-840 sccm / s, and the hydrogen flow rate is 10000 sccm / s-12000 sccm / s.

[0062] In some embodiments of the present invention, the above also includes step S7, annealing the silicon wafer after depositing the third oxide layer.

[0063] In some embodiments of the present invention, the annealing temperature is 910℃-925℃, the pressure is 800Pa-900Pa, nitrogen gas is introduced at 3000sccm / s-4500sccm / s during annealing to maintain the furnace tube pressure, and the annealing time is 1800s-2000s.

[0064] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0065] Example 1

[0066] A passivation method for TOPCon batteries includes the following steps:

[0067] S1. The back-polished silicon wafer is deposited for 70 seconds under the conditions of temperature 425℃, pressure 800mtorr, power supply 14000w, and duty cycle 20 / 2000. During the deposition, the nitrous oxide flow rate is maintained at 10000sccm / s to obtain a tunneling oxide layer with a thickness of 1-2nm.

[0068] S2. Then, under the conditions of temperature 425℃, pressure 3200mtorr, power supply 14500w, silane flow rate 3000sccm / s, hydrogen flow rate 10000sccm / s, and phosphine flow rate 300sccm / s, the tunneling oxide layer is treated for 80s to form a first poly layer with a thickness of 9-11nm.

[0069] S3. The first poly layer is treated for 18 seconds at a temperature of 425℃, a pressure of 1800 mtorr, a power of 14500 W, a duty cycle of 20 / 2000, and a nitrous oxide flow rate of 10000 sccm / s to form a first oxide layer with a thickness of 0.3-0.5 nm.

[0070] S4. Under the conditions of temperature 425℃, pressure 3200mtorr, power supply 14500w, duty cycle 40 / 450, silane flow rate 3000sccm / s, hydrogen flow rate 10000sccm / s, and phosphine flow rate 630sccm / s, the first oxide layer is treated for 180s to form a second poly layer with a thickness of 25-35nm.

[0071] S5. The second poly layer is treated for 28-33 seconds at a temperature of 425-435℃, a pressure of 1800-2000 mtorr, a power of 14500-15000 W, a duty cycle of 20 / 2000, and a nitric oxide flow rate of 10000-12000 sccm / s to form a second oxide layer with a thickness of 0.5-0.7 nm.

[0072] S6. Under the conditions of temperature 425℃, pressure 3200mtorr, power supply 14500w, duty cycle 40 / 400, silane flow rate 3000sccm / s, hydrogen flow rate 10000sccm / s, and phosphine flow rate 820sccm / s, the second oxide layer is treated for 280s to form a third poly layer with a thickness of 40-60nm.

[0073] S7. Anneal the silicon wafer for 1800s at a temperature of 910℃, a pressure of 800Pa, and a nitrogen flow rate of 3000sccm / s.

[0074] Structural reference Figure 1 .

[0075] Example 2

[0076] A passivation method for TOPCon batteries includes the following steps:

[0077] S1. The back-polished silicon wafer is deposited for 75s under the conditions of temperature 430℃, pressure 1200mtorr, power supply 14500w, and duty cycle 20 / 2000. During the deposition, the nitrous oxide flow rate is maintained at 11000sccm / s to obtain a tunneling oxide layer with a thickness of 1-2nm.

[0078] S2. Then, under the conditions of temperature 430℃, pressure 3300mtorr, power supply 14800w, silane flow rate 3200sccm / s, hydrogen flow rate 11000sccm / s, and phosphine flow rate 310sccm / s, the tunneling oxide layer is treated for 90s to form a first poly layer with a thickness of 9-11nm.

[0079] S3. The first poly layer is treated for 20 seconds at a temperature of 430℃, a pressure of 1900 mtorr, a power of 14800 W, a duty cycle of 20 / 2000, and a nitrous oxide flow rate of 11000 sccm / s to form a first oxide layer with a thickness of 0.3-0.5 nm.

[0080] S4. Under the conditions of temperature 430℃, pressure 3300mtorr, power supply 14800w, duty cycle 40 / 450, silane flow rate 3200sccm / s, hydrogen flow rate 11000sccm / s, and phosphine flow rate 650sccm / s, the first oxide layer is treated for 190s to form a second poly layer with a thickness of 25-35nm.

[0081] S5. The second poly layer is treated for 30 seconds at a temperature of 425-435℃, a pressure of 1900 mtorr, a power of 14800 W, a duty cycle of 20 / 2000, and a nitric oxide flow rate of 11000 sccm / s to form a second oxide layer with a thickness of 0.5-0.7 nm.

[0082] S6. Under the conditions of temperature 430℃, pressure 3300mtorr, power supply 14800w, duty cycle 40 / 400, silane flow rate 3200sccm / s, hydrogen flow rate 11000sccm / s, and phosphine flow rate 830sccm / s, the second oxide layer is treated for 300s to form a third poly layer with a thickness of 40-60nm.

[0083] S7. Anneal the silicon wafer for 1900s at a temperature of 920℃, a pressure of 850Pa, and a nitrogen flow rate of 4000sccm / s.

[0084] Example 3

[0085] A passivation method for TOPCon batteries includes the following steps:

[0086] S1. The back-polished silicon wafer is deposited for 80s under the conditions of temperature 435℃, pressure 2000mtorr, power supply 15000w, and duty cycle 20 / 2000. During the deposition, the nitrous oxide flow rate is maintained at 12000sccm / s to obtain a tunneling oxide layer with a thickness of 2nm.

[0087] S2. Then, under the conditions of temperature 435℃, pressure 3400mtorr, power supply 15000w, silane flow rate 3300sccm / s, hydrogen flow rate 12000sccm / s, and phosphine flow rate 320sccm / s, the tunneling oxide layer is treated for 100s to form a first poly layer with a thickness of 9-11nm.

[0088] S3. The first poly layer is treated for 23 seconds at a temperature of 435℃, a pressure of 2000 mtorr, a power of 15000 W, a duty cycle of 20 / 2000, and a nitrous oxide flow rate of 12000 sccm / s to form a first oxide layer with a thickness of 0.3-0.5 nm.

[0089] S4. Under the conditions of temperature 435℃, pressure 3400mtorr, power supply 15000w, duty cycle 40 / 450, silane flow rate 3300sccm / s, hydrogen flow rate 12000sccm / s, and phosphine flow rate 670sccm / s, the first oxide layer is treated for 200s to form a second poly layer with a thickness of 25-35nm.

[0090] S5. The second poly layer is treated for 33 seconds at a temperature of 435℃, a pressure of 2000 mtorr, a power of 15000 W, a duty cycle of 20 / 2000, and a nitric oxide flow rate of 12000 sccm / s to form a second oxide layer with a thickness of 0.5-0.7 nm.

[0091] S6. Under the conditions of temperature 435℃, pressure 3400mtorr, power supply 15000w, duty cycle 40 / 400, silane flow rate 3300sccm / s, hydrogen flow rate 12000sccm / s, and phosphine flow rate 840sccm / s, the second oxide layer is treated for 320s to form a third poly layer with a thickness of 40-60nm.

[0092] S7. Anneal the silicon wafer for 2000s at a temperature of 925℃, a pressure of 900Pa, and a nitrogen flow rate of 4500sccm / s.

[0093] Comparative Example 1

[0094] This comparative example is basically the same as Example 2, except that no oxide layer was added, and the layer structure is, in sequence, a tunneling oxide layer, a first poly layer, a second poly layer and a third poly layer.

[0095] Structural reference Figure 2 .

[0096] Comparative Example 2

[0097] This comparative example is basically the same as Example 2, except that the layer structure is, in sequence, a tunneling oxide layer, a first poly layer, a first oxide layer, and a second poly layer.

[0098] Comparative Example 3

[0099] This comparative example is basically the same as Example 2, except that the layer structure is as follows: tunneling oxide layer, first poly layer, first oxide layer, second poly layer, second oxide layer, third poly layer, third oxide layer and fourth poly layer.

[0100] Comparative Example 4

[0101] This comparative example is basically the same as Example 2, except that the thickness of the first oxide layer is 1.2 nm and the thickness of the second oxide layer is 1.2 nm.

[0102] The results are as follows Figure 7 As shown. Observation Figure 7 It is known that excessive oxide layer thickness leads to weakened or even failed tunneling effect, resulting in severe EL defects, which will seriously affect conversion efficiency.

[0103] The passivated silicon wafers of Examples 2 and 1-3 were subjected to the same treatment, including annealing, removal of the front-side plating, front-side alumina thickness of 3-5 nm at 220°C, front-side silicon nitride thickness of 75-80 nm at 480°C, and back-side silicon nitride thickness of 80-85 nm at 510°C. Finally, metallization was performed to obtain TOPCon cells. The cells were tested for electrical performance, and the results are shown in Table 1 and 2. Figure 3-6 As shown.

[0104] Table 1

[0105]

[0106]

[0107] As can be seen from Table 1, Example 2 has the best overall performance.

[0108] Reference Figures 3-6 In the figure, L represents Example 2, L1 represents Comparative Example 1, L2 represents Comparative Example 2, and L3 represents Comparative Example 3.

[0109] according to Figure 3 Minority carrier lifetime (µs) is an important parameter of solar cell performance. The left axis represents the minority carrier lifetime value. Figure 3 The minority carrier lifetime of Example 2 is the highest, around 2500. Since the length of the minority carrier lifetime directly affects the photoelectric conversion efficiency of the battery, it can be concluded that Example 2 has the best photoelectric conversion efficiency.

[0110] Figure 4 The left coordinate represents the open-circuit voltage value, according to Figure 4 As can be seen from the open-circuit voltages in Table 1, Example 2 has the highest open-circuit voltage.

[0111] according to Figure 5 The left-hand axis represents the saturation current density value, and the saturation current density (A / cm²) of Example 2 is shown. 2 The average is the lowest. According to common knowledge, the lower the saturation current density, the lower the recombination rate of the PN junction and the lower the leakage current of the battery in the dark state. This is beneficial to improving the open circuit voltage (Voc) and photoelectric conversion efficiency of the solar cell. This shows that the photoelectric conversion efficiency of Example 2 is the best.

[0112] according to Figure 6 As shown in Table 1, Example 2 has the highest fill factor, which reflects the efficiency with which the battery converts light energy into electrical energy. Therefore, Example 2 has the best photoelectric conversion efficiency.

[0113] In summary, this invention, by adding an oxide layer between poly layers, effectively controls the silver paste etching rate while reducing the total thickness of the poly layer. Based on the original thin poly layer, the silver paste etching rate can be better controlled, avoiding damage to the tunneling oxide layer by the silver paste, preserving better passivation performance, reducing the loss of filler factor, and significantly improving conversion efficiency.

[0114] The embodiments described above are some, but not all, embodiments of the present invention. The detailed description of the embodiments of the present invention is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

Claims

1. A passivation method for a TOPCon battery, characterized in that, Includes the following steps: S1. Deposit a tunnel oxide layer on the back-side polished silicon wafer; S2. Then, the first poly layer is formed on the tunneling oxide layer; S3. A first oxide layer is formed on the first poly layer; S4. A second poly layer is formed on the first oxide layer; S5. A second oxide layer is formed on the second poly layer; S6. A third poly layer is formed on the second oxide layer; The processing time for the first poly layer is 80s-100s, and the phosphine flow rate is 300sccm / s-320sccm / s.

2. The passivation method for a TOPCon battery according to claim 1, characterized in that, The thickness of the tunneling oxide layer is 1nm-2nm, the thickness of the first poly layer is 9nm-11nm, the thickness of the first oxide layer is 0.3nm-0.5nm, the thickness of the second poly layer is 25nm-35nm, the thickness of the second oxide layer is 0.5nm-0.7nm, and the thickness of the third poly layer is 40nm-60nm.

3. A passivation method for a TOPCon battery according to claim 1 or 2, characterized in that, The tunneling oxide layer treatment time is 70s-80s, the tunneling oxide layer deposition temperature is 425℃-435℃, the deposition pressure is 1800mtorr-2000mtorr, the deposition power is 14000w-15000w, and the duty cycle is 20 / 2000.

4. The passivation method for a TOPCon battery according to claim 1, characterized in that, The first poly layer is deposited at a temperature of 425℃-435℃, a deposition pressure of 3200mtorr-3400mtorr, a power supply of 14500w-15000w, a duty cycle of 60 / 600, and is purged with silane, phosphine and hydrogen gas during deposition, with a deposition time of 80s-100s.

5. The passivation method for a TOPCon battery according to claim 1, characterized in that, The processing time for the first oxide layer is 18s-23s, the deposition temperature is 425℃-435℃, the deposition pressure is 1800mtorr-2000mtorr, the power supply is 14500w-15000w, and the duty cycle is 20 / 2000.

6. The passivation method for a TOPCon battery according to claim 1, characterized in that, The second poly layer is deposited at a temperature of 425℃-435℃, a deposition pressure of 3200-3400 mtorr, and is supplied with silane, phosphine, and hydrogen during deposition. The power supply is 14500w-15000w, the duty cycle is 40 / 450, and the deposition time is 180s-200s.

7. The passivation method for a TOPCon battery according to claim 1, characterized in that, The deposition temperature of the second oxide layer is 425℃-435℃, the deposition pressure is 1800mtorr-2000mtorr, the power supply is 14500w-15000w, the duty cycle is 20 / 2000, and the deposition time is 28s-33s.

8. The passivation method for a TOPCon battery according to claim 1, characterized in that, The deposition temperature of the third poly layer is 425℃-435℃, the deposition pressure is 3200mtorr-3400mtorr, silane, phosphine and hydrogen are introduced during deposition, the power supply is 14500w-15000w, the duty cycle is 40 / 400, and the deposition time is 280s-320s.

9. The passivation method for a TOPCon battery according to claim 1, characterized in that, It also includes step S7, annealing the silicon wafer after depositing the third oxide layer.

10. The passivation method for a TOPCon battery according to claim 9, characterized in that, The annealing temperature is 910℃-925℃, the pressure is 800Pa-900Pa, nitrogen gas is introduced at 3000sccm / s-4500sccm / s during annealing, and the annealing time is 1800s-2000s.

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