Semiconductor device and method for fabricating peripheral wall structure in fan-out redistribution layer

Abstract

A semiconductor device and method of fabricating a peripheral wall structure in a fan-out redistribution layer. A semiconductor device has a build-up interconnect structure. An opening is formed through the build-up interconnect structure. A peripheral wall structure is formed around the opening. A photonic semiconductor die is disposed over the build-up interconnect structure, wherein a photonic circuit of the photonic semiconductor die is aligned with the opening. A gap remains between the build-up interconnect structure and the photonic semiconductor die over the peripheral wall structure. An underfill or encapsulant is deposited between the build-up interconnect structure and the photonic semiconductor die.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods for fabricating peripheral wall structures in fan-out redistribution layers. Background Technology

[0002] Semiconductor devices are ubiquitous in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electrical energy, and creating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Photonic semiconductor devices capable of transmitting or receiving signals via light are becoming increasingly common. Photonic semiconductor dies are encapsulated with optical windows or grating regions to allow optical signals to enter and exit. When the package is molded or sealed, sealing materials such as molding compounds, underfill, or molded underfill can flow over the optical windows or grating regions, which can obstruct the proper transmission or reception of optical signals by the photonic circuitry. Therefore, there is a need for improved methods to retain sealing materials from the grating surface or optical windows of the photonic semiconductor die. Attached Figure Description

[0004] Figures 1a-1c The illustration shows a semiconductor wafer with multiple photonic semiconductor dies separated by saw tracks; Figures 2a-2l The illustration shows a semiconductor package with a photonic semiconductor die and a peripheral wall structure. Figures 3a-3d The diagram illustrates the substitution process flow; Figures 4a-4e The diagram illustrates the formation of the back-side interconnect; Figure 5a and Figure 5b An embodiment of the heat sink is illustrated; Figure 6 Another embodiment is illustrated; Figure 7a and Figure 7b The illustration shows an embodiment of the trench; and Figure 8a and Figure 8b The illustration shows an electronic device with a semiconductor package. Detailed Implementation

[0005] The invention is described in one or more embodiments with reference to the figures in the following description, wherein similar reference numerals denote the same or similar elements. While the invention is described with respect to the best mode for carrying out the objectives of the invention, those skilled in the art will appreciate that, as supported by the following disclosure and the figures, it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents. Features shown in the figures are not necessarily drawn to scale. Elements assigned the same reference numerals in the figures have similar functions and descriptions to each other. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0006] Semiconductor devices are generally manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create the voltage and current relationships necessary to perform the circuit's function.

[0007] Back-end manufacturing refers to the process of dicing or dicing finished wafers into individual semiconductor dies and packaging these dies for structural support, electrical interconnection, and environmental isolation. To dice a semiconductor die, the wafer is scribed and broken along non-functional areas known as serrations or kerfs. The wafer is diced using a laser cutting tool or saw blade. After dicing, the individual semiconductor dies are placed on a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed on top of the semiconductor die are then connected to contact pads within the package. Electrical connections can be fabricated using conductive layers, bumps, column bumps, conductive adhesive, or wire bonding. Sealants or other molding materials are deposited on top of the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, and the functionality of the semiconductor device is made available for use with other system components.

[0008] Figure 1aA semiconductor wafer 100 with a base substrate material 102 (such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials for structural support) is shown. Multiple photonic semiconductor dies 104 are formed on the wafer 100, separated by non-active inter-die wafer regions or saw tracks 106. The saw tracks 106 provide dicing areas to cut the semiconductor wafer 100 into individual photonic semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm). The wafer 100 may include hundreds or thousands of photonic semiconductor dies 104. In some embodiments, the photonic semiconductor die 104 is a silicon photonic die (PIC), a photodetector, or a vertical external cavity surface-emitting laser (VESCEL) assembly. In other embodiments, other types of photonic semiconductor dies are used.

[0009] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each photonic semiconductor die 104 has a back or non-active surface 108 and an active surface including a photonic circuit 110 formed within the die. The photonic circuit 110 is an electronic circuit capable of receiving optical signals and converting them into electrical signals for further processing, generating optical signals based on the received electrical signals, or both. In some embodiments, a region of the photonic circuit 110, or on or above it, may be referred to as a grating region because a grating connector is mounted there. The active surface may also include one or more transistors, diodes, and other circuit elements formed within the active surface to implement analog or digital circuitry, such as a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a memory, or other signal processing circuitry. The photonic semiconductor die 104 may also include IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

[0010] Wafer 100 is a wafer delivered by a wafer manufacturer to a manufacturer of a semiconductor package that will include a photonic semiconductor die 104. The manufacturer of wafer 100 has already formed an interconnect structure above an active surface including contact pads 112 for external interconnection. The interconnect structure may have one or more conductive trace layers, with insulating layers formed between said layers. The interconnect structure also electrically interconnects photonic circuitry 110 and contact pads 112 according to the intended functionality of the photonic semiconductor die 104.

[0011] The conductive layer, including the contact pad 112, is formed over the wafer 100 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, electroless plating, or another suitable metal deposition process. The conductive layer can be one or more layers as described below: aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Any conductive layer mentioned above or below can be formed using the same methods and materials. In some embodiments, the contact pad 112 includes under-bump metallization (UBM).

[0012] Conductive micropillars, microbumps, or micropillars 114 are formed on the contact pads 112 of each semiconductor die 104 to provide external interconnects. Conductive micropillars 114 are typically formed by depositing conductive material into openings in a photomask layer and then removing the photomask layer. The material of the micropillars 114 can be any of the materials mentioned herein for conductive layers, such as copper. In one embodiment, the micropillars 114 have a 30-micrometer-thick Ti / Cu-plated copper core. The micropillars 114 represent only one possible interconnect method. Other embodiments use bonding leads, conductive paste, columnar bumps, solder bumps, or any other suitable type of electrical interconnect. In some embodiments, an additional insulating or passivation layer is formed on the active surface around the micropillars 114, wherein the micropillars extend over the insulating layer.

[0013] exist Figure 1c In this process, semiconductor wafer 100 is cut into individual photonic semiconductor dies 104 through saw grooves 106 using a saw blade or laser cutting tool 118. Individual photonic semiconductor dies 104 can be inspected and electrically tested after cutting for identification as known good dies (KGD) or known good units (KGU).

[0014] Figures 2a-2l The illustration shows the formation of an optical semiconductor package including a photonic semiconductor die 104. Figure 2a A carrier 119a is shown, which has an interface layer, release adhesive layer, or double-sided tape 119b optionally formed or disposed above the carrier 119a as a temporary adhesive bonding film, etch stop layer, heat release layer, or UV release layer. The carrier 119a contains a sacrificial base material, such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid material for structural support. The combination of the carrier 119a and the interface layer 119b is referred to as carrier 119.

[0015] Stacked interconnect structure 120 is formed on carrier 119. The term stacked interconnect structure 120 refers to the method of forming the interconnect structure by successively stacking insulating and conductive layers on carrier 119 until the desired signal routing is achieved.

[0016] The formation of interconnect structure 120 begins by forming an insulating or passivation layer 122 on carrier 119. Insulating layer 122 comprises one or more layers as described below: silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide (PI), photosensitive polyimide (PSPI), benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. Insulating layer 122 can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, or thermal oxidation. Any of the insulating, passivation, or dielectric layers mentioned above or below can be formed using any of the materials or methods described for insulating layer 122.

[0017] An opening is formed through the insulating layer 122 using chemical etching, photolithography, mechanical drilling, laser drilling, or another suitable process to expose the underlying carrier 119. A conductive layer 124 is formed over the insulating layer 122 and includes conductive vias extending through the opening for subsequent vertical electrical interconnects. In other embodiments, the conductive layer 124 is formed on the insulating layer 122 without openings within the insulating layer. Later, openings may be formed to expose contact pads of the conductive layer 124 for electrical interconnects.

[0018] The conductive layer 124 is formed using any of the methods and materials described above for conductive layer 112. In other embodiments, any suitable conductive layer deposition and patterning method may be used, for example, using an additive or subtractive process. Any conductive layer mentioned above or below may be formed as described for conductive layers 124 and 112. In some embodiments, the conductive layer 124 is first formed on a carrier 119 that does not have a passivation layer 122.

[0019] An insulating layer 126 is formed over the passivation layer 122 and the conductive layer 124 using the methods and materials described above for the passivation layer 122. Openings are formed through the insulating layer 126 to expose contact pads or other portions of the underlying conductive layer 124. These openings can be formed by chemical etching, photolithography, mechanical drilling, laser drilling, or any other suitable means. Additional conductive and insulating layers can be staggered over the carrier 119 as needed to achieve desired electrical signal routing.

[0020] After the desired number of conductive and insulating layers have been deposited, micropillars or other interconnect structures 130 are formed on the top conductive layer 124 through openings in the top insulating layer 126. The micropillars 130 are formed using any of the methods and materials discussed above for the conductive layer 124 or the micropillars 114. In some embodiments, the micropillars 130 are formed prior to the insulating layer 126. The micropillars 130 are formed directly on the conductive layer 124 to physically and electrically contact the underlying conductive layer and extend vertically for electrical interconnection. The micropillars 130 include solder paste or solder caps 132 disposed on top of the micropillar using stencil printing or another suitable process.

[0021] Openings 136 are formed through interconnect structure 120 using chemical etching, mechanical drilling, laser ablation, or another suitable process. Openings 136 are formed after interconnect structure 120 is completed. In other embodiments, openings 136 are formed separately in each layer along with openings formed for conductive vias. Openings 136 are configured such that when photonic semiconductor die 104 is mounted to micropillar 130, photonic circuitry 110 will align with the opening. Openings 136 will then allow optical signals to pass through interconnect structure 120 to photonic circuitry 110.

[0022] The conductive layer 124 includes a portion 124a consisting of conductive traces fanning in or out horizontally across a device coverage area, and optionally includes contact pads at the ends of the traces for connection to underlying conductive vias and for subsequent formation of an overlying conductive structure. The conductive layer 124 also includes a portion 124b formed and patterned together with portion 124a but physically separated from portion 124a, said portion 124b forming a square or other shaped ring around the opening 136. The portion 124b has features discussed below and... Figure 2f The outer wall structure shown in the diagram has a similar or identical coverage area.

[0023] In one embodiment, Figures 2b-2f The formation of the peripheral wall structure 150 on the interconnect structure 120 is shown. Figure 2b In this process, a photoresist layer 140 is deposited over the interconnect structure 120. Light 142 is used to weaken the photoresist layer 140 where a desired peripheral wall structure 150 is desired. The light 142 is masked elsewhere such that when the photoresist layer is developed, it passes through the photoresist layer to form an opening 144 in the desired shape for the peripheral wall structure, as shown. Figure 2c As shown in the diagram.

[0024] Opening 144 extends in the complete circuit surrounding opening 136, such that when the opening is filled with... Figure 2dWhen the insulating material is deposited as shown, the insulating material forms a peripheral wall structure 150 of a desired shape that extends completely around the opening 136. Figure 2e and Figure 2f The photoresist layer 140 is removed to leave a peripheral wall structure 150 on the insulating layer 126 above the conductive layer portion 124b. The peripheral wall structure 150 can be formed using any of the materials and methods discussed above for the insulating layer 122. In one embodiment, the insulating layer 122, the insulating layer 126, and the peripheral wall structure 150 are all formed of polyimide.

[0025] In another embodiment, the photoresist layer 140 is a negative photoresist. Figure 2b Light 142 is used to solidify the photoresist layer 140 at the desired peripheral wall structure 150. During development, the remaining portion of the photoresist layer 140 is washed away, leaving only the peripheral wall structure 150, which is the portion of the photoresist layer 140 exposed to light 142. In a negative photoresist embodiment, as development removes the portion of the photoresist layer 140 where light 142 is masked, the process flow directly from... Figure 2b walk to Figure 2e and Figure 2f As an alternative to forming a peripheral wall structure 150 above the interconnect structure 120, trenches can be formed in the insulating layer 126, as shown in the attached diagram. Figure 7a and 7b As shown in the diagram. Without the conductive layer portion 124b, the trench can extend all the way through the insulating layer 126 to expose the underlying insulating layer 122. Alternatively, the trench can extend entirely through the interconnect structure 120, or the conductive layer portion 124b can be used as an etch stop layer.

[0026] Figure 2e A cross-sectional view of the peripheral wall structure 150 on the interconnect structure 120 is shown, while Figure 2f A plan view is shown. In some embodiments, the height of the peripheral wall structure 150 above the interconnect structure 120 is between 10 μm and 50 μm. In the plan view, the peripheral wall structure 150 completely and continuously surrounds the opening 136. The peripheral wall structure 150 has the same or similar shape as the opening 136, but is larger, such that the opening fits within the peripheral wall structure. For example, in the illustrated embodiment, both the opening 136 and the peripheral wall 150 are square, but both can be circular, hexagonal, elliptical, or any other suitable shape. Matching the shapes of the peripheral wall structure 150 and the opening 136 is technically unnecessary, but it is typically the most efficient use of the device substrate surface. It is optional to have the conductive layer portion 124b directly below the peripheral wall structure 150 and matching its coverage area, thus enhancing the structure or height of the peripheral wall structure.

[0027] exist Figure 2g In this configuration, the photonic semiconductor die 104 is picked up and placed above the interconnect structure 120. Each micropillar 114 from the photonic semiconductor die 104 is aligned with a corresponding micropillar 130 on the interconnect structure 120, such that when the photonic semiconductor die is lowered to... Figure 2h In the interconnect structure, the micropillars are electrically and physically connected to each other by reflowing the solder caps 132 between the respective micropillars. A gap 152 is maintained between the top of the peripheral wall structure 150 and the active surface of the photonic semiconductor die 104. The gap 152 ensures that the contact between the photonic semiconductor die 104 and the peripheral wall structure 150 does not cause damage to the corresponding dielectric layer during the flip chip assembly process or interference in the solder interconnect of the micropillars 130 and 114. In other embodiments, the photonic semiconductor die 104 rests on the peripheral wall structure 150.

[0028] exist Figure 2i In this process, an underfill 160 is deposited between the interconnect structure 120 and the photonic semiconductor die 104 using a dispenser head or nozzle 162. Other underfill deposition methods are used in other embodiments. The underfill 160 flows into the space between the interconnect structure 120 and the photonic semiconductor die 104 to fill the space and provide physical support. The underfill 160 may be a polymer composite material with or without added filler, such as epoxy resin or epoxy acrylate. In one embodiment, the gap 152 is configured to have a height smaller than the size of the filler used in the underfill 160, such that the filler does not physically fit through the gap 152 to reach the opening 136. For example, in one embodiment, a 10 μm filler is used, and the gap 152 has a height less than 10 μm. The filler size refers to the average or minimum physical size of the individual filler pieces disposed in the underfill.

[0029] The blocking material of the bottom filler 160 will ensure that almost no bottom filler passes through the gap 152 into the opening 136, which will block the desired light passing through the opening. Even without filler, or with filler smaller than the gap 152, the small gap sufficiently slows the flow of the bottom filler 160, making it almost impossible for any bottom filler to reach the opening 136 above the photonic circuit 110. In one embodiment, the nozzle 162 moves around the photonic die 104 to ensure that the space between the photonic semiconductor die and the interconnect structure 120 is always completely filled around the peripheral wall structure 150. Due to the blocking of the bottom filler by the peripheral wall structure 150, the opening 136 remains free of bottom filler 160. Instead of the peripheral wall structure 150 being formed on the insulating layer, in embodiments where trenches are formed into the insulating layer 126, any bottom filler 160 that has otherwise flowed into the opening 136 will be captured by the trenches. In any embodiment, when in Figure 2j When the bottom filler 160 is deposited, the bottom filler does not extend into the opening 136 or above the photonic circuit 110.

[0030] exist Figure 2k In this process, a sealant or molding compound 164 is deposited over and around the photonic semiconductor die 104 and interconnect structure 120 using solder paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. The sealant 164 can be a liquid or granular polymer composite, such as epoxy resin, epoxy acrylate, or another suitable polymer with or without fillers. The sealant 164 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external components and contaminants. In some embodiments, the underfill 160 is not used, and the peripheral wall structure 150 still provides the same benefits as mentioned above for the underfill by preventing the sealant 164 from flowing over the photonic circuit 110. Without the underfill 160, in addition to the two outer lines defining the region of the underfill 160 being removed, the line defining the inner boundary of the underfill between the peripheral wall structure 150 and the photonic semiconductor die 104 will instead be outside the inner boundary of the sealant 164. Figure 2k They will look the same.

[0031] Figure 2l The illustration shows a carrier 119 removed by heat, UV, or other release. The semiconductor package 170 is completed by adding any necessary structures for external interconnects (e.g., UBMs or contact pads 172 and solder bumps 174), and by dicing the sealant 164 and interconnect structure 120 if necessary to separate the packaged panels from each other. Contact pads 172 are formed as conductive layers on the surface of interconnect structure 120 and are patterned using the methods and materials described above for other conductive layers. The conductive layers may include conductive traces for fan-out or fan-in electrical connections from conductive layer 124, or simply contact pads formed on exposed conductive vias in conductive layer 124. In some embodiments, conductive layer 124 does not have vias extending through insulating layer 122, in which case openings are formed through insulating layer 122 before forming UBMs or contact pads 172 or directly on conductive layer 124 to form solder bumps 174.

[0032] To form solder bumps 174, conductive bump material is deposited over contact pads 172 using evaporation, electrolytic plating, electroless plating, droplet plating, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, or combinations thereof, with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to contact pads 172 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed to form balls or bumps 174 by heating the bump material above its melting point. Contact pads 172 can be or can include under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. Bumps 174 can also be compression bonded or thermocompressed to conductive layer 172.

[0033] Bump 174 represents a type of interconnect structure that can be formed above conductive layer 172. The interconnect structure can also utilize bonding leads, conductive paste, column bumps, microbumps, or other electrical interconnects. In one embodiment, contact pad 172 remains exposed without bump 174, allowing package 170 to be mounted using the opposing surface of sealant 164 on a PCB or other substrate to which a larger electronic device is attached, and then contact pad 172 can be connected to the substrate via bonding leads. This embodiment allows opening 136 to be oriented away from the electronic device substrate to which the package is mounted, making fiber optic cable connections easier.

[0034] In some embodiments, as part of the encapsulation process, the fiber optic connector is mounted in the opening 136. In other embodiments, the opening 136 remains open as illustrated, and the fiber optic connector or bare fiber is glued into the opening 136 as part of the process of mounting the package 170 into the terminal device. Alternatively, a lens may be glued into the opening 136 during or after encapsulation.

[0035] Package 170 includes a photonic semiconductor die 104 having photonic circuitry 110, which is protected from interference from the underfill 160 or sealant 164 by a peripheral wall structure 150. The peripheral wall structure 150 protects the optical window or grating surface of the photonic semiconductor die 104. The peripheral wall structure 150 defines a keep-out zone (KOZ) for the underfill or sealant, extending around the opening 136 and the photonic circuitry 110 to keep the sealant or underfill from light transmission interference. The peripheral wall structure 150 can be formed using the same methods and materials as the underlying insulating layer of the interconnect structure 120, therefore no new materials are required.

[0036] Instead of being formed on the interconnection structure 120 like the outer wall structure 150, Figures 3a-3d An embodiment with a peripheral wall structure 150a formed on a photonic semiconductor die 104 is illustrated. The peripheral wall structure 150a is formed using any of the methods and materials described above for the peripheral wall structure 150. Figure 3a In this process, a photonic semiconductor die 104 with a peripheral wall structure 150a is picked up and placed above the interconnect structure 120.

[0037] Figure 3b A photonic semiconductor die 104 mounted on an interconnect structure 120 is shown, wherein solder caps 132 have been reflowed between micropillars 130 and 114 for physical attachment and electrical connection of the photonic semiconductor die and the interconnect structure. For the same reasons discussed above regarding gap 152, a gap 152a may optionally be maintained between the peripheral wall structure 150a and the interconnect structure 120. As in the previous embodiments, the peripheral wall structure 150a surrounds the opening 136 in plan view as a complete circuit to block the bottom filler 160 or sealant 164.

[0038] Figure 3c The bottom filler 160, which has been deposited and does not flow into the opening 136 due to the outer wall structure 150a, is shown. Encapsulation 180 is... Figure 3d This is accomplished by depositing sealant 164, forming contact pads 172 and bumps 174 or another interconnect structure, and cutting the strips if necessary.

[0039] Figures 4a-4e An embodiment with a back-side external interconnect is illustrated. Figure 4a from Figure 2k Continuing, a conductive layer portion 124a is added outside the covered area of ​​the photonic semiconductor die 104, now extending outward toward the edge of the interconnect structure 120. Figure 4b An opening or via 190 is formed through the sealant 164 and insulating layer 126 down to the conductive layer 124. The via 190 is formed by chemical etching, laser etching, mechanical drilling, or another suitable means. The via 190 exposes the conductive layer 124 for subsequent electrical interconnection.

[0040] exist Figure 4c In this process, a conductive material is used to fill the via 190 to form a conductive via 192. The conductive via 192 is formed by any suitable conductive material deposition method, such as those discussed above for other conductive layers. The conductive via 192 can be formed by any suitable conductive material, such as those discussed above for conductive layers (generally, for example, copper). In some embodiments, the top surface of the conductive via 192 is made coplanar with the top surface of the sealant 164 by back-side grinding.

[0041] exist Figure 4d In this process, a conductive layer 194 and solder bumps 196 are formed on the back surface of the sealant 164. The conductive layer 194 is formed using the methods and materials mentioned above for the other conductive layers and is patterned to fan in the electrical connections from the conductive via 192 to the solder bumps 196. Bumps 196 are formed on the contact pads of the conductive layer 194 using the same methods and materials discussed above for the solder bumps 174.

[0042] exist Figure 4e In this process, the semiconductor package 200 is completed by removing the carrier 119 to expose the interconnect structure 120 and the photonic circuitry 110 through the opening 136 and performing dicing if necessary. Instead of forming bumps 196 on the interconnect structure 120, forming bumps 196 on the back surface of the sealant 164 allows for normal flip-chip mounting with bumps 196, exposing the photonic circuitry 110 in an orientation relative to the underlying device substrate, which is more convenient in many use cases.

[0043] The same general concept of the peripheral wall structure 150 can be used when leaving semiconductor dies or other electrical components exposed for virtually any reason. This is only one additional example. Figure 5a and Figure 5b A semiconductor package 220 is shown having a peripheral wall structure 150b for use with an exposed semiconductor die 204 to allow a heat sink 222 to be attached to the semiconductor die. Figure 5a The nearly completed package is shown, in which interconnect structure 120 extends to accommodate both the photonic semiconductor die 104 and the normal semiconductor die 204. Semiconductor die 204 is formed from a wafer in a similar manner to photonic semiconductor die 104, but does not include photonic circuitry. Instead, semiconductor die 204 has an active surface 210 with contact pads 212 for electrical interconnection.

[0044] A second opening 136b is formed in the interconnect structure 120 to accommodate the exposed active surface 210 of the semiconductor die 204. During the same processing steps as forming the first peripheral wall structure 150 around the opening 136b, a peripheral wall structure 150b is formed on the interconnect structure 120 around the opening 136b. The peripheral wall structure 150b blocks the bottom filler 160 from flowing into the opening 136b in the same manner described above for the peripheral wall structure 150. For the same benefits described above for the gap 152, the gap 152b is optionally left between the peripheral wall structure 150b and the semiconductor die 204.

[0045] exist Figure 5bIn this configuration, heat sink 222 is mounted onto the active surface 210 of semiconductor die 204 through opening 136b. Heat sink 222 can be soldered to active surface 210 using thermally conductive adhesive or by any other suitable means. In some embodiments, surface 208 is an active surface of semiconductor die 204, rather than an exposed surface, and is connected to contact pads 212 via through-silicon vias in the semiconductor die. Whether co-packaged with or not co-packaged with photonic semiconductor die 104, opening 136b can be used to expose the surface of any semiconductor die or other electrical component for any purpose.

[0046] Figure 6 A more complex embodiment with two photonic semiconductor dies 104a and 104b in the same semiconductor package 228 is illustrated. Photonic circuitry 110 is formed for each photonic semiconductor die 104 with separate openings 136 and peripheral wall structures 150. As in semiconductor package 200 above, package 228 uses conductive vias 192 for vertical interconnects. Additionally, through-silicon vias 230 are formed through photonic semiconductor dies 104a and 104b to provide additional vertical interconnects. Conductive vias 230 may be used in cases where conductive vias 192 are not present, and in other embodiments with only a single photonic semiconductor die. The conductive layer 194 is formed, if desired, as part of a stacked interconnect structure interleaved with one or more insulating layers 234 and additional conductive layers.

[0047] Additional electrical components 238 are disposed on interconnect structure 120 together with photonic semiconductor dies 104a and 104b. In all the embodiments described above, any desired electrical components used to achieve the electrical functionality of the formed semiconductor package are mounted on interconnect structure 120. Additional electrical components 238 may be discrete electrical devices such as diodes, transistors, resistors, capacitors, or inductors. Electrical components 238 may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, and may include integrated passive devices (IPDs).

[0048] Figure 7a and Figure 7b An embodiment is illustrated in which the groove 240 is used instead of the outer wall structure 150. Figure 7a The diagram illustrates a trench 240 formed through insulating layer 126. Trench 240 may be formed only partially through insulating layer 126, or it may extend completely through insulating layer 126 and partially through insulating layer 122. Trench 240 extends within the complete circuitry surrounding opening 136, as shown in the diagram. Figure 2fThe plan view of the outer wall structure 150 is the same. When the bottom packing 160 is deposited, the bottom packing flows into the trench 240 before reaching the opening 136. The trench 240 is large enough to capture any excess bottom packing. Figure 7b The diagram illustrates a complete package 250 with trench 240. Opening 136 remains free of bottom filler 160 because trench 240 traps the bottom filler before it flows into the main opening. In any of the embodiments above, trench 240 can be used instead of peripheral wall structure 240.

[0049] Figure 8a and Figure 8b The illustration shows the integration of the aforementioned semiconductor package (e.g., semiconductor package 200) into a larger electronic device 300. Figure 8a The illustration shows a partial cross-section of a semiconductor package 200, which is mounted as part of an electronic device 300 onto a printed circuit board (PCB) or other substrate 302. Solder bumps 196 are reflowed onto the conductive layer 304 of the PCB 302 to physically attach and electrically connect the semiconductor package 200 to the PCB. In other embodiments, thermal compression or another suitable attachment and connection method is used. In some embodiments, an adhesive or underfill layer is used between the semiconductor package 200 and the PCB 302. The photonic semiconductor die 104 is electrically coupled to the conductive layer 304 via bumps 196, conductive layer 194, conductive via 192, conductive layer 124, micropillars 130, solder 132, and micropillars 114.

[0050] Figure 8b The illustration shows an electronic device 300 having a chip carrier substrate or PCB 302, wherein multiple semiconductor packages, including semiconductor package 200, are disposed on the surface of the PCB 302. Depending on the application, the electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages.

[0051] Electronic device 300 can be a standalone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electronic device 300 can be a sub-component of a larger system. For example, electronic device 300 can be part of a tablet, cellular phone, digital camera, communication system, or other electronic device. Alternatively, electronic device 300 can be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packages can include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are crucial for products to gain market acceptance. The distance between semiconductor devices can be reduced to achieve higher density. PCB 302 can have more irregular shapes to facilitate fitting into more ergonomic and smaller device housings.

[0052] exist Figure 8b In this PCB 302, a general substrate is provided for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed above the surface of PCB 302 or within layers of PCB 302 using evaporation, electrolytic plating, chemical plating, screen printing, or other suitable metal deposition processes. Signal traces 304 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. Trace 304 also provides power and ground connections to each of the semiconductor packages.

[0053] In some embodiments, the semiconductor device has two packaging levels. The first-level package is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second-level package involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, the semiconductor device may have only a first-level package, where the die is directly mechanically and electrically mounted on the PCB.

[0054] For illustrative purposes, several types of first-level packages are shown on PCB 302, including a bonded lead package 346 and a flip chip 348. Additionally, several types of second-level packages disposed on PCB 302 are shown, including a ball grid array (BGA) 350, a bump chip carrier (BCC) 352, a ground grid array (LGA) 356, a multi-chip module (MCM) or SIP module 358, a quad flat no-lead package (QFN) 360, a quad flat package 362, and an embedded die-level ball grid array (eWLB) 364. In one embodiment, eWLB 364 is a fan-out die-level package (Fo-WLP) or a fan-in die-level package (Fi-WLP).

[0055] Depending on system requirements, any combination of semiconductor packages configured with first-level and second-level packaging styles, along with other electrical components, can be connected to PCB 302. In some embodiments, electronics 300 comprises a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate prefabricated components into electronics and systems. Because semiconductor packages include complex functionality, electronics can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to fail and less expensive to manufacture, reducing upstream and downstream costs in the supply chain.

[0056] Although one or more embodiments of the invention have been illustrated in detail, those skilled in the art will appreciate that modifications and adaptations can be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Forming a stacked interconnect structure; An opening is formed through the stacked interconnect structure; An outer wall structure is formed around the opening; A photonic semiconductor die is disposed above a stacked interconnect structure, wherein the photonic circuit of the photonic semiconductor die is aligned with the opening, and a gap is maintained between the stacked interconnect structure above the peripheral wall structure and the photonic semiconductor die; and Deposit an underlayer filler or sealant between the stacked interconnect structure and the photonic semiconductor die.

2. The method of claim 1, wherein the underlying filler or sealant comprises a filler having a size larger than the gap.

3. The method of claim 1, further comprising: A peripheral wall structure is formed on the stacked interconnect structure; and A stacked interconnect structure is formed to include a portion of the conductive layer beneath the peripheral wall structure.

4. The method of claim 1, further comprising depositing a second sealant over the photonic semiconductor die after depositing the underlayer filler or sealant.

5. The method of claim 1, further comprising forming a conductive layer over a photonic semiconductor die opposite to the stacked interconnect structure.

6. The method of claim 5, further comprising forming a conductive via extending between the stacked interconnect structure and the conductive layer.

7. A method for manufacturing a semiconductor device, comprising: Forming a stacked interconnect structure; An opening is formed through the stacked interconnect structure; An outer wall structure is formed around the opening; A semiconductor die is positioned above the opening; and Deposit an underlayer filler or sealant between the stacked interconnect structure and the semiconductor die.

8. The method of claim 7, further comprising forming a peripheral wall structure on the stacked interconnect structure.

9. The method of claim 8, further comprising forming a stacked interconnect structure to include a portion of a conductive layer beneath the peripheral wall structure.

10. A semiconductor device, comprising: Stacked interconnect structure; Passing through the opening formed by the stacked interconnect structure; The outer wall structure extending around the opening; A photonic semiconductor die is positioned above a stacked interconnect structure, wherein the photonic circuitry of the photonic semiconductor die is aligned with the opening; and The underlying filler or sealant deposited between the stacked interconnect structure and the photonic semiconductor die.

11. The semiconductor device of claim 10, wherein the peripheral wall structure is formed on the stacked interconnect structure.

12. The semiconductor device of claim 11, wherein the stacked interconnect structure includes a portion of a conductive layer beneath the peripheral wall structure.

13. The semiconductor device of claim 10, further comprising a second sealant deposited on a photonic semiconductor die opposite to the underlying filler or sealant.

14. The semiconductor device of claim 10, further comprising a conductive layer formed over a photonic semiconductor die opposite to the stacked interconnect structure.

15. The semiconductor device of claim 14, further comprising a conductive via extending between the stacked interconnect structure and the conductive layer.

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