Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof.The solar cell comprises a silicon wafer and a plurality of thin grid lines distributed on the surface of the silicon wafer in parallel, the thin grid lines comprise first thin grid lines and second thin grid lines which are stacked on the surface of the silicon wafer, the first thin grid lines are distributed at intervals in the first direction, and the second thin grid lines are distributed at intervals in the second direction. The second fine grid lines are distributed along the first direction, the second fine grid lines partially cover the intervals of the first fine grid lines on the surface of the silicon wafer along the first direction, the second fine grid lines partially cover the first fine grid lines along the first direction, and the silver content of the first fine grid lines is greater than that of the second fine grid lines. The thin grid lines adopt the composite structure of the first thin grid lines and the second thin grid lines, the first thin grid lines are designed at intervals, and the silver content in the second thin grid lines is relatively low, so that the consumption of metal silver can be greatly reduced on the premise of not influencing the cell efficiency, and the preparation cost is further greatly reduced.

Description

Technical Field

[0001] This invention belongs to the field of solar cell technology, specifically relating to a solar cell and its preparation method. Background Technology

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in both domestic and international photovoltaic markets are constantly increasing, prompting industry manufacturers to focus on the research and development of high-efficiency cells. TOPCon (Tunnel Oxide Passivated Contact) cells are a new type of high-efficiency N-type cell. By sequentially fabricating an ultra-thin tunnel oxide layer and a doped polycrystalline silicon layer on the back of the cell, it can improve the surface passivation performance of the cell, reduce the metal contact recombination current, and effectively improve the open-circuit voltage and short-circuit current of the cell.

[0003] In recent years, TOPCon cells have been widely adopted by numerous companies as a primary technology due to their significant advantages, including high conversion efficiency, low degradation performance, and high cost-effectiveness in mass production. In 2023, their production capacity expanded to over 300GW. Silver (Ag) has low resistivity, effectively transporting charge carriers and exhibiting low resistance loss, making it widely used in the photovoltaic and electronics industries. However, as a precious metal, Ag is expensive, accounting for approximately 70% of the cost of non-silicon solar cells. The use of expensive silver materials in both the bifacial metal electrodes of TOPCon cells contributes to their high cost.

[0004] Therefore, in order to address the above-mentioned technical problems, it is necessary to provide a solar cell and a method for its fabrication. Summary of the Invention

[0005] The purpose of this invention is to provide a solar cell and its preparation method, so as to reduce the preparation cost while ensuring cell efficiency.

[0006] To achieve the above objectives, an embodiment of the present invention provides the following technical solution:

[0007] A solar cell includes a silicon wafer and a plurality of fine grid lines distributed in parallel on the surface of the silicon wafer. The fine grid lines include a first fine grid line and a second fine grid line stacked on the surface of the silicon wafer. The first fine grid lines are spaced apart along a first direction, and the second fine grid lines are also distributed along the first direction. The second fine grid lines partially cover the spaced areas of the first fine grid lines along the first direction on the surface of the silicon wafer, and partially cover the area above the first fine grid lines along the first direction. The silver content of the first fine grid lines is greater than the silver content of the second fine grid lines.

[0008] In one embodiment, the first fine gate line is a silver gate line, and the second fine gate line is a base metal gate line.

[0009] In one embodiment, the material of the second fine grid line includes one or more of silver-clad copper, silver-clad nickel, and silver-clad aluminum; and / or,

[0010] The silver content in the second fine gate line is 30% to 80%.

[0011] In one embodiment, the discontinuity ratio of the first fine grid line along the first direction is 15% to 90% or 15% to 60%, wherein the discontinuity ratio is X / L, where X is the spacing distance between two adjacent first fine grid lines, and L is the sum of the spacing distance between two adjacent first fine grid lines and the length of one first fine grid line.

[0012] In one embodiment, the fine gate lines are distributed on the backlight surface of the silicon wafer, the second fine gate lines are partially stacked on the first fine gate lines, and the linewidth of the second fine gate lines is greater than or equal to the linewidth of the first fine gate lines.

[0013] In one embodiment, the linewidth of the fine gate line is 20 μm to 60 μm, and the height is 2 μm to 10 μm; and / or,

[0014] The first fine gate line has a linewidth of 10 μm to 40 μm and a height of 1 μm to 5 μm; and / or,

[0015] The linewidth of the second fine gate line is 20μm to 60μm, the height of the second fine gate line stacked on the silicon wafer is 2μm to 10μm, and the height of the second fine gate line stacked on the first fine gate line is 1μm to 5μm.

[0016] In one embodiment, the fine gate lines are distributed on the light-receiving surface of the silicon wafer, the second fine gate lines are partially stacked on the first fine gate lines, and the linewidth of the second fine gate lines is less than or equal to the linewidth of the first fine gate lines.

[0017] In one embodiment, the solar cell further includes multiple parallel main grid lines that intersect with fine grid lines. At the intersection of the main grid lines and the fine grid lines, the fine grid lines are stacked on top of the main grid lines and are electrically connected to each other.

[0018] Another embodiment of the present invention provides the following technical solution:

[0019] A method for preparing a solar cell, the method comprising the following steps:

[0020] A first fine gate line is printed on the surface of a silicon wafer using a first fine gate paste, and the first fine gate line is spaced apart along a first direction;

[0021] A second fine gate line is printed on the surface of a silicon wafer using a second fine gate paste. The second fine gate line is distributed along a first direction, and the second fine gate line partially covers the interval of the first fine gate line along the first direction on the surface of the silicon wafer, and partially covers the first fine gate line above it along the first direction.

[0022] The silver content in the first fine grid paste is greater than the silver content in the second fine grid paste.

[0023] In one embodiment, the second fine grid paste includes one or more of silver-coated copper paste, silver-coated nickel paste, and silver-coated aluminum paste; and / or,

[0024] The silver content in the second fine grid paste is 30% to 80%.

[0025] In one embodiment, the process further includes, prior to printing the first fine grid line:

[0026] The main grid lines are printed on the surface of the silicon wafer using main grid paste.

[0027] In one embodiment, the process further includes, before printing the second fine grid line:

[0028] The silicon wafer with the first fine gate line printed on it is sintered at a high temperature of 650℃~800℃; and / or,

[0029] Laser sintering is performed on silicon wafers printed with the first fine grid lines. The reverse voltage is 30V to 60V, the laser power is 5W to 50W, and the laser scanning speed is 10m / s to 50m / s.

[0030] In one embodiment, after the second fine grid line is printed, it further includes:

[0031] The second fine grid line is dried at a temperature of 150℃~300℃.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The fine grid lines of this invention adopt a composite structure of first fine grid lines and second fine grid lines. The first fine grid lines are spaced apart, and the silver content in the second fine grid lines is low. This can greatly reduce the consumption of metallic silver without affecting the battery efficiency, thereby greatly reducing the manufacturing cost. At the same time, the first fine grid lines can be sintered normally, while the second fine grid lines do not need to be sintered at high temperature, making them suitable for TOPCon battery processes. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the planar structure of the solar cell in Embodiment 1 of the present invention;

[0036] Figure 2 This is a schematic cross-sectional view of the solar cell in Embodiment 1 of the present invention;

[0037] Figure 3 This is a three-dimensional structural diagram of the first fine gate line on the back side of the silicon wafer in Embodiment 1 of the present invention;

[0038] Figure 4 This is a three-dimensional structural diagram of the fine gate lines on the back of the silicon wafer in Embodiment 1 of the present invention;

[0039] Figures 5a-5c This is a flowchart illustrating the fabrication process of the solar cell in Embodiment 1 of the present invention;

[0040] Figure 6 This is a schematic cross-sectional view of the solar cell in Embodiment 2 of the present invention;

[0041] Figure 7 This is a three-dimensional structural diagram of the fine gate lines on the back of the silicon wafer in Embodiment 2 of the present invention. Detailed Implementation

[0042] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0043] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0044] This invention discloses a solar cell, comprising a silicon wafer and a plurality of fine grid lines distributed in parallel on the surface of the silicon wafer. The fine grid lines include a first fine grid line and a second fine grid line stacked on the surface of the silicon wafer. The first fine grid lines are spaced apart along a first direction, and the second fine grid lines are also distributed along the first direction. The second fine grid lines partially cover the spaced areas of the first fine grid lines along the first direction on the surface of the silicon wafer, and partially cover the area above the first fine grid lines along the first direction. The silver content of the first fine grid lines is greater than the silver content of the second fine grid lines.

[0045] The present invention also discloses a method for manufacturing a solar cell, comprising the following steps:

[0046] Print first fine grid lines on the surface of the silicon wafer, and the first fine grid lines are distributed at intervals along a first direction;

[0047] Print second fine grid lines on the surface of the silicon wafer, the second fine grid lines are distributed along the first direction, and part of the second fine grid lines cover the intervals of the first fine grid lines along the first direction on the surface of the silicon wafer, and part cover above the first fine grid lines along the first direction;

[0048] Wherein, the silver content in the first fine grid paste is greater than the silver content in the second fine grid paste.

[0049] The fine grid lines of the present invention adopt a composite structure of first fine grid lines and second fine grid lines. The first fine grid lines are designed at intervals, and the silver content in the second fine grid lines is relatively low, which can greatly reduce the consumption of metallic silver, and thus greatly reduce the manufacturing cost.

[0050] The following further illustrates the present invention with specific examples.

[0051] Example 1:

[0052] Refer Figure 1 Shown is a schematic plan view of the solar cell in this embodiment. The solar cell 100 is a TOPCon cell, including a silicon wafer and grid electrode lines on the surface of the silicon wafer. The silicon wafer is an N-type silicon wafer. Taking the TOPCon 210 cell as an example, the size of the full-piece solar cell is 210mm * 210mm. The full-piece solar cell includes two identical half-piece solar cells, with a cutting channel 101 reserved in the middle.

[0053] Wherein, the grid electrode lines include main grid lines 11 and fine grid lines 12. There are multiple main grid lines 11 and they are parallelly distributed along a first direction (horizontal direction), and there are multiple fine grid lines 12 and they are parallelly distributed along a second direction (vertical direction), and the first direction and the second direction are perpendicular to each other.

[0054] Combined with Figure 2 Shown, the silicon wafer 20 in this embodiment includes a light-receiving surface (i.e., the front surface) and a light-back surface (i.e., the back surface) which are oppositely arranged. Both the front surface and the back surface are provided with main grid lines and fine grid lines, and the main grid lines and the fine grid lines are perpendicularly intersected. At the intersection of the main grid lines and the fine grid lines, the fine grid lines are stacked on top of the main grid lines and are electrically conductive with each other.

[0055] Wherein, the main grid lines and the fine grid lines 12 on the light-receiving surface of the silicon wafer 20 are the front grid electrode lines of a conventional TOPCon cell, which will not be elaborated here.

[0056] Combined with Figure 3 、 Figure 4As shown, in this embodiment, the fine grid lines on the backlight surface of the silicon wafer include a first fine grid line 121 and a second fine grid line 122 stacked on the surface of the silicon wafer. The first fine grid lines 121 are distributed at intervals along the first direction (i.e., the lateral direction). The second fine grid lines 122 are distributed along the first direction, and a part of the second fine grid lines 122 covers the intervals of the first fine grid lines 121 along the first direction on the surface of the silicon wafer, and a part covers above the first fine grid lines 121 along the first direction.

[0057] In this embodiment, the silver content of the first fine grid line 121 is greater than that of the second fine grid line 122. Specifically, the first fine grid line 121 is a silver grid line, and the second fine grid line 122 is a base metal grid line. Preferably, the material of the base metal grid line includes one or more of silver-coated copper, silver-coated nickel, silver-coated aluminum, etc., and the silver content (i.e., the mass percentage of silver in the total mass of the metal) is 30% - 80%. In this embodiment, silver-coated copper is taken as an example for illustration, and the silver content is 30%.

[0058] Refer Figure 3 As shown, in this embodiment, the first fine grid lines 121 are equally spaced at intervals along the first direction. The length S of each first fine grid line 121 is equal, and the interval distance X between adjacent two first fine grid lines 121 is equal. The interruption ratio of the first fine grid line 121 is defined as X / L, where L is the sum of the interval distance X between adjacent two first fine grid lines and the length S of one first fine grid line. In this embodiment, the interruption ratio of the first fine grid line along the first direction is 15% - 90%, preferably 15% - 60%.

[0059] Specifically, taking the interruption ratio of 50% as an example, the length S of each first fine grid line 121 and the interval distance X between adjacent two first fine grid lines 121 satisfy: X / (X + S) = 50%, that is, X = S. For example, X = 50μm and S = 50μm. Taking the interruption ratio of 40% as an example, the length S of each first fine grid line 121 and the interval distance X between adjacent two first fine grid lines 121 satisfy: X / (X + S) = 40%. For example, X = 40μm and S = 60μm. The length S of the first fine grid line 121 and the interval distance X between adjacent two first fine grid lines 121 under other interruption ratios will not be exemplified one by one.

[0060] In other embodiments, the first fine grid lines 121 may also be distributed at non-uniform intervals along the first direction. In this case, the interruption ratio can be defined as X 总 / L 总 , X 总 is the sum of the interval distances between all adjacent two first fine grid lines, S 总 is the sum of the lengths S of all first fine grid lines 总 , L 总 = X 总 + S 总 .

[0061] Refer to Figure 2 and in combination with Figure 4 As shown, in this embodiment, the line width of the second fine grid line 122 is greater than that of the first fine grid line 121. All the first fine grid lines 121 distributed at intervals are covered by the second fine grid line 122, and the upper surfaces of the second fine grid lines 122 are flush.

[0062] Specifically, the overall line width of the first fine grid line 121 and the second fine grid line 122 is 20μm - 60μm, and the overall height is 2μm - 10μm. Among them, the line width of the first fine grid line 121 is 10μm - 40μm, and the height is 1μm - 5μm; the line width of the second fine grid line 122 is 20μm - 60μm, the height of the second fine grid line laminated on the silicon wafer is 2μm - 10μm, and the height of the second fine grid line laminated on the first fine grid line is 1μm - 5μm.

[0063] Exemplarily, in this embodiment, the line width of the first fine grid line 121 is 30μm, the height is 4μm, the line width of the second fine grid line 122 is 40μm, the height of the second fine grid line laminated on the silicon wafer is 7μm, the height of the second fine grid line laminated on the first fine grid line is 3μm. All the first fine grid lines 121 are covered by the second fine grid line 122, and the overall line width of the first fine grid line 121 and the second fine grid line 122 is 40μm, and the overall height is 7μm.

[0064] The preparation method of the solar cell in this embodiment includes the following steps:

[0065] 1. Print the back main grid line on the back of the silicon wafer with the main grid paste and dry it.

[0066] The printing of the back main grid line is exactly the same as the prior art and will not be elaborated here.

[0067] 2. Refer to Figure 5a As shown, print the first fine grid line 121 on the back of the silicon wafer 20 with the first fine grid paste and dry it. The first fine grid paste is silver paste.

[0068] Specifically, in this step, the discontinuous ratio of the first fine grid line 121 is 50%. The length S of each first fine grid line 121 and the interval distance X between two adjacent first fine grid lines 121 are both 50μm, the line width is 30μm, the height is 4μm, and the wet weight of the silver paste is 26.5mg.

[0069] 3. Print the front main grid line on the front of the silicon wafer 20 with the main grid paste and dry it.

[0070] The printing of the front main grid line is exactly the same as the prior art and will not be elaborated here.

[0071] 4. Refer to Figure 5bAs shown, fine grid lines 12 are printed on the front side of silicon wafer 20 using fine grid paste and then dried.

[0072] The printing of the fine grid lines on the front is exactly the same as in existing technology, so it will not be described in detail here.

[0073] 5. The silicon wafer 20 with the first fine gate line 121 and the front fine gate line 12 printed on it is subjected to high-temperature sintering, which specifically includes two steps: high-temperature sintering and laser sintering.

[0074] High-temperature sintering is a crucial step in solar cell manufacturing, significantly impacting the cell's electrical performance. The main purpose of high-temperature sintering is to achieve good ohmic contact between the underlying fine grid lines and the silicon wafer surface through high-temperature heating, thereby improving the photoelectric conversion efficiency of the solar cell. For example, in this embodiment, the sintering temperature is 650℃~800℃.

[0075] Laser sintering involves generating electron-hole pairs using a laser, then applying a reverse voltage to separate these pairs and generate current. This current creates high temperatures at areas of poor contact, causing the underlying fine gate lines to re-sinter with the silicon wafer, forming a good contact. For example, in this embodiment, the reverse voltage for laser sintering is 30V–60V, the laser power is 5W–50W, and the laser scanning speed is 10m / s–50m / s.

[0076] Furthermore, light injection can be performed between the high-temperature sintering and laser sintering steps. Light injection can activate the doped elements in the crystalline silicon thin film, thereby further improving the photoelectric conversion efficiency of the battery.

[0077] 6. Participate Figure 5c As shown, a second fine gate line 122 is printed on the back side of the silicon wafer 20 using a second fine gate paste. The second fine gate line 122 is distributed along the first direction, and the second fine gate line 122 partially covers the interval of the first fine gate line 121 on the back side of the silicon wafer along the first direction, and partially covers the first fine gate line 121 along the first direction, and is then dried.

[0078] Specifically, in this embodiment, the second fine gate paste is a silver-coated copper paste with a silver content of 30%. The linewidth of the second fine gate line 122 is 40 μm, and the height of the second fine gate line stacked on the silicon wafer is 7 μm. The height of the second fine gate line 122 stacked on the first fine gate line 121 is 3 μm. The first fine gate line 121 is completely covered by the second fine gate line 122. The overall linewidth of the first fine gate line 121 and the second fine gate line 122 is 40 μm, and the overall height is 7 μm. The final wet weight of the silver-coated copper paste is 27.6 mg.

[0079] In addition, the drying temperature of the second fine grid line 122 is 150°C to 300°C. In this embodiment, 200°C is used as an example for explanation.

[0080] 7. Test and sort the finished batteries obtained in step 6.

[0081] In this embodiment, the discontinuous ratio of the first fine grid line 121 is illustrated by taking 50% as an example. In other embodiments, the wet weight of the paste, silver content, and photovoltaic performance parameters of the battery corresponding to different discontinuous ratios are as follows in the table:

[0082]

[0083] Among them, the discontinuous ratio of 0% is the fine grid line used in mass-produced batteries in the prior art. It can be seen that the larger the discontinuous ratio, the lower the silver consumption. By overprinting the base metal paste on the discontinuous first fine grid line, the current derived from the discontinuous grid line can be collected to the main grid line through the second fine grid line (base metal grid line). The discontinuous grid line will cause an increase in contact resistance. By increasing the use of the base metal paste, the line resistance can be reduced, and the loss caused by current transmission can be reduced, thereby compensating for the current loss caused by the increase in the contact of the fine grid line.

[0084] As shown in the above table, when the discontinuous ratio of the first fine grid line is 50%, the wet weight of the first fine grid paste on the back is 26.5 mg, the wet weight of the second fine grid paste is 27.6 mg, the silver content is 31.8 mg, and the battery efficiency is slightly lower than that of the mass-produced battery by 0.006%, but the actual silver consumption is reduced by 15.9 mg (about 33.3%), and the cost reduction effect is very obvious.

[0085] As can be seen from the above table, the discontinuous ratio is preferably controlled between 15% and 60%, which can reduce the preparation cost while ensuring the battery efficiency.

[0086] Embodiment 2:

[0087] Refer Figure 6 、 Figure 7 As shown, the solar cell in this embodiment is substantially the same as that in Embodiment 1. The difference is that the line width of the second fine grid line 122 in this embodiment is equal to the line width of the first fine grid line 121, both being 20 μm to 60 μm.

[0088] Exemplarily, in this embodiment, the line width of the first fine grid line 121 is 40 μm, the height is 4 μm, the line width of the second fine grid line 122 is 40 μm, the height of the second fine grid line laminated on the silicon wafer is 7 μm, the height of the second fine grid line laminated on the first fine grid line is 3 μm, and the second fine grid line 122 is only laminated on the first fine grid line 121 and between adjacent first fine grid lines 121.

[0089] In this embodiment, it is necessary to ensure the printing alignment accuracy of the first fine grid line and the second fine grid line. In Embodiment 1, since the line width of the second fine grid line is wider than that of the first fine grid line, the printing alignment accuracy of the fine grid line can be reduced.

[0090] It should be understood that the above embodiments are illustrated by taking a composite fine gate line structure with a first fine gate line 121 and a second fine gate line 122 on the back surface of the silicon wafer as an example. In other embodiments, the above composite fine gate line structure can also be provided on the light-receiving surface of the silicon wafer.

[0091] Because the battery requires a high degree of metal shading when exposed to light, if the linewidth of the second fine grid line 122 on the front side is greater than the linewidth of the first fine grid line 121, it will lead to significant current loss and affect battery efficiency. Therefore, the linewidth of the second fine grid line 122 can be set to be smaller than the linewidth of the first fine grid line 121. In this way, the second fine grid line 122 is stacked on top of part of the first fine grid line 121, which can reduce the metal shading area.

[0092] In addition, the solar cells in the above embodiments are multi-busbar (MBB) cells or super-multi-busbar (SMBB) cells. The fine grid line structure design in this embodiment is also applicable to gridless (OBB) cells, that is, it only contains fine grid lines and does not contain main grid lines. The grid line electrode structure and preparation method for gridless cells will not be described in detail here.

[0093] As can be seen from the above technical solution, the present invention has the following beneficial effects:

[0094] The fine grid lines of this invention adopt a composite structure of first fine grid lines and second fine grid lines. The first fine grid lines are spaced apart, and the silver content in the second fine grid lines is low. This can greatly reduce the consumption of metallic silver without affecting the battery efficiency, thereby greatly reducing the manufacturing cost. At the same time, the first fine grid lines can be sintered normally, while the second fine grid lines do not need to be sintered at high temperature, making them suitable for TOPCon battery processes.

[0095] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0096] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A solar cell, characterized in that, The solar cell includes a silicon wafer and multiple fine grid lines distributed in parallel on the surface of the silicon wafer. The fine grid lines include a first fine grid line and a second fine grid line stacked on the surface of the silicon wafer. The first fine grid lines are spaced apart along a first direction, and the second fine grid lines are also distributed along the first direction. The second fine grid lines partially cover the spaced areas of the first fine grid lines along the first direction on the surface of the silicon wafer, and partially cover the area above the first fine grid lines along the first direction. The silver content of the first fine grid lines is greater than the silver content of the second fine grid lines.

2. The solar cell according to claim 1, characterized in that, The first fine gate line is a silver gate line, and the second fine gate line is a base metal gate line.

3. The solar cell according to claim 2, characterized in that, The material of the second fine grid line includes one or more of silver-clad copper, silver-clad nickel, and silver-clad aluminum; and / or, The silver content in the second fine gate line is 30% to 80%.

4. The solar cell according to claim 1, characterized in that, The discontinuity ratio of the first fine grid line along the first direction is 15% to 90% or 15% to 60%, wherein the discontinuity ratio is X / L, where X is the spacing distance between two adjacent first fine grid lines, and L is the sum of the spacing distance between two adjacent first fine grid lines and the length of one first fine grid line.

5. The solar cell according to claim 1, characterized in that, The fine gate lines are distributed on the back surface of the silicon wafer, and the second fine gate line is partially stacked on the first fine gate line, and the linewidth of the second fine gate line is greater than or equal to the linewidth of the first fine gate line.

6. The solar cell according to claim 5, characterized in that, The fine gate lines have a linewidth of 20μm to 60μm and a height of 2μm to 10μm; and / or, The first fine gate line has a linewidth of 10 μm to 40 μm and a height of 1 μm to 5 μm; and / or, The linewidth of the second fine gate line is 20μm to 60μm, the height of the second fine gate line stacked on the silicon wafer is 2μm to 10μm, and the height of the second fine gate line stacked on the first fine gate line is 1μm to 5μm.

7. The solar cell according to claim 1, characterized in that, The fine gate lines are distributed on the light-receiving surface of the silicon wafer, and the second fine gate line is partially stacked on the first fine gate line, and the line width of the second fine gate line is less than or equal to the line width of the first fine gate line.

8. The solar cell according to claim 1, characterized in that, The solar cell also includes multiple parallel main grid lines, which intersect with fine grid lines. At the intersection of the main grid lines and the fine grid lines, the fine grid lines are stacked on top of the main grid lines and are electrically connected to each other.

9. A method for preparing a solar cell, characterized in that, The preparation method includes the following steps: A first fine gate line is printed on the surface of a silicon wafer using a first fine gate paste, and the first fine gate line is spaced apart along a first direction; A second fine gate line is printed on the surface of a silicon wafer using a second fine gate paste. The second fine gate line is distributed along a first direction, and the second fine gate line partially covers the interval of the first fine gate line along the first direction on the surface of the silicon wafer, and partially covers the first fine gate line above it along the first direction. The silver content in the first fine grid paste is greater than the silver content in the second fine grid paste.

10. The preparation method according to claim 9, characterized in that, The second fine grid paste includes one or more of silver-coated copper paste, silver-coated nickel paste, and silver-coated aluminum paste; and / or, The silver content in the second fine grid paste is 30% to 80%.

11. The preparation method according to claim 9, characterized in that, The process before printing the first fine grid line also includes: The main grid lines are printed on the surface of the silicon wafer using main grid paste.

12. The preparation method according to claim 9, characterized in that, The process before printing the second fine grid line also includes: The silicon wafer with the first fine gate line printed on it is sintered at a high temperature of 650℃~800℃; and / or, Laser sintering is performed on silicon wafers printed with the first fine grid lines. The reverse voltage is 30V to 60V, the laser power is 5W to 50W, and the laser scanning speed is 10m / s to 50m / s.

13. The preparation method according to claim 9, characterized in that, The second fine grid line printing also includes: The second fine grid line is dried at a temperature of 150℃~300℃.

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