Solar cell, manufacturing method thereof and electric device

Abstract

The invention provides a solar cell, a manufacturing method thereof and an electric device. The solar cell comprises a substrate which is provided with a first surface and a second surface which are oppositely arranged, and the first surface comprises first areas and second areas which are alternately arranged; the tunneling oxide layer and the doped polycrystalline silicon layer are located on a first area in the first surface, and the tunneling oxide layer is arranged between the first surface and the doped polycrystalline silicon layer; the first passivation layer comprises a first passivation sub-layer and a second passivation sub-layer; the first passivation sub-layer covers the doped polycrystalline silicon layer in the first region; the second passivation sub-layer covers the second region; the intrinsic amorphous silicon layer and the doped amorphous silicon layer are located on the second surface, and the intrinsic amorphous silicon layer is arranged between the second surface and the doped amorphous silicon layer; wherein the doped polycrystalline silicon layer and the doped amorphous silicon layer are different in conduction type.

Description

Technical Field

[0001] This disclosure relates to the field of solar cell technology, and in particular to a solar cell, a method for manufacturing the same, and an electrical device thereof. Background Technology

[0002] In Tunnel Oxide Passivated Contact (TOPCon) cells, a P-type doped polycrystalline silicon layer is formed on the front side. The passivation effect is poor and the contact characteristics are poor, which means that the photoelectric conversion efficiency of TOPCon cells still has some room for improvement compared to the theoretical efficiency.

[0003] Therefore, there is an urgent need to improve TOPCon cells to enhance their photoelectric conversion efficiency. Summary of the Invention

[0004] In view of this, the present disclosure provides a solar cell, a method for manufacturing the same, and an electrical device thereof.

[0005] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, this disclosure provides a solar cell, the solar cell comprising: a substrate having a first surface and a second surface disposed opposite to each other, the first surface including alternating first regions and second regions; a tunneling oxide layer and a doped polycrystalline silicon layer disposed on the first region of the first surface, the tunneling oxide layer being disposed between the first surface and the doped polycrystalline silicon layer; a first passivation layer including a first passivation sub-layer covering the doped polycrystalline silicon layer in the first region and a second passivation sub-layer covering the second region; an intrinsic amorphous silicon layer and a doped amorphous silicon layer disposed on the second surface, the intrinsic amorphous silicon layer being disposed between the second surface and the doped amorphous silicon layer; wherein the doped polycrystalline silicon layer and the doped amorphous silicon layer have different conductivity types.

[0007] In some embodiments, the solar cell further includes: a first antireflection layer covering the first passivation layer; and a first electrode penetrating the first antireflection layer and the first passivation sublayer and in contact with the doped polycrystalline silicon layer.

[0008] In some embodiments, the solar cell further includes: a second passivation layer covering the doped amorphous silicon layer; a second antireflection layer covering the second passivation layer; and a second electrode penetrating the second antireflection layer and the second passivation layer and in contact with the doped amorphous silicon layer.

[0009] In some embodiments, the substrate includes an N-type semiconductor substrate; the doped polycrystalline silicon layer includes an N-type doped polycrystalline silicon layer; and the doped amorphous silicon layer includes a P-type doped amorphous silicon layer.

[0010] In some embodiments, the thickness of the tunneling oxide layer is 0.5–3 nm; and the thickness of the doped polycrystalline silicon layer is 60–130 nm.

[0011] In some embodiments, the thickness of the intrinsic amorphous silicon layer is 5–9 nm; the thickness of the doped amorphous silicon layer is 30–40 nm.

[0012] In a second aspect, this disclosure provides a method for manufacturing a solar cell, the method comprising: providing a substrate; the substrate having a first surface and a second surface disposed opposite to each other, the first surface including alternating first regions and second regions; sequentially forming a tunneling oxide layer and a doped polycrystalline silicon layer on the first surface; patterning the doped polycrystalline silicon layer and the tunneling oxide layer to expose a second region in the first surface; sequentially forming an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the second surface; wherein the doped polycrystalline silicon layer and the doped amorphous silicon layer have different conductivity types; forming a first passivation layer on the first surface, the first passivation layer including a first passivation sublayer covering the doped polycrystalline silicon layer in the first region and a second passivation sublayer covering the second region.

[0013] In some embodiments, the step of sequentially forming an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the second surface includes: using a plasma-enhanced chemical vapor deposition process, introducing a silicon source gas and reacting to form the intrinsic amorphous silicon layer; and introducing a silicon source gas and a gas containing a dopant element and reacting to form the doped amorphous silicon layer.

[0014] In some embodiments, the temperature of the plasma-enhanced chemical vapor deposition process is 200–400°C.

[0015] In some embodiments, the method further includes: forming a second passivation layer on the second surface, the second passivation layer covering the doped amorphous silicon layer; forming a first antireflection layer on the first surface, the first antireflection layer covering the first passivation layer; and forming a second antireflection layer on the second surface, the second antireflection layer covering the second passivation layer.

[0016] In some embodiments, the method further includes: forming a first electrode that penetrates the first antireflection layer and the first passivation sublayer and is in contact with the doped polycrystalline silicon layer; and forming a second electrode that penetrates the second antireflection layer and the second passivation layer and is in contact with the doped amorphous silicon layer.

[0017] Thirdly, this disclosure provides an electrical device, the electrical device comprising: a solar cell as described in the first aspect of this disclosure.

[0018] This disclosure provides a solar cell, a method for manufacturing the same, and an electrical device thereof. In this disclosure, a tunneling oxide layer and a doped polycrystalline silicon layer are disposed on a first region of a first surface of a substrate (i.e., the front side of the substrate). A first passivation sublayer is disposed on the doped polycrystalline silicon layer, and a second passivation sublayer is disposed on a second region of the first surface of the substrate. The first and second passivation sublayers together form a first passivation layer. An intrinsic amorphous silicon layer and a doped amorphous silicon layer are disposed on a second surface of the substrate (i.e., the back side of the substrate). Thus, in the solar cell provided by this disclosure, the intrinsic amorphous silicon layer on the back side of the cell has high passivation characteristics, and the doped amorphous silicon layer has easy doping characteristics, which can reduce recombination on the back side of the cell. The front side of the cell employs a patterned tunneling oxide layer and a doped polycrystalline silicon layer, and a first passivation layer covering the first and second regions of the first surface is formed on the front side of the cell, which can increase the contact passivation characteristics of the front side of the cell, thereby improving the photoelectric conversion efficiency of the solar cell. Attached Figure Description

[0019] Figure 1 Cross-sectional views of tunneled oxide passivated contact cells provided for some examples;

[0020] Figure 2 Flowcharts for fabricating tunnel oxide passivated contact cells are provided for some examples.

[0021] Figure 3 Cross-sectional views of intrinsic thin-film heterojunction cells provided for some examples;

[0022] Figure 4 This is a schematic flowchart of the method for manufacturing solar cells provided in this disclosure;

[0023] Figure 5 A cross-sectional view of the solar cell provided in this disclosure;

[0024] Figure 6 The flowchart for manufacturing a solar cell provided in this disclosure;

[0025] Figure 7 A schematic diagram of the electrical device provided in this disclosure.

[0026] The figure includes: 100, TOPCon cell; 110, substrate; 111, first surface; 112, second surface; 120, tunneling oxide layer; 131, N-type doped polycrystalline silicon layer; 132, P-type doped polycrystalline silicon layer; 140, passivation layer; 151, first antireflection layer; 152, second antireflection layer; 161, first electrode; 162, second electrode; 300, HJT cell; 310, substrate; 311, first surface; 312, second surface; 321, first intrinsic amorphous silicon layer; 322, second intrinsic amorphous silicon layer; 331, P-type doped amorphous silicon layer; 332, N-type doped amorphous silicon layer; 341, first transparent layer. 342. Conductive layer; 351. First electrode; 352. Second electrode; 500. Solar cell; 510. Substrate; 511. First surface; 512. Second surface; 511a. First region; 511b. Second region; 520. Tunneling oxide layer; 530. Doped polycrystalline silicon layer; 540. First passivation layer; 541. First passivation sublayer; 542. Second passivation sublayer; 550. Intrinsic amorphous silicon layer; 560. Doped amorphous silicon layer; 570. Second passivation layer; 581. First antireflection layer; 582. Second antireflection layer; 591. First electrode; 592. Second electrode; 700. Electrical device. Detailed Implementation

[0027] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0028] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0029] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0031] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0033] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0034] In the field of photovoltaic technology, the rapid rise of N-type photovoltaic technology has become a focus of attention. With the continuous optimization of N-type photovoltaic technology, we are ushering in an era of low carbon emissions and high efficiency. Due to the limitations of traditional P-type photovoltaic technology in efficiency and manufacturing processes, it has been gradually phased out, driving the industry to turn to more advanced technologies. The penetration rate of N-type products with higher efficiency is rapidly increasing.

[0035] Among them, the advantage of TOPCon cell technology lies in the fact that both it and emitter-back passivated cell (PERC) use high-temperature processes and have high process compatibility. This technology is more favored by traditional cell manufacturers and can more effectively improve the conversion efficiency of photovoltaic cells. Taking M10 as an example, the current industry average efficiency of single-sided TOPCon cells has reached 24.9%, and the highest conversion efficiency of TOPCon in the laboratory has reached 26.1%, but there is still a lot of room for improvement compared to the theoretical efficiency of crystalline silicon cells. Furthermore, according to calculations by the authoritative testing organization ISFH, the theoretical limit efficiency of TOPCon cells is 28.7%, indicating that there is still significant room for improvement in the future.

[0036] Before introducing this disclosure, the various directions that may be involved in the following description are explained. A first direction (i.e., the X direction) and a second direction (i.e., the Y direction) intersect in a plane parallel to the base, and a third direction (i.e., the Z direction) is defined perpendicular to the base. In some embodiments, the X and Y directions may be perpendicular to each other, such that the X, Y, and Z directions are mutually perpendicular.

[0037] refer to Figure 1 , Figure 1 Cross-sectional views of tunneled oxide passivated contact cells are provided as examples. Figure 1As shown, the TOPCon cell 100 includes: a substrate 110 having a first surface 111 and a second surface 112 disposed opposite to each other; a P-type doped polysilicon layer 132, a passivation layer 140, and a first antireflection layer 151 sequentially disposed on the first surface 111; a plurality of first electrodes 161 sequentially penetrating the first antireflection layer 151 and the passivation layer 140 and contacting the P-type doped polysilicon layer 132; a tunneling oxide layer 120, an N-type doped polysilicon layer 131, and a second antireflection layer 152 sequentially disposed on the second surface 112; and a plurality of second electrodes 162 penetrating the second antireflection layer 152 and contacting the N-type doped polysilicon layer 131. The TOPCon cell 100 includes, along the Z-direction, a second antireflection layer 152, an N-type doped polysilicon layer 131, a tunneling oxide layer 120, a substrate 110, a P-type doped polysilicon layer 132, a passivation layer 140, and a first antireflection layer 151 sequentially stacked.

[0038] refer to Figure 2 , Figure 2 Flowcharts for fabricating tunneled oxide passivated contact cells are provided for some examples. For instance... Figure 2 As shown, in step S201, the front side is textured, that is, the front side of the substrate is surface treated to form a textured structure.

[0039] In step S202, a P-type doped polysilicon layer is formed on the front side of the substrate by a boron diffusion process. The boron-doped polysilicon layer can serve as a P-type doped polysilicon layer.

[0040] Currently, the boron diffusion process includes: introducing BCl3 into a quartz tube to react chemically with O2 to generate B2O3 (as shown in Formula 1), introducing N2 to distribute B2O3 on the surface of a substrate (e.g., a silicon wafer), and further reacting B2O3 with the substrate (e.g., a silicon wafer) to complete the boron diffusion process (as shown in Formula 2) and prepare a PN junction.

[0041] 4BCl3 + 3O2 → 2B2O3 + 6Cl2 (Equation 1)

[0042] 2B₂O₃ + 3Si → 4B + 3SiO₂ (Equation 2)

[0043] Because boron's solid solubility in silicon is lower than that of SiO2, high temperature and high flow rate conditions are required during the boron doping process. The high reaction temperature in the boron diffusion process shortens the furnace tube's lifespan and increases production costs. Furthermore, the B2O3 formed during the reaction is adhesive and adheres to the furnace tube surface, causing uneven stress and increasing the risk of breakage over prolonged use, further raising production costs. Therefore, forming a P-type doped polycrystalline silicon layer in TOPCon cells requires high temperature and high flow rate conditions, and the boron doping process requires temperatures exceeding 900℃, resulting in high equipment wear and operating costs.

[0044] In step S203, alkaline polishing is performed, that is, surface treatment is performed on the back side of the substrate to remove the diffusion layer formed on the back side and periphery of the substrate in the previous diffusion process, such as borosilicate glass (BSG).

[0045] In step S204, an N-type doped polysilicon layer is formed, that is, a tunneling oxide layer and an N-type doped polysilicon layer are formed on the back side of the substrate.

[0046] In step S205, annealing is performed, that is, the N-type doped polycrystalline silicon layer is annealed.

[0047] In step S206, RCA standard cleaning is performed, that is, the phospho-silicate glass (PSG) formed on the front and periphery of the substrate in the previous step is removed.

[0048] In step S207, a passivation layer is formed on the front side of the substrate, that is, a passivation layer covering a P-type doped polysilicon layer is formed. The material of the passivation layer can be, for example, aluminum oxide.

[0049] In step S208, a first antireflection layer is formed on the front side and a second antireflection layer is formed on the back side. That is, a first antireflection layer covering a passivation layer is formed on the front side of the substrate, and a second antireflection layer covering an N-type doped polysilicon layer is formed on the back side of the substrate. The materials of the first and second antireflection layers can be, for example, silicon nitride.

[0050] In step S209, screen printing sintering light injection is performed, that is, a first electrode is formed on the front side of the substrate and a second electrode is formed on the back side of the substrate.

[0051] In step S210, laser-assisted sintering is performed, that is, good ohmic contact is formed by high-temperature sintering.

[0052] In step S211, the batteries are sorted by test to classify them according to their different conversion efficiencies.

[0053] In summary, the process of forming a TOPCon cell involves first texturing and cleaning the front side of the substrate to form a textured structure, then introducing BCl3 for thermal diffusion to perform PN junction doping (i.e., forming a P-type doped polycrystalline silicon layer on the front side of the substrate), followed by polishing the back side of the substrate, depositing a tunneling passivation layer on the back side of the substrate (i.e., forming a tunneling oxide layer and an N-type doped polycrystalline silicon layer on the back side of the substrate), cleaning, depositing an aluminum oxide layer on the front side of the substrate for passivation, depositing silicon nitride layers on both the front and back sides of the substrate for passivation and light absorption, and finally printing and sintering to conduct current.

[0054] In the aforementioned TOPCon cells, the boron-doped polycrystalline silicon layer formed on the front side of the substrate not only has high equipment losses and operating costs, but also has poor passivation effect, severe Auger recombination on the front side, and poor contact characteristics, resulting in low photoelectric conversion efficiency of the TOPCon cells.

[0055] Therefore, there is an urgent need to improve TOPCon cells to enhance passivation and contact characteristics, reduce equipment losses and operating costs, and thereby improve the photoelectric conversion efficiency of solar cells.

[0056] Intrinsic thin-film (HJT) solar cells can achieve a conversion efficiency of up to 25.3%, which is relatively high. However, due to the high cost of target materials, pastes, and equipment, their cost-effectiveness is low and they have not yet achieved large-scale mass production.

[0057] refer to Figure 3 , Figure 3 Cross-sectional views of intrinsic thin-film heterojunction cells provided as examples. For instance... Figure 3 As shown, the HJT cell 300 includes: a substrate 310 having a first surface 311 and a second surface 312 disposed opposite to each other; a first intrinsic amorphous silicon layer 321, a P-type doped amorphous silicon layer 331, and a first transparent conductive layer 341 sequentially disposed on the first surface 311; a plurality of first electrodes 351 in contact with the first transparent conductive layer 341; a second intrinsic amorphous silicon layer 322, an N-type doped amorphous silicon layer 332, and a second transparent conductive layer 342 sequentially disposed on the second surface 312; and a plurality of second electrodes 352 in contact with the second transparent conductive layer 342. The HJT cell 300, along the Z-direction, includes the second transparent conductive layer 342, the N-type doped amorphous silicon layer 332, the second intrinsic amorphous silicon layer 322, the substrate 310, the first intrinsic amorphous silicon layer 321, the P-type doped amorphous silicon layer 331, and the first transparent conductive layer 341 sequentially stacked.

[0058] Given the high equipment losses and operating costs of TOPCon cells, the poor passivation effect and contact characteristics of the P-type doped polycrystalline silicon layer leading to low photoelectric conversion efficiency, and the high production cost of HJT cells, this disclosure provides a novel solar cell. A tunneling oxide layer, an N-type doped polycrystalline silicon layer, and a first passivation layer are formed on the front side of the substrate, while an intrinsic amorphous silicon layer and a P-type amorphous silicon layer are formed on the back side of the substrate. This allows for upgrades to existing TOPCon cell production lines, resulting in lower production costs and effectively improving the conversion efficiency of the solar cell.

[0059] refer to Figure 4 , Figure 4 This is a schematic flowchart illustrating the manufacturing method of the solar cell provided in this disclosure. Figure 4 As shown, this disclosure provides a method for manufacturing a solar cell, the method comprising:

[0060] Step S401: Provide a substrate; the substrate has a first surface and a second surface disposed opposite to each other, the first surface including alternating first regions and second regions;

[0061] Step S402: A tunneling oxide layer and a doped polysilicon layer are sequentially formed on the first surface;

[0062] Step S403: Pattern the doped polysilicon layer and the tunneling oxide layer to expose the second region in the first surface;

[0063] Step S404: An intrinsic amorphous silicon layer and a doped amorphous silicon layer are sequentially formed on the second surface; wherein the doped polycrystalline silicon layer and the doped amorphous silicon layer have different conductivity types;

[0064] Step S405: A first passivation layer is formed on the first surface. The first passivation layer includes a first passivation sublayer covering the doped polysilicon layer in the first region and a second passivation sublayer covering the second region.

[0065] Compared to TOPCon and HJT cells, this disclosure features a tunneling oxide layer and a doped polycrystalline silicon layer on a first region of the first surface of the substrate (i.e., the front side of the substrate). A first passivation sublayer is formed on the doped polycrystalline silicon layer, and a second passivation sublayer is formed on a second region of the first surface of the substrate. The first and second passivation sublayers together form a first passivation layer. An intrinsic amorphous silicon layer and a doped amorphous silicon layer are formed on the second surface of the substrate (i.e., the back side of the substrate). Thus, in the solar cell provided by this disclosure, the intrinsic amorphous silicon layer on the back side of the cell has high passivation characteristics, and the doped amorphous silicon layer has easy doping characteristics, which can reduce recombination on the back side of the cell. The front side of the cell uses a patterned tunneling oxide layer and a doped polycrystalline silicon layer, and a first passivation layer covering the first and second regions of the first surface is formed on the front side of the cell, which can increase the contact passivation characteristics of the front side of the cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0066] refer to Figure 5 As shown, Figure 5 This is a cross-sectional view of the solar cell provided in this disclosure. The following will be combined with... Figure 4 and Figure 5 The present disclosure provides a detailed description of the manufacturing method of the solar cell.

[0067] In this disclosure, in step S401, a substrate is provided; the substrate has a first surface and a second surface disposed opposite to each other, the first surface including alternating first regions and second regions.

[0068] like Figure 5 As shown, the substrate 510 has a first surface 511 and a second surface 512 disposed opposite to each other along its thickness direction (i.e., the Z direction). The first surface 511 may also be referred to as the front side of the substrate 510, and the second surface 512 may also be referred to as the back side of the substrate 510.

[0069] Here, the first surface 511 of the substrate 510 can be divided into a first region 511a and a second region 511b arranged alternately along the X direction. Both the first region 511a and the second region 511b are portions of the first surface 511. The difference between the first region 511a and the second region 511b lies in the different film structures subsequently formed on their surfaces. Electrodes will subsequently form at the corresponding positions in the first region 511a, while electrodes will not form at the corresponding positions in the second region 511b. In other words, the first region 511a in the first surface 511 can also be called the electrode contact region, and the second region 511b in the first surface 511 can also be called the non-electrode contact region. This disclosure does not impose any special limitation on the ratio between the area of ​​the first region 511a (or the second region 511b) and the area of ​​the first surface 511, and it can be flexibly selected according to the actual situation.

[0070] In some embodiments, the material of the substrate 510 may include a semiconductor material, such as silicon.

[0071] In some embodiments, substrate 510 may include an N-type semiconductor substrate or a P-type semiconductor substrate. In this embodiment, substrate 510 may be an N-type silicon substrate.

[0072] In this disclosure, in step S402, a tunneling oxide layer and a doped polycrystalline silicon layer are sequentially formed on the first surface.

[0073] like Figure 5 As shown, a tunneling oxide layer 520 and a doped polysilicon layer 530 are sequentially formed on the first surface 511 of the substrate 510. Figure 5 The diagram illustrates a cross-sectional view after patterning the doped polysilicon layer 530 and the tunneling oxide layer 520. It should be noted that before patterning, the tunneling oxide layer 520 simultaneously covers the first region 511a and the second region 511b in the first surface 511, and the doped polysilicon layer 530 covers the tunneling oxide layer 520. That is, at this time, the doped polysilicon layer 530 also simultaneously covers the tunneling oxide layer 520 above the first region 511a and the second region 511b in the first surface 511; wherein, the tunneling oxide layer 520 is located between the first surface 511 of the substrate 510 and the doped polysilicon layer 530.

[0074] In some embodiments, the material of the tunneling oxide layer 520 may include silicon oxide.

[0075] In some embodiments, the doped polysilicon layer 530 may include an N-type doped polysilicon layer or a P-type doped polysilicon layer. In this embodiment, the doped polysilicon layer 530 is an N-type doped polysilicon layer (N-Poly).

[0076] In some embodiments, the process of forming the tunnel oxide layer 520 and the doped polysilicon layer 530 may include a plasma-enhanced chemical vapor deposition (PECVD) process or a low-pressure chemical vapor deposition (LPCVD) process.

[0077] In some embodiments, a protective layer may also be formed on the doped polysilicon layer 530. Here, the thickness of the protective layer may be 3–8 nm.

[0078] In some embodiments, the thickness of the tunneling oxide layer 520 is 0.5 to 3 nm. Exemplarily, the thickness of the tunneling oxide layer 520 can be, for example, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm. By limiting the thickness of the tunneling oxide layer 520, the surface passivation effect can be improved.

[0079] In some embodiments, the thickness of the N-type doped polysilicon layer is 60–130 nm. Exemplarily, the thickness of the N-type doped polysilicon layer can be, for example, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, or 130 nm. By limiting the thickness of the N-type doped polysilicon layer, the field passivation effect can be improved, and parasitic absorption on the front side can be reduced.

[0080] In this disclosure, in step S403, the doped polysilicon layer and the tunneling oxide layer are patterned to expose a second region in the first surface.

[0081] like Figure 5 As shown, the doped polysilicon layer 530 and the tunnel oxide layer 520 are patterned to remove the doped polysilicon layer 530 and the tunnel oxide layer 520 covering the second region 511b in the first surface 511 and expose the second region 511b in the first surface 511, while retaining the doped polysilicon layer 530 and the tunnel oxide layer 520 covering the first region 511a in the first surface 511.

[0082] Here, the specific process for patterning the doped polysilicon layer and tunneling oxide layer in this disclosure is not particularly limited. It is sufficient to remove the doped polysilicon layer and tunneling oxide layer covering the second region while retaining the doped polysilicon layer and tunneling oxide layer covering the first region. Exemplarily, the patterning process can be, for example, laser processing, etching paste, or chemical methods.

[0083] In this disclosure, a tunneling oxide layer and a doped polysilicon layer are disposed on a first region in the first surface of the substrate to reduce light loss; and a first passivation sub-layer is formed on the first region and a second passivation sub-layer is disposed on a second region in the first surface of the substrate, wherein the first region is the contact region of the first electrode and the second region is the non-contact region of the first electrode, which can also improve the passivation effect.

[0084] In this disclosure, in step S404, an intrinsic amorphous silicon layer and a doped amorphous silicon layer are sequentially formed on the second surface; wherein the doped polycrystalline silicon layer and the doped amorphous silicon layer have different conductivity types.

[0085] like Figure 5As shown, an intrinsic amorphous silicon layer 550 and a doped amorphous silicon layer 560 are sequentially formed on the second surface 512 of the substrate 510. The different conductivity types of the doped polycrystalline silicon layer 530 and the doped amorphous silicon layer 560 can include: when the doped polycrystalline silicon layer 530 is an N-type doped polycrystalline silicon layer, the doped amorphous silicon layer 560 is a P-type doped amorphous silicon layer; when the doped polycrystalline silicon layer 530 is a P-type doped polycrystalline silicon layer, the doped amorphous silicon layer 560 is an N-type doped amorphous silicon layer.

[0086] Here, the intrinsic amorphous silicon layer 550 may include a hydrogenated intrinsic amorphous silicon layer, which can be represented as i:Si:H. In this embodiment of the present disclosure, the intrinsic amorphous silicon layer 550 is a hydrogenated intrinsic amorphous silicon layer (i:Si:H).

[0087] Here, the doped amorphous silicon layer 560 may include a doped amorphous silicon layer or a doped microcrystalline silicon layer. The doped amorphous silicon layer may include a hydrogenated doped amorphous silicon layer, which can be represented as α:Si:H; the doped microcrystalline silicon layer may also include a hydrogenated doped microcrystalline silicon layer, which can be represented as μ:Si:H.

[0088] In some embodiments, the doped amorphous silicon layer 560 may include an N-type doped amorphous silicon layer or a P-type doped amorphous silicon layer, and the doped microcrystalline silicon layer may include an N-type doped microcrystalline silicon layer or a P-type doped microcrystalline silicon layer, wherein the P-type doped microcrystalline silicon layer may be represented as P-μ:Si:H. In this embodiment of the present disclosure, the doped amorphous silicon layer 560 is a P-type doped microcrystalline silicon layer (P-μ:Si:H).

[0089] In some embodiments, the process of forming the intrinsic amorphous silicon layer 550 and the doped amorphous silicon layer 560 may include a PECVD process.

[0090] In some embodiments, the thickness of the intrinsic amorphous silicon layer 550 is 5 to 9 nm. Exemplarily, the thickness of the intrinsic amorphous silicon layer 550 may be, for example, 5 nm, 6 nm, 7 nm, 8 nm, or 9 nm.

[0091] In some embodiments, the thickness of the p-type doped amorphous silicon layer is 30–40 nm. Exemplarily, the thickness of the p-type doped amorphous silicon layer may be, for example, 30 nm, 32 nm, 34 nm, 36 nm, 38 nm, or 40 nm.

[0092] In some embodiments, step S404 includes: using a PECVD process, introducing a silicon source gas to react and form an intrinsic amorphous silicon layer 550; introducing a silicon source gas and a gas containing doped elements to react and form a doped amorphous silicon layer 560.

[0093] Here, the PECVD process can be used to prepare the PN junction by ionizing SiH4 and B2H6. The substances participating in the chemical reaction are gases, as shown in Equations 3 and 4. First, SiH4 is used as the silicon source gas to ionize SiH4 and H2 to deposit an intrinsic amorphous silicon layer on the second surface of the substrate. As shown in Equations 3, 4 and 5, SiH4 is used as the silicon source gas and B2H6 is used as the gas containing dopant elements to ionize SiH4, B2H6 and H2 to deposit a P-type doped amorphous silicon layer on the intrinsic amorphous silicon layer.

[0094] SiH4→Si+4H + (Equation 3)

[0095] H2→2H + (Equation 4)

[0096] B2H6→2B+3H2 (Equation 5)

[0097] In some embodiments, the temperature of the PECVD process is 200–400°C. Exemplarily, the temperature for forming a P-type doped amorphous silicon layer is 220°C, 240°C, 260°C, 280°C, 300°C, 320°C, 340°C, 360°C, or 380°C.

[0098] Compared to TOPCon cells, forming a boron-doped polycrystalline silicon layer as a P-type doped polycrystalline silicon layer on the front side of the cell via a boron diffusion process requires controlling high temperature and high flow rate conditions, resulting in higher production costs and increased wear and maintenance costs for the furnace equipment. In this disclosure, the PECVD process can deposit and form both intrinsic amorphous silicon and P-type doped amorphous silicon layers at 200–400°C. This lower deposition temperature and reduced equipment wear and maintenance costs effectively lower production costs. Furthermore, the intrinsic amorphous silicon layer on the back side of the cell exhibits high passivation characteristics, and the doped amorphous silicon layer is easily doped, reducing recombination on the back side of the cell and thus improving the photoelectric conversion efficiency of the solar cell.

[0099] In this disclosure, in step S405, a first passivation layer 540 is formed on the first surface 511. The first passivation layer 540 includes a first passivation sublayer 541 covering the doped polysilicon layer 530 in the first region 511a and a second passivation sublayer 542 covering the second region 511b.

[0100] like Figure 5As shown, a first passivation layer 540 is formed on the first surface 511 of the substrate 510. At this time, a tunneling oxide layer 520 and a doped polysilicon layer 530 are formed on the first region 511a of the first surface 511 of the substrate 510, and the second region 511b of the first surface 511 of the substrate 510 is exposed. Therefore, a portion of the first passivation layer 540 covers the top surface of the doped polysilicon layer 530 on the first region 511a, and this portion of the first passivation layer is the first passivation sublayer 541; a portion of the first passivation layer 540 covers the second region 511b and the sidewalls of the patterned tunneling oxide layer 520 and the doped polysilicon layer 530, and this portion of the first passivation layer 540 is the second passivation sublayer 542. The first passivation sublayer 541 is in contact with the doped polysilicon layer 530, the second passivation sublayer 542 is in contact with the second region 511b in the first surface 511 of the substrate 510, and the tunneling oxide layer 520 is in contact with the sidewall of the doped polysilicon layer 530.

[0101] In some embodiments, the material of the first passivation layer 540 may include aluminum oxide.

[0102] In some embodiments, the thickness of the first passivation layer 540 is 3 to 5 nm. For example, the thickness of the first passivation layer 540 is 3 nm, 4 nm, or 5 nm.

[0103] like Figure 5 As shown, a second passivation layer 570 is formed on the second surface 512 of the substrate 510. At this time, an intrinsic amorphous silicon layer 550 and a doped amorphous silicon layer 560 are formed on the second surface 512 of the substrate 510. Therefore, the second passivation layer 570 covers the doped amorphous silicon layer 560, that is, the second passivation layer 570 and the doped amorphous silicon layer 560 are in contact.

[0104] In some embodiments, the material of the second passivation layer 570 may include aluminum oxide.

[0105] In some embodiments, the thickness of the second passivation layer 570 is 3 to 5 nm. For example, the thickness of the second passivation layer 570 is 3 nm, 4 nm, or 5 nm.

[0106] In some embodiments, the process of forming the first passivation layer 540 and the second passivation layer 570 may include atomic layer deposition (ALD).

[0107] like Figure 5As shown, a first antireflection layer 581 is formed on the first surface 511 of the substrate 510. The first antireflection layer 581 covers the first passivation layer 540, that is, the first antireflection layer 581, the first passivation sublayer 541, and the second passivation sublayer 542 are all in contact. At this time, the first antireflection layer 581 simultaneously covers the first region 511a and the second region 511b in the first surface 510. A second antireflection layer 582 is formed on the second surface 512. The second antireflection layer 582 covers the second passivation layer 570, that is, the second antireflection layer 582 and the second passivation layer 570 are in contact.

[0108] In this disclosure, a first passivation layer and a first antireflection layer are formed on a first surface of the substrate, which can improve the passivation effect on the first surface of the substrate; a second passivation layer and a second antireflection layer are formed on a second surface of the substrate, which can improve the passivation effect on the second surface of the substrate.

[0109] In some embodiments, the materials of the first antireflection layer 581 and the second antireflection layer 582 may include silicon nitride.

[0110] In some embodiments, the thickness of the first antireflective layer 581 is 70–90 nm. For example, the thickness of the first antireflective layer 581 is 70 nm, 75 nm, 80 nm, 85 nm, or 90 nm.

[0111] In some embodiments, the refractive index of the first antireflection layer 581 is 2.1 to 2.2.

[0112] In some embodiments, the thickness of the second antireflective layer 582 is 90–110 nm. For example, the thickness of the second antireflective layer 582 is 90 nm, 95 nm, 100 nm, 105 nm, or 110 nm.

[0113] In some embodiments, the refractive index of the second antireflection layer 582 is 2.2 to 2.3.

[0114] In HJT solar cells, transparent conductive layers are formed on both the front and back sides to reduce the series resistance. However, the transparent conductive layer contains indium, and the material is primarily imported, resulting in high costs for its formation. This disclosure eliminates the need for transparent conductive layers on both the front and back sides of the solar cell, thereby reducing manufacturing costs.

[0115] like Figure 5 As shown, a first contact hole is formed that penetrates the first antireflection layer 581 and the first passivation sublayer 541 and exposes the doped polycrystalline silicon layer 530, and a second contact hole is formed that penetrates the second antireflection layer 582 and the second passivation layer 570 and exposes the doped amorphous silicon layer 560; a first electrode 591 is formed in the first contact hole, and a second electrode 592 is formed in the second contact hole.

[0116] Here, a laser can be used to create openings in the first antireflection layer 581 and the first passivation sublayer 541 to form a first contact hole, and a laser can be used to create openings in the second antireflection layer 582 and the second passivation layer 570 to form a second contact hole.

[0117] In some embodiments, the wavelength of the laser can be 300–1100 nm, and the laser spot size can be 50–100 μm.

[0118] Here, screen printing of a front metallization pattern can be performed to form the first electrode 591, and screen printing of a back metallization pattern can be performed to form the second electrode 592.

[0119] In some embodiments, the dimension of the first electrode along the X direction is less than or equal to the dimension of the patterned doped polysilicon layer 530 along the X direction.

[0120] refer to Figure 6 , Figure 6 This is a flowchart illustrating the manufacturing process of a solar cell, as provided in this disclosure. Figure 6 As shown, in step S601, the front side is texturized.

[0121] Before forming the film structure on the front side of the substrate, the front side of the substrate needs to be cleaned. For example, KOH or NaOH can be used to clean the front side of the substrate to remove dirt and impurities. Simultaneously, a textured surface structure (i.e., a pyramid structure) needs to be formed on the front side of the substrate to reduce the reflection of incident light, thereby improving the photoelectric conversion efficiency of the solar cell.

[0122] In some embodiments, after the front texturing step, the weight of the substrate is reduced by 0.2 to 0.4 g.

[0123] In some embodiments, after the front-side texturing step, the reflectivity of the front side of the substrate is 8-10%, and the size of its texturing structure is 1.4-1.8 μm, and the height is 0.8-1.2 μm.

[0124] like Figure 6 As shown, in step S602, an N-type doped polycrystalline silicon layer is formed.

[0125] Here, PECVD or LPCVD processes can be used to form a tunneling oxide layer and an N-type doped polysilicon layer on the front side of the substrate. Considering that the front side of the substrate has a textured structure, compared to forming the tunneling oxide layer and N-type doped polysilicon layer on the back side of the substrate in TOPCon cells, the overall ventilation volume required to form the tunneling oxide layer and N-type doped polysilicon layer on the front side of the substrate needs to be increased.

[0126] In some embodiments, a protective layer may be formed on the front side of the substrate, the protective layer covering an N-type doped polysilicon layer.

[0127] like Figure 6 As shown, in step S603, annealing occurs.

[0128] Here, the N-type doped polycrystalline silicon layer needs to be annealed. In an atmosphere containing a small amount of oxygen, the N-type doped polycrystalline silicon layer is crystallized and annealed to form voids that tunnel through the oxide layer, forming effective internal expansion and completing the field passivation of the substrate. The sheet resistance after annealing is 25 to 65 Ω / sq.

[0129] In some embodiments, the doping concentration of the N-type doped polysilicon layer is 1E+20 to 8E+20N / cm². 3 .

[0130] In some embodiments, the doping depth of the N-type doped polysilicon layer is 40–110 nm.

[0131] like Figure 6 As shown, in step S604, the front side is patterned.

[0132] Here, the N-type doped polysilicon layer and tunneling oxide layer formed on the front side of the substrate can be patterned using processes including but not limited to laser processing, etching paste, or chemical methods to remove the N-type doped polysilicon layer and tunneling oxide layer in the non-electrode contact area. This disclosure does not specifically limit the front-side patterning process; it is sufficient to remove the tunneling oxide layer and N-type doped polysilicon layer covering the second region while retaining the tunneling oxide layer and N-type doped polysilicon layer covering the first region.

[0133] like Figure 6 As shown, in step S605, the back side is texturized.

[0134] Here, before forming the film structure on the back side of the substrate, the back side of the substrate needs to be cleaned to remove the protective layer and form a textured structure. For example, HF can be used to remove the protective layer on the back side of the substrate, and KOH or NaOH can be used to clean the back side of the substrate to remove dirt and impurities and form a textured structure.

[0135] In some embodiments, after the back-side texturing step, the weight of the substrate is reduced by 0.1 to 0.2 g.

[0136] In some embodiments, after the back-side texturing step, the reflectivity of the back side of the substrate is 12-14%, and the size of its texturing structure is 2.4-3.8 μm, and the height is 0.8-1.2 μm.

[0137] like Figure 6 As shown, in step S606, the intrinsic amorphous silicon layer and the P-type amorphous silicon layer are...

[0138] Here, a backplane PECVD process can be performed to form an intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the back side of the substrate.

[0139] like Figure 6 As shown, in step S607, RCA standard cleaning is performed.

[0140] Here, the PSG formed on the front and around the substrate in the previous step can be removed.

[0141] like Figure 6 As shown, in step S608, a double-sided passivation layer is applied.

[0142] Here, a first passivation layer can be formed on the front side of the substrate, and a second passivation layer can be formed on the back side of the substrate.

[0143] like Figure 6 As shown, in step S609, there is a first anti-reflection layer on the front and a second anti-reflection layer on the back.

[0144] Here, a first antireflective layer can be formed on the front side of the substrate, and a second antireflective layer can be formed on the back side of the substrate.

[0145] like Figure 6 As shown, in step S610, double-sided laser grooving is performed.

[0146] Here, a laser is used to create openings in the first antireflective layer and the first passivation layer on the front side of the substrate to form a first contact hole, and a laser is used to create openings in the second antireflective layer and the second passivation layer on the back side of the substrate to form a second contact hole.

[0147] like Figure 6 As shown, in step S611, screen printing sintering light injection is performed.

[0148] Here, a front-side metallization pattern is screen-printed on the front side of the substrate to form the first electrode, and a back-side metallization pattern is screen-printed on the back side of the substrate to form the second electrode. After low-temperature sintering, light injection is performed to passivate the interior of the solar cell.

[0149] like Figure 6 As shown, in step S612, the sorting test is performed.

[0150] like Figure 5As shown, this disclosure provides a solar cell 500, which includes: a substrate 510 having a first surface 511 and a second surface 512 disposed opposite to each other; the first surface 511 including alternating first regions 511a and second regions 511b; a tunneling oxide layer 520 and a doped polycrystalline silicon layer 530 located on the first region 511a of the first surface 511, the tunneling oxide layer 520 being disposed between the first surface 511 and the doped polycrystalline silicon layer 530; a first passivation layer 540 including a first passivation sub-layer 541 covering the doped polycrystalline silicon layer 530 in the first region 511a and a second passivation sub-layer 542 covering the second region 511b; an intrinsic amorphous silicon layer 550 and a doped amorphous silicon layer 560 located on the second surface 512, the intrinsic amorphous silicon layer 550 being disposed between the second surface 512 and the doped amorphous silicon layer 560; wherein the doped polycrystalline silicon layer 530 and the doped amorphous silicon layer 560 have different conductivity types.

[0151] In some embodiments, the solar cell 500 further includes: a first antireflection layer 581 covering the first passivation layer 540; and a first electrode 591 penetrating the first antireflection layer 581 and the first passivation sublayer 541 and in contact with the doped polycrystalline silicon layer 530.

[0152] In some embodiments, the solar cell 500 further includes: a second passivation layer 570 covering a doped amorphous silicon layer 560; a second antireflection layer 582 covering the second passivation layer 570; and a second electrode 592 penetrating the second antireflection layer 582 and the second passivation layer 570 and in contact with the doped amorphous silicon layer 560.

[0153] In some embodiments, the substrate 510 includes an N-type semiconductor substrate; the doped polysilicon layer 530 includes an N-type doped polysilicon layer; and the doped amorphous silicon layer 560 includes a P-type doped amorphous silicon layer.

[0154] In some embodiments, the thickness of the tunneling oxide layer 520 is 0.5–3 nm; the thickness of the doped polysilicon layer 530 is 60–130 nm.

[0155] In some embodiments, the thickness of the intrinsic amorphous silicon layer 550 is 5–9 nm; the thickness of the doped amorphous silicon layer 560 is 30–40 nm.

[0156] refer to Figure 7 , Figure 7 This is a schematic diagram of the electrical installation provided in this disclosure. Figure 7 As shown, this disclosure provides an electrical device 700, which includes a solar cell 500 as described in the above technical solution.

[0157] Here, solar cells can be used as a power source for electrical devices or as energy storage units for electrical devices. Electrical devices can include, but are not limited to, mobile devices (such as mobile phones, laptops, etc.), electric vehicles (such as pure electric vehicles, hybrid electric vehicles, plug-in hybrid electric vehicles, electric bicycles, electric scooters, electric golf carts, electric trucks, etc.), electric trains, ships and satellites, energy storage systems, etc.

[0158] Example

[0159] The following describes embodiments of this application. The embodiments described below are exemplary and are only used to explain this application, and should not be construed as limiting this application. Where specific techniques or conditions are not specified in the embodiments, they are performed according to the techniques or conditions described in the literature in this field or according to the product instructions. Reagents or instruments used, unless otherwise specified, are all conventional products that can be obtained commercially.

[0160] Example 1

[0161] The steps for preparing the solar cell of Example 1 are as follows:

[0162] 1. Texturing: The silicon wafer surface is cleaned and impurities are removed using KOH, and the surface structure is completed on the front side.

[0163] 2. The front-side SiO2-N-Poly deposition was completed using the PECVD method. The thickness of the front-side tunneling oxide layer SiO2 was 1.7 nm, the thickness of the N-Poly layer was 90 nm, and the thickness of the protective layer was 5.5 nm.

[0164] 3. Annealing of the silicon wafer was performed in a nitrogen atmosphere at a flow rate of 7500 sccm and a temperature of 900℃ to complete the crystallization annealing of N-Poly, forming tunneling oxide layer voids, achieving effective internal expansion, and completing the field passivation of the substrate. The sheet resistance after annealing was 45 Ω / sq, and the doping concentration measured by ECV was 4.5E+20N / cm. 3 The doping depth is 75nm;

[0165] 4. Perform patterning treatment on the front side of SiO2-N-Poly, retain 70μm wide N-Poly in the gate contact area to ensure electrode contact, remove N-Poly in non-gate area and tunnel oxide layer SiO2 to reduce light shading loss.

[0166] 5. Texturing and cleaning: HF is used to remove the back-side protective layer, KOH is used to etch the back-side layer, and texturing is performed on the back side. The weight is reduced by 0.15g, the reflectivity is 13%, the texture size is 3.2μm, and the height is 1.0μm.

[0167] 6. Perform backplane PECVD with an intrinsic amorphous silicon layer thickness of 7nm and a P-type doped amorphous silicon layer thickness of 35nm.

[0168] 7. Deposit alumina on both the front and back sides, with an alumina thickness of 4 nm;

[0169] 8. Deposit silicon nitride on the front side, with a thickness of 80 nm and a refractive index of 2.15;

[0170] 9. Deposit silicon nitride on the back side, with a thickness of 100 nm and a refractive index of 2.25;

[0171] 10. Make openings for the front and back silicon nitride aluminum oxide lasers to ensure good contact of the electrodes. Use a 650nm wavelength laser with a spot size of 90μm.

[0172] 11. Perform screen printing and drying of the back metallization pattern, screen printing of the front metallization pattern, low-temperature sintering, light injection, and passivation of the cell interior.

[0173] 12. Testing and sorting.

[0174] Comparative Example 1

[0175] The steps for preparing the solar cell of Comparative Example 1 are as follows:

[0176] 1. Texturing: This process removes damage and prepares the surface structure of the silicon wafer, resulting in a weight reduction of 0.28g, a reflectivity of 10%, a textured surface size of 1.4μm, and a texture height of 1.1μm.

[0177] 2. Boron diffusion: BCl3 is introduced into a tube furnace to complete the boron doping of the substrate, forming a front-side PN junction with a sheet resistance of 250 Ω / sq and a doping concentration of 5E+18N / cm. 3 The junction depth is 1.0 μm;

[0178] 3. Alkali polishing: First, use HF to remove BSG from the edges and back side, then use KOH to etch the edges and back side, keeping the reflectivity of the back side at 43%.

[0179] 4. Tunneling oxide layer SiO2 and N-Poly: N2O is ionized using PECVD to form a 1.5nm tunneling oxide layer on the back side. SiH4 and PH3 are ionized to form N-Poly with a thickness of 110nm. N2O and SiH4 are ionized to form a silicon dioxide protective layer with a thickness of 6nm.

[0180] 5. Perform nitrogen annealing treatment. After annealing, the sheet resistance is 30 Ω / sq, and the surface concentration is 5E+19N / cm. 3 The thickness is 100nm;

[0181] 6. RCA cleaning, HF for front BSG removal, NaOH / KOH for front N-Poly removal, and HF for front BSG and back protective layer removal.

[0182] 7. Front-side alumina, with an alumina thickness of 8nm;

[0183] 8. The front-side silicon nitride thickness is 78nm, and the refractive index is 2.1;

[0184] 9. The back side silicon nitride thickness is 88nm, and the refractive index is 2.2;

[0185] 10. Screen printing and sintering;

[0186] 11. Laser-assisted sintering;

[0187] 12. Testing and sorting.

[0188] Test case

[0189] Standard Test Conditions (STC) are the internationally recognized benchmark for solar cell performance testing. The testing machine is a Halm IV (Cetispv-xf-tube type) tester, and the test parameters include the following aspects:

[0190] (1) Light intensity: The solar radiation intensity is 1000 watts per square meter (W / m2), or equivalent to 100 mW / cm2.

[0191] (2) Temperature: The cell temperature is 25℃.

[0192] (3) Spectral distribution: The spectral distribution must meet the AM1.5G standard, which is to simulate the spectral characteristics of sunlight passing through the atmosphere to reach the ground.

[0193] Table 1 shows the test results for Comparative Example 1 and Example 1.

[0194]

[0195] As shown in Table 1, compared to the TOPCon cell provided in Comparative Example 1, the solar cell provided in Example 1 has a higher photoelectric conversion efficiency (Eta), which is 1.3% higher. Comparative Example 1 shows improvements in open-circuit voltage (Uoc), short-circuit current (Isc), fill factor (FF), and parallel resistance (RshuntDfDr), while the series resistance (RserLfDf) shows no significant change. The solar cell provided in this disclosure can be upgraded from existing TOPCon cell lines, resulting in low equipment procurement costs; the process temperature is lower, leading to less equipment loss.

[0196] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this disclosure. The sequence numbers of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0197] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A solar cell, characterized in that, The solar cell (500) includes: The substrate (510) has a first surface (511) and a second surface (512) disposed opposite to each other, the first surface (511) including an alternately arranged first region (511a) and a second region (511b); A tunneling oxide layer (520) and a doped polysilicon layer (530) are located on a first region (511a) in the first surface (511), wherein the tunneling oxide layer (520) is disposed between the first surface (511) and the doped polysilicon layer (530). The first passivation layer (540) includes a first passivation sublayer (541) covering the doped polysilicon layer (530) in the first region (511a) and a second passivation sublayer (542) covering the second region (511b); An intrinsic amorphous silicon layer (550) and a doped amorphous silicon layer (560) are located on the second surface (512), wherein the intrinsic amorphous silicon layer (550) is disposed between the second surface (512) and the doped amorphous silicon layer (560); wherein the doped polycrystalline silicon layer (530) and the doped amorphous silicon layer (560) have different conductivity types.

2. The solar cell according to claim 1, characterized in that, The solar cell (500) also includes: A first antireflection layer (581) covering the first passivation layer (540); A first electrode (591) that penetrates the first antireflection layer (581) and the first passivation sublayer (541) and is in contact with the doped polysilicon layer (530).

3. The solar cell according to claim 1, characterized in that, The solar cell (500) also includes: A second passivation layer (570) covering the doped amorphous silicon layer (560); A second antireflection layer (582) covering the second passivation layer (570); A second electrode (592) that penetrates the second antireflection layer (582) and the second passivation layer (570) and is in contact with the doped amorphous silicon layer (560).

4. The solar cell according to claim 1, characterized in that, The substrate (510) includes an N-type semiconductor substrate; the doped polycrystalline silicon layer (530) includes an N-type doped polycrystalline silicon layer; and the doped amorphous silicon layer (560) includes a P-type doped amorphous silicon layer.

5. The solar cell according to claim 1, 2, or 4, characterized in that, The thickness of the tunneling oxide layer (520) is 0.5–3 nm; the thickness of the doped polycrystalline silicon layer (530) is 60–130 nm.

6. The solar cell according to claim 1, 2, or 4, characterized in that, The thickness of the intrinsic amorphous silicon layer (550) is 5-9 nm; the thickness of the doped amorphous silicon layer (560) is 30-40 nm.

7. A method for manufacturing a solar cell, characterized in that, The method includes: A substrate (510) is provided; the substrate (510) has a first surface (511) and a second surface (512) disposed opposite to each other, the first surface (511) including an alternately arranged first region (511a) and a second region (511b); A tunneling oxide layer (520) and a doped polycrystalline silicon layer (530) are sequentially formed on the first surface (511); The doped polysilicon layer (530) and the tunneling oxide layer (520) are patterned to expose the second region (511b) in the first surface (511); An intrinsic amorphous silicon layer (550) and a doped amorphous silicon layer (560) are sequentially formed on the second surface (512); wherein the doped polycrystalline silicon layer (530) and the doped amorphous silicon layer (560) have different conductivity types. A first passivation layer (540) is formed on the first surface (511), the first passivation layer (540) including a first passivation sublayer (541) covering the doped polysilicon layer (530) in the first region (511a) and a second passivation sublayer (542) covering the second region (511b).

8. The manufacturing method according to claim 7, characterized in that, The step of sequentially forming an intrinsic amorphous silicon layer (550) and a doped amorphous silicon layer (560) on the second surface (512) includes: The intrinsic amorphous silicon layer (550) is formed by introducing silicon source gas using a plasma-enhanced chemical vapor deposition process. A silicon source gas and a gas containing doped elements are introduced to react and form the doped amorphous silicon layer (560).

9. The manufacturing method according to claim 8, characterized in that, The temperature of the plasma-enhanced chemical vapor deposition process is 200–400°C.

10. The manufacturing method according to claim 7, 8, or 9, characterized in that, The method further includes: A second passivation layer (570) is formed on the second surface (512), the second passivation layer (570) covering the doped amorphous silicon layer (560); A first antireflection layer (581) is formed on the first surface (511), and the first antireflection layer (581) covers the first passivation layer (540); A second antireflection layer (582) is formed on the second surface (512), and the second antireflection layer (582) covers the second passivation layer (570).

11. The manufacturing method according to claim 10, characterized in that, The method further includes: A first electrode (591) is formed that penetrates the first antireflection layer (581) and the first passivation sublayer (541) and is in contact with the doped polysilicon layer (530); A second electrode (592) is formed that penetrates the second antireflection layer (582) and the second passivation layer (570) and is in contact with the doped amorphous silicon layer (560).

12. An electrical appliance, characterized in that, The electrical device (700) includes: a solar cell (500) as claimed in any one of claims 1 to 6.

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