Solar cell and photovoltaic module

Abstract

The invention provides a solar cell and a photovoltaic module, and belongs to the technical field of semiconductors. The solar cell comprises a semiconductor substrate which comprises a first surface and a second surface which are opposite to each other, the first surface comprises first areas which are distributed at intervals along a first direction, interval areas are arranged between adjacent first areas, each interval area is provided with a first texture structure, and the side surface is provided with a fourth texture structure; the first doped conductive layer is located on a first region of the semiconductor substrate, and the first region is provided with a second texture structure; the passivation layer is located on the surface of the spacer region and located on the surface of at least one of the following structures: the second surface, the side surface and the surface, away from the semiconductor substrate, of the first doped conductive layer; and a first electrode on the first doped conductive layer in electrical contact with the first doped conductive layer, wherein the height of the first texture structure is smaller than that of the second texture structure, and / or the surface size of the first texture structure is larger than that of the second texture structure.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, specifically to a solar cell and a photovoltaic module. Background Technology

[0002] When a solar cell is working, light enters the semiconductor substrate, generating electron-hole pairs. Favorable electron-hole pairs are separated by carriers, causing electrons to accumulate near the negative electrode and holes to accumulate near the positive electrode. By connecting the positive and negative electrodes to an external circuit, current can be output, realizing photoelectric conversion.

[0003] With the development of solar cell technology, higher requirements have been placed on the photoelectric conversion efficiency of solar cells, and there is still room for further improvement in the structure of solar cells. Summary of the Invention

[0004] In view of the above, in order to at least partially solve at least one of the aforementioned technical problems, this application provides a solar cell and a photovoltaic module.

[0005] To achieve the above objectives, the technical solution of this application is as follows:

[0006] According to one embodiment of this application, a solar cell is provided, comprising: a semiconductor substrate including opposing first surfaces, second surfaces, and a side surface connected between the first and second surfaces; the first surface including first regions spaced apart along a first direction, with spacer regions between adjacent first regions, the spacer regions having a first textured structure; and the side surface having a fourth textured structure; a first doped conductive layer located on the first region of the semiconductor substrate, the first region having a second textured structure; a passivation layer located on the surface of the spacer region and on at least one of the following structural surfaces: the second surface, the side surface, and the surface of the first doped conductive layer away from the semiconductor substrate; and a first electrode located on the first doped conductive layer and in electrical contact with the first doped conductive layer; wherein the height of the first textured structure is less than the height of the second textured structure, and / or the surface size of the first textured structure is greater than the surface size of the second textured structure, and / or the surface size of the fourth textured structure is greater than the surface size of the first textured structure.

[0007] In one alternative implementation, the height of the fourth texture structure is less than the height of the second texture structure.

[0008] In one alternative implementation, the height of the fourth texture structure is greater than the height of the first texture structure.

[0009] In one alternative implementation, a portion of the first texture structure is arranged in stripes along the extension direction of the first region, and a portion of the second texture structure is arranged in stripes along the extension direction of the first region.

[0010] In one alternative implementation, the interval region includes a plurality of first sub-regions and a plurality of second sub-regions, the first sub-regions and the second sub-regions being alternately arranged along a second direction, the second direction intersecting the first direction; the first sub-regions having a third texture structure, and the second sub-regions having a first texture structure; the height of the first texture structure is less than the height of the third texture structure, and / or the surface size of the first texture structure is greater than the surface size of the third texture structure.

[0011] In one alternative embodiment, the spacing region includes a plurality of first sub-regions and a plurality of second sub-regions, the first sub-regions and the second sub-regions being alternately arranged along a second direction, the second direction intersecting the first direction; the first sub-regions have a third texture structure, and the second sub-regions have a first texture structure; the third texture structures partially overlap in the first sub-regions, and along the direction away from the surface of the first sub-regions, the distance between the bottom surface of the outermost third texture structure and the bottom surface of its adjacent third texture structure is less than or equal to 2 μm.

[0012] In one alternative implementation, the height of the second texture structure is less than the height of the third texture structure.

[0013] In one alternative embodiment, the surface size of the first texture structure ranges from 10 to 25 μm; or, the surface size of the second texture structure ranges from 5 to 15 μm; or, the surface size of the third texture structure ranges from 5 to 15 μm; or, the surface size of the fourth texture structure ranges from 20 to 40 μm.

[0014] In one alternative embodiment, the spacing region includes a plurality of first sub-regions and a plurality of second sub-regions, the first sub-regions and the second sub-regions being alternately arranged along a second direction, the second direction intersecting the first direction; the first sub-regions have a third texture structure, and the second sub-regions have a first texture structure; along the second direction, the width of the first sub-region is less than or equal to 400 μm, and / or the spacing between adjacent first sub-regions is 20 μm to 400 μm.

[0015] In one optional implementation, the interval region includes a plurality of first sub-regions and a plurality of second sub-regions; the first sub-regions have a third texture structure, the second sub-regions have a first texture structure, the first and second sub-regions are alternately arranged along a second direction, and the second direction intersects the first direction; the height of the first texture structure is less than the height of the third texture structure, and / or, the surface size of the first texture structure is greater than the surface size of the third texture structure; the width of the first sub-region accounts for a proportion greater than or equal to 20% and less than or equal to 70% of the sum of the width of the first sub-region and the spacing between adjacent first sub-regions; and / or, the area of ​​the first sub-region accounts for a proportion greater than or equal to 20% and less than or equal to 70% of the area of ​​the interval region.

[0016] In one alternative implementation, along the thickness direction of the semiconductor substrate, the surface of the spacer region is closer to the second surface than the surface of the first region.

[0017] In one alternative implementation, the height difference between the surface of the first region and the surface of the spacer region is 1 μm to 5 μm.

[0018] In one alternative embodiment, the first surface further includes a transition region located between the first region and the interval region; wherein the transition region has a raised structure, the one-dimensional dimension of which is different from the one-dimensional dimension of both the first texture structure and the second texture structure.

[0019] In one alternative embodiment, the width of the transition region along the first direction is 1 μm to 50 μm; and / or, along the first direction, the transition region has a protruding end that protrudes toward the spacer region and a recessed end that is recessed away from the spacer region, the distance between the protruding end and the recessed end being less than or equal to 50 μm; and / or, the height of the surface of the transition region is different from the height of the surface of the spacer region and the surface of the first region.

[0020] In one alternative embodiment, the transition region bends and extends into a plurality of serrated structures along a second direction intersecting the first direction; wherein, along the second direction, the length of the serrated structure is less than or equal to 200 μm; and / or, at the recessed end of the serrated structure that is recessed away from the spacer region, the angle formed by the extension direction of the serrated structure and the extension direction of the first doped conductive layer is a first serrated angle, the first serrated angle being less than or equal to 30°; and / or, at the recessed end of the serrated structure that is recessed away from the spacer region, the angle formed between the extension directions of the serrated structure is a second serrated angle, the second serrated angle being greater than or equal to 120°.

[0021] In one optional implementation, the interval region includes a plurality of first sub-regions and a plurality of second sub-regions; the first sub-regions have a third texture structure, and the second sub-regions have the first texture structure; the height of the first texture structure is less than the height of the third texture structure, and / or the surface size of the first texture structure is greater than the surface size of the third texture structure; wherein, along the first direction, the recessed end is correspondingly set to the region where the third texture structure is located.

[0022] In one alternative implementation, the height of the region where the fourth texture structure is distributed along the thickness direction of the semiconductor substrate accounts for less than or equal to 98% of the height of the side surface.

[0023] In one alternative embodiment, the solar cell includes: a tunneling oxide layer located on a first region; a first doped conductive layer located on the surface of the tunneling oxide layer, wherein the first doped conductive layer has a dopant element having the same conductivity type as the semiconductor substrate; a passivation layer located on the surface of the first doped conductive layer and the surface of the spacer region; the solar cell further includes a third doped conductive layer located on the side surface; the ratio of the width of the third doped conductive layer covering the side surface to the width of the side surface is greater than or equal to 50%; the third doped conductive layer has the same doping type as the first doped conductive layer.

[0024] In one alternative embodiment, the passivation layer material includes an aluminum oxide layer with a thickness greater than or equal to 5 nm and less than or equal to 10 nm.

[0025] In one alternative embodiment, the first surface further includes a second region, which is alternately distributed with respect to the first region, with the spacer region located between the first and second regions; the solar cell further includes a second doped conductive layer located on the second region of the semiconductor substrate, the second doped conductive layer on the second region having a fifth textured structure.

[0026] According to another embodiment of this application, a photovoltaic module is provided, comprising: a plurality of solar cells as described above; an interconnection member electrically interconnected with the plurality of solar cells to connect the solar cells into a solar cell string; and an encapsulation layer covering the surface of the plurality of solar cells.

[0027] According to the embodiments of this application, the solar cell, by removing the first doped conductive layer in the non-electrode region (i.e., the spacer region) and forming a patterned first doped conductive layer in the first region (i.e., the conductive region), can help reduce optical parasitic absorption. Furthermore, by forming a textured structure of different sizes between the first doped conductive layer and the spacer region, the different needs of the first doped conductive layer and the spacer region can be accommodated. For example, if an electrode is formed in the first region, designing a first textured structure with a larger height on the surface of the first region facilitates contact with the electrode paste and improves electrical contact performance. A passivation layer can be deposited on the surface of the spacer region. By setting a second textured structure with a larger surface size, it is more conducive to forming a uniform passivation and antireflection layer, such as a nanometer-thick alumina layer or a silicon nitride stack, ensuring uniformity while maintaining a suitable thickness. This avoids the passivation layer being too thick, which would hinder the formation of a high-density and high-uniformity passivation layer, thus affecting the tunneling and passivation effect of the passivation layer.

[0028] Compared to the spacer region, the first doped conductive layer provides additional passivation to the conductive region. Therefore, the spacer region requires a higher-quality passivation layer to achieve a better passivation effect. By differentiating the texture structure between the conductive and spacer regions—that is, the first texture structure has a smaller height and a larger surface area than the second texture structure—a higher-quality passivation layer can be formed, further enhancing the passivation effect of the spacer region. In summary, by designing differentiated structures between the conductive and spacer regions, the different needs of both regions can be better met, thereby optimizing battery performance and improving battery efficiency.

[0029] After removing the first doped conductive layer in the spacer region, the path of charge carriers transporting to the first electrode increases through the first doped conductive layer. At this point, a better passivation effect is needed to reduce the possibility of charge carrier recombination during transport. Therefore, a fourth textured structure is designed on the side surface of the solar cell. Its surface size is larger than that of the first and second textured structures, which can improve the film quality of the passivation layer on the side surface C, enhance its passivation effect, thereby increasing the power on the back side of the solar cell and improving the bifaciality of the solar cell.

[0030] This design fully utilizes the surface of the battery structure without a doped conductive layer for light absorption and efficient light conversion. Surface morphology design within the battery structure enhances power generation, particularly the back-side power, thereby increasing the bifaciality of the battery. Furthermore, the size relationship between the surface dimensions of the fourth, first, and second textured structures better accommodates the process of patterning the first surface into the first region and the spacer region, reducing process complexity and improving production yield. Attached Figure Description

[0031] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0032] Figure 1 This is a partial cross-sectional schematic diagram of a solar cell according to an embodiment of this application;

[0033] Figure 2 for Figure 1 A top view of the solar cell shown.

[0034] Figure 3 for Figure 1 A side view of the solar cell shown.

[0035] Figure 4 This is a schematic diagram of the first texture structure, the second texture structure, and the fourth texture structure;

[0036] Figure 5 This is a scanning electron microscope (SEM) image of the first texture structure according to an embodiment of this application.

[0037] Figure 6 This is a top view schematic diagram of a solar cell according to another embodiment of this application;

[0038] Figure 7 This is a schematic diagram of the third texture structure according to another embodiment of this application;

[0039] Figure 8 This is a top SEM side view of a solar cell according to another embodiment of this application;

[0040] Figure 9 This is a schematic diagram showing a height difference between the interval area and the first region in another embodiment of this application;

[0041] Figure 10 This is a SEM image of the transition region of a solar cell according to another embodiment of this application;

[0042] Figure 11 This is a SEM image of the transition region of a solar cell according to another embodiment of this application;

[0043] Figure 12A and Figure 12B This is a schematic diagram of a stepped structure within the transition region of a solar cell, which is an exemplary embodiment of this application.

[0044] Figure 13 This is a schematic diagram of the overall structure of the solar cell according to an embodiment of this application;

[0045] Figure 14 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of this application;

[0046] Figure 15 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of this application.

[0047] In the above figures, the meanings of the reference numerals are as follows:

[0048] 101. Semiconductor substrate; 1011. First textured structure; 1012. Third textured structure; 1013. Protrusion structure; 1014. Fourth textured structure; 102. First doped conductive layer; 1021. Second textured structure; 103. Tunneling oxide layer; 104. Passivation layer; 105. First electrode; 106. Second doped conductive layer; 107. Another tunneling oxide layer; 108. Second electrode; 109. Another passivation layer; A. First surface; A1. First region; A2. Second region; A3. Transition region; gap; G1. First sub-region; G2. Second sub-region; B. Second surface; C. Side surface; X. First direction; Y. Second direction; Z. Thickness direction of semiconductor substrate. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0050] In the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments of this application. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "comprising" as used herein indicates the presence of features, steps, or operations, but does not exclude the presence or addition of one or more other features.

[0052] When using expressions such as "at least one of A, B, and C," the expression should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art. For example, "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C.

[0053] In this application, the relative position between two components (e.g., a membrane or region), as referred to by terms such as "above," "on," or "above," can mean that the two components are in direct contact or that they are not in direct contact. Similarly, the relative position between two components, as referred to by terms such as "below," "under," or "below," can mean that the two components are in direct contact or that they are not in direct contact. For example, when one component (e.g., a membrane or region) is referred to as "on another component," it can be directly on the other component, or there may be other components between them. On the other hand, when a component is referred to as "directly on another component," there are no components between them. Furthermore, when one component is referred to as "on another component," the two components have a vertical relationship in the planar view, and this component can be above or below the other component, thus this vertical relationship depends on the orientation of the device.

[0054] In solar cell technologies, bifaciality is a crucial factor affecting cell efficiency. To improve bifaciality, in bifacial contact cells such as tunnel oxide passivated contact (TOPCon) cells, laser etching is used to create grooves in the doped conductive layer on the back side, forming finger-like structures (such as poly fingers) to reduce the significant optical parasitic absorption introduced by the doped conductive layer. However, this structural improvement typically focuses on the thickness design of the doped conductive layer, neglecting the different requirements for passivation and contact between the spacer region and the doped conductive layer.

[0055] Similarly, the same applies to back contact batteries, such as tunnel oxide passivated back contact (TopCon-Back Contact) batteries. Usually, more attention is paid to the design of the doped conductive layer to improve carrier collection in the conductive region, while ignoring the different requirements of the gap region and the doped conductive layer for passivation, contact, etc. There is room for further improvement in battery performance.

[0056] In realizing the concept of this application, it was discovered that after removing the first doped conductive layer using laser etching, the difference in texture structure between the conductive area and the spacer area can be adjusted by controlling the laser conditions and then polishing the spacer area. This improves the passivation layer film quality of the spacer area while ensuring the electrical contact performance of the conductive area, thereby enhancing its passivation effect. This has a significant effect on improving the bifaciality of the battery and thus improving the battery efficiency.

[0057] Specifically, according to one embodiment of this application, a solar cell is provided. Figure 1 This is a partial cross-sectional view of a solar cell according to an embodiment of this application. Figure 2 for Figure 1 The diagram shows a top view of the solar cell. Figure 3 for Figure 1 The side view of the solar cell shown is as follows. Figures 1 to 3 As shown, the solar cell of this application includes: a semiconductor substrate 101, a first doped conductive layer 102, a passivation layer 104, and a first electrode 105, wherein: the semiconductor substrate 101 includes a first surface A, a second surface (not shown in the figure), and a side surface C connected between the first surface A and the second surface; the first surface A includes first regions A1 spaced apart along a first direction X, with gaps between adjacent first regions A1, the gaps having a first texture structure 1011, and the side surface C having a fourth texture structure; the first doped conductive layer 102 is located on the first region A1 of the semiconductor substrate 101, the first region A1 having a second texture structure 1021; the passivation layer 104 is located on the surface of the gaps and on at least one of the following structural surfaces: the second surface, the side surface C, and the surface of the first doped conductive layer 102 away from the semiconductor substrate 101; the first electrode 105 is located on the first doped conductive layer 102 and is in electrical contact with the first doped conductive layer 102.

[0058] It is understandable that, such as Figure 1 As shown, in some examples, the passivation layer 104 is located on the surface of the spacer region gap and the first doped conductive layer 102 away from the semiconductor substrate 101. In other examples, the passivation layer 104 may also be located on the side surface C and / or the second surface. The passivation layers on these surfaces may be prepared in the same deposition process or in different deposition processes without particular limitation.

[0059] According to some embodiments of this application, the height of the first texture structure 1011 is less than the height of the second texture structure 1021, and / or the surface size of the first texture structure 1011 is greater than the surface size of the second texture structure 1021; the surface size of the fourth texture structure is greater than the surface size of the second texture structure 1021.

[0060] In the embodiments of this application, by removing the first doped conductive layer 102 in the non-electrode region, i.e., the gap region, and forming a patterned first doped conductive layer 102 on the first region A1, i.e., the conductive region, it is beneficial to reduce optical parasitic absorption. Based on this, by forming a textured structure of different sizes between the first doped conductive layer 102 and the gap region, the different needs of the first doped conductive layer 102 and the gap region can be considered. For example, if an electrode is formed on the first region A1, designing a first textured structure 1011 with a larger height on the surface of the first region A1 facilitates contact with the electrode paste and improves electrical contact performance. A passivation layer can be deposited on the surface of the gap region. By setting a second textured structure 1021 with a larger surface size, it is more beneficial to form a uniform passivation antireflection layer, such as a nanometer-thick alumina layer or a silicon nitride stack, ensuring uniformity while maintaining a suitable thickness. This avoids the passivation layer being too thick, which would hinder the formation of a high-density and high-uniformity passivation layer, thus affecting the tunneling and passivation effect of the passivation layer.

[0061] Compared to the spacer gap, the first doped conductive layer 102 provides additional passivation for the conductive region. Therefore, the spacer gap requires a higher-quality passivation layer to achieve a better passivation effect. By differentiating the texture structure between the conductive region and the spacer gap—that is, the height of the first texture structure 1011 is smaller than that of the second texture structure 1021, and its surface size is larger than that of the second texture structure 1021—a higher-quality passivation layer can be formed, further enhancing the passivation effect of the spacer gap. In summary, by differentiating the structure between the conductive region and the spacer gap, the different needs of the conductive region and the spacer gap can be better met, thereby optimizing battery performance and improving battery efficiency.

[0062] According to one embodiment of this application, based on the difference in corrosion degree between the side surface and the first surface during acid and alkali washing processes, the surface size of the fourth texture structure being larger than that of the first texture structure can be controlled by selecting appropriate acid and alkali washing conditions and cycles. The side surface C has a fourth texture structure 1014, and the surface size of the fourth texture structure 1014 is larger than that of the first texture structure 1011. In the solar cell of this application, the first doped conductive layer 102 of the gap region is removed. The path of the charge carriers generated in the gap region to the first electrode increases through the first doped conductive layer 102. At this time, the probability of recombination of charge carriers generated on the back side within or on the surface of the semiconductor substrate is greatly increased. Therefore, better passivation is needed to reduce the possibility of recombination of charge carriers during transport. Furthermore, because the first doped conductive layer 102 or the second doped conductive layer 106 remains on some parts of the side of the cell, and because of the different surface heights formed during the acid and alkali washing processes, the roughness of the side surface C is relatively large. Therefore, designing a fourth texture structure 1014 on the side surface C of the solar cell, whose surface size is larger than that of the first texture structure 1011, can further improve the passivation layer film quality on the side surface C and enhance its passivation effect. This can comprehensively improve the power on the back of the solar cell and increase the bifaciality of the solar cell by increasing the back light receiving area and reducing the carrier recombination probability.

[0063] This design in solar cells fully utilizes the surface of the cell structure without a doped conductive layer for light absorption and efficient light conversion. In existing cell structures, surface morphology design improves power generation, particularly back-side power, thereby increasing the bifaciality. Furthermore, the size relationship between the surface dimensions of the fourth, first, and second textured structures better accommodates the process of patterning the first surface into the first region and the spacing region, reducing process complexity and improving production yield.

[0064] According to some embodiments of this application, similarly, based on the difference in corrosion degree between the side surface and the first surface in the acid and alkali washing process, by selecting appropriate acid and alkali washing conditions and times, the surface size of the fourth texture structure 1014 can be adjusted to be larger than the surface size of the second texture structure 1021. This size structure design can facilitate the preparation and formation of the fourth texture structure 1014, improve preparation efficiency, and save preparation costs.

[0065] According to one embodiment of this application, the height of the fourth texture structure 1014 on the side surface C is less than the height of the second texture structure 1021, reducing the surface roughness of the side surface C and further improving the coating quality of the side surface C. Roughness refers to the arithmetic mean of the absolute values ​​of the Z-direction deviation relative to the mean line over a sampling length. Roughness can be measured by comparison method, optical sectioning method, interferometry method, and stylus method.

[0066] According to one embodiment of this application, the height of the fourth texture structure 1014 on the side surface C is greater than the height of the first texture structure 1011. This structural design can improve the reflectivity of the side surface, improve the reflectivity of the side surface C for light incident on the unused part of the battery and reflected onto the side surface C, further improve battery efficiency, and increase the bifaciality of the battery.

[0067] According to some embodiments of this application, the gap region can also be located in the edge region of the solar cell, that is, between the first region and the edge of the solar cell. In this way, when the gap region has a first texture structure, it is more conducive to improving the passivation effect of the edge region, improving the situation where edge carriers are prone to recombination, thereby improving the collection of edge carriers.

[0068] According to some embodiments of this application, the semiconductor substrate 101 can be an N-type, P-type, or intrinsic crystalline silicon substrate, such as a semiconductor material selected from monocrystalline silicon, polycrystalline silicon, and microcrystalline silicon, preferably an N-type or P-type monocrystalline silicon substrate. Cells based on monocrystalline silicon substrates have higher conversion efficiency compared to other types, such as polycrystalline silicon cells. An N-type crystalline silicon substrate is obtained by introducing donor impurities such as group VA elements like phosphorus (P), arsenic (As), or antimony (Sb) into these semiconductor materials, or a P-type crystalline silicon substrate is obtained by introducing acceptor impurities such as group IIIA elements like boron (B), aluminum (Al), or gallium (Ga).

[0069] According to some embodiments of this application, the first surface A of the semiconductor substrate 101 can be the back surface of the battery. Generally, the front surface of the battery serves as the light-receiving surface, and the back surface serves as the back-lighting surface, or it can be light-receiving on both sides, in which case both the front and back surfaces serve as light-receiving surfaces. When the first surface A serves as the back surface of the battery, the requirements for passivation performance are relatively high. In this case, the differentiated setting between the first texture structure 1011 and the second texture structure 1021 is more conducive to leveraging its advantages in both improving the passivation effect of the electrical contact of the conductive area and the gap of the spacing area, which is more beneficial to improving the bifaciality and thus improving battery efficiency. Of course, it is understood that this is not the only possibility; in some other embodiments, the first surface A can be the front surface of the battery.

[0070] According to embodiments of this application, the doping type of the first doped conductive layer 102 can be N-type or P-type, which can be determined based on the battery type and the structure of the semiconductor substrate 101. Further, for example, N-type doping can be achieved by introducing donor impurities such as phosphorus (P), arsenic (As), or antimony (Sb) into the semiconductor material; and P-type doping can be achieved by introducing acceptor impurities such as boron (B), aluminum (Al), or gallium (Ga) into the aforementioned semiconductor material. In some examples, the material of the first doped conductive layer 102 can be one or more of amorphous silicon, polycrystalline silicon, and microcrystalline silicon; the first doped conductive layer 102 can be deposited on the surface of the semiconductor substrate 101, for example, by a chemical vapor deposition process.

[0071] According to some embodiments of this application, the width of the first doped conductive layer 102 along the first direction X is less than or equal to 1000 μm, for example, it can be 100 μm, 200 μm, 400 μm, 600 μm, 800 μm, 1000 μm, etc. If the width of the first doped conductive layer 102 is too large, it will increase optical parasitic absorption and reduce the battery short-circuit current. If the width is too small, it will increase the difficulty of the process, seriously affect the production capacity, and also increase the tunneling resistance, affecting the series resistance of the battery.

[0072] According to some embodiments of this application, Figure 4 The diagram shown is a structural schematic of the first texture structure 1011, the second texture structure 1021, and the fourth texture structure 1014, as follows: Figure 4 As shown, the first texture structure 1011, the second texture structure 1021, and the fourth texture structure 1014 exhibit polished microstructure morphology, which can be any morphology structure different from the flat surface. For example, it can be a texture structure composed of multiple grooves, a structure composed of multiple protrusions, or a texture structure composed of both grooves and protrusions. For another example, the first texture structure 1011 can exhibit a concave morphology, with its bottom surface being a polygonal plane. The shape of the polygonal plane includes at least one of rhombus, square, trapezoid, approximate rhombus, approximate square, and approximate trapezoid. It is understood that in the actual manufacturing process, the top surface morphology of the first texture structure 1011 or the second texture structure 1021 may be irregular.

[0073] According to some embodiments of this application, such as Figure 4 As shown, the height of the first texture structure 1011, the second texture structure 1021, and the fourth texture structure 1014 refers to the vertical distance h1 between the bottom surface and the top surface adjacent to the bottom for a groove or protrusion. The surface dimensions of the first texture structure 1011, the second texture structure 1021, and the fourth texture structure 1014 refer to the side length a of the bottom surface, such as the length of the long side, the width of the short side, the length of the diagonal, etc.

[0074] This application does not impose any restrictions on the measurement of the height and surface dimensions of the first texture structure 1011, the second texture structure 1021, and the fourth texture structure 1014. Those skilled in the art can perform the measurements using conventional methods in the field. For example, the surface dimensions can be measured using a scanning electron microscope (SEM). In this case, the passivation layer on the surface of the solar cell can be removed before performing SEM testing on the surface of the solar cell. Of course, it is not limited to this. Since the passivation layer can be conformally deposited on the surface of the first doped conductive layer 102 and the gap region, and has a groove structure consistent with the surface of the first doped conductive layer 102 and the semiconductor substrate 101, SEM testing can also be performed directly on the first texture structure 1011 and the second texture structure 1021 of the solar cell from a top-view perspective, or SEM testing can be performed directly on the fourth texture structure 1014 of the solar cell from a side-view perspective. Specifically, due to the varying heights of the first texture structure 1011, the second texture structure 1021, and the fourth texture structure 1014, there is a significant brightness difference between the bottom and top surfaces. The bottom position can be determined on the SEM top view, and the length, width, or diagonal of the bottom surface can be measured to obtain the surface dimensions of the first texture structure 1011 or the second texture structure 1021. Similarly, for height measurement, the cross-section of the solar cell can be tested with or without removing the passivation layer. The height of the first texture structure 1011 or the second texture structure 1021 can be obtained by measuring the height difference between adjacent top and bottom surfaces.

[0075] It is understandable that the height of the first texture structure 1011 is less than the height of the second texture structure 1021. This can be because, in at least one comparison test area, the average height of the first texture structure 1011 is less than the average height of the second texture structure 1021, or, for example, the height of the first texture structure 1011 is less than the minimum height of the second texture structure 1021 for a proportion of 50%, 60%, 70%, or even 80%. Similarly, the surface size of the first texture structure 1011 is greater than the surface size of the second texture structure 1021. This can be because, in at least one comparison test area, the average surface size of the first texture structure 1011 is greater than the average surface size of the second texture structure 1021, or, for example, the surface size of the first texture structure 1011 is greater than the maximum surface size of the second texture structure 1021 for a proportion of 50%, 60%, or even 80%. The surface size of the fourth texture structure is greater than the surface size of the first texture structure, which can be calculated in a similar way and will not be elaborated further here.

[0076] According to some embodiments of this application, the height of the second texture structure 1021 is less than or equal to 3 μm, for example, it can be 0.1 μm, 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2.0 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3.0 μm, etc. When the height of the second texture structure 1021 exceeds 3 μm, the roughness of the second texture structure 1021 is too large, the thickness of the doped conductive layer formed on the second texture structure 1021 is larger, and the uniformity is worse, which is not conducive to the formation of a high-density and high-uniformity doped conductive layer. Setting the height of the second texture structure 1021 within the above range can prevent the local phosphorus concentration from being too high due to the doped conductive layer, reduce the contact resistivity, increase the open-circuit voltage of the solar cell, and improve the fill factor and photoelectric conversion efficiency. Preferably, the height of the second texture structure 1021 is less than or equal to 2 μm.

[0077] According to some embodiments of this application, the surface size of the first texture structure 1011 is less than or equal to 25 μm, for example, it can be 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, 22 μm, 24 μm, 25 μm, etc. If the surface size of the first texture structure 1011 is too large, its surface undulations will be too gentle, which is not conducive to improving the light-trapping effect and reducing the light utilization rate. By setting the surface size of the first texture structure 1011 within the above-mentioned range, and combining it with the differentiated surface sizes of the first texture structure 1011 and the second texture structure 1021, it is possible to balance ensuring the light-trapping effect and improving the passivation performance. Preferably, the surface size of the first texture structure 1011 is less than or equal to 15 μm.

[0078] According to some embodiments of this application, the height of the first texture structure 1011 can be 0.1~2μm, for example, 0.1μm, 0.2μm, 0.5μm, 0.8μm, 1.0μm, 1.2μm, 1.5μm, 1.8μm, 2.0μm, etc. Thus, by controlling the height of the first texture structure 1011 within the above range, it is more advantageous to ensure the formation of a passivation layer with uniform film formation and better film quality. The surface size of the first texture structure 1011 can be 10~28μm, for example, 10μm, 12μm, 14μm, 16μm, 18μm, 20μm, 22μm, 24μm, 25μm, 28μm, etc. Thus, by controlling the surface size of the first texture structure 1011 within the above range, it is possible to simultaneously ensure light trapping effect and form a passivation layer with high density and high uniformity. For example, Figure 5 Here is a SEM image of the first texture structure according to an embodiment of this application, such as... Figure 5As shown, the surface size of the first texture structure 1011 is between 10 and 28 μm.

[0079] According to some embodiments of this application, the height of the second texture structure 1021 can be 0.5~3μm, for example, 0.5μm, 0.6μm, 0.8μm, 1.0μm, 1.2μm, 1.5μm, 1.8μm, 2.0μm, 2.2μm, 2.4μm, 2.6μm, 2.8μm, 3.0μm, etc. Thus, by controlling the height of the second texture structure 1021 within the above range, the uniformity of the doped conductive layer and the contact performance with the electrode can be better balanced. The surface size of the second texture structure 1021 can be 1~15μm, for example, 1μm, 2μm, 4μm, 6μm, 8μm, 10μm, 12μm, 14μm, 15μm, etc., and more preferably 5~15μm. By controlling the surface size of the second texture structure 1021 within the above range, its surface size will not be too small, which would lead to increased roughness and affect the uniformity and film quality of the deposited doped conductive layer.

[0080] According to some embodiments of this application, the height of the fourth texture structure 1014 can be 0.2~2.5μm, for example, 0.2μm, 0.5μm, 0.8μm, 1.0μm, 1.2μm, 1.5μm, 1.8μm, 2.0μm, 2.2μm, 2.4μm, 2.5μm, etc. If the height of the fourth texture structure 1014 is too high, it is not conducive to improving the coating quality; if the height is too low, it is not conducive to improving the light utilization rate. Therefore, by controlling the height of the fourth texture structure 1014 within the above range, a balance can be achieved between light utilization rate and coating quality on the side surface. The surface size of the fourth texture structure 1014 can be 15~40μm, for example, 15μm, 18μm, 20μm, 22μm, 24μm, 26μm, 28μm, 30μm, 32μm, 34μm, 36μm, 38μm, 40μm, etc. By controlling the surface dimensions of the fourth texture structure 1014 within the aforementioned range, it is more beneficial to improve the coating quality on the side surface, such as the uniformity of the film layer. In some examples, the projection shape of the fourth texture structure 1014 on the side surface can be square or rectangular, with the length of the base side ranging from 25 to 40 μm, for example, 25 μm, 26 μm, 28 μm, 30 μm, 32 μm, 34 μm, 36 μm, 38 μm, 40 μm, etc., and the length of the base side ranging from 15 to 30 μm, for example, 15 μm, 18 μm, 20 μm, 22 μm, 25 μm, 28 μm, 30 μm, etc.

[0081] In the process of realizing the technical concept of this application, it was discovered that when using laser etching to remove the first doped conductive layer 102, by adjusting the laser conditions, such as increasing the laser energy density, spot size and laser etching time, the texture structure of the gap region can be changed, which is beneficial to improving light utilization and thus improving battery efficiency.

[0082] Specifically, according to some embodiments of this application, Figure 6 This is a top view schematic diagram of a solar cell according to another embodiment of this application. Figure 7 This is a schematic diagram of the third texture structure according to another embodiment of this application; Figure 8 This is a top SEM side view of a solar cell according to another embodiment of this application, as shown. Figure 6 , Figure 7 and Figure 8 As shown, the gap region of this application may include multiple first sub-regions G1 and multiple second sub-regions G2, with the first sub-regions G1 and G2 arranged alternately along a second direction Y, which intersects with the first direction X. The first sub-regions G1 have a third texture structure 1012, and the second sub-regions G2 have a first texture structure 1011. The height of the first texture structure 1011 is less than the height of the third texture structure 1012, and / or the surface size of the first texture structure 1011 is greater than the surface size of the third texture structure 1012. It is understood that the third texture structure 1012 may be a polished microstructure similar to the first texture structure 1011 and the second texture structure 1021, which will not be elaborated upon here.

[0083] Thus, after removing the doped conductive layer in the non-electrode region to reduce optical parasitic absorption, the gap on the back side can also serve as a light absorption region. The main light sources for the gap on the back side are light reflected directly from the ground and light incident from the front that is not utilized and reaches the back side. The first textured structure 1011 has a larger and flatter surface size and lower reflectivity, thus making better use of the light reflected to the back side. The third textured structure 1012 has a greater depth and higher reflectivity, thus making better use of the light incident from the front to the back side. Overall, this improves the light utilization rate of the gap and increases battery efficiency.

[0084] According to some embodiments of this application, the height of the third texture structure 1012 can be 0.5~3μm, for example, 0.5μm, 0.6μm, 0.8μm, 1.0μm, 1.2μm, 1.5μm, 1.8μm, 2.0μm, 2.2μm, 2.4μm, 2.6μm, 2.8μm, 3.0μm, etc. Thus, by controlling the height of the third texture structure 1012 within the above range, light incident from the front to the back can be better utilized, improving the light utilization rate of the gap area. The surface size of the third texture structure 1012 can be 1~15μm, for example, 1μm, 2μm, 4μm, 6μm, 8μm, 10μm, 12μm, 14μm, 15μm, etc., and more preferably 5~15μm. By controlling the surface size of the third texture structure 1012 within the above range, its surface size will not be too small, which would lead to increased roughness and affect the uniformity and film quality of the deposited doped conductive layer.

[0085] In some specific embodiments, the gap region of this application may include multiple first sub-regions G1 and multiple second sub-regions G2, with the first sub-regions G1 and second sub-regions G2 alternately arranged along a second direction Y, which intersects with the first direction X. The first sub-regions G1 have a third texture structure 1012, and the second sub-regions G2 have a first texture structure 1011. Along the second direction Y, the width (L3) of the first sub-region G1 is less than or equal to 400 μm, for example, it can be 20 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, 320 μm, 350 μm, 380 μm, 400 μm, etc. For example, the width (L3) of the first sub-region G1 can be less than or equal to 200 nm, and more specifically, it can be 10~100 μm. If the first sub-region G1 is too wide, it will increase the laser etching time, thereby reducing the production capacity; conversely, if the first sub-region G1 is too narrow, the corresponding second sub-region G2 will be wider, which will affect the improvement of the light trapping effect, thereby reducing the short-circuit current of the battery.

[0086] In some specific embodiments, the spacing (L2) between adjacent first sub-regions G1 is 20 μm to 400 μm, for example, it can be 20 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, 320 μm, 350 μm, 380 nm, 400 μm, etc. For example, the spacing (L2) between adjacent first sub-regions G1 can be 10 to 100 μm. If the spacing is too narrow, the corresponding second sub-region G2 will be narrower, which will affect the density and uniformity of the passivation layer deposited on it. If the spacing is too wide, the corresponding second sub-region G2 will be wider, which will affect the improvement of the light-trapping effect.

[0087] Taking into account the effects of the first sub-region G1 and the second sub-region G2 on the light trapping effect, laser etching time and passivation effect, the ratio (L3 / L2) of the width of the first sub-region G1 and the distance between the first sub-region G1 and another first sub-region G1 adjacent to it is 1~2, for example, it can be 1, 1.2, 1.3, 1.5, 1.8, 2.0, etc.

[0088] In some examples, such as Figure 6 As shown, along the second direction Y, the width (L3) of the first sub-region G1 accounts for a proportion greater than or equal to 20% and less than or equal to 70% of the sum of the width of the first sub-region G1 and the spacing between adjacent first sub-regions G1 (L2+L3). For example, it can be 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, etc. In some other examples, the area of ​​the first sub-region accounts for a proportion greater than or equal to 20% and less than or equal to 70%, for example, it can be 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, etc.

[0089] Thus, since the third texture structure 1012 will disrupt the flatness of the first texture structure 1011, the size of the third texture structure can be effectively controlled by controlling the size and / or area ratio of the first sub-region, thereby balancing the passivation effect and the light trapping effect.

[0090] According to some embodiments of this application, for example... Figure 6 As shown, the gap region of this application may include multiple first sub-regions G1 and multiple second sub-regions G2, the first sub-regions G1 and the second sub-regions G2 are alternately arranged along a second direction Y, and the second direction Y intersects with the first direction X; the first sub-regions G1 have a third texture structure 1012, and the second sub-regions G2 have a first texture structure 1011; as Figure 7As shown (dashed lines represent different overlapping configurations of the third texture structure 1012), the third texture structures 1012 overlap in the first sub-region G1. In the direction away from the surface of the first sub-region G1, the distance h2 between the bottom surface of the outermost third texture structure 1012 and the bottom surface of its adjacent third texture structure 1012 is less than or equal to 2 μm. This configuration allows the overlapping third texture structures 1012 to effectively utilize light incident from the front to the back, improving the light-trapping effect. However, when the distance h2 exceeds 2 μm, the roughness of the overlapping third texture structures 1012 becomes too large, resulting in a thicker passivation layer formed on the third texture structure 1012, which is detrimental to forming a passivation layer with high density and high uniformity.

[0091] According to some embodiments of this application, the height of the second texture structure 1021 is less than the height of the third texture structure 1012. Because the third texture structure 1012 is taller, it can better utilize light incident from the front to the back in the gap area, while the second texture structure 1021 is shorter, thus better utilizing light reflected to the back in the conductive area.

[0092] Especially when the surface of the gap is closer to the second surface B than the surface of the first region A1, the gap comes into contact with the front incident light before the conductive region. By setting the height of the third texture structure 1012 higher, it is more conducive to the gap fully utilizing the front incident light. At the same time, the conductive region comes into contact with the back incident light before the gap. By setting the height of the second texture structure 1021 lower, it is more conducive to the conductive region fully utilizing the light reflected to the back.

[0093] According to some embodiments of this application, along the thickness direction Z of the semiconductor substrate, the surface of the gap region is closer to the second surface B than the surface of the first region A1. This height difference allows the gap region to contact the incident light first, increasing the number of light reflections and improving the light-trapping effect.

[0094] For example, Figure 9 This is a schematic diagram illustrating the height difference between the gap region and the first region A1 in another embodiment of this application, as shown below. Figure 9As shown, the height difference (H1) between the surface of the first region A1 and the surface of the gap region is 1 μm to 5 μm, for example, it can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, or 5 μm. If the height difference is too low, it will not be conducive to improving the light-trapping effect; if the height difference is too high, it will be difficult to uniformly cover the passivation layer during deposition, reducing the density and uniformity of the passivation layer, thus hindering the improvement of the passivation effect. Preferably, the height difference (H1) between the surface of the first region A1 and the surface of the gap region is 1 μm to 3 μm.

[0095] According to some embodiments of this application, when the first doped conductive layer 102 is formed on the first surface A by deposition, a height difference is generated between the surface of the first doped conductive layer 102 and the first surface A. Based on this height difference and / or the existence of a height difference between the surfaces of the first region A1 and the gap region, a transition region A3 is formed between the first region A1 and the gap region by selecting an appropriate polishing process.

[0096] Therefore, in some embodiments... Figure 10 This is a SEM image of the transition region A3 of a solar cell according to another embodiment of this application, as shown below. Figure 6 and Figure 10 As shown, the first surface A may further include a transition region A3 located between the first region A1 and the gap region; wherein, the transition region A3 has a protrusion structure 1013, and the one-dimensional dimension of the protrusion structure 1013 is different from the one-dimensional dimension of the first texture structure 1011 and the second texture structure 1021. Thus, by setting the protrusion structure 1013 in the transition region A3, the light trapping effect can be further enhanced.

[0097] It should be noted that the "one-dimensional dimension" here can be, for example, height, bottom dimension, etc. The meanings of height and bottom dimension are the same as those mentioned above, and will not be repeated here. The "protrusion structure 1013" presents a velvety microstructure or a combination of velvety microstructure and polished microstructure. For example, the protrusion structure 1013 can present at least one of the following: a prism, a pyramid, a near-prism, a near-pyramid, or an irregular protrusion.

[0098] According to some embodiments of this application, such as Figure 6 or Figure 10As shown, along the first direction X, the width (d1) of the transition region A3 can be 1μm to 50μm, for example, it can be 1μm, 3μm, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, etc. For example, the width (d1) of the transition region A3 can be 10 to 20μm. The width of the transition region A3 should be as small as possible. If it is too large, it will lead to an increase in recombination at the interface between the semiconductor substrate 101 and the first doped conductive layer 102, thereby reducing the open-circuit voltage of the battery. At the same time, the transition region A3 should be set as a textured microstructure or a combination of textured microstructure and polished microstructure as much as possible. This is because recombination at the grain boundary is inevitable when the transition region A3 is present. By reducing the width, the light absorption rate can be increased by increasing the protrusion structure 1013 to compensate for the carrier loss caused by recombination.

[0099] In some examples, the widths of the transition regions A3 located on either side of the gap can be the same or different. Under similar conditions, different regions of the cell have a relatively consistent design; under different conditions, the carrier collection balance in different regions can be adjusted according to the requirements of different regions of the solar cell.

[0100] According to some embodiments of this application, the transition region A3 can be bent and extended along the second direction Y. In this case, along the first direction X, the transition region A3 has a protruding end that bulges towards the gap region and a recessed end that is recessed away from the gap region. The distance (d2) between the protruding end and the recessed end is less than or equal to 50 μm, for example, it can be 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc. For example, the distance (d2) can be 20~40 μm. If this distance is too large, the transition region A3 will be too wide or the bend will be too large, easily exacerbating the recombination loss of the transition region A3, thereby reducing the open-circuit voltage.

[0101] For example, Figure 11 This is a SEM image of the transition region A3 of a solar cell according to another embodiment of this application, which exemplarily illustrates the dimensions of a portion of the transition region A3; as shown... Figure 10 and Figure 11 As shown, the width (d1) of the transition region A3 is 12.52 μm, and the distance (d2) between the protruding end and the concave end is 30.61 μm, which has a relatively suitable width (d1) and distance (d2).

[0102] According to some embodiments of this application, the transition region A3 can extend in a regularly bent manner along the second direction Y. For example, the transition region A3 extends in a bent manner into multiple sawtooth structures along the second direction Y intersecting the first direction X; such as Figure 10 and Figure 11 As shown. Thus, the regularity of the surface morphology can be enhanced by setting a serrated structure.

[0103] According to some embodiments of this application, the surface of the transition region A3 has a step with a height different from the surface of the interval region and the surface of the first region. That is, two step-like structures are formed at the junctions of the surface of the first region A1 and the surface of the transition region A3, and the surface of the transition region A3 and the interval region gap. In this way, the number of reflections of light in the transition region A3 and at the junctions of the transition region A3 with the surface of the first region A1 and the interval region gap can be increased, thereby increasing the light-trapping effect.

[0104] For example, Figure 12A and Figure 12B This is a schematic diagram of a stepped structure within the transition region of a solar cell, as an exemplary embodiment of this application. Figure 12A As shown, the stepped structure can be such that the height of the step on the surface of the transition region A3 is between the height of the surface of the interval region and the surface of the first region, or, as... Figure 12B As shown, the stepped structure can also be that the height of the step on the surface of the transition zone A3 is lower than the surface height of the first region, that is, the step is concave.

[0105] According to some embodiments of this application, for example... Figure 10 and Figure 11 As shown, along the first direction X, the recessed end of the sawtooth structure along the direction away from the gap area is set to correspond to the area where the third texture structure is located. In this way, the light reflected to the back of the battery, especially the light reflected at the third texture structure, can be received by the sawtooth structure more effectively, which is beneficial to improving the light utilization rate of the back of the battery, thereby improving the bifaciality.

[0106] In some specific embodiments, the length (L4) of the sawtooth structure along the second direction Y is less than or equal to 200 μm; for example, it can be 10 μm, 20 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, etc. For example, it can be 15 μm to 100 μm. If the length of the sawtooth structure is too large, the improvement in light-trapping effect is relatively limited. Furthermore, a suitable length range can be adapted to the spacing between adjacent first sub-regions G1 to further improve the light-trapping effect.

[0107] According to some embodiments of this application, such as Figure 10As shown, at the recessed end of the sawtooth structure that is recessed away from the gap region, the angle formed by the extension direction of the sawtooth structure and the extension direction of the first doped conductive layer 102 is the first sawtooth angle (θ1), which is less than or equal to 30°, and can be, for example, 1°, 2°, 5°, 8°, 10°, 12°, 15°, 18°, 20°, 22°, 25°, 28°, 30°, etc.; and / or, at the recessed end of the sawtooth structure that is recessed away from the gap region, the angle formed between the extension directions of the sawtooth structure is the second sawtooth angle, which is greater than or equal to 120°, and can be, for example, 120°, 125°, 130°, 135°, 140°, 145°, 150°, 155°, 160°, 165°, 170°, 175°, 180°, etc. The first sawtooth angle and the second sawtooth angle (θ2) can be adjusted by changing the angle of the laser spot. By setting the first sawtooth angle and / or the second sawtooth angle within the aforementioned range, current transmission can be facilitated, the series resistance of the battery can be reduced, and the recombination loss can be reduced due to the relatively gentle bending of the transition region A3, thereby improving the open circuit voltage.

[0108] According to some embodiments of this application, the first texture structure 1011 and / or the second texture structure 1021 can be arranged along a certain direction, and the arrangement direction has a certain angle with the extension direction of the first region A1, which can improve the regularity of the surface morphology of the first surface A and improve the uniformity of surface reflectivity. For example, as Figure 8 or Figure 10 As shown in the rectangular frame, part of the first texture structure 1011 is arranged in strips along the extension direction of the first region A1, and part of the second texture structure 1021 is arranged in strips along the extension direction of the first region A1.

[0109] To facilitate understanding, we will use a double-sided contact battery, such as the TOPCon battery, as an example to illustrate the applicability of the fourth texture structure in double-sided contact batteries. Figure 13 This is a schematic diagram of the overall structure of the solar cell according to an embodiment of this application, as shown below. Figure 13 As shown, the semiconductor substrate 101 further includes a side surface C connected between the first surface A and the second surface B. The side surface C has a fourth texture structure, such as... Figure 3 As shown. The solar cell also includes a passivation layer located on the side surface C, which has a fourth textured structure. It is understandable that this applies not only to bifacial contact cells but also to back-contact cells, thereby improving the side passivation effect.

[0110] According to some embodiments of this application, for example... Figure 13As shown, the semiconductor substrate 101 also includes a side surface C connected between the first surface A and the second surface B. The side surface C has a fourth texture structure. Along the thickness direction Z of the semiconductor substrate, the height (h3) of the region where the fourth texture structure is distributed accounts for a proportion (h3 / h4) of the height (h4) of the side surface C that is less than or equal to 98%. For example, it can be 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, 98%, etc.

[0111] In some implementations, the fourth textured structure can be obtained during the fabrication of the solar cell by simultaneously performing alkaline washing and polishing on the first surface A and the side surface C. In this case, in a double-sided contact cell, the entire side surface C can be left untreated by alkaline washing and polishing to adjust the ratio (h3 / h4), allowing for a greater formation of the fourth textured structure on the cell's side surface and ensuring passivation performance to reduce recombination losses. In a back-contact cell, the alkaline-washed and polished side surface C can be further texturized by alkaline washing to adjust the ratio (h3 / h4), improving light trapping and, in conjunction with the passivation layer on the side surface C, reducing recombination losses. At least a portion of the side surface C can have a textured microstructure; it is understood that "at least a portion of the side surface C" can refer to either a part or the entire side surface C.

[0112] To facilitate understanding of the applicability of different solar cell types in this application, we will continue to use a bifacial contact cell, such as a TOPCon cell, as an example to further explain the solar cell structure. For example... Figure 13 As shown, the solar cell includes: a tunneling oxide layer 103 located on a first region A1; a first doped conductive layer 102 located on the surface of the tunneling oxide layer 103, wherein the first doped conductive layer 102 has doping elements of the same conductivity type as the semiconductor substrate 101; and a passivation layer 104 located on the surface of the first doped conductive layer 102 and the surface of the gap region. The gap region may have a first texture structure 1011, and may further have a third texture structure 1012. The first region A1 may have a second texture structure 1021. The configuration of the first texture structure 1011, the second texture structure 1021, and the third texture structure 1012 is as described above and will not be repeated here.

[0113] Thus, based on the first texture structure 1011 on the gap surface, good uniformity and density are ensured without the passivation layer thickness being too thick. Since both the first doped conductive layer 102 and the passivation layer can provide good passivation effects, the electrical contact between the first doped conductive layer 102 and the first electrode 105 can be improved based on the second texture structure 1021 of the first doped conductive layer 102 while ensuring passivation performance.

[0114] For example, the tunneling oxide layer 103 can be aluminum oxide, silicon oxide, titanium oxide, etc., used to selectively pass through majority carriers and achieve a field passivation effect, thereby improving carrier separation and collection. The tunneling oxide layer 103 of the aforementioned materials also serves to prevent the first electrode 105 from corroding the semiconductor substrate 101 inward. For example, the first doped conductive layer 102 can be, for example, a first doped polysilicon layer, and the tunneling oxide layer 103 can form a tunneling oxide passivation contact structure with the first doped polysilicon layer.

[0115] For example, the tunneling oxide layer 103 can be prepared by low-temperature chemical vapor deposition (LPCVD) and the thickness can be 0.5~10 nm, for example, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 4 nm, 6 nm, 8 nm, 10 nm, etc.

[0116] According to some embodiments of this application, the passivation layer 104 may be a single-layer film formed of silicon dioxide, aluminum oxide, silicon nitride, or silicon oxynitride, or a multilayer film composed of one or more of the aforementioned materials. In some examples, the passivation layer may include a first passivation layer and a second passivation layer sequentially disposed along a direction away from the semiconductor substrate 101. The first passivation layer includes at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer. The second passivation layer includes at least one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. For example, an aluminum oxide passivation layer may be prepared first using, for example, an ALD (atomic layer deposition) method, and then one or more silicon nitride layers may be formed thereon using, for example, a PECVD (plasma chemical vapor deposition) method.

[0117] For example, the thickness of the first passivation layer is 0.5 nm to 10 nm, such as 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 4 nm, 5 nm, 6 nm, 8 nm, 10 nm, etc. The thickness of the second passivation layer is 60 nm to 200 nm, such as 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, 160 nm, 180 nm, 200 nm, etc., and can be further selected as 5 to 10 nm, which can be more beneficial to improving the passivation performance of the gap region.

[0118] According to some embodiments of this application, the first electrode 105 makes electrical contact through the passivation layer and the first doped conductive layer 102. Based on the second texture structure 1021 on the surface of the first doped conductive layer 102, the contact area between the first electrode 105 and the first doped conductive layer 102 is increased, thereby improving the electrical contact performance.

[0119] For example, the first electrode 105 can be made of copper, silver-plated copper, aluminum, or silver, and can be manufactured by printing or electroplating, thus eliminating the need for additional photolithography for patterning. For instance, metal paste can be printed onto the passivation layer, and then the metal paste can be sintered to achieve metallization. The printing method can be, for example, screen printing or inkjet printing, preferably the lower-cost screen printing method.

[0120] According to some embodiments of this application, for example... Figure 13 As shown, the solar cell may further include a second doped conductive layer 106 disposed on at least a portion of the second surface B of the semiconductor substrate 101. In other words, the second doped conductive layer 106 may cover the entire second surface B or may be disposed on a portion of the second surface B. In some examples, the second surface B has a textured structure, such as including multiple pyramidal structures, to improve light trapping effect.

[0121] According to some embodiments of this application, the second doped conductive layer 106 has the opposite doping type to the first doped conductive layer 102, and can be N-type or P-type, specifically determined according to the battery type and the doping type of the silicon substrate. The material of the second doped conductive layer 106 can be one or more of materials such as monocrystalline silicon, polycrystalline silicon, and microcrystalline silicon.

[0122] In some examples, such as Figure 13 As shown, the second doped conductive layer 106 can be obtained, for example, within the second surface B of the semiconductor substrate 101 through a doping process, ion implantation, or other methods. For example, a P-type conductive layer formed within the surface of the n-type semiconductor substrate 101 by a boron diffusion process can be used. + Emitter, etc. Not limited to this, in other examples, the second doped conductive layer 106 may be deposited on the second surface B of the semiconductor substrate 101 by means of a chemical vapor deposition process, etc.

[0123] According to some embodiments of this application, a passivation layer is further disposed on the surface and side surface C of the second doped conductive layer 106 away from the semiconductor substrate 101. The solar cell also includes a second electrode 108, which is electrically connected through the passivation layer and the second doped conductive layer 106. The material of the second electrode 108 is similar to that of the first electrode 105, and will not be described in detail here.

[0124] It is understood that the passivation layer 104 can be fabricated after the first doped conductive layer and the second doped conductive layer are fabricated, and can be double-sided coated using ALD. Therefore, it is located on the surfaces of the first and second doped conductive layers that are away from the semiconductor substrate 101, as well as on the gap surface and side surface C. Furthermore, the aforementioned materials and structures of the passivation layer 104, such as its thickness setting, are suitable not only for double-sided contact batteries but also for back-contact batteries.

[0125] Based on the above examples, the battery performance of the TOPCon battery provided in this application example and the conventional TOPCon battery were tested. The main difference between the conventional TOPCon battery and the TOPCon battery in this application example is that in the TOPCon battery provided in this application example, the first surface A of the semiconductor substrate 101 is provided with a first texture structure, a second texture structure, and a third texture structure as described above, and the first doped conductive layer is spaced apart on the first region. In contrast, the first texture structure is arranged on the entire first surface of the semiconductor substrate 101 of the conventional TOPCon battery, and the first doped conductive layer covers the first surface. The test results are shown in Table 1 below. It can be seen that after adopting the specific texture structure setting of this application, although the series resistance (Rs) increases, causing some photoelectric loss and reducing the fill factor (FF), the short-circuit current (Isc), open-circuit voltage (Voc), and conversion efficiency (Eff) are all significantly improved. This shows that the photogenerated carrier capability of the solar cell provided in this application example is enhanced, and the bifaciality is improved.

[0126] Table 1

[0127]

[0128] In some examples, such as Figure 13 As shown, the semiconductor substrate 101 also includes a side surface C connected between the first surface A and the second surface B. The side surface C has a fourth texture structure, the configuration of which is the same as described above and will not be repeated here. In this case, the passivation layer can be located on the side surface C with the fourth texture structure, which is beneficial for forming a passivation layer with higher density and uniformity and reducing recombination loss of the side surface C, but is not limited to this.

[0129] In other examples, Figure 14 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of this application, as shown below. Figure 14As shown, the semiconductor substrate 101 also includes a side surface C connected between the first surface A and the second surface B. The solar cell may also include a third doped conductive layer located on the side surface. The third doped conductive layer may cover the entire side surface C or partially cover the side surface C. For example, the ratio of the width of the third doped conductive layer covering the side surface to the width of the side surface is greater than or equal to 50%, such as 50%, 60%, 70%, 80%, 90%, 100%, etc. The third doped conductive layer is continuously disposed with the first doped conductive layer 102 and has the same doping type.

[0130] For example Figure 14 As shown, the solar cell may further include an interface passivation layer located between the side surface C of the semiconductor substrate 101 and the third doped conductive layer. In this case, the uniformity and density of the film formation can be improved based on the fourth texture structure on the side surface C, thereby improving the chemical passivation of the side surface C. Further, the interface passivation layer is a tunneling oxide layer 103. The third doped conductive layer can form a tunneling oxide passivation contact structure with the tunneling oxide layer 103 on the side surface C. The passivation contact structure reduces the probability of recombination of carriers of different polarities on the side of the solar cell by selectively utilizing the carriers, thereby improving the field passivation performance of the side surface C.

[0131] The following uses back-contact batteries, such as TBC batteries, as an example to explain their applicability in this application. Figure 15 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of this application. Figure 15 As shown, the first surface A further includes a second region A2, which is alternately distributed with the first region A1, with the gap region located between the first region A1 and the second region A2. The solar cell may also include a second doped conductive layer 106, located on the second region A2 of the semiconductor substrate 101, and the second region A2 has a fifth texture structure. In this case, the gap region may have a first texture structure 1011, and may further have a third texture structure 1012. The first region A1 may have a second texture structure 1021. The configuration of the first texture structure 1011, the second texture structure 1021 and the third texture structure 1012 is the same as described above, and will not be repeated here.

[0132] Since the first doped conductive layer 102 on the first region A1 and the second doped conductive layer 106 on the second region A2 are formed after different surface treatment processes, the dimensions of the fifth texture structure and the second texture structure 1021 can be different. In some examples, the first doped conductive layer 102 can be a P-type doped conductive layer, and the second doped conductive layer 106 can be an N-type doped conductive layer. In this case, the surface size of the fifth texture structure can be larger than the surface size of the second texture structure 1021, and / or, the height of the fifth texture structure can be smaller than the height of the second texture structure 1021. This is more conducive to increasing the contact area between the P-type doped conductive layer and the first electrode 105, thereby improving the hole collection effect. When the conductivity of the P-type doped conductive layer is worse than that of the N-type doped conductive layer, it is beneficial to maintain the balance of hole and electron transport.

[0133] For example, the first doped conductive layer 102 may be a P-type doped polycrystalline silicon layer, the second doped conductive layer 106 may be an N-type doped polycrystalline silicon layer, and the solar cell may also include a tunneling oxide layer 103 located between the semiconductor substrate 101 and the first doped conductive layer 102, and another tunneling oxide layer 107 located between the semiconductor substrate 101 and the second doped conductive layer 106.

[0134] Of course, this is not the only example. In other examples, the first doped conductive layer 102 can be an N-type doped conductive layer and the second doped conductive layer 106 can be a P-type doped conductive layer. In this case, the surface size of the fifth texture structure can be smaller than the surface size of the second texture structure 1021, and the surface size of the fifth texture structure can be larger than the height of the second texture structure 1021.

[0135] For example, the first doped conductive layer 102 may be an N-type doped polycrystalline silicon layer, and the second doped conductive layer 106 may be a P-type doped amorphous silicon layer. The solar cell may also include a tunneling oxide layer 103 located between the semiconductor substrate 101 and the first doped conductive layer 102, and an intrinsic amorphous silicon layer located between the semiconductor substrate 101 and the second doped conductive layer 106. In this case, the corresponding solar cell type is a hybrid cell combining TBC (TopCon-Back Contact) and HJT phases.

[0136] In some examples, the solar cell may also include a passivation layer located on the surface of the first doped conductive layer 102, the second doped conductive layer 106 and the gap region, and another passivation layer 109 located on the second surface B.

[0137] In some examples, such as Figure 15As shown, the semiconductor substrate 101 also includes a side surface C connected between the first surface A and the second surface B. The side surface C has a fourth texture structure, the configuration of which is the same as described above and will not be repeated here. In this case, the passivation layer can also be located on the side surface C with the fourth texture structure, which is beneficial for forming a passivation layer with higher density and uniformity and reducing recombination loss of the side surface C, but it is not limited to this.

[0138] The fabrication of the first textured structure 1011 and the second textured structure 1021 is described below. Specifically, taking a double-sided contact battery as an example, the second textured structure 1021 can be obtained by texturing and polishing the first surface A of the semiconductor substrate 101 to obtain a polished microstructure, i.e., the second textured structure 1021. A first doped conductive layer 102 is formed on the polished first surface A. Since the first doped conductive layer 102 can be deposited relatively conformally, the second textured structure 1021 with the same morphology as the polished microstructure is retained on the first doped conductive layer 102.

[0139] In some examples, after a mask is formed on the first doped conductive layer 102, appropriate laser conditions such as energy density and spot size are selected, and laser etching is used to remove part of the mask and perform alkaline washing to form the first doped conductive layer 102 with spaced distribution and the spacer gap, so that the surface of the spacer gap has a first texture structure 1011.

[0140] Specifically, taking the first doped conductive layer 102 as the first doped polycrystalline silicon layer as an example, an intrinsic amorphous silicon layer is deposited on the surface by chemical vapor deposition, and then a doped polycrystalline silicon layer, namely the first doped conductive layer 102, is formed by diffusion process. At this time, a layer of phosphosilicate glass can be formed on the surface of the first doped conductive layer 102 as a mask for alkaline washing.

[0141] It is understandable that, compared to double-sided contact batteries, the preparation methods of the first texture structure 1011 and the second texture structure 1021 in the back contact battery are similar. The main difference is that, after patterning the first doped conductive layer 102, a second doped conductive layer 106 and a mask are deposited on the surface. Laser etching is used to remove part of the mask and alkaline washing is performed to form alternating first doped conductive layers 102 and second doped conductive layers 106 and gap regions, so that the surface of the gap regions has the first texture structure 1011.

[0142] According to another embodiment of this application, a photovoltaic module is provided, comprising: a plurality of solar cells as described above; an interconnecting element electrically interconnected with the plurality of solar cells to connect the solar cells into a solar cell string; and an encapsulation layer covering the surface of the plurality of solar cells.

[0143] According to embodiments of this application, the number of solar cells connected in series can be 4 to 80. Multiple solar cells can form several battery modules, each module having the same number of back-contact cells. The cells within a module are connected in series, and the modules can be connected in series or in parallel.

[0144] According to embodiments of this application, the interconnecting component may be solder ribbon, metal wire, conductive tape, etc.

[0145] According to embodiments of this application, the encapsulation structure may include a backplate, an encapsulating film, a glass panel, etc., to improve the stability of the solar cell string. The glass panel is located on the front of the solar cell string, and the backplate is located on the back of the solar cell string, both serving a protective function. The adhesive film is the adhesive film between the solar cell string and the glass panel and backplate, serving a bonding and fixing function, and must be made of a transparent material.

[0146] In some examples, the encapsulating film can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene elastomer (POE) film, or polyethylene terephthalate (PET) film. In some examples, the cover or backing plate can be a light-transmitting film layer such as a glass cover or a plastic cover.

[0147] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A solar cell, comprising: A semiconductor substrate includes a first surface, a second surface, and a side surface connected between the first surface and the second surface. The first surface includes first regions spaced apart along a first direction, and there are gap regions between adjacent first regions. The gap regions have a first texture structure. The side surface has a fourth texture structure. A first doped conductive layer is located on the first region of the semiconductor substrate, and the first region has a second textured structure; A passivation layer is located on the surface of the spacer region and on at least one of the following structural surfaces: the second surface, the side surface, and the surface of the first doped conductive layer away from the semiconductor substrate. The first electrode is located on the first doped conductive layer and is in electrical contact with the first doped conductive layer. Wherein, the height of the first texture structure is less than the height of the second texture structure, and / or the surface size of the first texture structure is greater than the surface size of the second texture structure; the surface size of the fourth texture structure is greater than the surface size of the first texture structure.

2. The solar cell according to claim 1, wherein, The height of the fourth texture structure is less than the height of the second texture structure.

3. The solar cell according to claim 1, wherein, The height of the fourth texture structure is greater than the height of the first texture structure.

4. The solar cell according to claim 1, wherein, Some of the first texture structures are arranged in stripes along the extension direction of the first region, and some of the second texture structures are arranged in stripes along the extension direction of the first region.

5. The solar cell according to claim 1, wherein, The interval region includes multiple first sub-regions and multiple second sub-regions; The first sub-region has a third texture structure, the second sub-region has the first texture structure, the first sub-region and the second sub-region are arranged alternately along a second direction, and the second direction intersects with the first direction; The height of the first texture structure is less than the height of the third texture structure, and / or the surface size of the first texture structure is greater than the surface size of the third texture structure.

6. The solar cell according to claim 1, wherein, The interval region includes a plurality of first sub-regions and a plurality of second sub-regions, the first sub-regions and the second sub-regions being arranged alternately along a second direction, the second direction intersecting the first direction; The first sub-region has a third texture structure, and the second sub-region has the first texture structure; The third texture structures partially overlap in the first sub-region. Along the direction away from the surface of the first sub-region, the distance between the bottom surface of the outermost third texture structure and the bottom surface of its adjacent third texture structure is less than or equal to 2 μm.

7. The solar cell according to claim 5 or 6, wherein, The height of the second texture structure is less than the height of the third texture structure.

8. The solar cell according to claim 1, wherein, The surface size of the first texture structure ranges from 10 to 28 μm; Alternatively, the surface size of the second texture structure ranges from 5 to 15 μm; Alternatively, the surface size of the third texture structure ranges from 5 to 15 μm; Alternatively, the surface size of the fourth texture structure may range from 15 to 40 μm.

9. The solar cell according to claim 1, wherein, The interval region includes a plurality of first sub-regions and a plurality of second sub-regions, the first sub-regions and the second sub-regions being arranged alternately along a second direction, the second direction intersecting the first direction; The first sub-region has a third texture structure, and the second sub-region has the first texture structure; Along the second direction, the width of the first sub-region is less than or equal to 400 μm, and / or the spacing between adjacent first sub-regions is 20 μm to 400 μm.

10. The solar cell according to claim 1, wherein, The interval region includes multiple first sub-regions and multiple second sub-regions; The first sub-region has a third texture structure, the second sub-region has the first texture structure, the first sub-region and the second sub-region are arranged alternately along a second direction, and the second direction intersects with the first direction; The height of the first texture structure is less than the height of the third texture structure, and / or the surface size of the first texture structure is greater than the surface size of the third texture structure; Along the second direction, the width of the first sub-region accounts for a proportion of the sum of the width of the first sub-region and the spacing between adjacent first sub-regions that is greater than or equal to 20% and less than or equal to 70%. And / or, the area of ​​the first sub-region is greater than or equal to 20% and less than or equal to 70% of the area of ​​the interval region.

11. The solar cell according to claim 1, wherein, Along the thickness direction of the semiconductor substrate, the surface of the spacer region is closer to the second surface than the surface of the first region.

12. The solar cell according to claim 11, wherein, The height difference between the surface of the first region and the surface of the interval region is 1 μm to 5 μm.

13. The solar cell according to claim 1 or 11, wherein, The first surface further includes a transition region located between the first region and the interval region; The transition region has a raised structure, and the one-dimensional dimension of the raised structure is different from the one-dimensional dimension of both the first texture structure and the second texture structure.

14. The solar cell according to claim 13, wherein, Along the first direction, the width of the transition region is 1 μm to 50 μm; And / or, along the first direction, the transition region has a protruding end that protrudes toward the interval region and a recessed end that is recessed away from the interval region, the distance between the protruding end and the recessed end being less than or equal to 50 μm; And / or, the surface of the transition zone has a step with a height different from the surface of the interval zone and the surface of the first region.

15. The solar cell according to claim 13, wherein, The transition region bends and extends into multiple serrated structures along a second direction intersecting the first direction; Wherein, along the second direction, the length of the serrated structure is less than or equal to 200 μm; and / or, at the recessed end of the serrated structure that is recessed away from the spacer region, the angle formed by the extension direction of the serrated structure and the extension direction of the first doped conductive layer is a first serrated angle, the first serrated angle being less than or equal to 30°; and / or, at the recessed end of the serrated structure that is recessed away from the spacer region, the angle formed between the extension directions of the serrated structure is a second serrated angle, the second serrated angle being greater than or equal to 120°.

16. The solar cell according to claim 14, wherein, The interval region includes multiple first sub-regions and multiple second sub-regions; The first sub-region has a third texture structure, and the second sub-region has the first texture structure; The height of the first texture structure is less than the height of the third texture structure, and / or the surface size of the first texture structure is greater than the surface size of the third texture structure; Wherein, along the first direction, the recessed end is set in a region corresponding to the area where the third texture structure is located.

17. The solar cell according to claim 1, wherein, Along the thickness direction of the semiconductor substrate, the height of the region where the fourth texture structure is distributed accounts for less than or equal to 98% of the height of the side surface.

18. The solar cell according to claim 1, wherein, The solar cell includes: The tunneling oxide layer located in the first region; The first doped conductive layer is located on the surface of the tunneling oxide layer, and the first doped conductive layer has doping elements of the same conductivity type as the semiconductor substrate; The passivation layer located on the surface of the first doped conductive layer and the surface of the spacer region; The solar cell further includes a third doped conductive layer located on the side surface, wherein the ratio of the width of the third doped conductive layer covering the side surface to the width of the side surface is greater than or equal to 50%. The third doped conductive layer has the same doping type as the first doped conductive layer.

19. The solar cell according to claim 1, wherein, The passivation layer material includes an aluminum oxide layer, the thickness of which is greater than or equal to 5 nm and less than or equal to 10 nm.

20. The solar cell according to claim 1, wherein, The first surface further includes a second region, which is distributed alternately with the first region, the interval region being located between the first region and the second region; The solar cell also includes: A second doped conductive layer is located on the second region of the semiconductor substrate, the second region having a fifth texture structure.

21. A photovoltaic module, comprising: Multiple solar cells as described in any one of claims 1 to 20; Interconnectors are electrically interconnected with multiple solar cells to connect the solar cells into a solar cell string; as well as An encapsulation layer covers the surface of the plurality of solar cells.

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