Solar cell and preparation method thereof
By forming specific protrusions on the surface of the N-type and P-type doped regions of solar cells, the surface roughness difference is optimized, thus solving the problem of surface roughness difference affecting the performance of solar cells and achieving higher photoelectric conversion efficiency.
Patent Information
- Application Number
- CN202511914555.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-17
- Publication Date
- 2026-03-13
AI Technical Summary
In the prior art, the difference in surface roughness between p-poly Si doped regions and N-poly Si doped regions affects the contact resistance and passivation effect of solar cells, resulting in poor performance.
By forming protrusions with specific height and area ratios on the surfaces of N-type and P-type doped regions, the roughness of the N-type doped region is controlled and the roughness of the P-type doped region is reduced. Combined with the use of a tunneling layer, the metal contact and interface passivation effects are optimized.
This increases the contact area between the N-type doped region and the metal electrode, reduces the contact resistivity, enhances the fill factor and open-circuit voltage, and thus improves the photoelectric conversion efficiency of the solar cell.
Smart Images
Figure CN121665772A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of battery technology, specifically to a solar cell and its fabrication method. Background Technology
[0002] Different elements are doped into the polycrystalline silicon layer of solar cells, forming N-type polycrystalline silicon (N-poly Si) doped regions and P-type polycrystalline silicon (p-poly Si) doped regions to achieve selective carrier tunneling transport and surface passivation. Under conventional process conditions, the surface roughness of the p-poly Si doped region is higher than that of the N-poly Si doped region, which is considered a process inhomogeneity and attempted to be eliminated. In fact, the difference in surface roughness between the p-poly Si and N-poly Si doped regions affects the contact resistance and passivation effect of the solar cell. Therefore, how to effectively utilize the surface roughness of the p-poly Si and N-poly Si doped regions to improve the performance of solar cells is an urgent problem to be solved. Summary of the Invention
[0003] Therefore, the present invention provides a solar cell and a method for preparing the same, in order to solve the problem of poor performance of solar cells in the prior art.
[0004] To achieve the above objectives, a first aspect of the present invention provides a solar cell, comprising a silicon substrate and a polycrystalline silicon layer, wherein the polycrystalline silicon layer is disposed on the surface of the silicon substrate, the polycrystalline silicon layer includes at least one N-type doped region, and a first protrusion is formed on the surface of the N-type doped region, the height of the first protrusion being 10-30 nm, and the ratio of the projected area of the first protrusion of at least one N-type doped region on the surface of the silicon substrate to the surface area of the N-type doped region being 5-20%.
[0005] The polycrystalline silicon layer further includes a P-type doped region, and a second protrusion is formed on the surface of the P-type doped region. The height of the second protrusion is 0~15 nm, and the ratio of the projected area of the second protrusion of at least one P-type doped region on the silicon substrate surface to the surface area of the P-type doped region is 15~40%.
[0006] The ratio of the roughness Ra2 of the P-type doped region to the roughness Ra1 of the N-type doped region is 1.2 to 3.0.
[0007] The roughness Ra1 of the N-type doped region is 0.1~15nm, and the roughness Ra2 of the P-type doped region is 0.3~30nm.
[0008] This also includes:
[0009] A tunneling layer disposed on the surface of the silicon substrate;
[0010] The tunneling layer is one or more of the following: silicon oxide layer, aluminum oxide layer, titanium oxide layer, zinc oxide layer, intrinsic amorphous silicon layer, intrinsic polycrystalline silicon layer, intrinsic nanocrystalline silicon layer, and intrinsic mixed-crystal silicon layer.
[0011] The polycrystalline silicon layer is disposed on the surface of the tunneling layer away from the silicon substrate.
[0012] The silicon substrate includes a first surface and a second surface disposed opposite to each other;
[0013] The first surface is a light-facing surface, and a first tunneling layer, a P-type doped layer and a first electrode are sequentially stacked on the first surface. The second surface is sequentially stacked with a second tunneling layer, an N-type doped layer and a second electrode.
[0014] The first tunneling layer and the second tunneling layer are one or more of the following: silicon oxide layer, aluminum oxide layer, titanium oxide layer, zinc oxide layer, intrinsic amorphous silicon layer, intrinsic polycrystalline silicon layer, intrinsic nanocrystalline silicon layer, and intrinsic mixed-crystal silicon layer.
[0015] The silicon substrate includes a first surface and a second surface disposed opposite to each other;
[0016] The first surface is a light-facing surface, and a textured surface is provided on the first surface. The second surface is provided with alternating P-type doped regions and N-type doped regions.
[0017] A second aspect of the present invention provides a method for preparing a solar cell, comprising:
[0018] A tunneling layer is formed on the surface of a silicon substrate;
[0019] A polycrystalline silicon layer is formed on the surface of the tunneling layer. The polycrystalline silicon layer includes at least one N-type doped region. A first protrusion is formed on the surface of the N-type doped region. The height of the first protrusion is 10~30nm. The ratio of the projected area of the first protrusion of at least one N-type doped region on the silicon substrate surface to the N-type doped region is 5~20%.
[0020] The formation of a polycrystalline silicon layer on the surface of the tunneling layer includes:
[0021] An amorphous silicon layer is deposited on the surface of the tunneling layer;
[0022] The amorphous silicon layer is patterned to form a first region;
[0023] The first region is doped to obtain the N-type doped region;
[0024] The N-type doped region is annealed at a temperature of 700~900℃ to obtain an N-type doped polycrystalline silicon layer.
[0025] The formation of a polycrystalline silicon layer on the surface of the tunneling layer includes:
[0026] At a temperature of 560~630℃, a polycrystalline silicon layer is directly deposited on the surface of the first region of the tunneling layer;
[0027] The polycrystalline silicon in the first region is doped to obtain the N-type doped polycrystalline silicon layer.
[0028] In this process, a grain growth promoter is added to the doping source.
[0029] The promoter includes at least one of aluminum and gallium.
[0030] The polycrystalline silicon layer further includes a P-type doped region, and a second protrusion is formed on the surface of the P-type doped region. The height of the second protrusion is 0~15nm, and the ratio of the projected area of the second protrusion of at least one P-type doped region on the silicon substrate surface to the surface area of the P-type doped region is 15~40%.
[0031] The formation of a polycrystalline silicon layer on the surface of the tunneling layer includes:
[0032] An amorphous silicon layer is deposited on the surface of the tunneling layer;
[0033] The amorphous silicon layer is patterned to form a second region;
[0034] The second region is doped to obtain the P-type doped region;
[0035] The P-type doped region is annealed at a temperature above 850°C to obtain a polycrystalline silicon layer doped with P-type dopant.
[0036] The formation of a polycrystalline silicon layer on the surface of the tunneling layer includes:
[0037] A polycrystalline silicon layer is directly deposited on the surface of the second region of the tunneling layer at a temperature of 560~650℃.
[0038] The polycrystalline silicon in the second region is doped to obtain the P-type doped polycrystalline silicon layer.
[0039] In the doping process, a grain growth inhibitor is added to the doping source.
[0040] The inhibitor includes at least one of carbon, nitrogen, oxygen, and fluorine.
[0041] The solar cell provided by this invention includes a silicon substrate and a polycrystalline silicon layer. The polycrystalline silicon layer is disposed on the surface of the silicon substrate and includes at least one N-type doped region. A first protrusion is formed on the surface of the N-type doped region. The height of the first protrusion is 10-30 nm. The ratio of the projected area of the first protrusion of the at least one N-type doped region on the surface of the silicon substrate to the surface area of the N-type doped region is 5-20%. Compared with the roughness of existing N-type doped regions, this embodiment improves the protrusion density and height on the surface of the N-type doped region, that is, improves the roughness of the N-type doped region 11. This allows more point contacts to be formed in the N-type doped region, thereby enhancing the contact area between the N-type doped region and the metal electrode, helping to reduce the contact resistivity of the N-type doped region, thereby improving the cell fill factor and open-circuit voltage, and thus improving the photoelectric conversion efficiency of the solar cell. Attached Figure Description
[0042] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof.
[0043] Figure 1 This is a top view of a partial structure of a solar cell provided in an embodiment of the present invention;
[0044] Figure 2 The surface morphology of the N-type doped region in the polycrystalline silicon layer is shown;
[0045] Figure 3 A cross-sectional topography of the N-type doped region in the polycrystalline silicon layer is shown.
[0046] Figure 4 The surface morphology of the P-type doped region in the polycrystalline silicon layer is shown;
[0047] Figure 5 The cross-sectional morphology of the P-type doped region in the polycrystalline silicon layer is shown;
[0048] Figure 6 A cross-sectional view of a partial structure of a solar cell provided in an embodiment of the present invention is shown;
[0049] Figure 7 A cross-sectional view of a partial structure of another solar cell provided in an embodiment of the present invention is shown;
[0050] Figure 8 A cross-sectional view of a partial structure of another solar cell provided in an embodiment of the present invention is shown;
[0051] Figure 9 A flowchart of a solar cell fabrication method provided in this embodiment is shown. Detailed Implementation
[0052] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.
[0053] As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the related enumerated entries.
[0054] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used in this disclosure, the singular forms “a” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.
[0055] When the terms “comprising” and / or “made of” are used in this disclosure, they specify the presence of a feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0056] Embodiments of this disclosure can be described with reference to plan views and / or cross-sectional views, taking into account the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.
[0057] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so specified in this disclosure.
[0058] In one aspect, this embodiment provides a solar cell.
[0059] Figure 1 This is a top view of a partial structure of a solar cell provided in an embodiment of the present invention. Figure 2 The surface morphology of the N-type doped region in the polycrystalline silicon layer is shown. Figure 3 A cross-sectional topography of the N-type doped region in a polycrystalline silicon layer is shown. Combined with... Figures 1 to 3The solar cell includes a silicon substrate 20 and a polycrystalline silicon layer 10. The polycrystalline silicon layer 10 is disposed on the surface of the silicon substrate 20 and includes at least one N-type doped region 11. A first protrusion 111 is formed on the surface of the N-type doped region 11. The height of the first protrusion 111 is 10-30 nm. The ratio of the projected area of the first protrusion 111 on the surface of the silicon substrate 20 to the surface area of the N-type doped region 11 is 5-20%. Compared with the roughness of the existing N-type doped region 11, this embodiment improves the roughness of the N-type doped region 11 by controlling the height of the first protrusion of the N-type doped region to 10-30 nm and the ratio of the projected area of the first protrusion on the surface of the silicon substrate 20 to the surface area of the N-type doped region 11 to 5-20%, thereby forming more point contacts in the N-type doped region. This enhances the contact area between the N-type doped region and the metal electrode, which helps to reduce the contact resistivity of the N-type doped region. This increases the fill factor (FF) and open-circuit voltage (Voc) of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.
[0060] Figure 4 The surface morphology of the P-type doped region in the polycrystalline silicon layer is shown. Figure 5 The cross-sectional morphology of the P-type doped region in the polycrystalline silicon layer is shown. Combined with... Figure 1 , Figure 4 and Figure 5 The polysilicon layer also includes at least one P-type doped region 12, and a second protrusion 121 is formed on the surface of the P-type doped region 12. For example... Figure 5 As shown, the height of the second protrusion 121 is 0~15nm, and the ratio of the projected area of the second protrusion 121 on the silicon substrate surface to the surface area of the P-type doped region is 15~40%. Compared with the roughness of the existing P-type doped region 12, this embodiment reduces the roughness of the P-type doped region 12 by controlling the height of the second protrusion to 0~15nm and the ratio of the projected area of the second protrusion on the silicon substrate surface to the surface area of the P-type doped region to 15~40%. This helps to reduce the interface state density of the P-type doped region 12 and improve the interface passivation effect, thereby improving the cell fill factor and open circuit voltage, and thus improving the photoelectric conversion efficiency of the solar cell.
[0061] It should be noted that the height of the first protrusion and the second protrusion mentioned in this embodiment refers to the height of the first protrusion and the second protrusion above the surrounding grains.
[0062] In some embodiments, the ratio of the roughness Ra2 of the P-type doped region 12 to the roughness Ra1 of the N-type doped region 11 is greater than or equal to 1.2. By controlling the ratio of Ra2 to Ra1 to be above 1.2, better metal contact and interface passivation can be achieved simultaneously by utilizing the difference in surface roughness between the P-type doped region 12 and the N-type doped region 11.
[0063] In some embodiments, the ratio of the roughness Ra2 of the P-type doped region 12 to the roughness Ra1 of the N-type doped region 11 is 1.2 to 3.0.
[0064] In some embodiments, the roughness Ra1 of the N-type doped region 11 is 0.1~15 nm, and the roughness Ra2 of the P-type doped region 12 is 0.3~30 nm.
[0065] It should be noted that the roughness in this embodiment is measured in a vacuum environment using an atomic force microscope (AFM), which has a resolution of 0.01 nm. Roughness Ra1 and roughness Ra2 are the arithmetic mean of the absolute values of the height deviations relative to the central plane within the observation area, where roughness Ra1 is the arithmetic mean of the N-type doped region and roughness Ra2 is the arithmetic mean of the P-type doped region.
[0066] Figure 6 A cross-sectional view of a partial structure of a solar cell provided in an embodiment of the present invention is shown. Figure 6 As shown, the solar cell includes a silicon substrate 20 and a tunneling layer 30. The tunneling layer 30 is disposed on the surface of the silicon substrate 20, and a polycrystalline silicon layer 10 is disposed on the surface of the tunneling layer 30 away from the silicon substrate. The tunneling layer is one or more of the following: silicon oxide layer, aluminum oxide layer, titanium oxide layer, zinc oxide layer, intrinsic amorphous silicon layer, intrinsic polycrystalline silicon layer, intrinsic nanocrystalline silicon layer, and intrinsic mixed-crystal silicon layer.
[0067] Figure 7 A cross-sectional view of a partial structure of another solar cell provided in an embodiment of the present invention is shown. For example... Figure 7 As shown, the silicon substrate 20 includes a first surface and a second surface disposed opposite to each other; the first surface and the second surface are two opposing surfaces of the silicon substrate 20, for example, the first surface is the upper surface of the silicon substrate 20 and the second surface is the lower surface of the silicon substrate 20.
[0068] In some embodiments, the first surface is a light-facing surface, and a first tunneling layer 31, a P-type doped layer 62 and a first electrode 41 are sequentially stacked on the first surface, and a second tunneling layer 32, an N-type doped layer 61 and a second electrode 42 are sequentially stacked on the second surface.
[0069] In some embodiments, the first tunneling layer 31 and the second tunneling layer 32 are one or more of the following: silicon oxide layer, aluminum oxide layer, titanium oxide layer, zinc oxide layer, intrinsic amorphous silicon layer, intrinsic polycrystalline silicon layer, intrinsic nanocrystalline silicon layer, and intrinsic mixed-crystal silicon layer.
[0070] Figure 8 A cross-sectional view of a partial structure of another solar cell provided in an embodiment of the present invention is shown. Figure 8As shown, the silicon substrate includes a first surface and a second surface disposed opposite to each other; the first surface and the second surface are two opposing surfaces of the silicon substrate 20, for example, the first surface is the upper surface of the silicon substrate 20 and the second surface is the lower surface of the silicon substrate 20.
[0071] In some embodiments, the first surface is a light-facing surface, and a textured surface 50 is provided on the first surface. The second surface is provided with alternating P-type doped regions 12 and N-type doped regions 11. The P-type doped regions 12 are electrically connected to the first electrode 41, and the N-type doped regions 11 are electrically connected to the second electrode 42.
[0072] The solar cell provided in this embodiment has a first protrusion formed on the surface of the N-type doped region of the polycrystalline silicon layer. The height of the first protrusion is 10~30nm, and the ratio of the projected area of the first protrusion on the silicon substrate surface to the surface area of the N-type doped region is 5~20%. This increases the protrusion density and height on the surface of the N-type doped region, which can enhance the contact area between the N-type doped region and the metal electrode, reduce the contact resistance, thereby increasing the cell fill factor, improving the open circuit voltage, and thus improving the photoelectric conversion efficiency of the solar cell.
[0073] Secondly, this embodiment provides a method for preparing a solar cell.
[0074] Figure 9 A flowchart illustrating a solar cell fabrication method provided in this embodiment is shown. Figure 9 As shown, the method for fabricating a solar cell includes:
[0075] Step S701: A tunneling layer is formed on the surface of the silicon substrate.
[0076] For example, a silicon oxide layer is formed on the surface of a silicon substrate as a tunneling layer. The thickness of the silicon oxide layer can be 1 to 2 nanometers.
[0077] Step S702: A polysilicon layer is formed on the surface of the tunneling layer. The polysilicon layer includes at least one N-type doped region. A first protrusion is formed on the surface of the N-type doped region. The height of the first protrusion is 10~30 nm. The ratio of the projected area of the first protrusion of the at least one N-type doped region on the silicon substrate surface to the N-type doped region is 5~20%.
[0078] In the embodiments of this disclosure, the polycrystalline silicon layer can be obtained by plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD).
[0079] Forming a polycrystalline silicon layer on the surface of a tunneling layer by PECVD includes: depositing an amorphous silicon layer on the surface of the tunneling layer; patterning the amorphous silicon layer to form a first region; doping the first region to obtain an N-type doped region; and annealing the N-type doped region at a temperature of 700~900℃ to obtain an N-type doped polycrystalline silicon layer.
[0080] Forming a polycrystalline silicon layer on the surface of a tunneling layer by LPCVD includes: directly depositing a polycrystalline silicon layer on the surface of a first region of the tunneling layer at a temperature of 560~630℃; and doping the polycrystalline silicon in the first region to obtain an N-type doped polycrystalline silicon layer.
[0081] During doping, a grain growth promoter is added to the doping source. In some embodiments, the promoter includes at least one element selected from aluminum (Al) and gallium (Ga).
[0082] In some embodiments, the polysilicon layer further includes at least one P-type doped region, the surface of which is formed with a second protrusion, the height of which is 0-15 nm, and the ratio of the projected area of the second protrusion of the at least one P-type doped region on the silicon substrate surface to the surface area of the P-type doped region is 15-40%.
[0083] Forming a polycrystalline silicon layer on the surface of a tunneling layer by PECVD includes: depositing an amorphous silicon layer on the surface of the tunneling layer; patterning the amorphous silicon layer to form a second region; doping the second region to obtain a P-type doped region; and annealing the P-type doped region at a temperature above 850°C to obtain a P-type doped polycrystalline silicon layer.
[0084] Forming a polycrystalline silicon layer on the surface of a tunneling layer by LPCVD includes: directly depositing a polycrystalline silicon layer on the surface of a second region of the tunneling layer at a temperature of 560~650℃; and doping the polycrystalline silicon in the second region to obtain a P-type doped polycrystalline silicon layer.
[0085] During doping, a grain growth inhibitor is added to the dopant source. The inhibitor includes at least one element selected from carbon (C), nitrogen (N), oxygen (O), and fluorine (F).
[0086] To further understand the fabrication methods of solar cells, the following section uses the PECVD process as an example to introduce the fabrication process of back contact (BC) solar cells.
[0087] Step 1: Form a tunneling layer on the silicon substrate.
[0088] Step 2: Deposit an amorphous silicon layer on the surface of the tunneling layer.
[0089] Step 3: Pattern the amorphous silicon layer to form a first region and a second region. The first region can be subsequently used to form N-type polycrystalline silicon, and the second region can be subsequently used to form P-type polycrystalline silicon.
[0090] Step 4: Dope the first region with phosphorus (P) to form an N-type doped region; dope the second region with boron (B) to form a P-type doped region.
[0091] When implementing the doping process, trace amounts of grain growth promoters such as Al and / or Ga can be added to the doping source that forms the N-type doped region, and trace amounts of grain growth inhibitors such as C and / or F can be added to the doping source that forms the P-type doped region.
[0092] Step 5: Anneal and crystallize the N-type doped and P-type doped regions to obtain polycrystalline silicon layers with different roughness.
[0093] For N-type doped regions: annealing is performed at a temperature of 700-900℃ and / or for a shorter annealing time to promote the increase of polycrystalline silicon grain size and form a relatively smooth surface morphology. However, small-sized grains at the growth interface are squeezed by large-sized grains, resulting in a locally extruded convex structure.
[0094] For P-type doped regions: annealing is performed at temperatures above 850°C and / or for a longer annealing time to promote the rapid growth of polycrystalline silicon grains in N-type doped regions, thereby forming a surface morphology with higher roughness.
[0095] To further understand the fabrication methods of solar cells, the following section uses LPCVD as an example to introduce the fabrication process of BC solar cells and tunneling layer passivated contact (TOPCON) solar cells.
[0096] Step 1: Form a tunneling layer on the silicon substrate.
[0097] Step 2: Deposit a polycrystalline silicon layer on the surface of the tunneling layer.
[0098] In the first region, a large-grain polycrystalline silicon layer is directly deposited at a temperature of 560~630℃. During the growth of the large-grain polycrystalline silicon, due to the compression of the grains at the growth interface, some polycrystalline silicon is extruded and protrudes, forming the first protrusion.
[0099] In the second region, a polycrystalline silicon layer with fine grains is directly deposited at a temperature of 560~650℃. During the deposition process, the grains grow rapidly, resulting in obvious surface undulations and a significant increase in roughness.
[0100] Step 3: Dope the first region with phosphorus (P) to form an N-type doped region; dope the second region with boron (B) to form a P-type doped region.
[0101] When implementing the doping process, trace amounts of grain growth promoters such as Al and / or Ga can be added to the doping source that forms the N-type doped region, and trace amounts of grain growth inhibitors such as C and / or F can be added to the doping source that forms the P-type doped region.
[0102] During boron doping, the surface roughness of the P-type doped region is further improved because the diffusion temperature of boron is much higher than that of phosphorus.
[0103] In this embodiment, the height of the first bump in the N-type doped region is 10~30nm, and the height of the second bump in the P-type doped region is 0~15nm. Even if passivation layers such as Al2O3 and SiNx are formed on the surface of the polycrystalline silicon layer, the first bump and the second bump still exist.
[0104] The above-mentioned solar cell fabrication method can be carried out using existing process equipment, without the need for additional complex equipment, and is easy to implement on existing production lines with low production costs.
[0105] The solar cell fabrication method provided by this invention includes a polycrystalline silicon layer comprising at least one N-type doped region. A first protrusion is formed on the surface of the N-type doped region, the height of which is 10-30 nm. The projected area of the first protrusion of the at least one N-type doped region on the silicon substrate surface accounts for 5-20% of the N-type doped region. Compared with the roughness of existing N-type doped regions, this embodiment improves the protrusion density and height on the surface of the N-type doped region, i.e., improves the roughness of the N-type doped region 11. This allows for the formation of more point contacts in the N-type doped region, thereby enhancing the contact area between the N-type doped region and the metal electrode. This helps to reduce the contact resistivity of the N-type doped region, thereby improving the cell fill factor and open-circuit voltage, and ultimately improving the photoelectric conversion efficiency of the solar cell.
[0106] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.
Claims
1. A solar cell, characterized in that, The device includes a silicon substrate and a polysilicon layer. The polysilicon layer is disposed on the surface of the silicon substrate. The polysilicon layer includes at least one N-type doped region. A first protrusion is formed on the surface of the N-type doped region. The height of the first protrusion is 10-30 nm. The ratio of the projected area of the first protrusion of at least one N-type doped region on the surface of the silicon substrate to the surface area of the N-type doped region is 5-20%.
2. The solar cell according to claim 1, characterized in that, The polycrystalline silicon layer further includes at least one P-type doped region, and a second protrusion is formed on the surface of the P-type doped region. The height of the second protrusion is 0~15 nm, and the ratio of the projected area of the second protrusion of at least one P-type doped region on the silicon substrate surface to the surface area of the P-type doped region is 15~40%.
3. The solar cell according to claim 2, characterized in that, The ratio of the roughness Ra2 of the P-type doped region to the roughness Ra1 of the N-type doped region is 1.2 to 3.
0.
4. The solar cell according to claim 2, characterized in that, The roughness Ra1 of the N-type doped region is 0.1~15 nm, and the roughness Ra2 of the P-type doped region is 0.3~30 nm.
5. The solar cell according to any one of claims 1-4, characterized in that, Also includes: A tunneling layer disposed on the surface of the silicon substrate; The tunneling layer is one or more of the following: silicon oxide layer, aluminum oxide layer, titanium oxide layer, zinc oxide layer, intrinsic amorphous silicon layer, intrinsic polycrystalline silicon layer, intrinsic nanocrystalline silicon layer, and intrinsic mixed-crystal silicon layer. The polycrystalline silicon layer is disposed on the surface of the tunneling layer away from the silicon substrate.
6. The solar cell according to any one of claims 1-4, characterized in that, The silicon substrate includes a first surface and a second surface disposed opposite to each other; The first surface is a light-facing surface, and a first tunneling layer, a P-type doped layer and a first electrode are sequentially stacked on the first surface. The second surface is sequentially stacked with a second tunneling layer, an N-type doped layer and a second electrode. The first tunneling layer and the second tunneling layer are one or more of the following: silicon oxide layer, aluminum oxide layer, titanium oxide layer, zinc oxide layer, intrinsic amorphous silicon layer, intrinsic polycrystalline silicon layer, intrinsic nanocrystalline silicon layer, and intrinsic mixed-crystal silicon layer.
7. The solar cell according to any one of claims 1-4, characterized in that, The silicon substrate includes a first surface and a second surface disposed opposite to each other; The first surface is a light-facing surface, and a textured surface is provided on the first surface. The second surface is provided with alternating P-type doped regions and N-type doped regions.
8. A method for preparing a solar cell, characterized in that, include: A tunneling layer is formed on the surface of a silicon substrate; A polycrystalline silicon layer is formed on the surface of the tunneling layer. The polycrystalline silicon layer includes at least one N-type doped region. A first protrusion is formed on the surface of the N-type doped region. The height of the first protrusion is 10~30 nm. The ratio of the projected area of the first protrusion of at least one N-type doped region on the silicon substrate surface to the N-type doped region is 5~20%.
9. The method according to claim 8, characterized in that, The formation of a polycrystalline silicon layer on the surface of the tunneling layer includes: An amorphous silicon layer is deposited on the surface of the tunneling layer; The amorphous silicon layer is patterned to form a first region; The first region is doped to obtain the N-type doped region; The N-type doped region is annealed at a temperature of 700~900℃ to obtain an N-type doped polycrystalline silicon layer.
10. The method according to claim 8, characterized in that, The formation of a polycrystalline silicon layer on the surface of the tunneling layer includes: At a temperature of 560~630℃, a polycrystalline silicon layer is directly deposited on the surface of the first region of the tunneling layer; The polycrystalline silicon in the first region is doped to obtain the N-type doped polycrystalline silicon layer.
11. The method according to claim 9 or 10, characterized in that, During doping, a grain growth promoter is added to the doping source.
12. The method according to claim 11, characterized in that, The promoter includes at least one element selected from aluminum and gallium.
13. The method according to claim 8, characterized in that, The polycrystalline silicon layer further includes at least one P-type doped region, and a second protrusion is formed on the surface of the P-type doped region. The height of the second protrusion is 0~15 nm, and the ratio of the projected area of the second protrusion of at least one P-type doped region on the silicon substrate surface to the surface area of the P-type doped region is 15~40%.
14. The method according to claim 13, characterized in that, The formation of a polycrystalline silicon layer on the surface of the tunneling layer includes: An amorphous silicon layer is deposited on the surface of the tunneling layer; The amorphous silicon layer is patterned to form a second region; The second region is doped to obtain the P-type doped region; The P-type doped region is annealed at a temperature above 850°C to obtain a polycrystalline silicon layer doped with P-type dopant.
15. The method according to claim 13, characterized in that, The formation of a polycrystalline silicon layer on the surface of the tunneling layer includes: A polycrystalline silicon layer is directly deposited on the surface of the second region of the tunneling layer at a temperature of 560~650℃. The polycrystalline silicon in the second region is doped to obtain the P-type doped polycrystalline silicon layer.
16. The method according to claim 14 or 15, characterized in that, During doping, a grain growth inhibitor is added to the doping source.
17. The method according to claim 16, characterized in that, The inhibitor includes at least one element selected from carbon, nitrogen, oxygen, and fluorine.