Optical chip and display device

Abstract

The invention provides an optical chip and a display device. The optical chip can comprise a substrate, and a plurality of semiconductor laminated structures, a plurality of first electrodes, a second electrode and a first insulating layer which are arranged on the substrate; the first electrode is located between the semiconductor laminated structures and the substrate, and a groove is formed between any two adjacent semiconductor laminated structures; the second electrode comprises at least one body and a plurality of extension parts, the extension parts are arranged corresponding to the grooves, the extension parts are arranged in the grooves, and the body is connected with at least part of the semiconductor laminated structure; the extension part is isolated from the adjacent semiconductor laminated structure, the extension part is isolated from the adjacent first electrode, and the extension part is isolated from the substrate through a first insulating layer, so that the first insulating layer, a contact interface with the semiconductor laminated structure and a contact interface with the extension part form a structure similar to a capacitor; electrons and holes are prevented from flowing to the side wall of the semiconductor laminated structure, non-radiative recombination is reduced, and the luminous efficiency of the optical chip is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an optical chip and display device. Background Technology

[0002] An optical chip includes a light-emitting device and a driving circuit. The light-emitting device includes an anode, a semiconductor stacked structure, and a cathode. The anode and cathode are located on opposite sides of the semiconductor stacked structure, and the driving circuit is connected to the anode. As device size continues to shrink, the ratio of the sidewalls to the volume of the light-emitting device becomes increasingly larger. During the fabrication of the light-emitting device, damage to the sidewalls may increase. This can easily lead to non-radiative recombination of electrons and holes at the sidewalls, reducing the amount of electrons and holes recombinating in the semiconductor stacked structure and thus decreasing the luminous efficiency of the optical chip. Summary of the Invention

[0003] This application provides an optical chip and a display device to avoid non-radiative recombination of electrons and holes on the sidewalls, thereby improving the luminous efficiency of the optical chip.

[0004] In a first aspect, embodiments of this application provide an optical chip, which may include: a substrate, and a plurality of semiconductor stacked structures, a plurality of first electrodes, a second electrode, and a first insulating layer respectively disposed on the substrate; the plurality of first electrodes are correspondingly disposed with the plurality of semiconductor stacked structures, and the first electrodes are located between the corresponding semiconductor stacked structures and the substrate; a trench is formed between any two adjacent semiconductor stacked structures; the second electrode includes: at least one body and a plurality of extensions, the body being connected to at least a portion of the extensions, and the body also being connected to at least a portion of the semiconductor stacked structures; the extensions are correspondingly disposed with the trench, and the trench contains the extensions; the extensions are positioned between the extensions and adjacent semiconductor stacked structures, and between the extensions and adjacent first electrodes. The extension and the substrate are both isolated by a first insulating layer, which covers both the sidewalls and the bottom of the trench. One surface of the first insulating layer covering the trench sidewalls contacts and connects with one of the adjacent semiconductor stacked structures to form a first interface, while the opposite surface contacts and connects with the extension to form a second interface. The first interface, this portion of the first insulating layer, and the second interface constitute a capacitor-like structure. Under the effect of capacitance, the flow of electrons and holes to the sidewalls of the semiconductor stacked structure can be suppressed, thereby reducing non-radiative recombination of electrons and holes at the sidewalls, thus improving the luminous efficiency of the optical chip and reducing its heat generation. Furthermore, by isolating multiple first and second electrodes and isolating the second electrode from the substrate through the first insulating layer, short circuits between multiple first and second electrodes can be avoided, as can interference from structures on the substrate with the second electrode, thereby improving the reliability of the optical chip and ensuring its normal operation.

[0005] Optionally, the optical chip further includes a second insulating layer disposed on the first surface of the plurality of semiconductor stacked structures facing away from the substrate. The second insulating layer has a plurality of first openings and a plurality of second openings. The first openings correspond to trenches, and extensions are connected to corresponding bodies through corresponding first openings. The second openings correspond to semiconductor stacked structures, exposing a portion of the first surface. The semiconductor stacked structures are connected to the bodies through corresponding second openings. When a portion of the first surface is exposed by a second opening, it means that the second insulating layer covers another portion of the first surface. This prevents current from flowing to the sidewalls of the semiconductor stacked structures, extending the current flow path. Even if current flows to the sidewalls, the recombination of electrons and holes can be prevented due to the capacitance effect.

[0006] Furthermore, the second insulating layer covers the four edges of the first surface, which can effectively block the current flow to the sidewalls of the semiconductor stacked structure, effectively reduce or eliminate the current flow to the sidewalls of the semiconductor stacked structure, thereby further preventing non-radiative recombination of electrons and holes on the sidewalls of the semiconductor stacked structure and further improving the light emission efficiency of the optical chip.

[0007] Optionally, the first insulating layer extends to the first surface of the semiconductor stacked structure on the side opposite to the substrate, and covers the four edges of the first surface. This can block current from flowing to the sidewalls of the semiconductor stacked structure, thereby further preventing non-radiative recombination at the sidewalls of the semiconductor stacked structure and thus further improving the luminous efficiency of the optical chip. It should be understood that the current in this paragraph can be understood as the flow of charge carriers.

[0008] Furthermore, the length covered along the first normal direction at any edge of the first surface is the first length, and the length along the first normal direction at the center of two adjacent grooves is the second length. The ratio of the first length to the second length is 1 / 15 to 1 / 4, which can improve both luminous efficiency and luminous effect.

[0009] Optionally, the first insulating layer extends to the second surface of the semiconductor stack structure facing the substrate, and covers the four edges of the second surface. This blocks current from flowing to the sidewalls of the semiconductor stack structure, thereby preventing nonradiative recombination at the sidewalls and improving the luminous efficiency of the optical chip. It should be understood that the current in this paragraph can be interpreted as the flow of charge carriers.

[0010] Furthermore, the length covered along the second normal direction at any edge of the second surface is the third length, and the length along the second normal direction at the center of two adjacent trenches is the fourth length. The ratio of the third length to the fourth length is 1 / 15 to 1 / 4. The ratio of the third length to the fourth length can be set according to actual conditions. For example, if the ratio of the third length to the fourth length is set small, the obstruction effect on the flow of current to the sidewalls of the semiconductor stack will be weakened, and the luminous efficiency of the optical chip will decrease. Therefore, to improve the luminous efficiency, the ratio of the third length to the fourth length can be set larger.

[0011] Furthermore, the four edges of the first surface of the semiconductor stacked structure facing away from the substrate are covered by a first insulating layer or a second insulating layer. The length of the layer covering any edge of the first surface along the first normal direction of that edge is a first length. The first electrode is the anode, the second electrode is the cathode, and the third length is greater than the first length; or, the first electrode is the cathode, the second electrode is the anode, and the third length is less than the first length. In this way, more holes can be injected into the semiconductor stacked structure to balance the difference in the amount of electrons and holes in the semiconductor stacked structure caused by the slow hole flow rate, thereby further improving the luminous efficiency of the optical chip.

[0012] Optionally, the first insulating layer is made of a light-transmitting material, which can be an insulating light-transmitting material. This insulating light-transmitting material can include, but is not limited to, organic transparent materials such as polymethyl methacrylate, polyester, polycarbonate, polystyrene, polyimide, and silicone resin, and inorganic transparent materials such as silicon oxide, titanium oxide, aluminum nitride, aluminum oxide, silicon nitride, zirconium oxide, magnesium fluoride, tantalum oxide, and silicon carbide. The specific light-transmitting material can be selected according to actual needs and is not specifically limited here. Here, a light-transmitting material refers to a material with a light transmittance of 85%. Because the first insulating layer is made of an insulating light-transmitting material, light emitted from the semiconductor stacked structure can pass through the first insulating layer and enter the surface of the second electrode. When the material of the second electrode has a reflective effect, the second electrode can reflect the light incident on its surface back into the semiconductor stacked structure. This avoids optical crosstalk between the semiconductor stacked structures, thereby improving the luminous efficiency and luminous effect of the optical chip.

[0013] Secondly, embodiments of this application also provide a display device, including: an optical chip as described in the first aspect and any of the embodiments in the first aspect above, wherein when the optical chip has high luminous efficiency, the display device has a better display effect.

[0014] It should be understood that since the principle by which the display device solves the problem is similar to that of the aforementioned optical chip, the implementation and technical effects of the display device can be found in the implementation and technical effects of the aforementioned optical chip, and the repetitions will not be repeated. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of this application;

[0016] Figure 2 A three-dimensional structural diagram of an optical chip provided in an embodiment of this application;

[0017] Figure 3 A cross-sectional view of the optical chip provided in this application embodiment in a plane parallel to the x-direction and the z-direction;

[0018] Figure 4 This is a schematic diagram of the semiconductor stacked structure provided in the embodiments of this application;

[0019] Figure 5 Another cross-sectional view of the optical chip provided in the embodiments of this application in a plane parallel to the x-direction and the z-direction;

[0020] Figure 6 A schematic diagram illustrating the positional relationship between the semiconductor stacked structure and the first insulating layer provided in an embodiment of this application;

[0021] Figure 7 Another cross-sectional view of the optical chip provided in the embodiments of this application in a plane parallel to the x-direction and the z-direction;

[0022] Figure 8 A schematic diagram illustrating another positional relationship between the semiconductor stacked structure and the first insulating layer provided in an embodiment of this application;

[0023] Figure 9 This is another cross-sectional view of the optical chip provided in the embodiments of this application in a plane parallel to the x-direction and the z-direction.

[0024] Explanation of reference numerals in the attached figures:

[0025] 10-Lens, 10A-Optical waveguide, 10L-Left lens, 10R-Right lens, 11-Coupled grating, 12-Coupled grating, 20-Optical mechanism, 100-Structural component, 101-Right temple, 102-Frame, 103-Left temple, 200-Optical assembly, 30-Semiconductor stacked structure, 31-Second semiconductor layer, 32-Light-emitting layer, 33-First semiconductor layer, 40-First electrode, 50-Second electrode, 51-Body, 52-Extension Part, 61-first insulating layer, 61a-upper extension layer, 61b-lower extension layer, 62-second insulating layer, C0-trench, C1-capacitor-like structure, b1-first surface, b2-second surface, b3-side of the upper extension layer facing the center of the first surface, b4-side of the lower extension layer facing the center of the second surface, k0-light emission port, k1-first opening, k2-second opening, m1-substrate, m2-driving circuit layer, G1-hollow structure. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0027] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all such modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0028] To facilitate understanding of the technical solutions provided in the embodiments of this application, the application scenarios will be explained first below.

[0029] The optical chip provided in this application embodiment can be widely used in display devices, which may include, but are not limited to, various pixel art display devices or projectors. Pixel art display devices include, but are not limited to, augmented reality (AR) glasses, virtual reality (VR) glasses, mixed reality (MR) glasses, head-up display (HUD) devices, etc. In this application embodiment, the specific implementation of the display device including the optical chip can be designed according to actual needs and is not specifically limited here. Taking the application of the optical chip in AR glasses as an example... Figure 1 An exemplary schematic diagram of a display device, such as AR glasses, is shown, with reference to... Figure 1As shown, the display device may include a structural component 100 and an optical assembly 200. The structural component 100 is used to construct the overall external structure and install internal optical and electronic components. The optical assembly 200 is an optical component. The structural component 100 includes a frame 102 and temples, with the temples including a right temple 101 and a left temple 103. The right temple 101 and the left temple 103 are respectively connected to both sides of the frame 102. The connection between the temples and the frame 102 can be a rotatable connection or a fixed connection. When a user wears the display device, the frame 102 is located in front of the user's eyes, and the temples (right temple 101 and left temple 103) rest on the user's ears. The above structure of the structural component 100 is merely an example; in other embodiments, it can be designed as needed. For example, the structural component 100 can be a headband or helmet for a head-mounted display device.

[0030] The optical component 200 includes a lens 10 and an optical engine 20. The lens 10 is mounted to a frame 102 and is worn directly in front of the human eye. The lens 10 is transparent and has an optical waveguide 10A, which may be a diffractive waveguide structure. In one embodiment, all areas of the lens 10 are optical waveguides 10A, i.e., the optical waveguide 10A constitutes the lens of the display device. In other embodiments, the optical waveguide 10A may only constitute part of the lens 10. The optical waveguide 10A has a coupling grating 11 and a coupling grating 12. The optical engine 20 projects light onto the optical waveguide 10A. The optical engine 20 projects the light onto the coupling grating 11, couples the light into the optical waveguide 10A through the coupling grating 11, and performs total internal reflection within the optical waveguide 10A. The light is then emitted through the coupling grating 12, which generates a virtual image that enters the human eye.

[0031] The optical engine 20 is located between the left lens 10L and the right lens 10R, and is situated at the top of the frame 102. The optical engine 20 emits two beams of light. One beam passes through the coupling grating 11 on the left lens 10L and enters the optical waveguide 10A on the left lens 10L, then exits through the coupling grating 12 on the left lens 10L to form a virtual image. The other beam of light emitted by the optical engine 20 passes through the coupling grating 11 on the right lens 10R and enters the optical waveguide 10A on the right lens 10R, then exits through the coupling grating 12 on the right lens 10R to form a virtual image. Figure 1 In the illustrated embodiment, the optical engine 20 and the two coupling gratings 11 are both located at the intersection of the left lens 10L and the right lens 10R, i.e., the adjacent area. It should be understood that the location of the optical engine 20 is not limited to the intersection of the left lens 10L and the right lens 10R, but can also be located in other locations, such as, but not limited to, the temple, and is not specifically limited here.

[0032] The optical engine comprises an optical chip, a beam combiner, and an optical imaging unit. The optical chip is located on the light-incident side of the beam combiner, and the optical imaging unit is located on the light-outcident side. The optical chip serves as the light source for the optical engine. The beam combiner combines the light emitted from the optical chip to form a mixed beam, which is then transmitted to the optical imaging unit. The optical imaging unit receives the mixed beam emitted from the beam combiner, and the mixed beam, after passing through the optical imaging unit, is emitted onto the coupling grating of the optical waveguide. The optical imaging unit can be a lens group, and its optical axis can be the optical axis of the optical engine.

[0033] For example, an optical chip generally includes a light-emitting device and a driving circuit. The light-emitting device includes an anode, a semiconductor stacked structure, and a cathode. The anode and cathode are located on opposite sides of the semiconductor stacked structure. The driving circuit is connected to the anode and can provide an anode signal to the anode, enabling the anode to inject holes into the semiconductor stacked structure. The cathode is connected to a signal terminal for providing a cathode signal, enabling the cathode to inject electrons into the semiconductor stacked structure. The semiconductor stacked structure may include a P-type semiconductor layer, a light-emitting layer, and an N-type semiconductor layer stacked sequentially along the direction from the anode to the cathode. The P-type semiconductor layer can transport the injected holes to the light-emitting layer, and the N-type semiconductor layer can transport the injected electrons to the light-emitting layer. Electrons and holes recombine in the light-emitting layer to emit light, thereby realizing the driving circuit driving the semiconductor stacked structure to emit light.

[0034] As device size continues to shrink, the ratio of sidewalls to volume in light-emitting devices becomes larger and larger. During the fabrication of light-emitting devices, damage to the sidewalls may increase. This can easily lead to nonradiative recombination of electrons and holes on the sidewalls after they flow to them, reducing the amount of electrons and holes recombinating in the semiconductor stacked structure and thus reducing the light-emitting efficiency of the optical chip.

[0035] Based on this, embodiments of this application provide an optical chip, which may include: a substrate, and a plurality of semiconductor stacked structures, a plurality of first electrodes, a second electrode, and a first insulating layer respectively disposed on the substrate; the plurality of first electrodes are correspondingly disposed with the plurality of semiconductor stacked structures, and the first electrodes are located between the corresponding semiconductor stacked structures and the substrate; a trench is formed between any two adjacent semiconductor stacked structures; the second electrode includes: at least one body and a plurality of extensions, the body being connected to at least a portion of the extensions, and the body also being connected to at least a portion of the semiconductor stacked structures; the extensions are correspondingly disposed with the trenches, and the trenches contain extensions; the extensions are positioned between the extensions and adjacent semiconductor stacked structures, and between the extensions and adjacent first electrodes; The extension and the substrate are both isolated by a first insulating layer, which covers both the sidewalls and the bottom of the trench. One surface of the first insulating layer covering the trench sidewalls contacts and connects with one of the adjacent semiconductor stacked structures to form a first interface, while the opposite surface contacts and connects with the extension to form a second interface. The first interface, this portion of the first insulating layer, and the second interface constitute a capacitor-like structure. Under the effect of capacitance, the flow of electrons and holes to the sidewalls of the semiconductor stacked structure can be suppressed, thereby reducing non-radiative recombination of electrons and holes at the sidewalls, thus improving the luminous efficiency of the optical chip and reducing its heat generation. Furthermore, by isolating multiple first and second electrodes and isolating the second electrode from the substrate through the first insulating layer, short circuits between multiple first and second electrodes can be avoided, as can interference from structures on the substrate with the second electrode, thereby improving the reliability of the optical chip and ensuring its normal operation.

[0036] The optical chip provided in this application will be described below with reference to specific embodiments.

[0037] Figures 2 to 4 An exemplary schematic diagram of an optical chip according to an embodiment of this application is shown. See also... Figures 2 to 4 As shown, Figure 2 This is a schematic diagram of the three-dimensional structure of an optical chip. Figure 3 This is a cross-sectional view of the plane parallel to the x-direction and the z-direction. Figure 4 This is a schematic diagram of a semiconductor stacked structure 30; the optical chip may include: a substrate m1, a driving circuit layer m2, multiple semiconductor stacked structures 30, multiple first electrodes 40, second electrodes 50, and a first insulating layer 61. The light-emitting surface of the optical chip can be... Figure 3 The upper surface of the structure shown is the side of the semiconductor stacked structure 30 that is away from the substrate m1. Of course, the light-emitting surface can also be the side of the substrate m1 that is away from the semiconductor stacked structure 30. However, no matter which side the light-emitting surface is located on, normal light emission can be achieved by setting the materials of the relevant structures in the optical chip.

[0038] The substrate m1 can be made of materials with a certain degree of hardness, such as silicon oxide, silicon, and sapphire, to provide a certain support function.

[0039] The driving circuit layer m2 is located on the substrate m1. Multiple semiconductor stacked structures 30, multiple first electrodes 40, second electrodes 50, and a first insulating layer 61 are all located on the side of the driving circuit layer m2 facing away from the substrate m1. The driving circuit layer m2 may include multiple driving circuits. Figure 3 (Not shown in the diagram), the driving circuit is correspondingly disposed and connected to the first electrode 40, so that the driving circuit can provide a first electrode signal to the corresponding first electrode 40. The driving circuit, the semiconductor stack structure 30, and the first electrode 40 are all disposed in a one-to-one correspondence to realize that the driving circuit drives the corresponding semiconductor stack structure 30 to emit light. It should be understood that the driving circuit can be implemented using any structure known to those skilled in the art that can achieve its function, and the structure of the driving circuit in the embodiments of this application is not specifically limited.

[0040] Each semiconductor stack structure 30 may include: a first semiconductor layer 33, a light-emitting layer 32, and a second semiconductor layer 31, which are sequentially stacked along the direction from the substrate m1 to the driving circuit layer m2. The first semiconductor layer 33 can inject a first type of charge carrier into the light-emitting layer 32, and the second semiconductor layer 31 can inject a second type of charge carrier into the light-emitting layer 32. When the first type of charge carrier is a hole, the second type of charge carrier is an electron; or when the first type of charge carrier is an electron, the second type of charge carrier is a hole, so that electrons and holes can recombine in the light-emitting layer 32 to achieve light emission. The multiple semiconductor stack structures 30 can be arranged in an array on the driving circuit layer m2, and there is a trench C0 between any two adjacent semiconductor stack structures 30, so that each semiconductor stack structure 30 is separated from each other, and each semiconductor stack structure 30 can emit light of the target color to meet the light emission requirements of the optical chip. For example, the light-emitting layer 32 can be made of at least one of quantum hydrazine, quantum dots, gallium nitride, organic light-emitting materials, etc. When the first charge carrier is a hole and the second charge carrier is an electron, the first semiconductor layer 33 can be made of a material capable of transporting holes, such as, but not limited to, P-type gallium nitride, P-type gallium arsenide, P-type aluminum gallium indium phosphide, etc., and the second semiconductor layer 31 can be made of a material capable of transporting electrons, such as, but not limited to, N-type gallium nitride, N-type gallium arsenide, N-type aluminum gallium indium phosphide, etc.; conversely, when the first charge carrier is an electron and the second charge carrier is a hole, the first semiconductor layer 33 can be made of a material capable of transporting electrons, but not limited to, the second semiconductor layer 31 can be made of a material capable of transporting holes. The specific materials used can be set according to actual needs and are not specifically limited here. Furthermore, in the embodiments of this application, the device composed of the semiconductor stacked structure 30, the first electrode 40 and the second electrode 50 is not limited to a micro light-emitting diode (μLED), but can also be other light-emitting devices, which can be set according to actual needs, and are not specifically limited here.

[0041] The first electrode 40 is located between the corresponding semiconductor stacked structure 30 and the substrate m1. Further, the first electrode 40 is located between the corresponding semiconductor stacked structure 30 and the driving circuit layer m2. Multiple first electrodes 40 are insulated from each other, such that each semiconductor stacked structure 30 and the substrate m1 has one first electrode 40 disposed therebetween. The material used to fabricate the first electrode 40 may include at least one of the following: Cr, Ti, Al, Pt, Ni, Cu, Ag, Au, CuW, W, TiN, TaN, etc. The specific material can be selected according to actual needs and is not specifically limited here.

[0042] The second electrode 50 may include: at least one body 51 and a plurality of extensions 52, each body 51 being connected to at least a portion of the extensions 52, the extensions 52 being oriented along a direction perpendicular to the surface of the body 51 (i.e., Figure 3 (The part extending from the side surface of the corresponding body 51 toward the substrate m1 in the opposite direction of the z-direction indicated in the text) can be considered as an integrally formed structure of the body 51 and the corresponding extension 52. When the body 51 has one extension, see [reference needed]. Figure 2 As shown, the body 51 is in contact with and connected to the second semiconductor layer 31 in each semiconductor stacked structure 30, and the body 51 is connected to each extension 52. The body 51 has multiple hollow structures G1, which can expose the semiconductor stacked structure 30 to facilitate light emission. Each extension 52 is correspondingly disposed in each trench C0, and each extension 52 is disposed in the corresponding trench C0. That is, each trench C0 is provided with one extension 52. The body 51 is disposed on the side surface of the corresponding extension 52 away from the substrate m1. In this case, the second electrode 50 can be regarded as a common electrode. Alternatively, multiple bodies 51 can be provided (not shown). Each body 51 is connected to a portion of the extension 52, and each trench C0 corresponds to one second electrode 50. In this case, the extension 52 is disposed in the corresponding trench C0, and the body 51 is in contact with and connected to the second semiconductor layer 31 in the semiconductor stacked structure 30 that forms the corresponding trench C0. In this case, the second electrode 50 can be regarded as a non-common electrode. Therefore, the number of bodies 51 can be set according to actual needs and is not limited here. The material used to fabricate the second electrode 50 can include at least one of the following: Cr, Ti, Al, Pt, Ni, Cu, Ag, Au, CuW, W, TiN, TaN, and other metals or metal alloys. Furthermore, the materials used to fabricate the first electrode 40 and the second electrode 50 can be the same or different, and the specific choice can be made according to actual needs; no specific limitation is made here. It should be understood that in... Figure 2 and Figure 3 To facilitate the indication of trench C0, only a portion of the second electrode 50 and extension 52 at trench C0 are shown; not every second electrode 50 and extension 52 at trench C0 is shown. Furthermore, to clearly illustrate the relationship between the body 51 and the extension 52, Figure 2 The diagram shows the main body 51 and extension 52 separated, but in reality, the main body 51 and extension 52 are connected rather than separate; also, to make it easier to see the positional relationship between the trench C0 and the first insulating layer 61, Figure 2 The extension 52 is set to be transparent, but this does not mean that the extension 52 is made of transparent material.

[0043] The first electrode 40 can be an anode, and the corresponding second electrode 50 can be a cathode. When the body 51 has one electrode, a common cathode is formed; or, the first electrode 40 can be a cathode, and the corresponding second electrode 50 can be an anode. When the body 51 has one electrode, a common anode is formed.

[0044] Each trench C0 is provided with a first insulating layer 61. The first insulating layers 61 in each trench C0 are connected to each other. The first insulating layers 61 respectively isolate the extension 52 in the corresponding trench C0 from the adjacent semiconductor stack structure 30, isolate the extension 52 in the corresponding trench C0 from the adjacent first electrode 40, and isolate the extension 52 in the corresponding trench C0 from the driving circuit layer m2. This can prevent the first electrode 40 and the second electrode 50 from being short-circuited, and prevent the structure in the driving circuit layer m2 from interfering with the second electrode 50. This can improve the reliability of the optical chip and ensure the normal use of the optical chip. The first insulating layer 61 can be a single-layer or multi-layer structure, and it can be made of an insulating, light-transmitting material. This material can include, but is not limited to, organic transparent materials such as polymethyl methacrylate, polyester, polycarbonate, polystyrene, polyimide, and silicone resin, as well as inorganic transparent materials such as silicon oxide, titanium oxide, aluminum nitride, aluminum oxide, silicon nitride, zirconium oxide, magnesium fluoride, tantalum oxide, and silicon carbide. The specific material can be selected based on actual needs and is not specifically limited here. The light-transmitting material refers to a material with a transmittance of 85%. Because the first insulating layer 61 is made of an insulating, light-transmitting material, the light emitted from the semiconductor stacked structure 30 can pass through the first insulating layer 61 and enter the surface of the second electrode 50. When the material of the second electrode 50 has a reflective effect, the second electrode 50 can reflect the light incident on its surface back into the semiconductor stacked structure 30. This avoids optical crosstalk between the semiconductor stacked structures 30, thereby improving the luminous efficiency and luminous effect of the optical chip.

[0045] Furthermore, when the first insulating layer 61 isolates the extension 52 from the adjacent semiconductor stacked structure 30, the extension 52 from the adjacent first electrode 40, and the extension 52 from the substrate m1, the first insulating layer 61 covers both the sidewalls of the trench C0 and the bottom of the trench C0. For this part of the first insulating layer 61 covering the sidewalls of the trench C0, one side surface is in contact with the adjacent semiconductor stacked structure 30 to form a first interface, and the opposite side surface is in contact with the extension 52 to form a second interface. The first interface, this part of the first insulating layer 61, and the second interface constitute a structure C1 similar to a capacitor. Under the effect of capacitance, the flow of electrons and holes to the sidewalls of the semiconductor stacked structure 30 can be suppressed, thereby reducing the nonradiative recombination of electrons and holes at the sidewalls and improving the adverse effects caused by the quantum confinement Stark effect. This can improve the luminous efficiency of the optical chip and reduce the heat generation of the optical chip. It should be understood that the quantum confinement Stark effect refers to the phenomenon in quantum hydrazine where the energy band of the semiconductor is tilted, electron-hole pairs are spatially separated, wave function overlap is reduced, resulting in decreased luminous efficiency and a red shift of the emission peak. Therefore, the quantum confinement Stark effect reduces the luminous efficiency of the optical chip, while the capacitance effect can eliminate the quantum confinement Stark effect, thereby improving the luminous efficiency of the optical chip.

[0046] For example, see Figure 4 As shown, the surface of the semiconductor stacked structure 30 facing away from the first electrode 40 is referred to as the first surface b1, and the surface of the semiconductor stacked structure 30 facing the first electrode 40 is referred to as the second surface b2. The ratio of the area of ​​the first surface b1 to the area of ​​the second surface b2 can be set to 0.85:1.1 to 1.1:0.85. Further, the ratio of the area of ​​the first surface b1 to the area of ​​the second surface b2 can be set to 0.95:1.05, such that the areas of the first surface b1 and the second surface b2 are approximately the same. The areas of surface b1 and the second surface b2 can be the same, or the area of ​​the first surface b1 can be larger than the area of ​​the second surface b2, or the area of ​​the first surface b1 can be smaller than the area of ​​the second surface b2. Furthermore, the angle α between the sidewall of the semiconductor stacked structure 30 and the surface of the first electrode 40 can be set to 80° to 90°, and further, the angle α between the sidewall of the semiconductor stacked structure 30 and the surface of the first electrode 40 can be set to 85° to 90°, making the sidewall of the semiconductor stacked structure 30 approximately perpendicular to the surface of the first electrode 40. This increases the area of ​​the light-emitting layer in the semiconductor stacked structure 30, thereby increasing the ratio of the area of ​​the light-emitting layer to the area of ​​the optical chip, improving the internal quantum efficiency of the semiconductor stacked structure 30, and thus improving the photoelectric conversion efficiency. Furthermore, when using the same current to drive the semiconductor stacked structure 30, the current density in the semiconductor stacked structure 30 is lower, thereby reducing the heat generated by the optical chip and improving the performance of the optical chip.

[0047] Figure 5 and Figure 6 An exemplary schematic diagram of another optical chip structure according to an embodiment of this application is shown below. Figure 5 and Figure 6 As shown, the optical chip in this embodiment is similar to that in the aforementioned embodiments. Figures 2 to 4 The structure of the optical chip described in the previous section is basically similar, except that the first insulating layer 61 extends onto the first surface b1 of the semiconductor stacked structure 30 on the side opposite to the substrate m1. For example, the first insulating layer 61 extends into the first surface b1 and covers the four edges of the first surface b1, such as... Figure 6 As shown, Figure 6 This is a diagram showing the positional relationship between the semiconductor stacked structure 30 and the first insulating layer 61 from the perspective of the first surface b1. To clearly show the first surface b1, only a portion of the structure within the first insulating layer 61 extending into the first surface b1 is shown. If the first insulating layer 61 located above the first surface b1 is referred to as the upper extension layer 61a, the body 51 wraps around the side b3 of the upper extension layer 61a facing the center of the first surface b1. Therefore, even though the first insulating layer 61 extends into the first surface b1, the body 51 maintains its position by wrapping around the upper extension layer 61a towards the first surface b1. The side b3 at the center of 1 still allows the body 51 to contact and connect with the first surface b1 of the semiconductor stacked structure 30, facilitating the injection of charge carriers from the body 51 in the second electrode 50 into the semiconductor stacked structure 30, thus ensuring that the semiconductor stacked structure 30 can emit light. Furthermore, the upper extension layer 61a located at the periphery of the first surface b1 of the semiconductor stacked structure 30 can block current flow to the sidewalls of the semiconductor stacked structure 30, further preventing non-radiative recombination at the sidewalls of the semiconductor stacked structure 30, thereby further improving the luminous efficiency of the optical chip. It should be understood that the current in this paragraph can be interpreted as the flow of charge carriers.

[0048] Wherein, at any edge of the first surface b1, along the first normal direction of that edge (e.g. Figure 5The length covered by the upper extension layer 61a in the x-direction shown is the first length d1, and the length of the center of two adjacent trenches along the first normal direction is the second length d2. The ratio of the first length d1 to the second length d2 is 1 / 15 to 1 / 4, and further, the ratio of the first length d1 to the second length d2 is 1 / 10 to 1 / 4. The ratio of the first length d1 to the second length d2 can be set according to actual conditions. For example, although the first insulating layer 61 is made of a transparent material, the body 51 needs to wrap the side b3 of the upper extension layer 61a and connect to the first surface b1 of the semiconductor stacked structure 30. When the body 51 is made of a non-transparent material, and the light-emitting surface is the side of the semiconductor stacked structure 30 facing away from the substrate m1, if the ratio of the first length d1 to the second length d2 is set too large, the area of ​​the light-emitting port k0 will be reduced, thereby reducing the light-emitting effect of the optical chip. Therefore, in order to... To improve the light emission effect, the ratio of the first length d1 to the second length d2 can be set smaller. For example, if the ratio of the first length d1 to the second length d2 is set small, the obstruction effect on the flow of current to the sidewall of the semiconductor stacked structure 30 will be weakened, and the light emission efficiency of the optical chip will decrease. Therefore, in order to improve the light emission efficiency, the ratio of the first length d1 to the second length d2 can be set larger. Based on this, setting the ratio of the first length d1 to the second length d2 within the above range can improve both the light emission efficiency and the light emission effect.

[0049] The thickness h1 of the upper extension layer 61a can be set from 10nm to 250nm, and can be set according to actual needs, and is not limited here. For example, if the thickness h1 of the upper extension layer 61a is set to be large, it will increase the thickness of the optical chip, and thus increase the size of the optical chip, which is not conducive to the miniaturization design of the optical chip; if the thickness h1 of the upper extension layer 61a is set to be small, the obstruction effect on the flow of current to the sidewall of the semiconductor stacked structure 30 will be weakened, resulting in a decrease in luminous efficiency. Based on this, when the thickness h1 of the upper extension layer 61a is set within a suitable range, both the miniaturization design of the optical chip and the luminous efficiency can be improved.

[0050] It should be understood that the optical chip in this embodiment is different from that in the aforementioned embodiments. Figures 2 to 4 The structural similarities of the optical chips described in the previous embodiments can be found in the relevant descriptions, and the repeated parts will not be repeated.

[0051] Figure 7 and Figure 8 An exemplary schematic diagram of another optical chip structure according to an embodiment of this application is shown below. Figure 7 and Figure 8 As shown, the optical chip in this embodiment is similar to that in the aforementioned embodiments. Figures 2 to 6The structure of the optical chip described in the previous section is basically similar, except that the first insulating layer 61 extends onto the second surface b2 of the semiconductor stacked structure 30 facing the substrate m1. Exemplarily, the first insulating layer 61 extends into the second surface b2 and covers the four edges of the second surface b2, such as... Figure 8 As shown, Figure 8 This is a diagram showing the positional relationship between the semiconductor stacked structure 30 and the first insulating layer 61 from the perspective of the second surface b2. To clearly show the second surface b2, only a portion of the structure of the first insulating layer 61 extending into the second surface b2 is shown. If the first insulating layer 61 located above the second surface b2 is referred to as the lower extension layer 61b, the first electrode 40 wraps around the side b4 of the lower extension layer 61b facing the center of the second surface b2. Therefore, even though the first insulating layer 61 extends into the second surface b2 of the semiconductor stacked structure 30, the first electrode 40, by wrapping the lower extension layer... The side surface b4 of the extended layer 61b facing the center of the second surface b2 still allows the first electrode 40 to contact and connect with the second surface b2 of the semiconductor stacked structure 30, facilitating the injection of charge carriers from the first electrode 40 into the semiconductor stacked structure 30, thus ensuring that the semiconductor stacked structure 30 can emit light. Furthermore, the lower extended layer 61b located at the periphery of the second surface b2 of the semiconductor stacked structure 30 can block current flow to the sidewalls of the semiconductor stacked structure 30, thereby preventing non-radiative recombination at the sidewalls and improving the luminous efficiency of the optical chip. It should be understood that the current in this paragraph can be interpreted as the flow of charge carriers.

[0052] Wherein, at any edge of the second surface b2, along the second normal direction of that edge (e.g. Figure 7 The length covered by the lower extension layer 61b in the x-direction shown is the third length d3, and the length along the second normal direction between the centers of two adjacent trenches is the fourth length d4. The ratio of the third length d3 to the fourth length d4 is 1 / 15 to 1 / 4, and further, the ratio of the third length d3 to the fourth length d4 is 1 / 10 to 1 / 4. The ratio of the third length d3 to the fourth length d4 can be set according to the actual situation. For example, if the ratio of the third length d3 to the fourth length d4 is set to be small, the obstruction effect on the flow of current to the sidewall of the semiconductor stacked structure 30 will be weakened, and the luminous efficiency of the optical chip will be reduced. Therefore, in order to improve the luminous efficiency, the ratio of the third length d3 to the fourth length d4 can be set to be larger.

[0053] The first insulating layer 61 also has an upper extending layer 61a, which covers the four edges of the first surface b1, and extends along the first normal direction of any edge of the first surface b1 (e.g., ...). Figure 7When the length covered by the upper extension layer 61a in the x-direction shown is the first length h1, if the first electrode is the anode and the second electrode is the cathode, then the third length d3 can be greater than the first length h1, such as... Figure 7 As shown, the lower extension layer 61b covers a larger area of ​​the semiconductor stacked structure 30 than the upper extension layer 61a. Since electrons flow faster than holes, the larger lower extension layer 61b can inject more holes into the semiconductor stacked structure 30 to balance the difference in the number of electrons and holes within the semiconductor stacked structure 30 caused by the slower hole flow, thereby further improving the luminous efficiency of the optical chip. Alternatively, if the first electrode is a cathode and the second electrode is an anode, the third length d3 can be smaller than the first length h1 (not shown) to balance the difference in the number of electrons and holes within the semiconductor stacked structure 30 caused by the slower hole flow, thereby further improving the luminous efficiency of the optical chip. Of course, the first length h1 and the third length h3 can also be set to be the same to improve the flexibility of the optical chip design.

[0054] The thickness h2 of the lower extension layer 61b can be set from 10nm to 250nm, and can be set according to actual needs, without limitation here. For example, if the thickness h2 of the lower extension layer 61b is set to be large, it will increase the thickness of the optical chip, thereby increasing the size of the optical chip, which is not conducive to the miniaturization design of the optical chip; if the thickness h2 of the lower extension layer 61b is set to be small, the obstruction effect on the flow of current to the sidewall of the semiconductor stack structure 30 will be weakened, resulting in a decrease in luminous efficiency. Based on this, when the thickness h2 of the lower extension layer 61b is set within a suitable range, both the miniaturization design of the optical chip and the luminous efficiency can be improved.

[0055] It is worth noting that when the semiconductor stacked structure 30 is a six-sided structure, and the first insulating layer 61 extends into the first surface b1 and the second surface b2 of the semiconductor stacked structure 30 respectively, it can cover all six sides of the semiconductor stacked structure 30, effectively suppressing the flow of current to the sidewalls of the semiconductor stacked structure 30, thereby effectively avoiding non-radiative recombination at the sidewalls, and thus effectively improving the light-emitting efficiency of the optical chip.

[0056] It should be understood that the optical chip in this embodiment is different from that in the aforementioned embodiments. Figures 2 to 6 The structural similarities of the optical chips described in the previous embodiments can be found in the relevant descriptions, and the repeated parts will not be repeated.

[0057] Figure 9 An exemplary schematic diagram of another optical chip structure according to an embodiment of this application is shown below. Figure 9 As shown, the optical chip in this embodiment is similar to that in the aforementioned embodiments. Figures 2 to 4 , Figure 7 and Figure 8 The structure of the optical chip described in the previous section is basically similar, except that the optical chip also includes a second insulating layer 62. Exemplarily, the second insulating layer 62 is disposed on the first surface b1 of the semiconductor stacked structure 30 on the side opposite to the substrate m1. The second insulating layer 62 has a plurality of first openings k1 and a plurality of second openings k2, each first opening k1 corresponding to a trench (…). Figure 9 The extension 52 and the corresponding body 51 are connected through the corresponding first opening k1 (not shown in the image). At this time, the body 51 and the corresponding extension 52 can be non-integrated, so the extension 52 can also be connected to the corresponding body 51 through the first opening k1. Each second opening k2 is connected to each semiconductor stack structure 30. The second opening k2 can expose a part of the first surface b1. The semiconductor stack structure 30 and the body 51 can be connected through the second opening k2. At this time, the second opening k2 can be regarded as a light outlet. Light can be emitted outward through the second opening k2 to realize the light emission function of the light chip.

[0058] In other words, the second insulating layer 62 can be a whole layer disposed on the side of the semiconductor stacked structure 30 away from the substrate m1. In order to realize the connection between the body 51 and the corresponding extension 52, the connection between the body 51 and the corresponding semiconductor stacked structure 30, and the outward emission, when the semiconductor stacked structure 30 is fabricated, the first insulating layer 61 and the extension 52 are formed in the trench, and then the second insulating layer 62 and the body 51 are formed in sequence. This helps to simplify the fabrication difficulty of the optical chip and reduce the manufacturing cost.

[0059] When the second opening k2 exposes a portion of the first surface b1, it indicates that the second insulating layer 62 covers another portion of the first surface b1. This prevents current from flowing to the sidewalls of the semiconductor stacked structure 30, extending the current flow path. Even if the current flows to the sidewalls, the recombination of electrons and holes can be avoided due to the capacitance effect.

[0060] Furthermore, the second insulating layer 62 covers the four edges of the first surface b1, which effectively blocks the current flow to the sidewalls of the semiconductor stacked structure 30, effectively reducing or eliminating the current flow to the sidewalls of the semiconductor stacked structure 30. This further prevents non-radiative recombination of electrons and holes on the sidewalls of the semiconductor stacked structure 30, thereby further improving the luminous efficiency of the optical chip. The size of the first surface b1 covered by the second insulating layer 62 can be the same as the size of the first surface b1 covered by the upper extension layer described in the above embodiments, and will not be detailed here.

[0061] For example, the thickness h3 of the second insulating layer 62 can be set from 10 nm to 250 nm, and can be set according to actual needs, and is not limited here. For example, if the thickness h3 of the second insulating layer 62 is set to be large, it will increase the thickness of the optical chip, and thus increase the size of the optical chip, which is not conducive to the miniaturization design of the optical chip; if the thickness h3 of the second insulating layer 62 is set to be small, the obstruction effect on the flow of current to the sidewall of the semiconductor stacked structure 30 will be weakened, resulting in a decrease in luminous efficiency. Based on this, when the thickness h3 of the second insulating layer 62 is set within a suitable range, both the miniaturization design of the optical chip and the luminous efficiency can be improved.

[0062] The material used to fabricate the second insulating layer 62 may include insulating light-transmitting materials, and such materials may include, but are not limited to, organic transparent materials such as polymethyl methacrylate, polyester, polycarbonate, polystyrene, polyimide, and silicone resin, as well as inorganic transparent materials such as silicon oxide, titanium oxide, aluminum nitride, aluminum oxide, silicon nitride, zirconium oxide, magnesium fluoride, tantalum oxide, and silicon carbide. The specific material can be selected based on actual needs and is not specifically limited here. When the second insulating layer 62 is fabricated using an insulating light-transmitting material, the light emitted from the semiconductor stacked structure 30 can pass through the second insulating layer 62 and be incident on the surface of the second electrode 50. When the material used to fabricate the second electrode 50 has a reflective effect, the second electrode 50 can reflect the light incident on its surface back into the semiconductor stacked structure 30. This avoids optical crosstalk between the semiconductor stacked structures 30, thereby improving the luminous efficiency and luminous effect of the optical chip.

[0063] It should be understood that the optical chip in this embodiment is different from that in the aforementioned embodiments. Figures 2 to 4 , Figure 7 and Figure 8 The structural similarities of the optical chips described in the previous embodiments can be found in the relevant descriptions, and the repeated parts will not be repeated.

[0064] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. An optical chip, characterized in that, include: A substrate, and a plurality of semiconductor stacked structures, a plurality of first electrodes, a second electrode and a first insulating layer respectively disposed on the substrate; The plurality of first electrodes are disposed corresponding to the plurality of semiconductor stacked structures, and the first electrodes are located between the corresponding semiconductor stacked structure and the substrate; A trench exists between any two adjacent semiconductor stacked structures; The second electrode includes: at least one body and a plurality of extensions, the body being connected to at least a portion of the extensions, and the body also being connected to at least a portion of the semiconductor stacked structure; The extension is provided corresponding to the groove, and the extension is provided inside the groove; The extension is isolated from the adjacent semiconductor stack, from the adjacent first electrode, and from the substrate by the first insulating layer.

2. The optical chip as described in claim 1, characterized in that, The optical chip further includes a second insulating layer, which is disposed on a first surface of the plurality of semiconductor stacked structures on the side opposite to the substrate. The second insulating layer has a plurality of first openings and a plurality of second openings. The first openings are corresponding to the trenches. The extension is connected to the corresponding body through the corresponding first opening. The second openings are corresponding to the semiconductor stacked structure. The second openings expose a portion of the first surface. The semiconductor stacked structure is connected to the body through the corresponding second opening.

3. The optical chip as described in claim 2, characterized in that, The second insulating layer covers the four edges of the first surface.

4. The optical chip as described in claim 1, characterized in that, The first insulating layer extends to a first surface of the semiconductor stack structure opposite to the substrate, and the first insulating layer covers the four edges of the first surface.

5. The optical chip according to any one of claims 2-4, characterized in that, The length covered at any edge of the first surface along the first normal direction of that edge is the first length, the length of the center of two adjacent grooves along the first normal direction is the second length, and the ratio of the first length d1 to the second length d2 is 1 / 15 to 1 / 4.

6. The optical chip according to any one of claims 1-5, characterized in that, The first insulating layer extends to the second surface of the semiconductor stack structure facing the substrate, and the first insulating layer covers the four edges of the second surface.

7. The optical chip as described in claim 6, characterized in that, The length covered at any edge of the second surface along the second normal direction of that edge is the third length, and the length of the center of two adjacent grooves along the second normal direction is the fourth length. The ratio of the third length to the fourth length is 1 / 15 to 1 / 4.

8. The optical chip as described in claim 7, characterized in that, The four edges of the first surface of the semiconductor stacked structure facing away from the substrate are covered by the first insulating layer or the second insulating layer, and the length of the first edge covered along the first normal direction of the edge is the first length. The first electrode is the anode, the second electrode is the cathode, and the third length is greater than the first length; or, the first electrode is the cathode, the second electrode is the anode, and the third length is less than the first length.

9. The optical chip according to any one of claims 1-8, characterized in that, The first insulating layer is made of a light-transmitting material.

10. A display device, characterized in that, include: The optical chip as described in any one of claims 1-9.

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