Vertical flip-chip light-emitting element and vertical flip-chip light-emitting element manufacturing method

Abstract

The invention provides a vertical flip chip type light-emitting element which comprises a bare chip group, two first connecting pads, two second connecting pads and an electric connecting layer. The die set includes two dies and a first type semiconductor connection portion. The first type semiconductor connection portion is connected between the first type semiconductor layers of the two dies. A first one of the two first pads is disposed below a first one of the two dies, and a second one of the two first pads corresponds to but does not directly contact a second one of the two dies. A first one of the two second pads is disposed over a first one of the two dies, and a second one of the two second pads is disposed over a second one of the two dies. The electric connection layer is electrically connected with the second one of the two second connection pads and the first connection pad. Therefore, when a bare crystal is damaged, current can still flow into a normal bare crystal, so that a self-compensation function is realized.

Description

Technical Field

[0001] This invention relates to a light-emitting element and a method for manufacturing the light-emitting element, and particularly to a vertical flip-chip light-emitting element and a method for manufacturing the vertical flip-chip light-emitting element. Background Technology

[0002] Technological advancements have enabled the miniaturization of light-emitting diodes (LEDs), allowing them to be used in a wider range of products, such as Mini LEDs or Micro LEDs in displays. Furthermore, Chips on Board (COB) packaging has become increasingly popular because it allows bare dies to be directly mounted onto circuit boards or substrates.

[0003] Flip-chip LEDs are the preferred choice for chip-on-board (COB) because they can be directly connected to the substrate without leads. However, due to the lack of a protective encapsulation layer, damaged flip-chip LEDs are not easy to repair, and therefore have room for improvement. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides a vertical flip-chip light-emitting element and a method for manufacturing the vertical flip-chip light-emitting element. Through the structural configuration of the vertical flip-chip light-emitting element, the vertical flip-chip light-emitting element can have a self-compensation function without the need for repair.

[0005] According to one embodiment of the present invention, a vertical flip-chip light-emitting element is provided, comprising a die assembly, two first pads, two second pads, and an electrical connection layer. The die assembly includes two dies and a first-type semiconductor interconnect. Each die includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer. The first-type semiconductor interconnect is connected between the first-type semiconductor layers of the two dies. A first of the two first pads is disposed below either the first of the two dies or below the first-type semiconductor interconnect, and a second of the two first pads corresponds to but does not directly contact a second of the two dies. A first of the two second pads is disposed above the first of the two dies, and a second of the two second pads is disposed above the second of the two dies. The electrical connection layer electrically connects the two second pads and the second of the first pads. In this process, a first shunt of the current flows through the first of the two first pads, the first of the two bare dies, the first of the two second pads, the electrical connection layer, and the second of the two first pads; a second shunt of the current flows through the first of the two first pads, the first type semiconductor connection portion, the second of the two bare dies, the second of the two second pads, the electrical connection layer, and the second of the two first pads.

[0006] Therefore, by giving the two bare chips a vertical light-emitting diode structure and electrically connecting them via a first-type semiconductor interconnect and sharing two first pads, the easy soldering function of flip-chip light-emitting diodes can also be achieved. In addition, when one of the two bare chips is damaged, current can still flow into the normal bare chip to make it emit light, thus having a self-compensation function and eliminating the need for additional repairs.

[0007] The vertical flip-chip light-emitting element according to the embodiment may further include an insulating layer disposed directly beneath the second of the two bare chips. The second of the two first contact pads is at least partially located beneath the insulating layer.

[0008] According to the embodiment, the vertical flip-chip light-emitting element may further include a first protective layer covering the two bare chips and including two openings, the two openings respectively corresponding to two second pads, so that the two second pads are exposed. An electrical connection layer is located above the first protective layer and electrically connects the two second pads exposed through the two openings.

[0009] According to the embodiment of the vertical flip-chip light-emitting element, the second of the two first pads may include a metal upper surface, the metal upper surface is not blocked by an insulating layer, an extension of the first protective layer extends to the metal upper surface through an outer sidewall of the second of the two bare chips, the outer sidewall is away from the first of the two bare chips, and the electrical connection layer is located outside the extension and extends to the metal upper surface.

[0010] According to the embodiment of the vertical flip-chip light-emitting element, the upper metal surface is aligned with an insulating upper surface of the insulating layer, and the lower metal surface of the first of the two first pads is aligned with the lower metal surface of the second of the two first pads.

[0011] The vertical flip-chip light-emitting element according to the embodiment may further include a second protective layer that covers the electrical connection layer.

[0012] According to another embodiment of the present invention, a method for fabricating a vertical flip-chip light-emitting element is provided, comprising an epitaxial structure formation step, a first pad formation step, a native substrate removal step, an etching step, a second pad formation step, and an electrical connection layer formation step. In the epitaxial structure formation step, an epitaxial structure is formed on a native substrate. In the first pad formation step, a plurality of first pad groups are formed on the epitaxial structure. Each first pad group includes two first pads and an insulating layer. A first pad in each first pad group is connected to a proximal side of the insulating layer, and a second pad in each first pad group covers a distal side of the insulating layer. The first and second pads in each first pad group do not directly contact each other. In the native substrate removal step, the plurality of first pads are bonded to a transient substrate, and the native substrate is removed. In the etching step, the epitaxial structure is etched to form multiple bare die groups. Each bare die group includes two bare dies and a first-type semiconductor interconnect. Each bare die includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer. The first-type semiconductor interconnect connects the first-type semiconductor layers of the two bare dies. Each bare die group corresponds to a first pad group. The first of the two first pads in each first pad group is directly attached to the underside of the first of the two bare dies in each bare die group. The insulating layer of each first pad group is directly attached to the underside of the second of the two bare dies in each bare die group. In the second pad formation step, multiple second pad groups are formed, each corresponding to the aforementioned multiple bare die groups. Each second pad group includes two second pads. The first of the two second pads in each second pad group is disposed above the first of the two bare dies in each bare die group, and the second of the two second pads in each second pad group is disposed above the second of the two bare dies in each bare die group. In the step of forming an electrical connection layer, a plurality of electrical connection layers are formed, each corresponding to the aforementioned plurality of bare die groups. Each electrical connection layer is electrically connected to the second second pad of each second pad group and the second of the second first pad of each first pad group.

[0013] According to the method for fabricating a vertical flip-chip light-emitting element, the method may further include a first protective layer forming step, forming a plurality of first protective layers corresponding to the aforementioned plurality of bare die groups. Each first protective layer covers the top of each bare die group and includes two openings. The two openings of each first protective layer correspond to two second pads of each bare die group, so that the two second pads of each second pad group are exposed. Each electrical connection layer is located above each first protective layer, and each electrical connection layer is electrically connected to the two second pads exposed in the two openings in each second pad group.

[0014] The vertical flip-chip light-emitting element fabrication method according to the embodiment may further include a second protective layer forming step, forming a plurality of second protective layers corresponding to the aforementioned plurality of bare die groups, with each second protective layer covering the top of each electrical connection layer.

[0015] According to the method for fabricating a vertical flip-chip light-emitting element according to the embodiment, in the first protective layer forming step, an extension of each first protective layer extends through an outer sidewall of the second of the two bare chips in each bare chip group to a metal upper surface of the second of the two first pads in the corresponding first pad group. In the electrical connection layer forming step, each electrical connection layer is located outside the extension of each first protective layer and extends to the metal upper surface of the second of the two first pads in the corresponding first pad group. Attached Figure Description

[0016] Figure 1 A side view schematic diagram of a vertical flip-chip light-emitting element according to an embodiment of the present invention is shown;

[0017] Figure 2 A flowchart illustrating the steps of a method for manufacturing a vertical flip-chip light-emitting element according to another embodiment of the present invention is shown.

[0018] Figure 3 Draw Figure 2 The embodiment illustrates a side view of the fabrication process for a vertical flip-chip light-emitting element.

[0019] Figure 4 Draw Figure 2 Another side view schematic diagram of the fabrication of a vertical flip-chip light-emitting element according to the embodiment;

[0020] Figure 5 Draw Figure 2 Another side view schematic diagram of the fabrication of a vertical flip-chip light-emitting element according to the embodiment;

[0021] Figure 6 Draw Figure 2 A bottom view diagram illustrating the fabrication method of a vertical flip-chip light-emitting element according to an embodiment; and

[0022] Figure 7 Draw Figure 2 A top view schematic diagram of the method for fabricating a vertical flip-chip light-emitting element according to the embodiment.

[0023] The reference numerals in the attached figures are explained as follows:

[0024] 1000, 2000: Vertical flip-chip light-emitting element

[0025] 1100, 2100: Bare Crystal Group

[0026] 1110, 1120, 2110, 2120: Bare crystal

[0027] 1111,1121,2111,2121: Type I semiconductor layer

[0028] 1112,1122,2112,2122: Type II semiconductor layer

[0029] 1113,1123,2113,2123: Active layer

[0030] 1130, 2130: Type I semiconductor interconnect

[0031] 1210,1220,2210,2220: First bonding pad

[0032] 1211a, 1221a: Lower surface of the metal

[0033] 1221: Welding section

[0034] 1222: Protruding segment

[0035] 1222a: Metal upper surface

[0036] 1230, 2230: Insulation layer

[0037] 1231: Insulating upper surface

[0038] 1310, 1320, 2310, 2320: Second pad

[0039] 1400, 2400: Electrical connection layer

[0040] 1500, 2500: First protective layer

[0041] 1510, 2510: Extension

[0042] 1520,2520: upper part

[0043] 1600, 2600: Second protective layer

[0044] 2200: First pad assembly

[0045] 2300: Second pad assembly

[0046] 2501, 2502: Opening

[0047] B1: Blue membrane

[0048] E1: Extensional structure

[0049] I1: First branch

[0050] I2: Second Diversion

[0051] P1: Circuit board

[0052] S1: native substrate

[0053] S2000: Manufacturing Method of Vertical Flip Chip Light Emitting Element

[0054] S2100: Steps for forming an epitaxial structure

[0055] S2200: First pad formation step

[0056] S2300: Native substrate removal procedure

[0057] S2400: Etching Steps

[0058] S2500: Second pad formation step

[0059] S2600: Steps for forming the first protective layer

[0060] S2700: Electrical interconnection layer formation steps

[0061] S2800: Steps for forming the second protective layer

[0062] T1: Transient substrate

[0063] T11: Colloid Detailed Implementation

[0064] Embodiments of the present invention will now be described with reference to the accompanying drawings. For clarity, numerous practical details will be set forth in the following description. However, the reader should understand that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity in the drawings, some conventionally used structures and elements will be illustrated in a simple schematic manner; and repeated elements may be denoted using the same or similar designations.

[0065] In this document, the terms "first," "second," and "third" are used only to describe different components or parts, and do not restrict the components / parts themselves. Therefore, the first component / part can also be referred to as the second component / part. Furthermore, the combinations of components / parts / mechanisms / modules in this document are not generally known, conventional, or existing combinations in this field. Whether a component / part / mechanism / module is existing cannot be used to determine whether its combination relationship is easily accomplished by someone with ordinary knowledge in the technical field. In addition, the directions "above" and "below" in this document are only relative positional relationships and do not refer to "above" and "below" in actual use.

[0066] Please see Figure 1 ,in Figure 1The diagram illustrates a side view of a vertical flip-chip light-emitting element 1000 according to an embodiment of the present invention. The vertical flip-chip light-emitting element 1000 includes a die assembly 1100, two first pads 1210 and 1220, two second pads 1310 and 1320, and an electrical connection layer 1400.

[0067] The die assembly 1100 includes two dies 1110 and 1120 and a first-type semiconductor interconnect 1130. Each die 1110 and 1120 includes a first-type semiconductor layer 1111 and 1121, an active layer 1113 and 1123, and a second-type semiconductor layer 1112 and 1122. The first-type semiconductor interconnect 1130 connects the first-type semiconductor layers 1111 and 1121 of the two dies 1110 and 1120.

[0068] One of the two first pads 1210 and 1220 (i.e., first pad 1210, hereinafter referred to as first pad 1210) is disposed below one of the two bare dies 1110 and 1120 (i.e., bare die 1110, hereinafter referred to as bare die 1110) or below the first type semiconductor connection portion 1130. One of the two first pads 1210 and 1220 (i.e., first pad 1220, hereinafter referred to as first pad 1220) corresponds to but does not directly contact one of the two bare dies 1110 and 1120 (i.e., bare die 1120, hereinafter referred to as bare die 1120). The first of the two second pads 1310 and 1320 (i.e., the second pad 1310, hereinafter referred to as the second pad 1310) is disposed above the bare die 1110, and the second of the two second pads 1310 and 1320 (i.e., the second pad 1320, hereinafter referred to as the second pad 1320) is disposed above the bare die 1120. The electrical connection layer 1400 electrically connects the two second pads 1310 and 1320.

[0069] A first shunt I1 of a current flows through the first pad 1210, the bare die 1110, the second pad 1310, the electrical connection layer 1400, and the first pad 1220; a second shunt I2 of the current flows through the first pad 1210, the first type semiconductor connection 1130, the bare die 1120, the second pad 1320, the electrical connection layer 1400, and the first pad 1220.

[0070] Therefore, by giving the two bare chips 1110 and 1120 a vertical light-emitting diode structure, and electrically connecting them via the first type semiconductor connection portion 1130 and sharing two first pads 1210 and 1220, the easy soldering function of flip-chip light-emitting diodes can also be achieved. Furthermore, when one of the two bare chips 1110 and 1120 is damaged, current can still flow into the normal bare chip 1110 and 1120 to make it emit light, thus possessing a self-compensation function and eliminating the need for additional repairs.

[0071] In each bare die 1110 and 1120, the first type semiconductor layers 1111 and 1121 can be, for example, N-type nitride semiconductor stacked layers, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), or indium gallium nitride (InGaN) doped with N-type dopants. The active layers 1113 and 1123 can be quantum wells, such as multiple quantum wells. The second type semiconductor layers 1112 and 1122 can be, for example, P-type nitride semiconductor stacked layers, such as gallium nitride, aluminum gallium nitride, aluminum indium gallium nitride, or indium gallium nitride doped with P-type dopants. The materials used in this invention are examples as above, but are not limited thereto. The material of the first type semiconductor interconnect 1130 is the same as that of the first type semiconductor layers 1111 and 1121, and can be formed together during manufacturing. Some of the material can be removed by etching, but this is not a limitation.

[0072] The first pads 1210 and 1220 may be conductive metal. The vertical flip-chip light-emitting element 1000 may further include an insulating layer 1230, which is directly disposed below the bare die 1120, and the first pad 1220 is at least partially located below the insulating layer 1230. Furthermore, the first pad 1220 may include a metal upper surface 1222a, which is not obscured by the insulating layer 1230, and the metal upper surface 1222a may be aligned with an insulating upper surface 1231 of the insulating layer 1230. A metal lower surface 1211a of the first pad 1210 may be aligned with a metal lower surface 1221a of the first pad 1220.

[0073] Specifically, the insulating layer 1230 is located below the first type semiconductor layer 1121 of the bare die 1120 and is in close proximity to the side of the first pad 1210. The first pad 1220 may include a solder section 1221 and a protruding section 1222. The solder section 1221 is located below the insulating layer 1230 and does not contact the first pad 1210. The protruding section 1222 is connected to the solder section 1221 and is located on a distal side of the insulating layer 1230. The upper metal surface 1222a refers to the surface of the protruding section 1222 close to the surface of the bare die 1120, and the upper metal surface 1222a may be at the same height as the upper insulating surface 1231 and aligned with each other. The lower metal surface 1211a of the first pad 1210 refers to the surface away from the bare die 1110, and the lower metal surface 1221a of the first pad 1220 refers to the surface away from the bare die 1120, both at the same height and aligned with each other. Therefore, this facilitates manufacturing and subsequent soldering applications.

[0074] The second pad 1310 can be disposed above the bare die 1110, and the second pad 1320 can be disposed above the bare die 1120, and both the second pad 1310 and the second pad 1320 are metal. The vertical flip-chip light-emitting element 1000 may further include a first protective layer 1500, which covers the two bare dies 1110 and 1120 and includes two openings (not shown), the two openings corresponding to the two second pads 1310 and 1320 respectively, so that the two second pads 1310 and 1320 are exposed. The electrical connection layer 1400 is located above the first protective layer 1500 and electrically connects the two second pads 1310 and 1320 exposed through the two openings. An extension 1510 of the first protective layer 1500 extends from an outer sidewall of the bare die 1120 to the upper metal surface 1222a. The outer sidewall is away from the bare die 1110. The electrical connection layer 1400 is located outside the extension 1510 and extends to the upper metal surface 1222a.

[0075] Specifically, the first protective layer 1500 may further include an upper portion 1520 covering the bare dies 1110, 1120 and the first type semiconductor interconnect 1130, thereby protecting the bare dies 1110, 1120 and the first type semiconductor interconnect 1130, and an extension portion 1510 extending downward from the upper portion 1520 to cover the outer sidewall of the bare die 1120. Thus, when the electrical connection layer 1400 extends from above to the upper metal surface 1222a and connects with the first pad 1220, the extension portion 1510 can block the electrical connection layer 1400 from the bare die 1120. In addition, since the electrical connection layer 1400 needs to electrically connect the two second pads 1310 and 1320, the upper part 1520 of the first protective layer 1500 will have two openings at the corresponding locations of the two second pads 1310 and 1320, so that the two second pads 1310 and 1320 can be exposed, so as to facilitate the electrical connection layer 1400 to electrically connect the second pads 1310 and 1320.

[0076] like Figure 1 As shown, the vertical flip-chip light-emitting element 1000 may further include a second protective layer 1600, which covers the electrical connection layer 1400 and may further protect the outer sidewalls of the bare die 1110 (i.e., Figure 1 The exposed portion on the right side and the portion of the electrical connection layer 1400 located outside the extension 1510. Thus, the electrical connection layer 1400 can be protected by the second protective layer 1600.

[0077] Accordingly, in application, the two first pads 1210 and 1220 can be soldered onto the circuit board, and the vertical flip-chip light-emitting element 1000 can be powered through the two first pads 1210 and 1220. When both bare dies 1110 and 1120 are normal, the first shunt I1 can flow through the first pad 1210 into the first type semiconductor layer 1111, active layer 1113, second type semiconductor layer 1112 and second pad 1310 of the bare die 1110, and then flow back to the first pad 1220 along the electrical connection layer 1400; the second shunt I2 can flow through the first pad 1210 into the first type semiconductor layer 1111, first type semiconductor connection portion 1130 of the bare die 1110, the first type semiconductor layer 1121, active layer 1113, second type semiconductor layer 1122 and second pad 1320 of the bare die 1120, and then flow back to the first pad 1220 along the electrical connection layer 1400. Therefore, both bare chips 1110 and 1120 emit light normally. If bare chip 1110 is damaged, all the current can flow along the path of the second shunt I2, enabling bare chip 1120 to emit light; conversely, if bare chip 1120 is damaged, all the current can flow along the path of the first shunt I1, enabling bare chip 1110 to emit light. Thus, regardless of whether bare chip 1110 or bare chip 1120 is damaged, the vertical flip-chip light-emitting element 1000 can still emit light. In this way, the vertical flip-chip light-emitting element 1000 has a self-compensation function and does not require additional maintenance. It should be noted that, in order to clearly illustrate the structure of each layer, Figure 1 The thicknesses shown are not drawn to scale. For example, the thickness of the electrical connection layer 1400 may be less than 100 nm, the thickness of the first protective layer 1500 may be 40 μm to 50 μm, and the thickness of the second protective layer 1600 may be 50 μm to 60 μm, without being limited to the figures.

[0078] Please see Figure 2 ,in Figure 2 A flowchart illustrating the steps of a vertical flip-chip light-emitting element fabrication method S2000 according to another embodiment of the present invention is shown. The vertical flip-chip light-emitting element fabrication method S2000 includes an epitaxial structure formation step S2100, a first pad formation step S2200, a native substrate removal step S2300, an etching step S2400, a second pad formation step S2500, and an electrical connection layer formation step S2700.

[0079] Please see Figure 3 , Figure 4 and Figure 5 See also Figure 2 ,in Figure 3 Draw Figure 2 The embodiment illustrates a side view of the fabrication process of a vertical flip-chip light-emitting element 2000, specifically the fabrication method S2000. Figure 4 Draw Figure 2Another side view schematic diagram illustrating the fabrication of a vertical flip-chip light-emitting element 2000 in the embodiment's method S2000. Figure 5 Draw Figure 2 This embodiment provides another side view diagram illustrating the fabrication of a vertical flip-chip light-emitting element 2000 using the fabrication method S2000. The following will be accompanied by... Figure 3 , Figure 4 and Figure 5 This section details the S2000 method for manufacturing vertical flip-chip light-emitting elements.

[0080] In the epitaxial structure formation step S2100, an epitaxial structure E1 is formed on a native substrate S1.

[0081] In the first pad forming step S2200, a plurality of first pad groups 2200 are formed on the epitaxial structure E1. Each first pad group 2200 includes two first pads 2210 and 2220 and an insulating layer 2230. The first of the two first pads 2210 and 2220 of each first pad group 2200 (i.e., the first pad 2210, hereinafter referred to as the first pad 2210) is connected to a proximal side of the insulating layer 2230. The second of the two first pads 2210 and 2220 of each first pad group 2200 (i.e., the first pad 2220, hereinafter referred to as the first pad 2220) covers a distal side of the insulating layer 2230. The first pads 2210 and 2220 of each first pad group 2200 are not in direct contact.

[0082] In the native substrate removal step S2300, the aforementioned plurality of first pads 2210, 2220 are bonded to a transient substrate T1, and the native substrate S1 is removed.

[0083] In etching step S2400, the epitaxial structure E1 is etched to form multiple bare die groups 2100. Each bare die group 2100 includes two bare dies 2110 and 2120 and a first-type semiconductor interconnect 2130. Each bare die 2110 and 2120 includes a first-type semiconductor layer 2111 and 2121, an active layer 2113 and 2123, and a second-type semiconductor layer 2112 and 2122. The first-type semiconductor interconnect 2130 is connected to the first-type semiconductor layers 2111 and 2122 of the two bare dies 2110 and 2120. Between 121, each bare die group 2100 corresponds to each first pad group 2200, wherein the first pad 2210 of each first pad group 2200 is directly attached to the underside of the first of the two bare dies 2110 and 2120 of each bare die group 2100 (i.e., bare die 2110, hereinafter referred to as bare die 2110), and the insulating layer 2230 of each first pad group 2200 is directly attached to the underside of the second of the two bare dies 2110 and 2120 of each bare die group 2100 (i.e., bare die 2120, hereinafter referred to as bare die 2120).

[0084] In the second pad forming step S2500, a plurality of second pad groups 2300 are formed corresponding to the aforementioned plurality of bare die groups 2100. Each second pad group 2300 includes two second pads 2310 and 2320. The first of the two second pads 2310 and 2320 of each second pad group 2300 (i.e., the second pad 2310, hereinafter referred to as the second pad 2310) is disposed above the bare die 2110. The second of the two second pads 2310 and 2320 of each second pad group 2300 (i.e., the second pad 2320, hereinafter referred to as the second pad 2320) is disposed above the bare die 2120 of each bare die group 2100.

[0085] In the step S2700 of forming an electrical connection layer, a plurality of electrical connection layers 2400 are formed corresponding to the aforementioned plurality of bare die groups 2100. Each electrical connection layer 2400 is electrically connected to the second second pads 2310 and 2320 of each second pad group 2300 and the first pad 2220 of each first pad group 2200.

[0086] The vertical flip-chip light-emitting element fabrication method S2000 may further include a first protective layer forming step S2600, forming a plurality of first protective layers 2500 corresponding to the aforementioned plurality of bare die groups 2100. Each first protective layer 2500 covers the top of each bare die group 2100 and includes two openings 2501 and 2502. The two openings 2501 and 2502 of each first protective layer 2500 correspond to the two second pads 2310 and 2320 of each second pad group 2300, so that the two second pads 2310 and 2320 of each second pad group 2300 are exposed. Each electrical connection layer 2400 is located above each first protective layer 2500, and each electrical connection layer 2400 is electrically connected to the two second pads 2310 and 2320 exposed in the two openings 2501 and 2502 in each second pad group 2300.

[0087] The vertical flip-chip light-emitting element fabrication method S2000 may further include a second protective layer forming step S2800, forming a plurality of second protective layers 2600 corresponding to the aforementioned plurality of bare die groups 2100, with each second protective layer 2600 covering the top of each electrical connection layer 2400.

[0088] like Figure 2 and Figure 3As shown, in the epitaxial structure formation step S2100, the epitaxial structure E1 can be formed using existing epitaxial growth methods. It sequentially includes a second type semiconductor material, an active layer material, and a first type semiconductor material from the native substrate S1 upwards. Next, in the first pad formation step S2200, a plurality of first pad groups 2200 are formed on one side of the epitaxial structure E1. Furthermore, to form the first pad groups 2200 on the other side of the epitaxial structure E1, the epitaxial structure E1 can be bonded to the transient substrate T1 in the native substrate removal step S2300. This allows the native substrate S1 to be removed, facilitating subsequent operations. It should be noted that the transient substrate T1 can be bonded to the first pad groups 2200 with an adhesive T11, and the adhesive T11 can be deformed by compression. After bonding the epitaxial structure E1 to the transient substrate T1, the epitaxial structure E1 can be facing upwards, and then the etching step S2400 can be performed. In etching step S2400, unnecessary parts can be removed, and the two bare dies 2110 and 2120 can be connected together to form a bare die assembly 2100. At this time, only the first type semiconductor layer 2111 and the first type semiconductor layer 2121 in the bare dies 2110 and 2120 are connected through the first type semiconductor connection portion 2130, while the second type semiconductor layer 2112 and the second type semiconductor layer 2122 are not directly connected, and the active layer 2113 and the active layer 2123 are also not directly connected.

[0089] like Figure 2 and Figure 4 As shown, second pads 2310 and 2320 are formed in the second pad formation step S2500. Subsequently, in the first protective layer formation step S2600, an extension 2510 of each first protective layer 2500 extends through the outer sidewall of the bare die 2120 of each die group 2100 to the metal upper surface of the first pad 2220 in the corresponding first pad group 2200. That is, an upper portion 2520 can be formed to cover the two bare dies 2110 and 2120 of each die group 2100, and an extension 2510 can be formed to cover the outer sidewall of the bare die 2120. After the upper portion 2520 covers the two bare dies 2110 and 2120 of each die group 2100, openings 2501 and 2502 can be etched to expose at least part of the surface of the second pads 2310 and 2320. Subsequently, in the electrical connection layer formation step S2700, each electrical connection layer 2400 can be located outside the extension 2510 of each first protective layer 2500 and extend to the metal upper surface of the first pad 2220 in the corresponding first pad group 2200, thereby completing the electrical connection of the second pad 2310, the second pad 2320 and the first pad 2220.

[0090] like Figure 2 and Figure 5As shown, the second protective layer 2600 is formed in the second protective layer formation step S2800, thereby completing multiple vertical flip-chip light-emitting elements 2000. Furthermore, due to process requirements, the second protective layer 2600 connects the vertical flip-chip light-emitting elements 2000. At this point, a portion of the second protective layer 2600 can be removed using plasma bombardment (without affecting the colloid T11), thus disconnecting the vertical flip-chip light-emitting elements 2000.

[0091] Please see Figure 6 See also Figure 5 ,in Figure 6 Draw Figure 2 A bottom view of the vertical flip-chip light-emitting element 2000 fabricated in the method S2000 for fabricating the vertical flip-chip light-emitting element 2000, as described in the embodiment. Figure 5 and Figure 6 As shown, the disconnected vertical flip-chip light-emitting element 2000 can be moved to a blue film B1 and the transient substrate T1 can be removed, which facilitates subsequent use.

[0092] Please see Figure 7 See also Figure 5 and Figure 6 ,in Figure 7 Draw Figure 2 The embodiment of the vertical flip-chip light-emitting element manufacturing method S2000 shows a top view of the manufacturing process of the vertical flip-chip light-emitting element 2000. The vertical flip-chip light-emitting element 2000 can be bonded to a circuit board P1 via solder pads, and the vertical flip-chip light-emitting element 2000 can emit light through the current provided by the circuit board P1.

[0093] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A vertical flip-chip light-emitting element, characterized in that, Include: A bare crystal assembly, comprising: Two bare crystals, each bare crystal comprising a first type semiconductor layer, an active layer, and a second type semiconductor layer; and A first type semiconductor interconnect is connected between the first type semiconductor layers of the two bare dies; two first pads, one of which is disposed below the first of the two bare dies or below the first type semiconductor interconnect, and a second of the two first pads corresponds to but does not directly contact the second of the two bare dies. Two second pads, a first of which is disposed above the first of the two bare dies, and a second of which is disposed above the second of the two bare dies; and An electrical connection layer electrically connects the second of the two second pads to the second of the two first pads; A first shunt of the current flows through the first of the two first pads, the first of the two bare dies, the first of the two second pads, the electrical connection layer, and the second of the two first pads; a second shunt of the current flows through the first of the two first pads, the first type semiconductor connection, the second of the two bare dies, the second of the two second pads, the electrical connection layer, and the second of the two first pads.

2. The vertical flip-chip light-emitting element as described in claim 1, characterized in that, Also includes: An insulating layer is disposed directly beneath the second of the two bare crystals; In this case, the second of the two first pads is at least partially located below the insulating layer.

3. The vertical flip-chip light-emitting element as described in claim 2, characterized in that, Also includes: A first protective layer covers the two bare crystals and includes two openings, the two openings respectively corresponding to the two second pads, so that the two second pads are exposed; The electrical connection layer is located above the first protective layer and is electrically connected to the two second pads exposed in the two openings.

4. The vertical flip-chip light-emitting element as described in claim 3, characterized in that, The second of the two first pads includes a metal upper surface that is not blocked by the insulating layer. An extension of the first protective layer extends from an outer sidewall of the second of the two bare crystals to the metal upper surface. The outer sidewall is away from the first of the two bare crystals. The electrical connection layer is located outside the extension and extends to the metal upper surface.

5. The vertical flip-chip light-emitting element as described in claim 4, characterized in that, The upper surface of the metal is aligned with an insulating upper surface of the insulating layer, and the lower surface of the metal of the first of the two first pads is aligned with the lower surface of the metal of the second of the two first pads.

6. The vertical flip-chip light-emitting element as described in claim 5, characterized in that, Also includes: A second protective layer covers the electrical connection layer.

7. A method for fabricating a vertical flip-chip light-emitting element, characterized in that, Include: An epitaxial structure formation step, wherein an epitaxial structure is formed on a native substrate; A first pad forming step involves forming a plurality of first pad groups on the epitaxial structure. Each first pad group includes two first pads and an insulating layer. A first one of the two first pads in each first pad group is connected to a proximal side of the insulating layer, and a second one of the two first pads in each first pad group covers a distal side of the insulating layer. The first and second first pads in each first pad group do not directly contact each other. A native substrate removal step involves bonding the plurality of first pads to a transient substrate and removing the native substrate. An etching step is performed to etch the epitaxial structure to form multiple bare die groups. Each bare die group includes two bare dies and a first type semiconductor interconnect. Each bare die includes a first type semiconductor layer, an active layer, and a second type semiconductor layer. The first type semiconductor interconnect is connected between the first type semiconductor layers of the two bare dies. Each bare die group corresponds to each first pad group. The first of the two first pads in each first pad group is directly attached to the underside of the first of the two bare dies in each bare die group. The insulating layer of each first pad group is directly attached to the underside of the second of the two bare dies in each bare die group. A second pad forming step involves forming a plurality of second pad groups corresponding to the plurality of bare die groups, wherein each second pad group includes two second pads, a first of the two second pads in each second pad group is disposed above the first of the two bare die groups in each bare die group, and a second of the two second pads in each second pad group is disposed above the second of the two bare die groups in each bare die group; and An electrical connection layer forming step is performed to form a plurality of electrical connection layers corresponding to the plurality of bare die groups, wherein each electrical connection layer is electrically connected to the second second pad of each second pad group and the second of the two first pads of each first pad group.

8. The method for fabricating a vertical flip-chip light-emitting element as described in claim 7, characterized in that, Also includes: A first protective layer forming step involves forming multiple first protective layers corresponding to the multiple bare die groups. Each first protective layer covers the top of each bare die group and includes two openings. The two openings of each first protective layer correspond to the two second pads of each bare die group, so that the two second pads of each second pad group are exposed. Each electrical connection layer is located above each first protective layer and is electrically connected to the two second pads exposed in the two openings of each second pad group.

9. The method for fabricating a vertical flip-chip light-emitting element as described in claim 8, characterized in that, Also includes: A second protective layer forming step involves forming multiple second protective layers corresponding to the multiple bare die groups, with each second protective layer covering the top of each electrical connection layer.

10. The method for fabricating a vertical flip-chip light-emitting element as described in claim 9, characterized in that, In the first protective layer forming step, an extension of each first protective layer extends through an outer sidewall of the second of the two bare crystals in each bare crystal group to a metal upper surface of the second of the two first pads in the corresponding first pad group. In the electrical connection layer forming step, each electrical connection layer is located outside the extension of each first protective layer and extends to the metal upper surface of the second of the two first pads in the corresponding first pad group.

Images